1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2021 Intel Corporation 4 */ 5 #include "iwl-trans.h" 6 #include "iwl-fh.h" 7 #include "iwl-context-info-gen3.h" 8 #include "internal.h" 9 #include "iwl-prph.h" 10 11 static void 12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13 struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14 u32 *control_flags) 15 { 16 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18 u32 dbg_flags = 0; 19 20 if (!iwl_trans_dbg_ini_valid(trans)) { 21 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22 23 iwl_pcie_alloc_fw_monitor(trans, 0); 24 25 if (fw_mon->size) { 26 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27 28 IWL_DEBUG_FW(trans, 29 "WRT: Applying DRAM buffer destination\n"); 30 31 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33 } 34 35 goto out; 36 } 37 38 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39 40 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41 case IWL_FW_INI_LOCATION_SRAM_PATH: 42 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43 IWL_DEBUG_FW(trans, 44 "WRT: Applying SMEM buffer destination\n"); 45 break; 46 47 case IWL_FW_INI_LOCATION_NPK_PATH: 48 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49 IWL_DEBUG_FW(trans, 50 "WRT: Applying NPK buffer destination\n"); 51 break; 52 53 case IWL_FW_INI_LOCATION_DRAM_PATH: 54 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55 struct iwl_dram_data *frag = 56 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59 dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 61 IWL_DEBUG_FW(trans, 62 "WRT: Applying DRAM destination (debug_token_config=%u)\n", 63 dbg_cfg->debug_token_config); 64 IWL_DEBUG_FW(trans, 65 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 66 alloc_id, 67 trans->dbg.fw_mon_ini[alloc_id].num_frags); 68 } 69 break; 70 default: 71 IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 72 } 73 out: 74 if (dbg_flags) 75 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 76 } 77 78 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 79 const struct fw_img *fw) 80 { 81 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 82 struct iwl_context_info_gen3 *ctxt_info_gen3; 83 struct iwl_prph_scratch *prph_scratch; 84 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 85 struct iwl_prph_info *prph_info; 86 u32 control_flags = 0; 87 int ret; 88 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 89 trans->cfg->min_txq_size); 90 91 switch (trans_pcie->rx_buf_size) { 92 case IWL_AMSDU_DEF: 93 return -EINVAL; 94 case IWL_AMSDU_2K: 95 break; 96 case IWL_AMSDU_4K: 97 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 98 break; 99 case IWL_AMSDU_8K: 100 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 101 /* if firmware supports the ext size, tell it */ 102 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 103 break; 104 case IWL_AMSDU_12K: 105 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 106 /* if firmware supports the ext size, tell it */ 107 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 108 break; 109 } 110 111 /* Allocate prph scratch */ 112 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 113 &trans_pcie->prph_scratch_dma_addr, 114 GFP_KERNEL); 115 if (!prph_scratch) 116 return -ENOMEM; 117 118 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 119 120 prph_sc_ctrl->version.version = 0; 121 prph_sc_ctrl->version.mac_id = 122 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 123 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 124 125 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 126 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 127 128 /* initialize RX default queue */ 129 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 130 cpu_to_le64(trans_pcie->rxq->bd_dma); 131 132 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 133 &control_flags); 134 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 135 136 /* allocate ucode sections in dram and set addresses */ 137 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 138 if (ret) 139 goto err_free_prph_scratch; 140 141 142 /* Allocate prph information 143 * currently we don't assign to the prph info anything, but it would get 144 * assigned later 145 * 146 * We also use the second half of this page to give the device some 147 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 148 * use this, but the hardware still reads/writes there and we can't let 149 * it go do that with a NULL pointer. 150 */ 151 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 152 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 153 &trans_pcie->prph_info_dma_addr, 154 GFP_KERNEL); 155 if (!prph_info) { 156 ret = -ENOMEM; 157 goto err_free_prph_scratch; 158 } 159 160 /* Allocate context info */ 161 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 162 sizeof(*ctxt_info_gen3), 163 &trans_pcie->ctxt_info_dma_addr, 164 GFP_KERNEL); 165 if (!ctxt_info_gen3) { 166 ret = -ENOMEM; 167 goto err_free_prph_info; 168 } 169 170 ctxt_info_gen3->prph_info_base_addr = 171 cpu_to_le64(trans_pcie->prph_info_dma_addr); 172 ctxt_info_gen3->prph_scratch_base_addr = 173 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 174 ctxt_info_gen3->prph_scratch_size = 175 cpu_to_le32(sizeof(*prph_scratch)); 176 ctxt_info_gen3->cr_head_idx_arr_base_addr = 177 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 178 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 179 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 180 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 181 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 182 ctxt_info_gen3->mtr_base_addr = 183 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 184 ctxt_info_gen3->mcr_base_addr = 185 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 186 ctxt_info_gen3->mtr_size = 187 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 188 ctxt_info_gen3->mcr_size = 189 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 190 191 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 192 trans_pcie->prph_info = prph_info; 193 trans_pcie->prph_scratch = prph_scratch; 194 195 /* Allocate IML */ 196 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 197 &trans_pcie->iml_dma_addr, 198 GFP_KERNEL); 199 if (!trans_pcie->iml) { 200 ret = -ENOMEM; 201 goto err_free_ctxt_info; 202 } 203 204 memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 205 206 iwl_enable_fw_load_int_ctx_info(trans); 207 208 /* kick FW self load */ 209 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 210 trans_pcie->ctxt_info_dma_addr); 211 iwl_write64(trans, CSR_IML_DATA_ADDR, 212 trans_pcie->iml_dma_addr); 213 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 214 215 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 216 CSR_AUTO_FUNC_BOOT_ENA); 217 218 return 0; 219 220 err_free_ctxt_info: 221 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 222 trans_pcie->ctxt_info_gen3, 223 trans_pcie->ctxt_info_dma_addr); 224 trans_pcie->ctxt_info_gen3 = NULL; 225 err_free_prph_info: 226 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 227 trans_pcie->prph_info_dma_addr); 228 229 err_free_prph_scratch: 230 dma_free_coherent(trans->dev, 231 sizeof(*prph_scratch), 232 prph_scratch, 233 trans_pcie->prph_scratch_dma_addr); 234 return ret; 235 236 } 237 238 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 239 { 240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 241 242 if (trans_pcie->iml) { 243 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 244 trans_pcie->iml_dma_addr); 245 trans_pcie->iml_dma_addr = 0; 246 trans_pcie->iml = NULL; 247 } 248 249 iwl_pcie_ctxt_info_free_fw_img(trans); 250 251 if (alive) 252 return; 253 254 if (!trans_pcie->ctxt_info_gen3) 255 return; 256 257 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 258 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 259 trans_pcie->ctxt_info_gen3, 260 trans_pcie->ctxt_info_dma_addr); 261 trans_pcie->ctxt_info_dma_addr = 0; 262 trans_pcie->ctxt_info_gen3 = NULL; 263 264 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 265 trans_pcie->prph_scratch, 266 trans_pcie->prph_scratch_dma_addr); 267 trans_pcie->prph_scratch_dma_addr = 0; 268 trans_pcie->prph_scratch = NULL; 269 270 /* this is needed for the entire lifetime */ 271 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 272 trans_pcie->prph_info_dma_addr); 273 trans_pcie->prph_info_dma_addr = 0; 274 trans_pcie->prph_info = NULL; 275 } 276 277 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 278 const void *data, u32 len) 279 { 280 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 281 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 282 &trans_pcie->prph_scratch->ctrl_cfg; 283 int ret; 284 285 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 286 return 0; 287 288 /* only allocate the DRAM if not allocated yet */ 289 if (!trans->pnvm_loaded) { 290 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 291 return -EBUSY; 292 293 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 294 &trans_pcie->pnvm_dram); 295 if (ret < 0) { 296 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", 297 ret); 298 return ret; 299 } 300 } 301 302 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 303 cpu_to_le64(trans_pcie->pnvm_dram.physical); 304 prph_sc_ctrl->pnvm_cfg.pnvm_size = 305 cpu_to_le32(trans_pcie->pnvm_dram.size); 306 307 return 0; 308 } 309 310 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 311 const void *data, u32 len) 312 { 313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 314 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 315 &trans_pcie->prph_scratch->ctrl_cfg; 316 int ret; 317 318 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 319 return 0; 320 321 /* only allocate the DRAM if not allocated yet */ 322 if (!trans->reduce_power_loaded) { 323 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 324 return -EBUSY; 325 326 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 327 &trans_pcie->reduce_power_dram); 328 if (ret < 0) { 329 IWL_DEBUG_FW(trans, 330 "Failed to allocate reduce power DMA %d.\n", 331 ret); 332 return ret; 333 } 334 } 335 336 prph_sc_ctrl->reduce_power_cfg.base_addr = 337 cpu_to_le64(trans_pcie->reduce_power_dram.physical); 338 prph_sc_ctrl->reduce_power_cfg.size = 339 cpu_to_le32(trans_pcie->reduce_power_dram.size); 340 341 return 0; 342 } 343