1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2016-2017 Intel Deutschland GmbH 5 * Copyright (C) 2018-2025 Intel Corporation 6 */ 7 #ifndef __IWL_CONFIG_H__ 8 #define __IWL_CONFIG_H__ 9 10 #include <linux/types.h> 11 #include <linux/netdevice.h> 12 #include <linux/ieee80211.h> 13 #include <linux/nl80211.h> 14 #include <linux/mod_devicetable.h> 15 #include "iwl-csr.h" 16 #include "iwl-drv.h" 17 18 enum iwl_device_family { 19 IWL_DEVICE_FAMILY_UNDEFINED, 20 IWL_DEVICE_FAMILY_1000, 21 IWL_DEVICE_FAMILY_100, 22 IWL_DEVICE_FAMILY_2000, 23 IWL_DEVICE_FAMILY_2030, 24 IWL_DEVICE_FAMILY_105, 25 IWL_DEVICE_FAMILY_135, 26 IWL_DEVICE_FAMILY_5000, 27 IWL_DEVICE_FAMILY_5150, 28 IWL_DEVICE_FAMILY_6000, 29 IWL_DEVICE_FAMILY_6000i, 30 IWL_DEVICE_FAMILY_6005, 31 IWL_DEVICE_FAMILY_6030, 32 IWL_DEVICE_FAMILY_6050, 33 IWL_DEVICE_FAMILY_6150, 34 IWL_DEVICE_FAMILY_7000, 35 IWL_DEVICE_FAMILY_8000, 36 IWL_DEVICE_FAMILY_9000, 37 IWL_DEVICE_FAMILY_22000, 38 IWL_DEVICE_FAMILY_AX210, 39 IWL_DEVICE_FAMILY_BZ, 40 IWL_DEVICE_FAMILY_SC, 41 IWL_DEVICE_FAMILY_DR, 42 }; 43 44 #if defined(__FreeBSD__) 45 static const char *iwl_device_family_str[] = { 46 [IWL_DEVICE_FAMILY_UNDEFINED] = "undefined", 47 [IWL_DEVICE_FAMILY_1000] = "1000", 48 [IWL_DEVICE_FAMILY_100] = "100", 49 [IWL_DEVICE_FAMILY_2000] = "2000", 50 [IWL_DEVICE_FAMILY_2030] = "2030", 51 [IWL_DEVICE_FAMILY_105] = "105", 52 [IWL_DEVICE_FAMILY_135] = "135", 53 [IWL_DEVICE_FAMILY_5000] = "5000", 54 [IWL_DEVICE_FAMILY_5150] = "5150", 55 [IWL_DEVICE_FAMILY_6000] = "6000", 56 [IWL_DEVICE_FAMILY_6000i] = "6000i", 57 [IWL_DEVICE_FAMILY_6005] = "6005", 58 [IWL_DEVICE_FAMILY_6030] = "6030", 59 [IWL_DEVICE_FAMILY_6050] = "6050", 60 [IWL_DEVICE_FAMILY_6150] = "6150", 61 [IWL_DEVICE_FAMILY_7000] = "7000", 62 [IWL_DEVICE_FAMILY_8000] = "8000", 63 [IWL_DEVICE_FAMILY_9000] = "9000", 64 [IWL_DEVICE_FAMILY_22000] = "22000", 65 [IWL_DEVICE_FAMILY_AX210] = "AX210", 66 [IWL_DEVICE_FAMILY_BZ] = "BZ", 67 [IWL_DEVICE_FAMILY_SC] = "SC", 68 }; 69 70 static inline const char * 71 iwl_device_family_name(enum iwl_device_family devive_family) 72 { 73 if (devive_family < 0 || 74 devive_family >= ARRAY_SIZE(iwl_device_family_str)) 75 return "unknown"; 76 return (iwl_device_family_str[devive_family]); 77 } 78 #endif 79 80 /* 81 * LED mode 82 * IWL_LED_DEFAULT: use device default 83 * IWL_LED_RF_STATE: turn LED on/off based on RF state 84 * LED ON = RF ON 85 * LED OFF = RF OFF 86 * IWL_LED_BLINK: adjust led blink rate based on blink table 87 * IWL_LED_DISABLE: led disabled 88 */ 89 enum iwl_led_mode { 90 IWL_LED_DEFAULT, 91 IWL_LED_RF_STATE, 92 IWL_LED_BLINK, 93 IWL_LED_DISABLE, 94 }; 95 96 /** 97 * enum iwl_nvm_type - nvm formats 98 * @IWL_NVM: the regular format 99 * @IWL_NVM_EXT: extended NVM format 100 * @IWL_NVM_SDP: NVM format used by 3168 series 101 */ 102 enum iwl_nvm_type { 103 IWL_NVM, 104 IWL_NVM_EXT, 105 IWL_NVM_SDP, 106 }; 107 108 /* 109 * This is the threshold value of plcp error rate per 100mSecs. It is 110 * used to set and check for the validity of plcp_delta. 111 */ 112 #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN 1 113 #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF 50 114 #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF 100 115 #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF 200 116 #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX 255 117 #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE 0 118 119 /* TX queue watchdog timeouts in mSecs */ 120 #define IWL_WATCHDOG_DISABLED 0 121 #define IWL_DEF_WD_TIMEOUT 2500 122 #define IWL_LONG_WD_TIMEOUT 10000 123 #define IWL_MAX_WD_TIMEOUT 120000 124 125 #define IWL_DEFAULT_MAX_TX_POWER 22 126 #define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\ 127 NETIF_F_TSO | NETIF_F_TSO6) 128 #define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM) 129 130 /* Antenna presence definitions */ 131 #define ANT_NONE 0x0 132 #define ANT_INVALID 0xff 133 #define ANT_A BIT(0) 134 #define ANT_B BIT(1) 135 #define ANT_C BIT(2) 136 #define ANT_AB (ANT_A | ANT_B) 137 #define ANT_AC (ANT_A | ANT_C) 138 #define ANT_BC (ANT_B | ANT_C) 139 #define ANT_ABC (ANT_A | ANT_B | ANT_C) 140 141 142 #define IWL_FW_AND_PNVM(pfx, api) \ 143 MODULE_FIRMWARE(pfx "-" __stringify(api) ".ucode"); \ 144 MODULE_FIRMWARE(pfx ".pnvm") 145 146 static inline u8 num_of_ant(u8 mask) 147 { 148 return !!((mask) & ANT_A) + 149 !!((mask) & ANT_B) + 150 !!((mask) & ANT_C); 151 } 152 153 /** 154 * struct iwl_fw_mon_reg - FW monitor register info 155 * @addr: register address 156 * @mask: register mask 157 */ 158 struct iwl_fw_mon_reg { 159 u32 addr; 160 u32 mask; 161 }; 162 163 /** 164 * struct iwl_fw_mon_regs - FW monitor registers 165 * @write_ptr: write pointer register 166 * @cycle_cnt: cycle count register 167 * @cur_frag: current fragment in use 168 */ 169 struct iwl_fw_mon_regs { 170 struct iwl_fw_mon_reg write_ptr; 171 struct iwl_fw_mon_reg cycle_cnt; 172 struct iwl_fw_mon_reg cur_frag; 173 }; 174 175 /** 176 * struct iwl_family_base_params - base parameters for an entire family 177 * @max_ll_items: max number of OTP blocks 178 * @shadow_ram_support: shadow support for OTP memory 179 * @led_compensation: compensate on the led on/off time per HW according 180 * to the deviation to achieve the desired led frequency. 181 * The detail algorithm is described in iwl-led.c 182 * @wd_timeout: TX queues watchdog timeout 183 * @max_event_log_size: size of event log buffer size for ucode event logging 184 * @shadow_reg_enable: HW shadow register support 185 * @apmg_not_supported: there's no APMG 186 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command 187 * is in flight. This is due to a HW bug in 7260, 3160 and 7265. 188 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled. 189 * @max_tfd_queue_size: max number of entries in tfd queue. 190 * @eeprom_size: EEPROM size 191 * @num_of_queues: number of HW TX queues supported 192 * @pcie_l1_allowed: PCIe L1 state is allowed 193 * @pll_cfg: PLL configuration needed 194 * @nvm_hw_section_num: the ID of the HW NVM section 195 * @features: hw features, any combination of feature_passlist 196 * @smem_offset: offset from which the SMEM begins 197 * @smem_len: the length of SMEM 198 * @mac_addr_from_csr: read HW address from CSR registers at this offset 199 * @d3_debug_data_base_addr: base address where D3 debug data is stored 200 * @d3_debug_data_length: length of the D3 debug data 201 * @min_ba_txq_size: minimum number of slots required in a TX queue used 202 * for aggregation 203 * @min_txq_size: minimum number of slots required in a TX queue 204 * @gp2_reg_addr: GP2 (timer) register address 205 * @min_umac_error_event_table: minimum SMEM location of UMAC error table 206 * @mon_dbgi_regs: monitor DBGI registers 207 * @mon_dram_regs: monitor DRAM registers 208 * @mon_smem_regs: monitor SMEM registers 209 * @ucode_api_max: Highest version of uCode API supported by driver. 210 * @ucode_api_min: Lowest version of uCode API supported by driver. 211 */ 212 struct iwl_family_base_params { 213 unsigned int wd_timeout; 214 215 u16 eeprom_size; 216 u16 max_event_log_size; 217 218 u8 pll_cfg:1, /* for iwl_pcie_apm_init() */ 219 shadow_ram_support:1, 220 shadow_reg_enable:1, 221 pcie_l1_allowed:1, 222 apmg_wake_up_wa:1, 223 apmg_not_supported:1, 224 scd_chain_ext_wa:1; 225 226 u16 num_of_queues; /* def: HW dependent */ 227 u32 max_tfd_queue_size; /* def: HW dependent */ 228 229 u8 max_ll_items; 230 u8 led_compensation; 231 u8 ucode_api_max; 232 u8 ucode_api_min; 233 u32 mac_addr_from_csr:10; 234 u8 nvm_hw_section_num; 235 netdev_features_t features; 236 u32 smem_offset; 237 u32 smem_len; 238 u32 min_umac_error_event_table; 239 u32 d3_debug_data_base_addr; 240 u32 d3_debug_data_length; 241 u32 min_txq_size; 242 u32 gp2_reg_addr; 243 u32 min_ba_txq_size; 244 const struct iwl_fw_mon_regs mon_dram_regs; 245 const struct iwl_fw_mon_regs mon_smem_regs; 246 const struct iwl_fw_mon_regs mon_dbgi_regs; 247 }; 248 249 /* 250 * @stbc: support Tx STBC and 1*SS Rx STBC 251 * @ldpc: support Tx/Rx with LDPC 252 * @use_rts_for_aggregation: use rts/cts protection for HT traffic 253 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40 254 */ 255 struct iwl_ht_params { 256 u8 ht_greenfield_support:1, 257 stbc:1, 258 ldpc:1, 259 use_rts_for_aggregation:1; 260 u8 ht40_bands; 261 }; 262 263 /* 264 * Tx-backoff threshold 265 * @temperature: The threshold in Celsius 266 * @backoff: The tx-backoff in uSec 267 */ 268 struct iwl_tt_tx_backoff { 269 s32 temperature; 270 u32 backoff; 271 }; 272 273 #define TT_TX_BACKOFF_SIZE 6 274 275 /** 276 * struct iwl_tt_params - thermal throttling parameters 277 * @ct_kill_entry: CT Kill entry threshold 278 * @ct_kill_exit: CT Kill exit threshold 279 * @ct_kill_duration: The time intervals (in uSec) in which the driver needs 280 * to checks whether to exit CT Kill. 281 * @dynamic_smps_entry: Dynamic SMPS entry threshold 282 * @dynamic_smps_exit: Dynamic SMPS exit threshold 283 * @tx_protection_entry: TX protection entry threshold 284 * @tx_protection_exit: TX protection exit threshold 285 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order. 286 * @support_ct_kill: Support CT Kill? 287 * @support_dynamic_smps: Support dynamic SMPS? 288 * @support_tx_protection: Support tx protection? 289 * @support_tx_backoff: Support tx-backoff? 290 */ 291 struct iwl_tt_params { 292 u32 ct_kill_entry; 293 u32 ct_kill_exit; 294 u32 ct_kill_duration; 295 u32 dynamic_smps_entry; 296 u32 dynamic_smps_exit; 297 u32 tx_protection_entry; 298 u32 tx_protection_exit; 299 struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE]; 300 u8 support_ct_kill:1, 301 support_dynamic_smps:1, 302 support_tx_protection:1, 303 support_tx_backoff:1; 304 }; 305 306 /* 307 * information on how to parse the EEPROM 308 */ 309 #define EEPROM_REG_BAND_1_CHANNELS 0x08 310 #define EEPROM_REG_BAND_2_CHANNELS 0x26 311 #define EEPROM_REG_BAND_3_CHANNELS 0x42 312 #define EEPROM_REG_BAND_4_CHANNELS 0x5C 313 #define EEPROM_REG_BAND_5_CHANNELS 0x74 314 #define EEPROM_REG_BAND_24_HT40_CHANNELS 0x82 315 #define EEPROM_REG_BAND_52_HT40_CHANNELS 0x92 316 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS 0x80 317 #define EEPROM_REGULATORY_BAND_NO_HT40 0 318 319 /* lower blocks contain EEPROM image and calibration data */ 320 #define OTP_LOW_IMAGE_SIZE_2K (2 * 512 * sizeof(u16)) /* 2 KB */ 321 #define OTP_LOW_IMAGE_SIZE_16K (16 * 512 * sizeof(u16)) /* 16 KB */ 322 #define OTP_LOW_IMAGE_SIZE_32K (32 * 512 * sizeof(u16)) /* 32 KB */ 323 324 struct iwl_eeprom_params { 325 const u8 regulatory_bands[7]; 326 bool enhanced_txpower; 327 }; 328 329 /* Tx-backoff power threshold 330 * @pwr: The power limit in mw 331 * @backoff: The tx-backoff in uSec 332 */ 333 struct iwl_pwr_tx_backoff { 334 u32 pwr; 335 u32 backoff; 336 }; 337 338 enum iwl_mac_cfg_ltr_delay { 339 IWL_CFG_TRANS_LTR_DELAY_NONE = 0, 340 IWL_CFG_TRANS_LTR_DELAY_200US = 1, 341 IWL_CFG_TRANS_LTR_DELAY_2500US = 2, 342 IWL_CFG_TRANS_LTR_DELAY_1820US = 3, 343 }; 344 345 /** 346 * struct iwl_mac_cfg - information about the MAC-specific device part 347 * 348 * These values are specific to the device ID and do not change when 349 * multiple configs are used for a single device ID. They values are 350 * used, among other things, to boot the NIC so that the HW REV or 351 * RFID can be read before deciding the remaining parameters to use. 352 * 353 * @base: pointer to basic parameters 354 * @device_family: the device family 355 * @umac_prph_offset: offset to add to UMAC periphery address 356 * @xtal_latency: power up latency to get the xtal stabilized 357 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY 358 * @gen2: 22000 and on transport operation 359 * @mq_rx_supported: multi-queue rx support 360 * @integrated: discrete or integrated 361 * @low_latency_xtal: use the low latency xtal if supported 362 * @bisr_workaround: BISR hardware workaround (for 22260 series devices) 363 * @ltr_delay: LTR delay parameter, &enum iwl_mac_cfg_ltr_delay. 364 * @imr_enabled: use the IMR if supported. 365 */ 366 struct iwl_mac_cfg { 367 const struct iwl_family_base_params *base; 368 enum iwl_device_family device_family; 369 u32 umac_prph_offset; 370 u32 xtal_latency; 371 u32 extra_phy_cfg_flags; 372 u32 gen2:1, 373 mq_rx_supported:1, 374 integrated:1, 375 low_latency_xtal:1, 376 bisr_workaround:1, 377 ltr_delay:2, 378 imr_enabled:1; 379 }; 380 381 /* 382 * These sizes were picked according to 8 MSDUs inside 64/256/612 A-MSDUs 383 * in an A-MPDU, with additional overhead to account for processing time. 384 * They will be doubled for MACs starting from So/Ty that don't support 385 * putting multiple frames into a single buffer. 386 */ 387 #define IWL_NUM_RBDS_NON_HE (64 * 8) 388 #define IWL_NUM_RBDS_HE (256 * 8) 389 #define IWL_NUM_RBDS_EHT (512 * 8) 390 391 /** 392 * struct iwl_rf_cfg 393 * @fw_name_pre: Firmware filename prefix. The api version and extension 394 * (.ucode) will be added to filename before loading from disk. The 395 * filename is constructed as <fw_name_pre>-<api>.ucode. 396 * name will be generated dynamically 397 * @ucode_api_max: Highest version of uCode API supported by driver. 398 * @ucode_api_min: Lowest version of uCode API supported by driver. 399 * @max_inst_size: The maximal length of the fw inst section (only DVM) 400 * @max_data_size: The maximal length of the fw data section (only DVM) 401 * @valid_tx_ant: valid transmit antenna 402 * @valid_rx_ant: valid receive antenna 403 * @non_shared_ant: the antenna that is for WiFi only 404 * @nvm_ver: NVM version 405 * @nvm_calib_ver: NVM calibration version 406 * @bw_limit: bandwidth limit for this device, if non-zero 407 * @ht_params: point to ht parameters 408 * @eeprom_params: EEPROM parameters (old devices) 409 * @thermal_params: Thermal throttling parameters 410 * @lp_xtal_workaround: low-power crystal workaround needed 411 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) 412 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity 413 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity 414 * @internal_wimax_coex: internal wifi/wimax combo device 415 * @host_interrupt_operation_mode: device needs host interrupt operation 416 * mode set 417 * @pwr_tx_backoffs: translation table between power limits and backoffs 418 * @dccm_offset: offset from which DCCM begins 419 * @dccm_len: length of DCCM (including runtime stack CCM) 420 * @dccm2_offset: offset from which the second DCCM begins 421 * @dccm2_len: length of the second DCCM 422 * @vht_mu_mimo_supported: VHT MU-MIMO support 423 * @nvm_type: see &enum iwl_nvm_type 424 * @uhb_supported: ultra high band channels supported 425 * @num_rbds: number of receive buffer descriptors to use 426 * (only used for multi-queue capable devices) 427 * 428 * We enable the driver to be backward compatible wrt. hardware features. 429 * API differences in uCode shouldn't be handled here but through TLVs 430 * and/or the uCode API version instead. 431 */ 432 struct iwl_rf_cfg { 433 /* params specific to an individual device within a device family */ 434 const char *fw_name_pre; 435 /* params likely to change within a device family */ 436 const struct iwl_ht_params ht_params; 437 const struct iwl_eeprom_params *eeprom_params; 438 const struct iwl_pwr_tx_backoff *pwr_tx_backoffs; 439 const struct iwl_tt_params *thermal_params; 440 enum iwl_led_mode led_mode; 441 enum iwl_nvm_type nvm_type; 442 u32 max_data_size; 443 u32 max_inst_size; 444 u32 dccm_offset; 445 u32 dccm_len; 446 u32 dccm2_offset; 447 u32 dccm2_len; 448 u16 nvm_ver; 449 u16 nvm_calib_ver; 450 u16 bw_limit; 451 u32 rx_with_siso_diversity:1, 452 tx_with_siso_diversity:1, 453 internal_wimax_coex:1, 454 host_interrupt_operation_mode:1, 455 lp_xtal_workaround:1, 456 vht_mu_mimo_supported:1, 457 uhb_supported:1; 458 u8 valid_tx_ant; 459 u8 valid_rx_ant; 460 u8 non_shared_ant; 461 u8 ucode_api_max; 462 u8 ucode_api_min; 463 u16 num_rbds; 464 }; 465 466 #define IWL_CFG_ANY (~0) 467 468 #define IWL_CFG_MAC_TYPE_PU 0x31 469 #define IWL_CFG_MAC_TYPE_TH 0x32 470 #define IWL_CFG_MAC_TYPE_QU 0x33 471 #define IWL_CFG_MAC_TYPE_CC 0x34 472 #define IWL_CFG_MAC_TYPE_QUZ 0x35 473 #define IWL_CFG_MAC_TYPE_SO 0x37 474 #define IWL_CFG_MAC_TYPE_TY 0x42 475 #define IWL_CFG_MAC_TYPE_SOF 0x43 476 #define IWL_CFG_MAC_TYPE_MA 0x44 477 #define IWL_CFG_MAC_TYPE_BZ 0x46 478 #define IWL_CFG_MAC_TYPE_GL 0x47 479 #define IWL_CFG_MAC_TYPE_SC 0x48 480 #define IWL_CFG_MAC_TYPE_SC2 0x49 481 #define IWL_CFG_MAC_TYPE_SC2F 0x4A 482 #define IWL_CFG_MAC_TYPE_BZ_W 0x4B 483 #define IWL_CFG_MAC_TYPE_BR 0x4C 484 #define IWL_CFG_MAC_TYPE_DR 0x4D 485 486 #define IWL_CFG_RF_TYPE_JF2 0x105 487 #define IWL_CFG_RF_TYPE_JF1 0x108 488 #define IWL_CFG_RF_TYPE_HR2 0x10A 489 #define IWL_CFG_RF_TYPE_HR1 0x10C 490 #define IWL_CFG_RF_TYPE_GF 0x10D 491 #define IWL_CFG_RF_TYPE_FM 0x112 492 #define IWL_CFG_RF_TYPE_WH 0x113 493 #define IWL_CFG_RF_TYPE_PE 0x114 494 495 #define IWL_CFG_RF_ID_TH 0x1 496 #define IWL_CFG_RF_ID_TH1 0x1 497 #define IWL_CFG_RF_ID_JF 0x3 498 #define IWL_CFG_RF_ID_JF1 0x6 499 #define IWL_CFG_RF_ID_JF1_DIV 0xA 500 #define IWL_CFG_RF_ID_HR 0x7 501 #define IWL_CFG_RF_ID_HR1 0x4 502 503 #define IWL_CFG_CORES_BT 0x0 504 #define IWL_CFG_CORES_BT_GNSS 0x5 505 506 #define IWL_CFG_NO_CDB 0x0 507 #define IWL_CFG_CDB 0x1 508 509 #define IWL_CFG_NO_JACKET 0x0 510 #define IWL_CFG_IS_JACKET 0x1 511 512 #define IWL_SUBDEVICE_RF_ID(subdevice) ((u16)((subdevice) & 0x00F0) >> 4) 513 #define IWL_SUBDEVICE_BW_LIM(subdevice) ((u16)((subdevice) & 0x0200) >> 9) 514 #define IWL_SUBDEVICE_CORES(subdevice) ((u16)((subdevice) & 0x1C00) >> 10) 515 516 struct iwl_dev_info { 517 const struct iwl_rf_cfg *cfg; 518 const char *name; 519 u16 device; 520 u16 subdevice; 521 u32 subdevice_m_l:4, 522 subdevice_m_h:4, 523 match_rf_type:1, 524 rf_type:9, 525 match_bw_limit:1, 526 bw_limit:1, 527 match_discrete:1, 528 discrete:1, 529 match_rf_id:1, 530 rf_id:4, 531 match_cdb:1, 532 cdb:1; 533 }; 534 535 #if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS) 536 extern const struct iwl_dev_info iwl_dev_info_table[]; 537 extern const unsigned int iwl_dev_info_table_size; 538 extern const struct pci_device_id iwl_hw_card_ids[]; 539 #endif 540 541 const struct iwl_dev_info * 542 iwl_pci_find_dev_info(u16 device, u16 subsystem_device, u16 rf_type, u8 cdb, 543 u8 rf_id, u8 bw_limit, bool discrete); 544 545 /* 546 * This list declares the config structures for all devices. 547 */ 548 extern const struct iwl_mac_cfg iwl1000_mac_cfg; 549 extern const struct iwl_mac_cfg iwl5000_mac_cfg; 550 extern const struct iwl_mac_cfg iwl2000_mac_cfg; 551 extern const struct iwl_mac_cfg iwl2030_mac_cfg; 552 extern const struct iwl_mac_cfg iwl105_mac_cfg; 553 extern const struct iwl_mac_cfg iwl135_mac_cfg; 554 extern const struct iwl_mac_cfg iwl5150_mac_cfg; 555 extern const struct iwl_mac_cfg iwl6005_mac_cfg; 556 extern const struct iwl_mac_cfg iwl6030_mac_cfg; 557 extern const struct iwl_mac_cfg iwl6000i_mac_cfg; 558 extern const struct iwl_mac_cfg iwl6050_mac_cfg; 559 extern const struct iwl_mac_cfg iwl6150_mac_cfg; 560 extern const struct iwl_mac_cfg iwl6000_mac_cfg; 561 extern const struct iwl_mac_cfg iwl7000_mac_cfg; 562 extern const struct iwl_mac_cfg iwl8000_mac_cfg; 563 extern const struct iwl_mac_cfg iwl9000_mac_cfg; 564 extern const struct iwl_mac_cfg iwl9560_mac_cfg; 565 extern const struct iwl_mac_cfg iwl9560_long_latency_mac_cfg; 566 extern const struct iwl_mac_cfg iwl9560_shared_clk_mac_cfg; 567 extern const struct iwl_mac_cfg iwl_qu_mac_cfg; 568 extern const struct iwl_mac_cfg iwl_qu_medium_latency_mac_cfg; 569 extern const struct iwl_mac_cfg iwl_qu_long_latency_mac_cfg; 570 extern const struct iwl_mac_cfg iwl_ax200_mac_cfg; 571 extern const struct iwl_mac_cfg iwl_ty_mac_cfg; 572 extern const struct iwl_mac_cfg iwl_so_mac_cfg; 573 extern const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg; 574 extern const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg; 575 extern const struct iwl_mac_cfg iwl_ma_mac_cfg; 576 extern const struct iwl_mac_cfg iwl_bz_mac_cfg; 577 extern const struct iwl_mac_cfg iwl_gl_mac_cfg; 578 extern const struct iwl_mac_cfg iwl_sc_mac_cfg; 579 extern const struct iwl_mac_cfg iwl_dr_mac_cfg; 580 581 extern const char iwl1000_bgn_name[]; 582 extern const char iwl1000_bg_name[]; 583 extern const char iwl100_bgn_name[]; 584 extern const char iwl100_bg_name[]; 585 extern const char iwl2000_2bgn_name[]; 586 extern const char iwl2000_2bgn_d_name[]; 587 extern const char iwl2030_2bgn_name[]; 588 extern const char iwl105_bgn_name[]; 589 extern const char iwl105_bgn_d_name[]; 590 extern const char iwl135_bgn_name[]; 591 extern const char iwl5300_agn_name[]; 592 extern const char iwl5100_bgn_name[]; 593 extern const char iwl5100_abg_name[]; 594 extern const char iwl5100_agn_name[]; 595 extern const char iwl5350_agn_name[]; 596 extern const char iwl5150_agn_name[]; 597 extern const char iwl5150_abg_name[]; 598 extern const char iwl6005_2agn_name[]; 599 extern const char iwl6005_2abg_name[]; 600 extern const char iwl6005_2bg_name[]; 601 extern const char iwl6005_2agn_sff_name[]; 602 extern const char iwl6005_2agn_d_name[]; 603 extern const char iwl6005_2agn_mow1_name[]; 604 extern const char iwl6005_2agn_mow2_name[]; 605 extern const char iwl6030_2agn_name[]; 606 extern const char iwl6030_2abg_name[]; 607 extern const char iwl6030_2bgn_name[]; 608 extern const char iwl6030_2bg_name[]; 609 extern const char iwl6035_2agn_name[]; 610 extern const char iwl6035_2agn_sff_name[]; 611 extern const char iwl1030_bgn_name[]; 612 extern const char iwl1030_bg_name[]; 613 extern const char iwl130_bgn_name[]; 614 extern const char iwl130_bg_name[]; 615 extern const char iwl6000i_2agn_name[]; 616 extern const char iwl6000i_2abg_name[]; 617 extern const char iwl6000i_2bg_name[]; 618 extern const char iwl6050_2agn_name[]; 619 extern const char iwl6050_2abg_name[]; 620 extern const char iwl6150_bgn_name[]; 621 extern const char iwl6150_bg_name[]; 622 extern const char iwl6000_3agn_name[]; 623 extern const char iwl7260_2ac_name[]; 624 extern const char iwl7260_2n_name[]; 625 extern const char iwl7260_n_name[]; 626 extern const char iwl3160_2ac_name[]; 627 extern const char iwl3160_2n_name[]; 628 extern const char iwl3160_n_name[]; 629 extern const char iwl3165_2ac_name[]; 630 extern const char iwl3168_2ac_name[]; 631 extern const char iwl7265_2ac_name[]; 632 extern const char iwl7265_2n_name[]; 633 extern const char iwl7265_n_name[]; 634 extern const char iwl8260_2n_name[]; 635 extern const char iwl8260_2ac_name[]; 636 extern const char iwl8265_2ac_name[]; 637 extern const char iwl8275_2ac_name[]; 638 extern const char iwl4165_2ac_name[]; 639 extern const char iwl_killer_1435i_name[]; 640 extern const char iwl_killer_1434_kix_name[]; 641 extern const char iwl9162_name[]; 642 extern const char iwl9260_name[]; 643 extern const char iwl9260_1_name[]; 644 extern const char iwl9270_name[]; 645 extern const char iwl9461_name[]; 646 extern const char iwl9462_name[]; 647 extern const char iwl9560_name[]; 648 extern const char iwl9162_160_name[]; 649 extern const char iwl9260_160_name[]; 650 extern const char iwl9270_160_name[]; 651 extern const char iwl9461_160_name[]; 652 extern const char iwl9462_160_name[]; 653 extern const char iwl9560_160_name[]; 654 extern const char iwl9260_killer_1550_name[]; 655 extern const char iwl9560_killer_1550i_name[]; 656 extern const char iwl9560_killer_1550s_name[]; 657 extern const char iwl_ax200_name[]; 658 extern const char iwl_ax203_name[]; 659 extern const char iwl_ax201_name[]; 660 extern const char iwl_ax101_name[]; 661 extern const char iwl_ax200_killer_1650w_name[]; 662 extern const char iwl_ax200_killer_1650x_name[]; 663 extern const char iwl_ax201_killer_1650s_name[]; 664 extern const char iwl_ax201_killer_1650i_name[]; 665 extern const char iwl_ax210_killer_1675w_name[]; 666 extern const char iwl_ax210_killer_1675x_name[]; 667 extern const char iwl9560_killer_1550i_160_name[]; 668 extern const char iwl9560_killer_1550s_160_name[]; 669 extern const char iwl_ax211_killer_1675s_name[]; 670 extern const char iwl_ax211_killer_1675i_name[]; 671 extern const char iwl_ax411_killer_1690s_name[]; 672 extern const char iwl_ax411_killer_1690i_name[]; 673 extern const char iwl_ax210_name[]; 674 extern const char iwl_ax211_name[]; 675 extern const char iwl_ax411_name[]; 676 extern const char iwl_killer_be1750s_name[]; 677 extern const char iwl_killer_be1750i_name[]; 678 extern const char iwl_killer_be1750w_name[]; 679 extern const char iwl_killer_be1750x_name[]; 680 extern const char iwl_killer_be1790s_name[]; 681 extern const char iwl_killer_be1790i_name[]; 682 extern const char iwl_be201_name[]; 683 extern const char iwl_be200_name[]; 684 extern const char iwl_be202_name[]; 685 extern const char iwl_be401_name[]; 686 extern const char iwl_be213_name[]; 687 extern const char iwl_killer_be1775s_name[]; 688 extern const char iwl_killer_be1775i_name[]; 689 extern const char iwl_be211_name[]; 690 extern const char iwl_killer_bn1850w2_name[]; 691 extern const char iwl_killer_bn1850i_name[]; 692 extern const char iwl_bn201_name[]; 693 extern const char iwl_be221_name[]; 694 extern const char iwl_be223_name[]; 695 #if IS_ENABLED(CONFIG_IWLDVM) 696 extern const struct iwl_rf_cfg iwl5300_agn_cfg; 697 extern const struct iwl_rf_cfg iwl5350_agn_cfg; 698 extern const struct iwl_rf_cfg iwl5100_n_cfg; 699 extern const struct iwl_rf_cfg iwl5100_abg_cfg; 700 extern const struct iwl_rf_cfg iwl5150_agn_cfg; 701 extern const struct iwl_rf_cfg iwl5150_abg_cfg; 702 extern const struct iwl_rf_cfg iwl6005_non_n_cfg; 703 extern const struct iwl_rf_cfg iwl6005_n_cfg; 704 extern const struct iwl_rf_cfg iwl6030_n_cfg; 705 extern const struct iwl_rf_cfg iwl6030_non_n_cfg; 706 extern const struct iwl_rf_cfg iwl6000i_2agn_cfg; 707 extern const struct iwl_rf_cfg iwl6000i_non_n_cfg; 708 extern const struct iwl_rf_cfg iwl6000i_non_n_cfg; 709 extern const struct iwl_rf_cfg iwl6000_3agn_cfg; 710 extern const struct iwl_rf_cfg iwl6050_2agn_cfg; 711 extern const struct iwl_rf_cfg iwl6050_2abg_cfg; 712 extern const struct iwl_rf_cfg iwl6150_bgn_cfg; 713 extern const struct iwl_rf_cfg iwl6150_bg_cfg; 714 extern const struct iwl_rf_cfg iwl1000_bgn_cfg; 715 extern const struct iwl_rf_cfg iwl1000_bg_cfg; 716 extern const struct iwl_rf_cfg iwl100_bgn_cfg; 717 extern const struct iwl_rf_cfg iwl100_bg_cfg; 718 extern const struct iwl_rf_cfg iwl130_bgn_cfg; 719 extern const struct iwl_rf_cfg iwl130_bg_cfg; 720 extern const struct iwl_rf_cfg iwl2000_2bgn_cfg; 721 extern const struct iwl_rf_cfg iwl2030_2bgn_cfg; 722 extern const struct iwl_rf_cfg iwl6035_2agn_cfg; 723 extern const struct iwl_rf_cfg iwl105_bgn_cfg; 724 extern const struct iwl_rf_cfg iwl135_bgn_cfg; 725 #endif /* CONFIG_IWLDVM */ 726 #if IS_ENABLED(CONFIG_IWLMVM) 727 extern const struct iwl_rf_cfg iwl7260_cfg; 728 extern const struct iwl_rf_cfg iwl7260_high_temp_cfg; 729 extern const struct iwl_rf_cfg iwl3160_cfg; 730 extern const struct iwl_rf_cfg iwl3165_2ac_cfg; 731 extern const struct iwl_rf_cfg iwl3168_2ac_cfg; 732 extern const struct iwl_rf_cfg iwl7265_cfg; 733 extern const struct iwl_rf_cfg iwl7265d_cfg; 734 extern const struct iwl_rf_cfg iwl8260_cfg; 735 extern const struct iwl_rf_cfg iwl8265_cfg; 736 extern const struct iwl_rf_cfg iwl_rf_jf; 737 extern const struct iwl_rf_cfg iwl_rf_jf_80mhz; 738 extern const struct iwl_rf_cfg iwl_rf_hr1; 739 extern const struct iwl_rf_cfg iwl_rf_hr; 740 extern const struct iwl_rf_cfg iwl_rf_hr_80mhz; 741 742 extern const struct iwl_rf_cfg iwl_rf_gf; 743 #endif /* CONFIG_IWLMVM */ 744 745 #if IS_ENABLED(CONFIG_IWLMLD) 746 extern const struct iwl_rf_cfg iwl_rf_fm; 747 extern const struct iwl_rf_cfg iwl_rf_fm_160mhz; 748 #define iwl_rf_wh iwl_rf_fm 749 #define iwl_rf_wh_160mhz iwl_rf_fm_160mhz 750 #define iwl_rf_pe iwl_rf_fm 751 #endif /* CONFIG_IWLMLD */ 752 753 #endif /* __IWL_CONFIG_H__ */ 754