1bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2bfcc09ddSBjoern A. Zeeb /* 3bfcc09ddSBjoern A. Zeeb * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4bfcc09ddSBjoern A. Zeeb * Copyright (C) 2016-2017 Intel Deutschland GmbH 5bfcc09ddSBjoern A. Zeeb */ 6bfcc09ddSBjoern A. Zeeb #ifndef __IWL_CONFIG_H__ 7bfcc09ddSBjoern A. Zeeb #define __IWL_CONFIG_H__ 8bfcc09ddSBjoern A. Zeeb 9bfcc09ddSBjoern A. Zeeb #include <linux/types.h> 10bfcc09ddSBjoern A. Zeeb #include <linux/netdevice.h> 11bfcc09ddSBjoern A. Zeeb #include <linux/ieee80211.h> 12bfcc09ddSBjoern A. Zeeb #include <linux/nl80211.h> 13bfcc09ddSBjoern A. Zeeb #include "iwl-csr.h" 14bfcc09ddSBjoern A. Zeeb 15bfcc09ddSBjoern A. Zeeb enum iwl_device_family { 16bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_UNDEFINED, 17bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_1000, 18bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_100, 19bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_2000, 20bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_2030, 21bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_105, 22bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_135, 23bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_5000, 24bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_5150, 25bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6000, 26bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6000i, 27bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6005, 28bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6030, 29bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6050, 30bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_6150, 31bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_7000, 32bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_8000, 33bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_9000, 34bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_22000, 35bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_AX210, 36bfcc09ddSBjoern A. Zeeb IWL_DEVICE_FAMILY_BZ, 37bfcc09ddSBjoern A. Zeeb }; 38bfcc09ddSBjoern A. Zeeb 39bfcc09ddSBjoern A. Zeeb /* 40bfcc09ddSBjoern A. Zeeb * LED mode 41bfcc09ddSBjoern A. Zeeb * IWL_LED_DEFAULT: use device default 42bfcc09ddSBjoern A. Zeeb * IWL_LED_RF_STATE: turn LED on/off based on RF state 43bfcc09ddSBjoern A. Zeeb * LED ON = RF ON 44bfcc09ddSBjoern A. Zeeb * LED OFF = RF OFF 45bfcc09ddSBjoern A. Zeeb * IWL_LED_BLINK: adjust led blink rate based on blink table 46bfcc09ddSBjoern A. Zeeb * IWL_LED_DISABLE: led disabled 47bfcc09ddSBjoern A. Zeeb */ 48bfcc09ddSBjoern A. Zeeb enum iwl_led_mode { 49bfcc09ddSBjoern A. Zeeb IWL_LED_DEFAULT, 50bfcc09ddSBjoern A. Zeeb IWL_LED_RF_STATE, 51bfcc09ddSBjoern A. Zeeb IWL_LED_BLINK, 52bfcc09ddSBjoern A. Zeeb IWL_LED_DISABLE, 53bfcc09ddSBjoern A. Zeeb }; 54bfcc09ddSBjoern A. Zeeb 55bfcc09ddSBjoern A. Zeeb /** 56bfcc09ddSBjoern A. Zeeb * enum iwl_nvm_type - nvm formats 57bfcc09ddSBjoern A. Zeeb * @IWL_NVM: the regular format 58bfcc09ddSBjoern A. Zeeb * @IWL_NVM_EXT: extended NVM format 59bfcc09ddSBjoern A. Zeeb * @IWL_NVM_SDP: NVM format used by 3168 series 60bfcc09ddSBjoern A. Zeeb */ 61bfcc09ddSBjoern A. Zeeb enum iwl_nvm_type { 62bfcc09ddSBjoern A. Zeeb IWL_NVM, 63bfcc09ddSBjoern A. Zeeb IWL_NVM_EXT, 64bfcc09ddSBjoern A. Zeeb IWL_NVM_SDP, 65bfcc09ddSBjoern A. Zeeb }; 66bfcc09ddSBjoern A. Zeeb 67bfcc09ddSBjoern A. Zeeb /* 68bfcc09ddSBjoern A. Zeeb * This is the threshold value of plcp error rate per 100mSecs. It is 69bfcc09ddSBjoern A. Zeeb * used to set and check for the validity of plcp_delta. 70bfcc09ddSBjoern A. Zeeb */ 71bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN 1 72bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF 50 73bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF 100 74bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF 200 75bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX 255 76bfcc09ddSBjoern A. Zeeb #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE 0 77bfcc09ddSBjoern A. Zeeb 78bfcc09ddSBjoern A. Zeeb /* TX queue watchdog timeouts in mSecs */ 79bfcc09ddSBjoern A. Zeeb #define IWL_WATCHDOG_DISABLED 0 80bfcc09ddSBjoern A. Zeeb #define IWL_DEF_WD_TIMEOUT 2500 81bfcc09ddSBjoern A. Zeeb #define IWL_LONG_WD_TIMEOUT 10000 82bfcc09ddSBjoern A. Zeeb #define IWL_MAX_WD_TIMEOUT 120000 83bfcc09ddSBjoern A. Zeeb 84bfcc09ddSBjoern A. Zeeb #define IWL_DEFAULT_MAX_TX_POWER 22 85bfcc09ddSBjoern A. Zeeb #define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\ 86bfcc09ddSBjoern A. Zeeb NETIF_F_TSO | NETIF_F_TSO6) 87*d9836fb4SBjoern A. Zeeb #define IWL_TX_CSUM_NETIF_FLAGS_BZ (NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6) 88*d9836fb4SBjoern A. Zeeb #define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | \ 89*d9836fb4SBjoern A. Zeeb IWL_TX_CSUM_NETIF_FLAGS_BZ | \ 90*d9836fb4SBjoern A. Zeeb NETIF_F_RXCSUM) 91bfcc09ddSBjoern A. Zeeb 92bfcc09ddSBjoern A. Zeeb /* Antenna presence definitions */ 93bfcc09ddSBjoern A. Zeeb #define ANT_NONE 0x0 94bfcc09ddSBjoern A. Zeeb #define ANT_INVALID 0xff 95bfcc09ddSBjoern A. Zeeb #define ANT_A BIT(0) 96bfcc09ddSBjoern A. Zeeb #define ANT_B BIT(1) 97bfcc09ddSBjoern A. Zeeb #define ANT_C BIT(2) 98bfcc09ddSBjoern A. Zeeb #define ANT_AB (ANT_A | ANT_B) 99bfcc09ddSBjoern A. Zeeb #define ANT_AC (ANT_A | ANT_C) 100bfcc09ddSBjoern A. Zeeb #define ANT_BC (ANT_B | ANT_C) 101bfcc09ddSBjoern A. Zeeb #define ANT_ABC (ANT_A | ANT_B | ANT_C) 102bfcc09ddSBjoern A. Zeeb 103bfcc09ddSBjoern A. Zeeb 104bfcc09ddSBjoern A. Zeeb static inline u8 num_of_ant(u8 mask) 105bfcc09ddSBjoern A. Zeeb { 106bfcc09ddSBjoern A. Zeeb return !!((mask) & ANT_A) + 107bfcc09ddSBjoern A. Zeeb !!((mask) & ANT_B) + 108bfcc09ddSBjoern A. Zeeb !!((mask) & ANT_C); 109bfcc09ddSBjoern A. Zeeb } 110bfcc09ddSBjoern A. Zeeb 111bfcc09ddSBjoern A. Zeeb /** 112bfcc09ddSBjoern A. Zeeb * struct iwl_base_params - params not likely to change within a device family 113bfcc09ddSBjoern A. Zeeb * @max_ll_items: max number of OTP blocks 114bfcc09ddSBjoern A. Zeeb * @shadow_ram_support: shadow support for OTP memory 115bfcc09ddSBjoern A. Zeeb * @led_compensation: compensate on the led on/off time per HW according 116bfcc09ddSBjoern A. Zeeb * to the deviation to achieve the desired led frequency. 117bfcc09ddSBjoern A. Zeeb * The detail algorithm is described in iwl-led.c 118bfcc09ddSBjoern A. Zeeb * @wd_timeout: TX queues watchdog timeout 119bfcc09ddSBjoern A. Zeeb * @max_event_log_size: size of event log buffer size for ucode event logging 120bfcc09ddSBjoern A. Zeeb * @shadow_reg_enable: HW shadow register support 121bfcc09ddSBjoern A. Zeeb * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command 122bfcc09ddSBjoern A. Zeeb * is in flight. This is due to a HW bug in 7260, 3160 and 7265. 123bfcc09ddSBjoern A. Zeeb * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled. 124bfcc09ddSBjoern A. Zeeb * @max_tfd_queue_size: max number of entries in tfd queue. 125bfcc09ddSBjoern A. Zeeb */ 126bfcc09ddSBjoern A. Zeeb struct iwl_base_params { 127bfcc09ddSBjoern A. Zeeb unsigned int wd_timeout; 128bfcc09ddSBjoern A. Zeeb 129bfcc09ddSBjoern A. Zeeb u16 eeprom_size; 130bfcc09ddSBjoern A. Zeeb u16 max_event_log_size; 131bfcc09ddSBjoern A. Zeeb 132bfcc09ddSBjoern A. Zeeb u8 pll_cfg:1, /* for iwl_pcie_apm_init() */ 133bfcc09ddSBjoern A. Zeeb shadow_ram_support:1, 134bfcc09ddSBjoern A. Zeeb shadow_reg_enable:1, 135bfcc09ddSBjoern A. Zeeb pcie_l1_allowed:1, 136bfcc09ddSBjoern A. Zeeb apmg_wake_up_wa:1, 137bfcc09ddSBjoern A. Zeeb scd_chain_ext_wa:1; 138bfcc09ddSBjoern A. Zeeb 139bfcc09ddSBjoern A. Zeeb u16 num_of_queues; /* def: HW dependent */ 140bfcc09ddSBjoern A. Zeeb u32 max_tfd_queue_size; /* def: HW dependent */ 141bfcc09ddSBjoern A. Zeeb 142bfcc09ddSBjoern A. Zeeb u8 max_ll_items; 143bfcc09ddSBjoern A. Zeeb u8 led_compensation; 144bfcc09ddSBjoern A. Zeeb }; 145bfcc09ddSBjoern A. Zeeb 146bfcc09ddSBjoern A. Zeeb /* 147bfcc09ddSBjoern A. Zeeb * @stbc: support Tx STBC and 1*SS Rx STBC 148bfcc09ddSBjoern A. Zeeb * @ldpc: support Tx/Rx with LDPC 149bfcc09ddSBjoern A. Zeeb * @use_rts_for_aggregation: use rts/cts protection for HT traffic 150bfcc09ddSBjoern A. Zeeb * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40 151bfcc09ddSBjoern A. Zeeb */ 152bfcc09ddSBjoern A. Zeeb struct iwl_ht_params { 153bfcc09ddSBjoern A. Zeeb u8 ht_greenfield_support:1, 154bfcc09ddSBjoern A. Zeeb stbc:1, 155bfcc09ddSBjoern A. Zeeb ldpc:1, 156bfcc09ddSBjoern A. Zeeb use_rts_for_aggregation:1; 157bfcc09ddSBjoern A. Zeeb u8 ht40_bands; 158bfcc09ddSBjoern A. Zeeb }; 159bfcc09ddSBjoern A. Zeeb 160bfcc09ddSBjoern A. Zeeb /* 161bfcc09ddSBjoern A. Zeeb * Tx-backoff threshold 162bfcc09ddSBjoern A. Zeeb * @temperature: The threshold in Celsius 163bfcc09ddSBjoern A. Zeeb * @backoff: The tx-backoff in uSec 164bfcc09ddSBjoern A. Zeeb */ 165bfcc09ddSBjoern A. Zeeb struct iwl_tt_tx_backoff { 166bfcc09ddSBjoern A. Zeeb s32 temperature; 167bfcc09ddSBjoern A. Zeeb u32 backoff; 168bfcc09ddSBjoern A. Zeeb }; 169bfcc09ddSBjoern A. Zeeb 170bfcc09ddSBjoern A. Zeeb #define TT_TX_BACKOFF_SIZE 6 171bfcc09ddSBjoern A. Zeeb 172bfcc09ddSBjoern A. Zeeb /** 173bfcc09ddSBjoern A. Zeeb * struct iwl_tt_params - thermal throttling parameters 174bfcc09ddSBjoern A. Zeeb * @ct_kill_entry: CT Kill entry threshold 175bfcc09ddSBjoern A. Zeeb * @ct_kill_exit: CT Kill exit threshold 176bfcc09ddSBjoern A. Zeeb * @ct_kill_duration: The time intervals (in uSec) in which the driver needs 177bfcc09ddSBjoern A. Zeeb * to checks whether to exit CT Kill. 178bfcc09ddSBjoern A. Zeeb * @dynamic_smps_entry: Dynamic SMPS entry threshold 179bfcc09ddSBjoern A. Zeeb * @dynamic_smps_exit: Dynamic SMPS exit threshold 180bfcc09ddSBjoern A. Zeeb * @tx_protection_entry: TX protection entry threshold 181bfcc09ddSBjoern A. Zeeb * @tx_protection_exit: TX protection exit threshold 182bfcc09ddSBjoern A. Zeeb * @tx_backoff: Array of thresholds for tx-backoff , in ascending order. 183bfcc09ddSBjoern A. Zeeb * @support_ct_kill: Support CT Kill? 184bfcc09ddSBjoern A. Zeeb * @support_dynamic_smps: Support dynamic SMPS? 185bfcc09ddSBjoern A. Zeeb * @support_tx_protection: Support tx protection? 186bfcc09ddSBjoern A. Zeeb * @support_tx_backoff: Support tx-backoff? 187bfcc09ddSBjoern A. Zeeb */ 188bfcc09ddSBjoern A. Zeeb struct iwl_tt_params { 189bfcc09ddSBjoern A. Zeeb u32 ct_kill_entry; 190bfcc09ddSBjoern A. Zeeb u32 ct_kill_exit; 191bfcc09ddSBjoern A. Zeeb u32 ct_kill_duration; 192bfcc09ddSBjoern A. Zeeb u32 dynamic_smps_entry; 193bfcc09ddSBjoern A. Zeeb u32 dynamic_smps_exit; 194bfcc09ddSBjoern A. Zeeb u32 tx_protection_entry; 195bfcc09ddSBjoern A. Zeeb u32 tx_protection_exit; 196bfcc09ddSBjoern A. Zeeb struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE]; 197bfcc09ddSBjoern A. Zeeb u8 support_ct_kill:1, 198bfcc09ddSBjoern A. Zeeb support_dynamic_smps:1, 199bfcc09ddSBjoern A. Zeeb support_tx_protection:1, 200bfcc09ddSBjoern A. Zeeb support_tx_backoff:1; 201bfcc09ddSBjoern A. Zeeb }; 202bfcc09ddSBjoern A. Zeeb 203bfcc09ddSBjoern A. Zeeb /* 204bfcc09ddSBjoern A. Zeeb * information on how to parse the EEPROM 205bfcc09ddSBjoern A. Zeeb */ 206bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_1_CHANNELS 0x08 207bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_2_CHANNELS 0x26 208bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_3_CHANNELS 0x42 209bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_4_CHANNELS 0x5C 210bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_5_CHANNELS 0x74 211bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_24_HT40_CHANNELS 0x82 212bfcc09ddSBjoern A. Zeeb #define EEPROM_REG_BAND_52_HT40_CHANNELS 0x92 213bfcc09ddSBjoern A. Zeeb #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS 0x80 214bfcc09ddSBjoern A. Zeeb #define EEPROM_REGULATORY_BAND_NO_HT40 0 215bfcc09ddSBjoern A. Zeeb 216bfcc09ddSBjoern A. Zeeb /* lower blocks contain EEPROM image and calibration data */ 217bfcc09ddSBjoern A. Zeeb #define OTP_LOW_IMAGE_SIZE_2K (2 * 512 * sizeof(u16)) /* 2 KB */ 218bfcc09ddSBjoern A. Zeeb #define OTP_LOW_IMAGE_SIZE_16K (16 * 512 * sizeof(u16)) /* 16 KB */ 219bfcc09ddSBjoern A. Zeeb #define OTP_LOW_IMAGE_SIZE_32K (32 * 512 * sizeof(u16)) /* 32 KB */ 220bfcc09ddSBjoern A. Zeeb 221bfcc09ddSBjoern A. Zeeb struct iwl_eeprom_params { 222bfcc09ddSBjoern A. Zeeb const u8 regulatory_bands[7]; 223bfcc09ddSBjoern A. Zeeb bool enhanced_txpower; 224bfcc09ddSBjoern A. Zeeb }; 225bfcc09ddSBjoern A. Zeeb 226bfcc09ddSBjoern A. Zeeb /* Tx-backoff power threshold 227bfcc09ddSBjoern A. Zeeb * @pwr: The power limit in mw 228bfcc09ddSBjoern A. Zeeb * @backoff: The tx-backoff in uSec 229bfcc09ddSBjoern A. Zeeb */ 230bfcc09ddSBjoern A. Zeeb struct iwl_pwr_tx_backoff { 231bfcc09ddSBjoern A. Zeeb u32 pwr; 232bfcc09ddSBjoern A. Zeeb u32 backoff; 233bfcc09ddSBjoern A. Zeeb }; 234bfcc09ddSBjoern A. Zeeb 235bfcc09ddSBjoern A. Zeeb enum iwl_cfg_trans_ltr_delay { 236bfcc09ddSBjoern A. Zeeb IWL_CFG_TRANS_LTR_DELAY_NONE = 0, 237bfcc09ddSBjoern A. Zeeb IWL_CFG_TRANS_LTR_DELAY_200US = 1, 238bfcc09ddSBjoern A. Zeeb IWL_CFG_TRANS_LTR_DELAY_2500US = 2, 239bfcc09ddSBjoern A. Zeeb IWL_CFG_TRANS_LTR_DELAY_1820US = 3, 240bfcc09ddSBjoern A. Zeeb }; 241bfcc09ddSBjoern A. Zeeb 242bfcc09ddSBjoern A. Zeeb /** 243bfcc09ddSBjoern A. Zeeb * struct iwl_cfg_trans - information needed to start the trans 244bfcc09ddSBjoern A. Zeeb * 245bfcc09ddSBjoern A. Zeeb * These values are specific to the device ID and do not change when 246bfcc09ddSBjoern A. Zeeb * multiple configs are used for a single device ID. They values are 247bfcc09ddSBjoern A. Zeeb * used, among other things, to boot the NIC so that the HW REV or 248bfcc09ddSBjoern A. Zeeb * RFID can be read before deciding the remaining parameters to use. 249bfcc09ddSBjoern A. Zeeb * 250bfcc09ddSBjoern A. Zeeb * @base_params: pointer to basic parameters 251bfcc09ddSBjoern A. Zeeb * @csr: csr flags and addresses that are different across devices 252bfcc09ddSBjoern A. Zeeb * @device_family: the device family 253bfcc09ddSBjoern A. Zeeb * @umac_prph_offset: offset to add to UMAC periphery address 254bfcc09ddSBjoern A. Zeeb * @xtal_latency: power up latency to get the xtal stabilized 255bfcc09ddSBjoern A. Zeeb * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY 256bfcc09ddSBjoern A. Zeeb * @rf_id: need to read rf_id to determine the firmware image 257bfcc09ddSBjoern A. Zeeb * @use_tfh: use TFH 258bfcc09ddSBjoern A. Zeeb * @gen2: 22000 and on transport operation 259bfcc09ddSBjoern A. Zeeb * @mq_rx_supported: multi-queue rx support 260bfcc09ddSBjoern A. Zeeb * @integrated: discrete or integrated 261bfcc09ddSBjoern A. Zeeb * @low_latency_xtal: use the low latency xtal if supported 262bfcc09ddSBjoern A. Zeeb * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay. 263bfcc09ddSBjoern A. Zeeb */ 264bfcc09ddSBjoern A. Zeeb struct iwl_cfg_trans_params { 265bfcc09ddSBjoern A. Zeeb const struct iwl_base_params *base_params; 266bfcc09ddSBjoern A. Zeeb enum iwl_device_family device_family; 267bfcc09ddSBjoern A. Zeeb u32 umac_prph_offset; 268bfcc09ddSBjoern A. Zeeb u32 xtal_latency; 269bfcc09ddSBjoern A. Zeeb u32 extra_phy_cfg_flags; 270bfcc09ddSBjoern A. Zeeb u32 rf_id:1, 271bfcc09ddSBjoern A. Zeeb use_tfh:1, 272bfcc09ddSBjoern A. Zeeb gen2:1, 273bfcc09ddSBjoern A. Zeeb mq_rx_supported:1, 274bfcc09ddSBjoern A. Zeeb integrated:1, 275bfcc09ddSBjoern A. Zeeb low_latency_xtal:1, 276bfcc09ddSBjoern A. Zeeb bisr_workaround:1, 277bfcc09ddSBjoern A. Zeeb ltr_delay:2; 278bfcc09ddSBjoern A. Zeeb }; 279bfcc09ddSBjoern A. Zeeb 280bfcc09ddSBjoern A. Zeeb /** 281bfcc09ddSBjoern A. Zeeb * struct iwl_fw_mon_reg - FW monitor register info 282bfcc09ddSBjoern A. Zeeb * @addr: register address 283bfcc09ddSBjoern A. Zeeb * @mask: register mask 284bfcc09ddSBjoern A. Zeeb */ 285bfcc09ddSBjoern A. Zeeb struct iwl_fw_mon_reg { 286bfcc09ddSBjoern A. Zeeb u32 addr; 287bfcc09ddSBjoern A. Zeeb u32 mask; 288bfcc09ddSBjoern A. Zeeb }; 289bfcc09ddSBjoern A. Zeeb 290bfcc09ddSBjoern A. Zeeb /** 291bfcc09ddSBjoern A. Zeeb * struct iwl_fw_mon_regs - FW monitor registers 292bfcc09ddSBjoern A. Zeeb * @write_ptr: write pointer register 293bfcc09ddSBjoern A. Zeeb * @cycle_cnt: cycle count register 294bfcc09ddSBjoern A. Zeeb * @cur_frag: current fragment in use 295bfcc09ddSBjoern A. Zeeb */ 296bfcc09ddSBjoern A. Zeeb struct iwl_fw_mon_regs { 297bfcc09ddSBjoern A. Zeeb struct iwl_fw_mon_reg write_ptr; 298bfcc09ddSBjoern A. Zeeb struct iwl_fw_mon_reg cycle_cnt; 299bfcc09ddSBjoern A. Zeeb struct iwl_fw_mon_reg cur_frag; 300bfcc09ddSBjoern A. Zeeb }; 301bfcc09ddSBjoern A. Zeeb 302bfcc09ddSBjoern A. Zeeb /** 303bfcc09ddSBjoern A. Zeeb * struct iwl_cfg 304bfcc09ddSBjoern A. Zeeb * @trans: the trans-specific configuration part 305bfcc09ddSBjoern A. Zeeb * @name: Official name of the device 306bfcc09ddSBjoern A. Zeeb * @fw_name_pre: Firmware filename prefix. The api version and extension 307bfcc09ddSBjoern A. Zeeb * (.ucode) will be added to filename before loading from disk. The 308bfcc09ddSBjoern A. Zeeb * filename is constructed as fw_name_pre<api>.ucode. 309bfcc09ddSBjoern A. Zeeb * @ucode_api_max: Highest version of uCode API supported by driver. 310bfcc09ddSBjoern A. Zeeb * @ucode_api_min: Lowest version of uCode API supported by driver. 311bfcc09ddSBjoern A. Zeeb * @max_inst_size: The maximal length of the fw inst section (only DVM) 312bfcc09ddSBjoern A. Zeeb * @max_data_size: The maximal length of the fw data section (only DVM) 313bfcc09ddSBjoern A. Zeeb * @valid_tx_ant: valid transmit antenna 314bfcc09ddSBjoern A. Zeeb * @valid_rx_ant: valid receive antenna 315bfcc09ddSBjoern A. Zeeb * @non_shared_ant: the antenna that is for WiFi only 316bfcc09ddSBjoern A. Zeeb * @nvm_ver: NVM version 317bfcc09ddSBjoern A. Zeeb * @nvm_calib_ver: NVM calibration version 318bfcc09ddSBjoern A. Zeeb * @lib: pointer to the lib ops 319bfcc09ddSBjoern A. Zeeb * @ht_params: point to ht parameters 320bfcc09ddSBjoern A. Zeeb * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) 321bfcc09ddSBjoern A. Zeeb * @rx_with_siso_diversity: 1x1 device with rx antenna diversity 322bfcc09ddSBjoern A. Zeeb * @tx_with_siso_diversity: 1x1 device with tx antenna diversity 323bfcc09ddSBjoern A. Zeeb * @internal_wimax_coex: internal wifi/wimax combo device 324bfcc09ddSBjoern A. Zeeb * @high_temp: Is this NIC is designated to be in high temperature. 325bfcc09ddSBjoern A. Zeeb * @host_interrupt_operation_mode: device needs host interrupt operation 326bfcc09ddSBjoern A. Zeeb * mode set 327bfcc09ddSBjoern A. Zeeb * @nvm_hw_section_num: the ID of the HW NVM section 328bfcc09ddSBjoern A. Zeeb * @mac_addr_from_csr: read HW address from CSR registers at this offset 329bfcc09ddSBjoern A. Zeeb * @features: hw features, any combination of feature_passlist 330bfcc09ddSBjoern A. Zeeb * @pwr_tx_backoffs: translation table between power limits and backoffs 331bfcc09ddSBjoern A. Zeeb * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response 332bfcc09ddSBjoern A. Zeeb * @dccm_offset: offset from which DCCM begins 333bfcc09ddSBjoern A. Zeeb * @dccm_len: length of DCCM (including runtime stack CCM) 334bfcc09ddSBjoern A. Zeeb * @dccm2_offset: offset from which the second DCCM begins 335bfcc09ddSBjoern A. Zeeb * @dccm2_len: length of the second DCCM 336bfcc09ddSBjoern A. Zeeb * @smem_offset: offset from which the SMEM begins 337bfcc09ddSBjoern A. Zeeb * @smem_len: the length of SMEM 338bfcc09ddSBjoern A. Zeeb * @vht_mu_mimo_supported: VHT MU-MIMO support 339bfcc09ddSBjoern A. Zeeb * @cdb: CDB support 340bfcc09ddSBjoern A. Zeeb * @nvm_type: see &enum iwl_nvm_type 341bfcc09ddSBjoern A. Zeeb * @d3_debug_data_base_addr: base address where D3 debug data is stored 342bfcc09ddSBjoern A. Zeeb * @d3_debug_data_length: length of the D3 debug data 343bfcc09ddSBjoern A. Zeeb * @bisr_workaround: BISR hardware workaround (for 22260 series devices) 344bfcc09ddSBjoern A. Zeeb * @min_txq_size: minimum number of slots required in a TX queue 345bfcc09ddSBjoern A. Zeeb * @uhb_supported: ultra high band channels supported 346*d9836fb4SBjoern A. Zeeb * @min_ba_txq_size: minimum number of slots required in a TX queue which 347*d9836fb4SBjoern A. Zeeb * based on hardware support (HE - 256, EHT - 1K). 348bfcc09ddSBjoern A. Zeeb * @num_rbds: number of receive buffer descriptors to use 349bfcc09ddSBjoern A. Zeeb * (only used for multi-queue capable devices) 350bfcc09ddSBjoern A. Zeeb * @mac_addr_csr_base: CSR base register for MAC address access, if not set 351bfcc09ddSBjoern A. Zeeb * assume 0x380 352bfcc09ddSBjoern A. Zeeb * 353bfcc09ddSBjoern A. Zeeb * We enable the driver to be backward compatible wrt. hardware features. 354bfcc09ddSBjoern A. Zeeb * API differences in uCode shouldn't be handled here but through TLVs 355bfcc09ddSBjoern A. Zeeb * and/or the uCode API version instead. 356bfcc09ddSBjoern A. Zeeb */ 357bfcc09ddSBjoern A. Zeeb struct iwl_cfg { 358bfcc09ddSBjoern A. Zeeb struct iwl_cfg_trans_params trans; 359bfcc09ddSBjoern A. Zeeb /* params specific to an individual device within a device family */ 360bfcc09ddSBjoern A. Zeeb const char *name; 361bfcc09ddSBjoern A. Zeeb const char *fw_name_pre; 362bfcc09ddSBjoern A. Zeeb /* params likely to change within a device family */ 363bfcc09ddSBjoern A. Zeeb const struct iwl_ht_params *ht_params; 364bfcc09ddSBjoern A. Zeeb const struct iwl_eeprom_params *eeprom_params; 365bfcc09ddSBjoern A. Zeeb const struct iwl_pwr_tx_backoff *pwr_tx_backoffs; 366bfcc09ddSBjoern A. Zeeb const char *default_nvm_file_C_step; 367bfcc09ddSBjoern A. Zeeb const struct iwl_tt_params *thermal_params; 368bfcc09ddSBjoern A. Zeeb enum iwl_led_mode led_mode; 369bfcc09ddSBjoern A. Zeeb enum iwl_nvm_type nvm_type; 370bfcc09ddSBjoern A. Zeeb u32 max_data_size; 371bfcc09ddSBjoern A. Zeeb u32 max_inst_size; 372bfcc09ddSBjoern A. Zeeb netdev_features_t features; 373bfcc09ddSBjoern A. Zeeb u32 dccm_offset; 374bfcc09ddSBjoern A. Zeeb u32 dccm_len; 375bfcc09ddSBjoern A. Zeeb u32 dccm2_offset; 376bfcc09ddSBjoern A. Zeeb u32 dccm2_len; 377bfcc09ddSBjoern A. Zeeb u32 smem_offset; 378bfcc09ddSBjoern A. Zeeb u32 smem_len; 379bfcc09ddSBjoern A. Zeeb u16 nvm_ver; 380bfcc09ddSBjoern A. Zeeb u16 nvm_calib_ver; 381bfcc09ddSBjoern A. Zeeb u32 rx_with_siso_diversity:1, 382bfcc09ddSBjoern A. Zeeb tx_with_siso_diversity:1, 383bfcc09ddSBjoern A. Zeeb bt_shared_single_ant:1, 384bfcc09ddSBjoern A. Zeeb internal_wimax_coex:1, 385bfcc09ddSBjoern A. Zeeb host_interrupt_operation_mode:1, 386bfcc09ddSBjoern A. Zeeb high_temp:1, 387bfcc09ddSBjoern A. Zeeb mac_addr_from_csr:10, 388bfcc09ddSBjoern A. Zeeb lp_xtal_workaround:1, 389bfcc09ddSBjoern A. Zeeb disable_dummy_notification:1, 390bfcc09ddSBjoern A. Zeeb apmg_not_supported:1, 391bfcc09ddSBjoern A. Zeeb vht_mu_mimo_supported:1, 392bfcc09ddSBjoern A. Zeeb cdb:1, 393bfcc09ddSBjoern A. Zeeb dbgc_supported:1, 394bfcc09ddSBjoern A. Zeeb uhb_supported:1; 395bfcc09ddSBjoern A. Zeeb u8 valid_tx_ant; 396bfcc09ddSBjoern A. Zeeb u8 valid_rx_ant; 397bfcc09ddSBjoern A. Zeeb u8 non_shared_ant; 398bfcc09ddSBjoern A. Zeeb u8 nvm_hw_section_num; 399bfcc09ddSBjoern A. Zeeb u8 max_tx_agg_size; 400bfcc09ddSBjoern A. Zeeb u8 ucode_api_max; 401bfcc09ddSBjoern A. Zeeb u8 ucode_api_min; 402bfcc09ddSBjoern A. Zeeb u16 num_rbds; 403bfcc09ddSBjoern A. Zeeb u32 min_umac_error_event_table; 404bfcc09ddSBjoern A. Zeeb u32 d3_debug_data_base_addr; 405bfcc09ddSBjoern A. Zeeb u32 d3_debug_data_length; 406bfcc09ddSBjoern A. Zeeb u32 min_txq_size; 407bfcc09ddSBjoern A. Zeeb u32 gp2_reg_addr; 408*d9836fb4SBjoern A. Zeeb u32 min_ba_txq_size; 409bfcc09ddSBjoern A. Zeeb const struct iwl_fw_mon_regs mon_dram_regs; 410bfcc09ddSBjoern A. Zeeb const struct iwl_fw_mon_regs mon_smem_regs; 411*d9836fb4SBjoern A. Zeeb const struct iwl_fw_mon_regs mon_dbgi_regs; 412bfcc09ddSBjoern A. Zeeb }; 413bfcc09ddSBjoern A. Zeeb 414bfcc09ddSBjoern A. Zeeb #define IWL_CFG_ANY (~0) 415bfcc09ddSBjoern A. Zeeb 416bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_PU 0x31 417bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_PNJ 0x32 418bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_TH 0x32 419bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_QU 0x33 420bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_QUZ 0x35 421bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_QNJ 0x36 422bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_SO 0x37 423bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_SNJ 0x42 424bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_SOF 0x43 425bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_MA 0x44 426bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_BZ 0x46 427bfcc09ddSBjoern A. Zeeb #define IWL_CFG_MAC_TYPE_GL 0x47 428bfcc09ddSBjoern A. Zeeb 429bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_TH 0x105 430bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_TH1 0x108 431bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_JF2 0x105 432bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_JF1 0x108 433bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_HR2 0x10A 434bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_HR1 0x10C 435bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_GF 0x10D 436bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_MR 0x110 437*d9836fb4SBjoern A. Zeeb #define IWL_CFG_RF_TYPE_MS 0x111 438bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_TYPE_FM 0x112 439bfcc09ddSBjoern A. Zeeb 440bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_TH 0x1 441bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_TH1 0x1 442bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_JF 0x3 443bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_JF1 0x6 444bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_JF1_DIV 0xA 445bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_HR 0x7 446bfcc09ddSBjoern A. Zeeb #define IWL_CFG_RF_ID_HR1 0x4 447bfcc09ddSBjoern A. Zeeb 448bfcc09ddSBjoern A. Zeeb #define IWL_CFG_NO_160 0x1 449bfcc09ddSBjoern A. Zeeb #define IWL_CFG_160 0x0 450bfcc09ddSBjoern A. Zeeb 451bfcc09ddSBjoern A. Zeeb #define IWL_CFG_CORES_BT 0x0 452bfcc09ddSBjoern A. Zeeb #define IWL_CFG_CORES_BT_GNSS 0x5 453bfcc09ddSBjoern A. Zeeb 454bfcc09ddSBjoern A. Zeeb #define IWL_CFG_NO_CDB 0x0 455bfcc09ddSBjoern A. Zeeb #define IWL_CFG_CDB 0x1 456bfcc09ddSBjoern A. Zeeb 457*d9836fb4SBjoern A. Zeeb #define IWL_CFG_NO_JACKET 0x0 458*d9836fb4SBjoern A. Zeeb #define IWL_CFG_IS_JACKET 0x1 459*d9836fb4SBjoern A. Zeeb 460bfcc09ddSBjoern A. Zeeb #define IWL_SUBDEVICE_RF_ID(subdevice) ((u16)((subdevice) & 0x00F0) >> 4) 461bfcc09ddSBjoern A. Zeeb #define IWL_SUBDEVICE_NO_160(subdevice) ((u16)((subdevice) & 0x0200) >> 9) 462bfcc09ddSBjoern A. Zeeb #define IWL_SUBDEVICE_CORES(subdevice) ((u16)((subdevice) & 0x1C00) >> 10) 463bfcc09ddSBjoern A. Zeeb 464bfcc09ddSBjoern A. Zeeb struct iwl_dev_info { 465bfcc09ddSBjoern A. Zeeb u16 device; 466bfcc09ddSBjoern A. Zeeb u16 subdevice; 467bfcc09ddSBjoern A. Zeeb u16 mac_type; 468bfcc09ddSBjoern A. Zeeb u16 rf_type; 469bfcc09ddSBjoern A. Zeeb u8 mac_step; 470bfcc09ddSBjoern A. Zeeb u8 rf_id; 471bfcc09ddSBjoern A. Zeeb u8 no_160; 472bfcc09ddSBjoern A. Zeeb u8 cores; 473bfcc09ddSBjoern A. Zeeb u8 cdb; 474*d9836fb4SBjoern A. Zeeb u8 jacket; 475bfcc09ddSBjoern A. Zeeb const struct iwl_cfg *cfg; 476bfcc09ddSBjoern A. Zeeb const char *name; 477bfcc09ddSBjoern A. Zeeb }; 478bfcc09ddSBjoern A. Zeeb 479bfcc09ddSBjoern A. Zeeb /* 480bfcc09ddSBjoern A. Zeeb * This list declares the config structures for all devices. 481bfcc09ddSBjoern A. Zeeb */ 482bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl9000_trans_cfg; 483bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl9560_trans_cfg; 484bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg; 485bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg; 486bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg; 487bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg; 488bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg; 489bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg; 490bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg; 491bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg; 492bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_so_trans_cfg; 493bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg; 494bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg; 495bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg; 496bfcc09ddSBjoern A. Zeeb extern const char iwl9162_name[]; 497bfcc09ddSBjoern A. Zeeb extern const char iwl9260_name[]; 498bfcc09ddSBjoern A. Zeeb extern const char iwl9260_1_name[]; 499bfcc09ddSBjoern A. Zeeb extern const char iwl9270_name[]; 500bfcc09ddSBjoern A. Zeeb extern const char iwl9461_name[]; 501bfcc09ddSBjoern A. Zeeb extern const char iwl9462_name[]; 502bfcc09ddSBjoern A. Zeeb extern const char iwl9560_name[]; 503bfcc09ddSBjoern A. Zeeb extern const char iwl9162_160_name[]; 504bfcc09ddSBjoern A. Zeeb extern const char iwl9260_160_name[]; 505bfcc09ddSBjoern A. Zeeb extern const char iwl9270_160_name[]; 506bfcc09ddSBjoern A. Zeeb extern const char iwl9461_160_name[]; 507bfcc09ddSBjoern A. Zeeb extern const char iwl9462_160_name[]; 508bfcc09ddSBjoern A. Zeeb extern const char iwl9560_160_name[]; 509bfcc09ddSBjoern A. Zeeb extern const char iwl9260_killer_1550_name[]; 510bfcc09ddSBjoern A. Zeeb extern const char iwl9560_killer_1550i_name[]; 511bfcc09ddSBjoern A. Zeeb extern const char iwl9560_killer_1550s_name[]; 512bfcc09ddSBjoern A. Zeeb extern const char iwl_ax200_name[]; 513bfcc09ddSBjoern A. Zeeb extern const char iwl_ax203_name[]; 514*d9836fb4SBjoern A. Zeeb extern const char iwl_ax204_name[]; 515bfcc09ddSBjoern A. Zeeb extern const char iwl_ax201_name[]; 516bfcc09ddSBjoern A. Zeeb extern const char iwl_ax101_name[]; 517bfcc09ddSBjoern A. Zeeb extern const char iwl_ax200_killer_1650w_name[]; 518bfcc09ddSBjoern A. Zeeb extern const char iwl_ax200_killer_1650x_name[]; 519bfcc09ddSBjoern A. Zeeb extern const char iwl_ax201_killer_1650s_name[]; 520bfcc09ddSBjoern A. Zeeb extern const char iwl_ax201_killer_1650i_name[]; 521bfcc09ddSBjoern A. Zeeb extern const char iwl_ax210_killer_1675w_name[]; 522bfcc09ddSBjoern A. Zeeb extern const char iwl_ax210_killer_1675x_name[]; 523bfcc09ddSBjoern A. Zeeb extern const char iwl9560_killer_1550i_160_name[]; 524bfcc09ddSBjoern A. Zeeb extern const char iwl9560_killer_1550s_160_name[]; 525bfcc09ddSBjoern A. Zeeb extern const char iwl_ax211_killer_1675s_name[]; 526bfcc09ddSBjoern A. Zeeb extern const char iwl_ax211_killer_1675i_name[]; 527bfcc09ddSBjoern A. Zeeb extern const char iwl_ax411_killer_1690s_name[]; 528bfcc09ddSBjoern A. Zeeb extern const char iwl_ax411_killer_1690i_name[]; 529bfcc09ddSBjoern A. Zeeb extern const char iwl_ax211_name[]; 530bfcc09ddSBjoern A. Zeeb extern const char iwl_ax221_name[]; 531bfcc09ddSBjoern A. Zeeb extern const char iwl_ax231_name[]; 532bfcc09ddSBjoern A. Zeeb extern const char iwl_ax411_name[]; 533bfcc09ddSBjoern A. Zeeb extern const char iwl_bz_name[]; 534bfcc09ddSBjoern A. Zeeb #if IS_ENABLED(CONFIG_IWLDVM) 535bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5300_agn_cfg; 536bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5100_agn_cfg; 537bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5350_agn_cfg; 538bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5100_bgn_cfg; 539bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5100_abg_cfg; 540bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5150_agn_cfg; 541bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl5150_abg_cfg; 542bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2agn_cfg; 543bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2abg_cfg; 544bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2bg_cfg; 545bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2agn_sff_cfg; 546bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2agn_d_cfg; 547bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2agn_mow1_cfg; 548bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6005_2agn_mow2_cfg; 549bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl1030_bgn_cfg; 550bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl1030_bg_cfg; 551bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6030_2agn_cfg; 552bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6030_2abg_cfg; 553bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6030_2bgn_cfg; 554bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6030_2bg_cfg; 555bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6000i_2agn_cfg; 556bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6000i_2abg_cfg; 557bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6000i_2bg_cfg; 558bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6000_3agn_cfg; 559bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6050_2agn_cfg; 560bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6050_2abg_cfg; 561bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6150_bgn_cfg; 562bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6150_bg_cfg; 563bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl1000_bgn_cfg; 564bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl1000_bg_cfg; 565bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl100_bgn_cfg; 566bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl100_bg_cfg; 567bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl130_bgn_cfg; 568bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl130_bg_cfg; 569bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl2000_2bgn_cfg; 570bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl2000_2bgn_d_cfg; 571bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl2030_2bgn_cfg; 572bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6035_2agn_cfg; 573bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl6035_2agn_sff_cfg; 574bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl105_bgn_cfg; 575bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl105_bgn_d_cfg; 576bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl135_bgn_cfg; 577bfcc09ddSBjoern A. Zeeb #endif /* CONFIG_IWLDVM */ 578bfcc09ddSBjoern A. Zeeb #if IS_ENABLED(CONFIG_IWLMVM) 579bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7260_2ac_cfg; 580bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp; 581bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7260_2n_cfg; 582bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7260_n_cfg; 583bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl3160_2ac_cfg; 584bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl3160_2n_cfg; 585bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl3160_n_cfg; 586bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl3165_2ac_cfg; 587bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl3168_2ac_cfg; 588bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265_2ac_cfg; 589bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265_2n_cfg; 590bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265_n_cfg; 591bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265d_2ac_cfg; 592bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265d_2n_cfg; 593bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl7265d_n_cfg; 594bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl8260_2n_cfg; 595bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl8260_2ac_cfg; 596bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl8265_2ac_cfg; 597bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl8275_2ac_cfg; 598bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl4165_2ac_cfg; 599bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9260_2ac_cfg; 600bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg; 601bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg; 602bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg; 603bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg; 604bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl9560_2ac_cfg_soc; 605bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_qu_b0_hr1_b0; 606bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_qu_c0_hr1_b0; 607bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_quz_a0_hr1_b0; 608bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_qu_b0_hr_b0; 609bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_qu_c0_hr_b0; 610bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax200_cfg_cc; 611bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax201_cfg_qu_hr; 612bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0; 613bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax201_cfg_quz_hr; 614bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr; 615bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr; 616bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0; 617bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0; 618bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0; 619bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0; 620bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650x_2ax_cfg; 621bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg killer1650w_2ax_cfg; 622bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg; 623bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0; 624bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0; 625bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long; 626bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0; 627bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0; 628bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long; 629bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0; 630bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0; 631bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_snj_hr_b0; 632bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0; 633bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0; 634bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0; 635bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0; 636bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0; 637*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_ms_a0; 638bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_ma_a0_fm_a0; 639bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0; 640*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_snj_a0_ms_a0; 641bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0; 642*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0; 643bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0; 644bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_a0_hr_b0; 645bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_a0_gf_a0; 646bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0; 647bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_a0_mr_a0; 648bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_a0_fm_a0; 649bfcc09ddSBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_gl_a0_fm_a0; 650*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bz_z0_gf_a0; 651*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0; 652*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0; 653*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0; 654*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0; 655*d9836fb4SBjoern A. Zeeb extern const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0; 656bfcc09ddSBjoern A. Zeeb #endif /* CONFIG_IWLMVM */ 657bfcc09ddSBjoern A. Zeeb 658bfcc09ddSBjoern A. Zeeb #endif /* __IWL_CONFIG_H__ */ 659