1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #if defined(__FreeBSD__) 9 #include <linux/delay.h> 10 #endif 11 #include "iwl-drv.h" 12 #include "runtime.h" 13 #include "dbg.h" 14 #include "debugfs.h" 15 #include "iwl-io.h" 16 #include "iwl-prph.h" 17 #include "iwl-csr.h" 18 19 /** 20 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 21 * 22 * @fwrt_ptr: pointer to the buffer coming from fwrt 23 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 24 * transport's data. 25 * @trans_len: length of the valid data in trans_ptr 26 * @fwrt_len: length of the valid data in fwrt_ptr 27 */ 28 struct iwl_fw_dump_ptrs { 29 struct iwl_trans_dump_data *trans_ptr; 30 void *fwrt_ptr; 31 u32 fwrt_len; 32 }; 33 34 #define RADIO_REG_MAX_READ 0x2ad 35 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 36 struct iwl_fw_error_dump_data **dump_data) 37 { 38 u8 *pos = (void *)(*dump_data)->data; 39 int i; 40 41 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 42 43 if (!iwl_trans_grab_nic_access(fwrt->trans)) 44 return; 45 46 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 47 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 48 49 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 50 u32 rd_cmd = RADIO_RSP_RD_CMD; 51 52 rd_cmd |= i << RADIO_RSP_ADDR_POS; 53 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 54 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 55 56 pos++; 57 } 58 59 *dump_data = iwl_fw_error_next_data(*dump_data); 60 61 iwl_trans_release_nic_access(fwrt->trans); 62 } 63 64 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 65 struct iwl_fw_error_dump_data **dump_data, 66 int size, u32 offset, int fifo_num) 67 { 68 struct iwl_fw_error_dump_fifo *fifo_hdr; 69 u32 *fifo_data; 70 u32 fifo_len; 71 int i; 72 73 fifo_hdr = (void *)(*dump_data)->data; 74 fifo_data = (void *)fifo_hdr->data; 75 fifo_len = size; 76 77 /* No need to try to read the data if the length is 0 */ 78 if (fifo_len == 0) 79 return; 80 81 /* Add a TLV for the RXF */ 82 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 83 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 84 85 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 86 fifo_hdr->available_bytes = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_D_SPACE + offset)); 89 fifo_hdr->wr_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_WR_PTR + offset)); 92 fifo_hdr->rd_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_RD_PTR + offset)); 95 fifo_hdr->fence_ptr = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_RD_FENCE_PTR + offset)); 98 fifo_hdr->fence_mode = 99 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 100 RXF_SET_FENCE_MODE + offset)); 101 102 /* Lock fence */ 103 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 104 /* Set fence pointer to the same place like WR pointer */ 105 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 106 /* Set fence offset */ 107 iwl_trans_write_prph(fwrt->trans, 108 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 109 110 /* Read FIFO */ 111 fifo_len /= sizeof(u32); /* Size in DWORDS */ 112 for (i = 0; i < fifo_len; i++) 113 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 114 RXF_FIFO_RD_FENCE_INC + 115 offset); 116 *dump_data = iwl_fw_error_next_data(*dump_data); 117 } 118 119 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the FIFO */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_FIFO_ITEM_CNT + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 TXF_LOCK_FENCE + offset)); 156 157 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 158 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 159 TXF_WR_PTR + offset); 160 161 /* Dummy-read to advance the read pointer to the head */ 162 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 163 164 /* Read FIFO */ 165 for (i = 0; i < fifo_len / sizeof(u32); i++) 166 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 167 TXF_READ_MODIFY_DATA + 168 offset); 169 170 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 171 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 172 fifo_data, fifo_len); 173 174 *dump_data = iwl_fw_error_next_data(*dump_data); 175 } 176 177 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 178 struct iwl_fw_error_dump_data **dump_data) 179 { 180 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 181 182 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 183 184 if (!iwl_trans_grab_nic_access(fwrt->trans)) 185 return; 186 187 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 188 /* Pull RXF1 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, 190 cfg->lmac[0].rxfifo1_size, 0, 0); 191 /* Pull RXF2 */ 192 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 193 RXF_DIFF_FROM_PREV + 194 fwrt->trans->trans_cfg->umac_prph_offset, 1); 195 /* Pull LMAC2 RXF1 */ 196 if (fwrt->smem_cfg.num_lmacs > 1) 197 iwl_fwrt_dump_rxf(fwrt, dump_data, 198 cfg->lmac[1].rxfifo1_size, 199 LMAC2_PRPH_OFFSET, 2); 200 } 201 202 iwl_trans_release_nic_access(fwrt->trans); 203 } 204 205 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 206 struct iwl_fw_error_dump_data **dump_data) 207 { 208 struct iwl_fw_error_dump_fifo *fifo_hdr; 209 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 210 u32 *fifo_data; 211 u32 fifo_len; 212 int i, j; 213 214 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 215 216 if (!iwl_trans_grab_nic_access(fwrt->trans)) 217 return; 218 219 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 220 /* Pull TXF data from LMAC1 */ 221 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 222 /* Mark the number of TXF we're pulling now */ 223 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 224 iwl_fwrt_dump_txf(fwrt, dump_data, 225 cfg->lmac[0].txfifo_size[i], 0, i); 226 } 227 228 /* Pull TXF data from LMAC2 */ 229 if (fwrt->smem_cfg.num_lmacs > 1) { 230 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 231 i++) { 232 /* Mark the number of TXF we're pulling now */ 233 iwl_trans_write_prph(fwrt->trans, 234 TXF_LARC_NUM + 235 LMAC2_PRPH_OFFSET, i); 236 iwl_fwrt_dump_txf(fwrt, dump_data, 237 cfg->lmac[1].txfifo_size[i], 238 LMAC2_PRPH_OFFSET, 239 i + cfg->num_txfifo_entries); 240 } 241 } 242 } 243 244 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 245 fw_has_capa(&fwrt->fw->ucode_capa, 246 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 247 /* Pull UMAC internal TXF data from all TXFs */ 248 for (i = 0; 249 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 250 i++) { 251 fifo_hdr = (void *)(*dump_data)->data; 252 fifo_data = (void *)fifo_hdr->data; 253 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 254 255 /* No need to try to read the data if the length is 0 */ 256 if (fifo_len == 0) 257 continue; 258 259 /* Add a TLV for the internal FIFOs */ 260 (*dump_data)->type = 261 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 262 (*dump_data)->len = 263 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 264 265 fifo_hdr->fifo_num = cpu_to_le32(i); 266 267 /* Mark the number of TXF we're pulling now */ 268 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 269 fwrt->smem_cfg.num_txfifo_entries); 270 271 fifo_hdr->available_bytes = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_FIFO_ITEM_CNT)); 274 fifo_hdr->wr_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_WR_PTR)); 277 fifo_hdr->rd_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_RD_PTR)); 280 fifo_hdr->fence_ptr = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_FENCE_PTR)); 283 fifo_hdr->fence_mode = 284 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 285 TXF_CPU2_LOCK_FENCE)); 286 287 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 288 iwl_trans_write_prph(fwrt->trans, 289 TXF_CPU2_READ_MODIFY_ADDR, 290 TXF_CPU2_WR_PTR); 291 292 /* Dummy-read to advance the read pointer to head */ 293 iwl_trans_read_prph(fwrt->trans, 294 TXF_CPU2_READ_MODIFY_DATA); 295 296 /* Read FIFO */ 297 fifo_len /= sizeof(u32); /* Size in DWORDS */ 298 for (j = 0; j < fifo_len; j++) 299 fifo_data[j] = 300 iwl_trans_read_prph(fwrt->trans, 301 TXF_CPU2_READ_MODIFY_DATA); 302 *dump_data = iwl_fw_error_next_data(*dump_data); 303 } 304 } 305 306 iwl_trans_release_nic_access(fwrt->trans); 307 } 308 309 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 310 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 311 312 struct iwl_prph_range { 313 u32 start, end; 314 }; 315 316 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 317 { .start = 0x00a00000, .end = 0x00a00000 }, 318 { .start = 0x00a0000c, .end = 0x00a00024 }, 319 { .start = 0x00a0002c, .end = 0x00a0003c }, 320 { .start = 0x00a00410, .end = 0x00a00418 }, 321 { .start = 0x00a00420, .end = 0x00a00420 }, 322 { .start = 0x00a00428, .end = 0x00a00428 }, 323 { .start = 0x00a00430, .end = 0x00a0043c }, 324 { .start = 0x00a00444, .end = 0x00a00444 }, 325 { .start = 0x00a004c0, .end = 0x00a004cc }, 326 { .start = 0x00a004d8, .end = 0x00a004d8 }, 327 { .start = 0x00a004e0, .end = 0x00a004f0 }, 328 { .start = 0x00a00840, .end = 0x00a00840 }, 329 { .start = 0x00a00850, .end = 0x00a00858 }, 330 { .start = 0x00a01004, .end = 0x00a01008 }, 331 { .start = 0x00a01010, .end = 0x00a01010 }, 332 { .start = 0x00a01018, .end = 0x00a01018 }, 333 { .start = 0x00a01024, .end = 0x00a01024 }, 334 { .start = 0x00a0102c, .end = 0x00a01034 }, 335 { .start = 0x00a0103c, .end = 0x00a01040 }, 336 { .start = 0x00a01048, .end = 0x00a01094 }, 337 { .start = 0x00a01c00, .end = 0x00a01c20 }, 338 { .start = 0x00a01c58, .end = 0x00a01c58 }, 339 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 340 { .start = 0x00a01c28, .end = 0x00a01c54 }, 341 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 342 { .start = 0x00a01c60, .end = 0x00a01cdc }, 343 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 344 { .start = 0x00a01d18, .end = 0x00a01d20 }, 345 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 346 { .start = 0x00a01d40, .end = 0x00a01d5c }, 347 { .start = 0x00a01d80, .end = 0x00a01d80 }, 348 { .start = 0x00a01d98, .end = 0x00a01d9c }, 349 { .start = 0x00a01da8, .end = 0x00a01da8 }, 350 { .start = 0x00a01db8, .end = 0x00a01df4 }, 351 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 352 { .start = 0x00a01e00, .end = 0x00a01e2c }, 353 { .start = 0x00a01e40, .end = 0x00a01e60 }, 354 { .start = 0x00a01e68, .end = 0x00a01e6c }, 355 { .start = 0x00a01e74, .end = 0x00a01e74 }, 356 { .start = 0x00a01e84, .end = 0x00a01e90 }, 357 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 358 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 359 { .start = 0x00a01f00, .end = 0x00a01f1c }, 360 { .start = 0x00a01f44, .end = 0x00a01ffc }, 361 { .start = 0x00a02000, .end = 0x00a02048 }, 362 { .start = 0x00a02068, .end = 0x00a020f0 }, 363 { .start = 0x00a02100, .end = 0x00a02118 }, 364 { .start = 0x00a02140, .end = 0x00a0214c }, 365 { .start = 0x00a02168, .end = 0x00a0218c }, 366 { .start = 0x00a021c0, .end = 0x00a021c0 }, 367 { .start = 0x00a02400, .end = 0x00a02410 }, 368 { .start = 0x00a02418, .end = 0x00a02420 }, 369 { .start = 0x00a02428, .end = 0x00a0242c }, 370 { .start = 0x00a02434, .end = 0x00a02434 }, 371 { .start = 0x00a02440, .end = 0x00a02460 }, 372 { .start = 0x00a02468, .end = 0x00a024b0 }, 373 { .start = 0x00a024c8, .end = 0x00a024cc }, 374 { .start = 0x00a02500, .end = 0x00a02504 }, 375 { .start = 0x00a0250c, .end = 0x00a02510 }, 376 { .start = 0x00a02540, .end = 0x00a02554 }, 377 { .start = 0x00a02580, .end = 0x00a025f4 }, 378 { .start = 0x00a02600, .end = 0x00a0260c }, 379 { .start = 0x00a02648, .end = 0x00a02650 }, 380 { .start = 0x00a02680, .end = 0x00a02680 }, 381 { .start = 0x00a026c0, .end = 0x00a026d0 }, 382 { .start = 0x00a02700, .end = 0x00a0270c }, 383 { .start = 0x00a02804, .end = 0x00a02804 }, 384 { .start = 0x00a02818, .end = 0x00a0281c }, 385 { .start = 0x00a02c00, .end = 0x00a02db4 }, 386 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 387 { .start = 0x00a03000, .end = 0x00a03014 }, 388 { .start = 0x00a0301c, .end = 0x00a0302c }, 389 { .start = 0x00a03034, .end = 0x00a03038 }, 390 { .start = 0x00a03040, .end = 0x00a03048 }, 391 { .start = 0x00a03060, .end = 0x00a03068 }, 392 { .start = 0x00a03070, .end = 0x00a03074 }, 393 { .start = 0x00a0307c, .end = 0x00a0307c }, 394 { .start = 0x00a03080, .end = 0x00a03084 }, 395 { .start = 0x00a0308c, .end = 0x00a03090 }, 396 { .start = 0x00a03098, .end = 0x00a03098 }, 397 { .start = 0x00a030a0, .end = 0x00a030a0 }, 398 { .start = 0x00a030a8, .end = 0x00a030b4 }, 399 { .start = 0x00a030bc, .end = 0x00a030bc }, 400 { .start = 0x00a030c0, .end = 0x00a0312c }, 401 { .start = 0x00a03c00, .end = 0x00a03c5c }, 402 { .start = 0x00a04400, .end = 0x00a04454 }, 403 { .start = 0x00a04460, .end = 0x00a04474 }, 404 { .start = 0x00a044c0, .end = 0x00a044ec }, 405 { .start = 0x00a04500, .end = 0x00a04504 }, 406 { .start = 0x00a04510, .end = 0x00a04538 }, 407 { .start = 0x00a04540, .end = 0x00a04548 }, 408 { .start = 0x00a04560, .end = 0x00a0457c }, 409 { .start = 0x00a04590, .end = 0x00a04598 }, 410 { .start = 0x00a045c0, .end = 0x00a045f4 }, 411 }; 412 413 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 414 { .start = 0x00a05c00, .end = 0x00a05c18 }, 415 { .start = 0x00a05400, .end = 0x00a056e8 }, 416 { .start = 0x00a08000, .end = 0x00a098bc }, 417 { .start = 0x00a02400, .end = 0x00a02758 }, 418 { .start = 0x00a04764, .end = 0x00a0476c }, 419 { .start = 0x00a04770, .end = 0x00a04774 }, 420 { .start = 0x00a04620, .end = 0x00a04624 }, 421 }; 422 423 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 424 { .start = 0x00a00000, .end = 0x00a00000 }, 425 { .start = 0x00a0000c, .end = 0x00a00024 }, 426 { .start = 0x00a0002c, .end = 0x00a00034 }, 427 { .start = 0x00a0003c, .end = 0x00a0003c }, 428 { .start = 0x00a00410, .end = 0x00a00418 }, 429 { .start = 0x00a00420, .end = 0x00a00420 }, 430 { .start = 0x00a00428, .end = 0x00a00428 }, 431 { .start = 0x00a00430, .end = 0x00a0043c }, 432 { .start = 0x00a00444, .end = 0x00a00444 }, 433 { .start = 0x00a00840, .end = 0x00a00840 }, 434 { .start = 0x00a00850, .end = 0x00a00858 }, 435 { .start = 0x00a01004, .end = 0x00a01008 }, 436 { .start = 0x00a01010, .end = 0x00a01010 }, 437 { .start = 0x00a01018, .end = 0x00a01018 }, 438 { .start = 0x00a01024, .end = 0x00a01024 }, 439 { .start = 0x00a0102c, .end = 0x00a01034 }, 440 { .start = 0x00a0103c, .end = 0x00a01040 }, 441 { .start = 0x00a01048, .end = 0x00a01050 }, 442 { .start = 0x00a01058, .end = 0x00a01058 }, 443 { .start = 0x00a01060, .end = 0x00a01070 }, 444 { .start = 0x00a0108c, .end = 0x00a0108c }, 445 { .start = 0x00a01c20, .end = 0x00a01c28 }, 446 { .start = 0x00a01d10, .end = 0x00a01d10 }, 447 { .start = 0x00a01e28, .end = 0x00a01e2c }, 448 { .start = 0x00a01e60, .end = 0x00a01e60 }, 449 { .start = 0x00a01e80, .end = 0x00a01e80 }, 450 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 451 { .start = 0x00a02000, .end = 0x00a0201c }, 452 { .start = 0x00a02024, .end = 0x00a02024 }, 453 { .start = 0x00a02040, .end = 0x00a02048 }, 454 { .start = 0x00a020c0, .end = 0x00a020e0 }, 455 { .start = 0x00a02400, .end = 0x00a02404 }, 456 { .start = 0x00a0240c, .end = 0x00a02414 }, 457 { .start = 0x00a0241c, .end = 0x00a0243c }, 458 { .start = 0x00a02448, .end = 0x00a024bc }, 459 { .start = 0x00a024c4, .end = 0x00a024cc }, 460 { .start = 0x00a02508, .end = 0x00a02508 }, 461 { .start = 0x00a02510, .end = 0x00a02514 }, 462 { .start = 0x00a0251c, .end = 0x00a0251c }, 463 { .start = 0x00a0252c, .end = 0x00a0255c }, 464 { .start = 0x00a02564, .end = 0x00a025a0 }, 465 { .start = 0x00a025a8, .end = 0x00a025b4 }, 466 { .start = 0x00a025c0, .end = 0x00a025c0 }, 467 { .start = 0x00a025e8, .end = 0x00a025f4 }, 468 { .start = 0x00a02c08, .end = 0x00a02c18 }, 469 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 470 { .start = 0x00a02c68, .end = 0x00a02c78 }, 471 { .start = 0x00a03000, .end = 0x00a03000 }, 472 { .start = 0x00a03010, .end = 0x00a03014 }, 473 { .start = 0x00a0301c, .end = 0x00a0302c }, 474 { .start = 0x00a03034, .end = 0x00a03038 }, 475 { .start = 0x00a03040, .end = 0x00a03044 }, 476 { .start = 0x00a03060, .end = 0x00a03068 }, 477 { .start = 0x00a03070, .end = 0x00a03070 }, 478 { .start = 0x00a0307c, .end = 0x00a03084 }, 479 { .start = 0x00a0308c, .end = 0x00a03090 }, 480 { .start = 0x00a03098, .end = 0x00a03098 }, 481 { .start = 0x00a030a0, .end = 0x00a030a0 }, 482 { .start = 0x00a030a8, .end = 0x00a030b4 }, 483 { .start = 0x00a030bc, .end = 0x00a030c0 }, 484 { .start = 0x00a030c8, .end = 0x00a030f4 }, 485 { .start = 0x00a03100, .end = 0x00a0312c }, 486 { .start = 0x00a03c00, .end = 0x00a03c5c }, 487 { .start = 0x00a04400, .end = 0x00a04454 }, 488 { .start = 0x00a04460, .end = 0x00a04474 }, 489 { .start = 0x00a044c0, .end = 0x00a044ec }, 490 { .start = 0x00a04500, .end = 0x00a04504 }, 491 { .start = 0x00a04510, .end = 0x00a04538 }, 492 { .start = 0x00a04540, .end = 0x00a04548 }, 493 { .start = 0x00a04560, .end = 0x00a04560 }, 494 { .start = 0x00a04570, .end = 0x00a0457c }, 495 { .start = 0x00a04590, .end = 0x00a04590 }, 496 { .start = 0x00a04598, .end = 0x00a04598 }, 497 { .start = 0x00a045c0, .end = 0x00a045f4 }, 498 { .start = 0x00a05c18, .end = 0x00a05c1c }, 499 { .start = 0x00a0c000, .end = 0x00a0c018 }, 500 { .start = 0x00a0c020, .end = 0x00a0c028 }, 501 { .start = 0x00a0c038, .end = 0x00a0c094 }, 502 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 503 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 504 { .start = 0x00a0c150, .end = 0x00a0c174 }, 505 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 506 { .start = 0x00a0c190, .end = 0x00a0c198 }, 507 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 508 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 509 }; 510 511 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 512 { .start = 0x00d03c00, .end = 0x00d03c64 }, 513 { .start = 0x00d05c18, .end = 0x00d05c1c }, 514 { .start = 0x00d0c000, .end = 0x00d0c174 }, 515 }; 516 517 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 518 u32 len_bytes, __le32 *data) 519 { 520 u32 i; 521 522 for (i = 0; i < len_bytes; i += 4) 523 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 524 } 525 526 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 527 const struct iwl_prph_range *iwl_prph_dump_addr, 528 u32 range_len, void *ptr) 529 { 530 struct iwl_fw_error_dump_prph *prph; 531 struct iwl_trans *trans = fwrt->trans; 532 struct iwl_fw_error_dump_data **data = 533 (struct iwl_fw_error_dump_data **)ptr; 534 u32 i; 535 536 if (!data) 537 return; 538 539 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 540 541 if (!iwl_trans_grab_nic_access(trans)) 542 return; 543 544 for (i = 0; i < range_len; i++) { 545 /* The range includes both boundaries */ 546 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 547 iwl_prph_dump_addr[i].start + 4; 548 549 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 550 (*data)->len = cpu_to_le32(sizeof(*prph) + 551 num_bytes_in_chunk); 552 prph = (void *)(*data)->data; 553 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 554 555 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 556 /* our range is inclusive, hence + 4 */ 557 iwl_prph_dump_addr[i].end - 558 iwl_prph_dump_addr[i].start + 4, 559 (void *)prph->data); 560 561 *data = iwl_fw_error_next_data(*data); 562 } 563 564 iwl_trans_release_nic_access(trans); 565 } 566 567 /* 568 * alloc_sgtable - allocates scallerlist table in the given size, 569 * fills it with pages and returns it 570 * @size: the size (in bytes) of the table 571 */ 572 static struct scatterlist *alloc_sgtable(int size) 573 { 574 int alloc_size, nents, i; 575 struct page *new_page; 576 struct scatterlist *iter; 577 struct scatterlist *table; 578 579 nents = DIV_ROUND_UP(size, PAGE_SIZE); 580 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 581 if (!table) 582 return NULL; 583 sg_init_table(table, nents); 584 iter = table; 585 for_each_sg(table, iter, sg_nents(table), i) { 586 new_page = alloc_page(GFP_KERNEL); 587 if (!new_page) { 588 /* release all previous allocated pages in the table */ 589 iter = table; 590 for_each_sg(table, iter, sg_nents(table), i) { 591 new_page = sg_page(iter); 592 if (new_page) 593 __free_page(new_page); 594 } 595 kfree(table); 596 return NULL; 597 } 598 alloc_size = min_t(int, size, PAGE_SIZE); 599 size -= PAGE_SIZE; 600 sg_set_page(iter, new_page, alloc_size, 0); 601 } 602 return table; 603 } 604 605 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 606 const struct iwl_prph_range *iwl_prph_dump_addr, 607 u32 range_len, void *ptr) 608 { 609 u32 *prph_len = (u32 *)ptr; 610 int i, num_bytes_in_chunk; 611 612 if (!prph_len) 613 return; 614 615 for (i = 0; i < range_len; i++) { 616 /* The range includes both boundaries */ 617 num_bytes_in_chunk = 618 iwl_prph_dump_addr[i].end - 619 iwl_prph_dump_addr[i].start + 4; 620 621 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 622 sizeof(struct iwl_fw_error_dump_prph) + 623 num_bytes_in_chunk; 624 } 625 } 626 627 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 628 void (*handler)(struct iwl_fw_runtime *, 629 const struct iwl_prph_range *, 630 u32, void *)) 631 { 632 u32 range_len; 633 634 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 636 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 637 } else if (fwrt->trans->trans_cfg->device_family >= 638 IWL_DEVICE_FAMILY_22000) { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 640 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 641 } else { 642 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 643 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 644 645 if (fwrt->trans->trans_cfg->mq_rx_supported) { 646 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 647 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 648 } 649 } 650 } 651 652 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 653 struct iwl_fw_error_dump_data **dump_data, 654 u32 len, u32 ofs, u32 type) 655 { 656 struct iwl_fw_error_dump_mem *dump_mem; 657 658 if (!len) 659 return; 660 661 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 662 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 663 dump_mem = (void *)(*dump_data)->data; 664 dump_mem->type = cpu_to_le32(type); 665 dump_mem->offset = cpu_to_le32(ofs); 666 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 667 *dump_data = iwl_fw_error_next_data(*dump_data); 668 669 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 670 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 671 dump_mem->data, len); 672 673 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 674 } 675 676 #define ADD_LEN(len, item_len, const_len) \ 677 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 678 while (0) 679 680 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 681 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 682 { 683 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 684 sizeof(struct iwl_fw_error_dump_fifo); 685 u32 fifo_len = 0; 686 int i; 687 688 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 689 return 0; 690 691 /* Count RXF2 size */ 692 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 693 694 /* Count RXF1 sizes */ 695 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 696 mem_cfg->num_lmacs = MAX_NUM_LMAC; 697 698 for (i = 0; i < mem_cfg->num_lmacs; i++) 699 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 700 701 return fifo_len; 702 } 703 704 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 705 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 706 { 707 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 708 sizeof(struct iwl_fw_error_dump_fifo); 709 u32 fifo_len = 0; 710 int i; 711 712 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 713 goto dump_internal_txf; 714 715 /* Count TXF sizes */ 716 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 717 mem_cfg->num_lmacs = MAX_NUM_LMAC; 718 719 for (i = 0; i < mem_cfg->num_lmacs; i++) { 720 int j; 721 722 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 723 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 724 hdr_len); 725 } 726 727 dump_internal_txf: 728 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 729 fw_has_capa(&fwrt->fw->ucode_capa, 730 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 731 goto out; 732 733 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 734 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 735 736 out: 737 return fifo_len; 738 } 739 740 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 741 struct iwl_fw_error_dump_data **data) 742 { 743 int i; 744 745 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 746 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 747 struct iwl_fw_error_dump_paging *paging; 748 struct page *pages = 749 fwrt->fw_paging_db[i].fw_paging_block; 750 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 751 752 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 753 (*data)->len = cpu_to_le32(sizeof(*paging) + 754 PAGING_BLOCK_SIZE); 755 paging = (void *)(*data)->data; 756 paging->index = cpu_to_le32(i); 757 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 758 PAGING_BLOCK_SIZE, 759 DMA_BIDIRECTIONAL); 760 memcpy(paging->data, page_address(pages), 761 PAGING_BLOCK_SIZE); 762 dma_sync_single_for_device(fwrt->trans->dev, addr, 763 PAGING_BLOCK_SIZE, 764 DMA_BIDIRECTIONAL); 765 (*data) = iwl_fw_error_next_data(*data); 766 767 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 768 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 769 fwrt->fw_paging_db[i].fw_offs, 770 paging->data, 771 PAGING_BLOCK_SIZE); 772 } 773 } 774 775 static struct iwl_fw_error_dump_file * 776 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 777 struct iwl_fw_dump_ptrs *fw_error_dump, 778 struct iwl_fwrt_dump_data *data) 779 { 780 struct iwl_fw_error_dump_file *dump_file; 781 struct iwl_fw_error_dump_data *dump_data; 782 struct iwl_fw_error_dump_info *dump_info; 783 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 784 struct iwl_fw_error_dump_trigger_desc *dump_trig; 785 u32 sram_len, sram_ofs; 786 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 787 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 788 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 789 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 790 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 791 0 : fwrt->trans->cfg->dccm2_len; 792 int i; 793 794 /* SRAM - include stack CCM if driver knows the values for it */ 795 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 796 const struct fw_img *img; 797 798 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 799 return NULL; 800 img = &fwrt->fw->img[fwrt->cur_fw_img]; 801 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 802 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 803 } else { 804 sram_ofs = fwrt->trans->cfg->dccm_offset; 805 sram_len = fwrt->trans->cfg->dccm_len; 806 } 807 808 /* reading RXF/TXF sizes */ 809 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 810 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 811 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 812 813 /* Make room for PRPH registers */ 814 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 815 iwl_fw_prph_handler(fwrt, &prph_len, 816 iwl_fw_get_prph_len); 817 818 if (fwrt->trans->trans_cfg->device_family == 819 IWL_DEVICE_FAMILY_7000 && 820 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 821 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 822 } 823 824 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 825 826 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 827 file_len += sizeof(*dump_data) + sizeof(*dump_info); 828 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 829 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 830 831 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 832 size_t hdr_len = sizeof(*dump_data) + 833 sizeof(struct iwl_fw_error_dump_mem); 834 835 /* Dump SRAM only if no mem_tlvs */ 836 if (!fwrt->fw->dbg.n_mem_tlv) 837 ADD_LEN(file_len, sram_len, hdr_len); 838 839 /* Make room for all mem types that exist */ 840 ADD_LEN(file_len, smem_len, hdr_len); 841 ADD_LEN(file_len, sram2_len, hdr_len); 842 843 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 844 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 845 } 846 847 /* Make room for fw's virtual image pages, if it exists */ 848 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 849 file_len += fwrt->num_of_paging_blk * 850 (sizeof(*dump_data) + 851 sizeof(struct iwl_fw_error_dump_paging) + 852 PAGING_BLOCK_SIZE); 853 854 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 855 file_len += sizeof(*dump_data) + 856 fwrt->trans->cfg->d3_debug_data_length * 2; 857 } 858 859 /* If we only want a monitor dump, reset the file length */ 860 if (data->monitor_only) { 861 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 862 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 863 } 864 865 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 866 data->desc) 867 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 868 data->desc->len; 869 870 dump_file = vzalloc(file_len); 871 if (!dump_file) 872 return NULL; 873 874 fw_error_dump->fwrt_ptr = dump_file; 875 876 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 877 dump_data = (void *)dump_file->data; 878 879 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 880 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 881 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 882 dump_info = (void *)dump_data->data; 883 dump_info->hw_type = 884 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 885 dump_info->hw_step = 886 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 887 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 888 sizeof(dump_info->fw_human_readable)); 889 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 890 sizeof(dump_info->dev_human_readable) - 1); 891 #if defined(__linux__) 892 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 893 sizeof(dump_info->bus_human_readable) - 1); 894 #elif defined(__FreeBSD__) /* XXX TODO */ 895 strncpy(dump_info->bus_human_readable, "<bus>", 896 sizeof(dump_info->bus_human_readable) - 1); 897 #endif 898 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 899 dump_info->lmac_err_id[0] = 900 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 901 if (fwrt->smem_cfg.num_lmacs > 1) 902 dump_info->lmac_err_id[1] = 903 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 904 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 905 906 dump_data = iwl_fw_error_next_data(dump_data); 907 } 908 909 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 910 /* Dump shared memory configuration */ 911 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 912 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 913 dump_smem_cfg = (void *)dump_data->data; 914 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 915 dump_smem_cfg->num_txfifo_entries = 916 cpu_to_le32(mem_cfg->num_txfifo_entries); 917 for (i = 0; i < MAX_NUM_LMAC; i++) { 918 int j; 919 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 920 921 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 922 dump_smem_cfg->lmac[i].txfifo_size[j] = 923 cpu_to_le32(txf_size[j]); 924 dump_smem_cfg->lmac[i].rxfifo1_size = 925 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 926 } 927 dump_smem_cfg->rxfifo2_size = 928 cpu_to_le32(mem_cfg->rxfifo2_size); 929 dump_smem_cfg->internal_txfifo_addr = 930 cpu_to_le32(mem_cfg->internal_txfifo_addr); 931 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 932 dump_smem_cfg->internal_txfifo_size[i] = 933 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 934 } 935 936 dump_data = iwl_fw_error_next_data(dump_data); 937 } 938 939 /* We only dump the FIFOs if the FW is in error state */ 940 if (fifo_len) { 941 iwl_fw_dump_rxf(fwrt, &dump_data); 942 iwl_fw_dump_txf(fwrt, &dump_data); 943 } 944 945 if (radio_len) 946 iwl_read_radio_regs(fwrt, &dump_data); 947 948 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 949 data->desc) { 950 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 951 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 952 data->desc->len); 953 dump_trig = (void *)dump_data->data; 954 memcpy(dump_trig, &data->desc->trig_desc, 955 sizeof(*dump_trig) + data->desc->len); 956 957 dump_data = iwl_fw_error_next_data(dump_data); 958 } 959 960 /* In case we only want monitor dump, skip to dump trasport data */ 961 if (data->monitor_only) 962 goto out; 963 964 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 965 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 966 fwrt->fw->dbg.mem_tlv; 967 968 if (!fwrt->fw->dbg.n_mem_tlv) 969 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 970 IWL_FW_ERROR_DUMP_MEM_SRAM); 971 972 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 973 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 974 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 975 976 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 977 le32_to_cpu(fw_dbg_mem[i].data_type)); 978 } 979 980 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 981 fwrt->trans->cfg->smem_offset, 982 IWL_FW_ERROR_DUMP_MEM_SMEM); 983 984 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 985 fwrt->trans->cfg->dccm2_offset, 986 IWL_FW_ERROR_DUMP_MEM_SRAM); 987 } 988 989 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 990 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 991 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 992 993 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 994 dump_data->len = cpu_to_le32(data_size * 2); 995 996 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 997 998 kfree(fwrt->dump.d3_debug_data); 999 fwrt->dump.d3_debug_data = NULL; 1000 1001 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1002 dump_data->data + data_size, 1003 data_size); 1004 1005 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 1006 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 1007 dump_data->data + data_size, 1008 data_size); 1009 1010 dump_data = iwl_fw_error_next_data(dump_data); 1011 } 1012 1013 /* Dump fw's virtual image */ 1014 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1015 iwl_dump_paging(fwrt, &dump_data); 1016 1017 if (prph_len) 1018 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1019 1020 out: 1021 dump_file->file_len = cpu_to_le32(file_len); 1022 return dump_file; 1023 } 1024 1025 /** 1026 * struct iwl_dump_ini_region_data - region data 1027 * @reg_tlv: region TLV 1028 * @dump_data: dump data 1029 */ 1030 struct iwl_dump_ini_region_data { 1031 struct iwl_ucode_tlv *reg_tlv; 1032 struct iwl_fwrt_dump_data *dump_data; 1033 }; 1034 1035 static int 1036 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1037 struct iwl_dump_ini_region_data *reg_data, 1038 void *range_ptr, int idx) 1039 { 1040 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1041 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1042 __le32 *val = range->data; 1043 u32 prph_val; 1044 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1045 le32_to_cpu(reg->dev_addr.offset); 1046 int i; 1047 1048 range->internal_base_addr = cpu_to_le32(addr); 1049 range->range_data_size = reg->dev_addr.size; 1050 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1051 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1052 if (prph_val == 0x5a5a5a5a) 1053 return -EBUSY; 1054 *val++ = cpu_to_le32(prph_val); 1055 } 1056 1057 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1058 } 1059 1060 static int 1061 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1062 struct iwl_dump_ini_region_data *reg_data, 1063 void *range_ptr, int idx) 1064 { 1065 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1066 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1067 __le32 *val = range->data; 1068 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1069 u32 indirect_rd_addr = WMAL_MRSPF_1; 1070 u32 prph_val; 1071 u32 addr = le32_to_cpu(reg->addrs[idx]); 1072 u32 dphy_state; 1073 u32 dphy_addr; 1074 int i; 1075 1076 range->internal_base_addr = cpu_to_le32(addr); 1077 range->range_data_size = reg->dev_addr.size; 1078 1079 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1080 indirect_wr_addr = WMAL_INDRCT_CMD1; 1081 1082 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1083 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1084 1085 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1086 return -EBUSY; 1087 1088 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1089 WFPM_LMAC1_PS_CTL_RW; 1090 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1091 1092 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1093 if (dphy_state == HBUS_TIMEOUT || 1094 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1095 WFPM_PHYRF_STATE_ON) { 1096 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1097 continue; 1098 } 1099 1100 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1101 WMAL_INDRCT_CMD(addr + i)); 1102 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1103 indirect_rd_addr); 1104 *val++ = cpu_to_le32(prph_val); 1105 } 1106 1107 iwl_trans_release_nic_access(fwrt->trans); 1108 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1109 } 1110 1111 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1112 struct iwl_dump_ini_region_data *reg_data, 1113 void *range_ptr, int idx) 1114 { 1115 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1116 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1117 __le32 *val = range->data; 1118 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1119 le32_to_cpu(reg->dev_addr.offset); 1120 int i; 1121 1122 range->internal_base_addr = cpu_to_le32(addr); 1123 range->range_data_size = reg->dev_addr.size; 1124 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1125 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1126 1127 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1128 } 1129 1130 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1131 struct iwl_dump_ini_region_data *reg_data, 1132 void *range_ptr, int idx) 1133 { 1134 struct iwl_trans *trans = fwrt->trans; 1135 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1136 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1137 __le32 *val = range->data; 1138 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1139 le32_to_cpu(reg->dev_addr.offset); 1140 int i; 1141 1142 /* we shouldn't get here if the trans doesn't have read_config32 */ 1143 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1144 return -EOPNOTSUPP; 1145 1146 range->internal_base_addr = cpu_to_le32(addr); 1147 range->range_data_size = reg->dev_addr.size; 1148 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1149 int ret; 1150 u32 tmp; 1151 1152 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1153 if (ret < 0) 1154 return ret; 1155 1156 *val++ = cpu_to_le32(tmp); 1157 } 1158 1159 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1160 } 1161 1162 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1163 struct iwl_dump_ini_region_data *reg_data, 1164 void *range_ptr, int idx) 1165 { 1166 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1167 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1168 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1169 le32_to_cpu(reg->dev_addr.offset); 1170 1171 range->internal_base_addr = cpu_to_le32(addr); 1172 range->range_data_size = reg->dev_addr.size; 1173 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1174 le32_to_cpu(reg->dev_addr.size)); 1175 1176 if ((le32_to_cpu(reg->id) & IWL_FW_INI_REGION_V2_MASK) == 1177 IWL_FW_INI_HW_SMEM_REGION_ID && 1178 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1179 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1180 range->data, 1181 le32_to_cpu(reg->dev_addr.size)); 1182 1183 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1184 } 1185 1186 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1187 void *range_ptr, int idx) 1188 { 1189 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1190 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1191 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1192 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1193 1194 range->page_num = cpu_to_le32(idx); 1195 range->range_data_size = cpu_to_le32(page_size); 1196 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1197 DMA_BIDIRECTIONAL); 1198 memcpy(range->data, page_address(page), page_size); 1199 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1200 DMA_BIDIRECTIONAL); 1201 1202 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1203 } 1204 1205 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1206 struct iwl_dump_ini_region_data *reg_data, 1207 void *range_ptr, int idx) 1208 { 1209 struct iwl_fw_ini_error_dump_range *range; 1210 u32 page_size; 1211 1212 /* all paged index start from 1 to skip CSS section */ 1213 idx++; 1214 1215 if (!fwrt->trans->trans_cfg->gen2) 1216 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx); 1217 1218 range = range_ptr; 1219 page_size = fwrt->trans->init_dram.paging[idx].size; 1220 1221 range->page_num = cpu_to_le32(idx); 1222 range->range_data_size = cpu_to_le32(page_size); 1223 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1224 page_size); 1225 1226 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1227 } 1228 1229 static int 1230 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1231 struct iwl_dump_ini_region_data *reg_data, 1232 void *range_ptr, int idx) 1233 { 1234 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1235 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1236 struct iwl_dram_data *frag; 1237 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1238 1239 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1240 1241 range->dram_base_addr = cpu_to_le64(frag->physical); 1242 range->range_data_size = cpu_to_le32(frag->size); 1243 1244 memcpy(range->data, frag->block, frag->size); 1245 1246 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1247 } 1248 1249 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1250 struct iwl_dump_ini_region_data *reg_data, 1251 void *range_ptr, int idx) 1252 { 1253 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1254 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1255 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1256 1257 range->internal_base_addr = cpu_to_le32(addr); 1258 range->range_data_size = reg->internal_buffer.size; 1259 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1260 le32_to_cpu(reg->internal_buffer.size)); 1261 1262 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1263 } 1264 1265 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1266 struct iwl_dump_ini_region_data *reg_data, int idx) 1267 { 1268 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1269 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1270 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1271 int txf_num = cfg->num_txfifo_entries; 1272 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1273 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1274 1275 if (!idx) { 1276 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1277 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1278 le32_to_cpu(reg->fifos.offset)); 1279 return false; 1280 } 1281 1282 iter->internal_txf = 0; 1283 iter->fifo_size = 0; 1284 iter->fifo = -1; 1285 if (le32_to_cpu(reg->fifos.offset)) 1286 iter->lmac = 1; 1287 else 1288 iter->lmac = 0; 1289 } 1290 1291 if (!iter->internal_txf) { 1292 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1293 iter->fifo_size = 1294 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1295 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1296 return true; 1297 } 1298 iter->fifo--; 1299 } 1300 1301 iter->internal_txf = 1; 1302 1303 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1304 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1305 return false; 1306 1307 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1308 iter->fifo_size = 1309 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1310 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1311 return true; 1312 } 1313 1314 return false; 1315 } 1316 1317 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1318 struct iwl_dump_ini_region_data *reg_data, 1319 void *range_ptr, int idx) 1320 { 1321 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1322 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1323 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1324 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1325 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1326 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1327 u32 registers_size = registers_num * sizeof(*reg_dump); 1328 __le32 *data; 1329 int i; 1330 1331 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1332 return -EIO; 1333 1334 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1335 return -EBUSY; 1336 1337 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1338 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1339 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1340 1341 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1342 1343 /* 1344 * read txf registers. for each register, write to the dump the 1345 * register address and its value 1346 */ 1347 for (i = 0; i < registers_num; i++) { 1348 addr = le32_to_cpu(reg->addrs[i]) + offs; 1349 1350 reg_dump->addr = cpu_to_le32(addr); 1351 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1352 addr)); 1353 1354 reg_dump++; 1355 } 1356 1357 if (reg->fifos.hdr_only) { 1358 range->range_data_size = cpu_to_le32(registers_size); 1359 goto out; 1360 } 1361 1362 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1363 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1364 TXF_WR_PTR + offs); 1365 1366 /* Dummy-read to advance the read pointer to the head */ 1367 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1368 1369 /* Read FIFO */ 1370 addr = TXF_READ_MODIFY_DATA + offs; 1371 data = (void *)reg_dump; 1372 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1373 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1374 1375 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1376 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1377 reg_dump, iter->fifo_size); 1378 1379 out: 1380 iwl_trans_release_nic_access(fwrt->trans); 1381 1382 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1383 } 1384 1385 struct iwl_ini_rxf_data { 1386 u32 fifo_num; 1387 u32 size; 1388 u32 offset; 1389 }; 1390 1391 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1392 struct iwl_dump_ini_region_data *reg_data, 1393 struct iwl_ini_rxf_data *data) 1394 { 1395 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1396 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1397 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1398 u8 fifo_idx; 1399 1400 if (!data) 1401 return; 1402 1403 /* make sure only one bit is set in only one fid */ 1404 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1405 "fid1=%x, fid2=%x\n", fid1, fid2)) 1406 return; 1407 1408 memset(data, 0, sizeof(*data)); 1409 1410 if (fid1) { 1411 fifo_idx = ffs(fid1) - 1; 1412 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1413 fifo_idx)) 1414 return; 1415 1416 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1417 data->fifo_num = fifo_idx; 1418 } else { 1419 u8 max_idx; 1420 1421 fifo_idx = ffs(fid2) - 1; 1422 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1423 SHARED_MEM_CFG_CMD, 0) <= 3) 1424 max_idx = 0; 1425 else 1426 max_idx = 1; 1427 1428 if (WARN_ONCE(fifo_idx > max_idx, 1429 "invalid umac fifo idx %d", fifo_idx)) 1430 return; 1431 1432 /* use bit 31 to distinguish between umac and lmac rxf while 1433 * parsing the dump 1434 */ 1435 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1436 1437 switch (fifo_idx) { 1438 case 0: 1439 data->size = fwrt->smem_cfg.rxfifo2_size; 1440 data->offset = iwl_umac_prph(fwrt->trans, 1441 RXF_DIFF_FROM_PREV); 1442 break; 1443 case 1: 1444 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1445 data->offset = iwl_umac_prph(fwrt->trans, 1446 RXF2C_DIFF_FROM_PREV); 1447 break; 1448 } 1449 } 1450 } 1451 1452 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1453 struct iwl_dump_ini_region_data *reg_data, 1454 void *range_ptr, int idx) 1455 { 1456 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1457 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1458 struct iwl_ini_rxf_data rxf_data; 1459 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1460 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1461 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1462 u32 registers_size = registers_num * sizeof(*reg_dump); 1463 __le32 *data; 1464 int i; 1465 1466 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1467 if (!rxf_data.size) 1468 return -EIO; 1469 1470 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1471 return -EBUSY; 1472 1473 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1474 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1475 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1476 1477 /* 1478 * read rxf registers. for each register, write to the dump the 1479 * register address and its value 1480 */ 1481 for (i = 0; i < registers_num; i++) { 1482 addr = le32_to_cpu(reg->addrs[i]) + offs; 1483 1484 reg_dump->addr = cpu_to_le32(addr); 1485 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1486 addr)); 1487 1488 reg_dump++; 1489 } 1490 1491 if (reg->fifos.hdr_only) { 1492 range->range_data_size = cpu_to_le32(registers_size); 1493 goto out; 1494 } 1495 1496 offs = rxf_data.offset; 1497 1498 /* Lock fence */ 1499 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1500 /* Set fence pointer to the same place like WR pointer */ 1501 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1502 /* Set fence offset */ 1503 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1504 0x0); 1505 1506 /* Read FIFO */ 1507 addr = RXF_FIFO_RD_FENCE_INC + offs; 1508 data = (void *)reg_dump; 1509 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1510 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1511 1512 out: 1513 iwl_trans_release_nic_access(fwrt->trans); 1514 1515 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1516 } 1517 1518 static int 1519 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1520 struct iwl_dump_ini_region_data *reg_data, 1521 void *range_ptr, int idx) 1522 { 1523 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1524 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1525 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1526 u32 addr = le32_to_cpu(err_table->base_addr) + 1527 le32_to_cpu(err_table->offset); 1528 1529 range->internal_base_addr = cpu_to_le32(addr); 1530 range->range_data_size = err_table->size; 1531 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1532 le32_to_cpu(err_table->size)); 1533 1534 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1535 } 1536 1537 static int 1538 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1539 struct iwl_dump_ini_region_data *reg_data, 1540 void *range_ptr, int idx) 1541 { 1542 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1543 struct iwl_fw_ini_region_special_device_memory *special_mem = 1544 ®->special_mem; 1545 1546 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1547 u32 addr = le32_to_cpu(special_mem->base_addr) + 1548 le32_to_cpu(special_mem->offset); 1549 1550 range->internal_base_addr = cpu_to_le32(addr); 1551 range->range_data_size = special_mem->size; 1552 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1553 le32_to_cpu(special_mem->size)); 1554 1555 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1556 } 1557 1558 static int 1559 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1560 struct iwl_dump_ini_region_data *reg_data, 1561 void *range_ptr, int idx) 1562 { 1563 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1564 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1565 __le32 *val = range->data; 1566 u32 prph_data; 1567 int i; 1568 1569 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1570 return -EBUSY; 1571 1572 range->range_data_size = reg->dev_addr.size; 1573 iwl_write_prph_no_grab(fwrt->trans, DBGI_SRAM_TARGET_ACCESS_CFG, 1574 DBGI_SRAM_TARGET_ACCESS_CFG_RESET_ADDRESS_MSK); 1575 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1576 prph_data = iwl_read_prph(fwrt->trans, (i % 2) ? 1577 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1578 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1579 if (prph_data == 0x5a5a5a5a) { 1580 iwl_trans_release_nic_access(fwrt->trans); 1581 return -EBUSY; 1582 } 1583 *val++ = cpu_to_le32(prph_data); 1584 } 1585 iwl_trans_release_nic_access(fwrt->trans); 1586 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1587 } 1588 1589 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1590 struct iwl_dump_ini_region_data *reg_data, 1591 void *range_ptr, int idx) 1592 { 1593 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1594 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1595 u32 pkt_len; 1596 1597 if (!pkt) 1598 return -EIO; 1599 1600 pkt_len = iwl_rx_packet_payload_len(pkt); 1601 1602 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1603 range->range_data_size = cpu_to_le32(pkt_len); 1604 1605 memcpy(range->data, pkt->data, pkt_len); 1606 1607 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1608 } 1609 1610 static void * 1611 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1612 struct iwl_dump_ini_region_data *reg_data, 1613 void *data) 1614 { 1615 struct iwl_fw_ini_error_dump *dump = data; 1616 1617 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1618 1619 return dump->data; 1620 } 1621 1622 /** 1623 * mask_apply_and_normalize - applies mask on val and normalize the result 1624 * 1625 * The normalization is based on the first set bit in the mask 1626 * 1627 * @val: value 1628 * @mask: mask to apply and to normalize with 1629 */ 1630 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1631 { 1632 return (val & mask) >> (ffs(mask) - 1); 1633 } 1634 1635 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1636 const struct iwl_fw_mon_reg *reg_info) 1637 { 1638 u32 val, offs; 1639 1640 /* The header addresses of DBGCi is calculate as follows: 1641 * DBGC1 address + (0x100 * i) 1642 */ 1643 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1644 1645 if (!reg_info || !reg_info->addr || !reg_info->mask) 1646 return 0; 1647 1648 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1649 1650 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1651 } 1652 1653 static void * 1654 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1655 struct iwl_dump_ini_region_data *reg_data, 1656 struct iwl_fw_ini_monitor_dump *data, 1657 const struct iwl_fw_mon_regs *addrs) 1658 { 1659 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1660 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1661 1662 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1663 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1664 return NULL; 1665 } 1666 1667 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1668 &addrs->write_ptr); 1669 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1670 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1671 1672 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1673 } 1674 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1675 &addrs->cycle_cnt); 1676 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1677 &addrs->cur_frag); 1678 1679 iwl_trans_release_nic_access(fwrt->trans); 1680 1681 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1682 1683 return data->data; 1684 } 1685 1686 static void * 1687 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1688 struct iwl_dump_ini_region_data *reg_data, 1689 void *data) 1690 { 1691 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1692 1693 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1694 &fwrt->trans->cfg->mon_dram_regs); 1695 } 1696 1697 static void * 1698 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1699 struct iwl_dump_ini_region_data *reg_data, 1700 void *data) 1701 { 1702 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1703 1704 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1705 &fwrt->trans->cfg->mon_smem_regs); 1706 } 1707 1708 static void * 1709 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1710 struct iwl_dump_ini_region_data *reg_data, 1711 void *data) 1712 { 1713 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1714 struct iwl_fw_ini_err_table_dump *dump = data; 1715 1716 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1717 dump->version = reg->err_table.version; 1718 1719 return dump->data; 1720 } 1721 1722 static void * 1723 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1724 struct iwl_dump_ini_region_data *reg_data, 1725 void *data) 1726 { 1727 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1728 struct iwl_fw_ini_special_device_memory *dump = data; 1729 1730 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1731 dump->type = reg->special_mem.type; 1732 dump->version = reg->special_mem.version; 1733 1734 return dump->data; 1735 } 1736 1737 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1738 struct iwl_dump_ini_region_data *reg_data) 1739 { 1740 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1741 1742 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1743 } 1744 1745 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1746 struct iwl_dump_ini_region_data *reg_data) 1747 { 1748 if (fwrt->trans->trans_cfg->gen2) { 1749 if (fwrt->trans->init_dram.paging_cnt) 1750 return fwrt->trans->init_dram.paging_cnt - 1; 1751 else 1752 return 0; 1753 } 1754 1755 return fwrt->num_of_paging_blk; 1756 } 1757 1758 static u32 1759 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1760 struct iwl_dump_ini_region_data *reg_data) 1761 { 1762 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1763 struct iwl_fw_mon *fw_mon; 1764 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1765 int i; 1766 1767 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1768 1769 for (i = 0; i < fw_mon->num_frags; i++) { 1770 if (!fw_mon->frags[i].size) 1771 break; 1772 1773 ranges++; 1774 } 1775 1776 return ranges; 1777 } 1778 1779 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1780 struct iwl_dump_ini_region_data *reg_data) 1781 { 1782 u32 num_of_fifos = 0; 1783 1784 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1785 num_of_fifos++; 1786 1787 return num_of_fifos; 1788 } 1789 1790 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1791 struct iwl_dump_ini_region_data *reg_data) 1792 { 1793 return 1; 1794 } 1795 1796 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1797 struct iwl_dump_ini_region_data *reg_data) 1798 { 1799 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1800 u32 size = le32_to_cpu(reg->dev_addr.size); 1801 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1802 1803 if (!size || !ranges) 1804 return 0; 1805 1806 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1807 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1808 } 1809 1810 static u32 1811 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1812 struct iwl_dump_ini_region_data *reg_data) 1813 { 1814 int i; 1815 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1816 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1817 1818 /* start from 1 to skip CSS section */ 1819 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1820 size += range_header_len; 1821 if (fwrt->trans->trans_cfg->gen2) 1822 size += fwrt->trans->init_dram.paging[i].size; 1823 else 1824 size += fwrt->fw_paging_db[i].fw_paging_size; 1825 } 1826 1827 return size; 1828 } 1829 1830 static u32 1831 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1832 struct iwl_dump_ini_region_data *reg_data) 1833 { 1834 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1835 struct iwl_fw_mon *fw_mon; 1836 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1837 int i; 1838 1839 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1840 1841 for (i = 0; i < fw_mon->num_frags; i++) { 1842 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1843 1844 if (!frag->size) 1845 break; 1846 1847 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1848 } 1849 1850 if (size) 1851 size += sizeof(struct iwl_fw_ini_monitor_dump); 1852 1853 return size; 1854 } 1855 1856 static u32 1857 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1858 struct iwl_dump_ini_region_data *reg_data) 1859 { 1860 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1861 u32 size; 1862 1863 size = le32_to_cpu(reg->internal_buffer.size); 1864 if (!size) 1865 return 0; 1866 1867 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1868 sizeof(struct iwl_fw_ini_error_dump_range); 1869 1870 return size; 1871 } 1872 1873 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1874 struct iwl_dump_ini_region_data *reg_data) 1875 { 1876 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1877 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1878 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1879 u32 size = 0; 1880 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1881 registers_num * 1882 sizeof(struct iwl_fw_ini_error_dump_register); 1883 1884 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1885 size += fifo_hdr; 1886 if (!reg->fifos.hdr_only) 1887 size += iter->fifo_size; 1888 } 1889 1890 if (!size) 1891 return 0; 1892 1893 return size + sizeof(struct iwl_fw_ini_error_dump); 1894 } 1895 1896 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1897 struct iwl_dump_ini_region_data *reg_data) 1898 { 1899 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1900 struct iwl_ini_rxf_data rx_data; 1901 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1902 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1903 sizeof(struct iwl_fw_ini_error_dump_range) + 1904 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1905 1906 if (reg->fifos.hdr_only) 1907 return size; 1908 1909 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1910 size += rx_data.size; 1911 1912 return size; 1913 } 1914 1915 static u32 1916 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1917 struct iwl_dump_ini_region_data *reg_data) 1918 { 1919 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1920 u32 size = le32_to_cpu(reg->err_table.size); 1921 1922 if (size) 1923 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1924 sizeof(struct iwl_fw_ini_error_dump_range); 1925 1926 return size; 1927 } 1928 1929 static u32 1930 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 1931 struct iwl_dump_ini_region_data *reg_data) 1932 { 1933 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1934 u32 size = le32_to_cpu(reg->special_mem.size); 1935 1936 if (size) 1937 size += sizeof(struct iwl_fw_ini_special_device_memory) + 1938 sizeof(struct iwl_fw_ini_error_dump_range); 1939 1940 return size; 1941 } 1942 1943 static u32 1944 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 1945 struct iwl_dump_ini_region_data *reg_data) 1946 { 1947 u32 size = 0; 1948 1949 if (!reg_data->dump_data->fw_pkt) 1950 return 0; 1951 1952 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 1953 if (size) 1954 size += sizeof(struct iwl_fw_ini_error_dump) + 1955 sizeof(struct iwl_fw_ini_error_dump_range); 1956 1957 return size; 1958 } 1959 1960 /** 1961 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1962 * @get_num_of_ranges: returns the number of memory ranges in the region. 1963 * @get_size: returns the total size of the region. 1964 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1965 * the first range or NULL if failed to fill headers. 1966 * @fill_range: copies a given memory range into the dump. 1967 * Returns the size of the range or negative error value otherwise. 1968 */ 1969 struct iwl_dump_ini_mem_ops { 1970 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1971 struct iwl_dump_ini_region_data *reg_data); 1972 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1973 struct iwl_dump_ini_region_data *reg_data); 1974 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1975 struct iwl_dump_ini_region_data *reg_data, 1976 void *data); 1977 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1978 struct iwl_dump_ini_region_data *reg_data, 1979 void *range, int idx); 1980 }; 1981 1982 /** 1983 * iwl_dump_ini_mem 1984 * 1985 * Creates a dump tlv and copy a memory region into it. 1986 * Returns the size of the current dump tlv or 0 if failed 1987 * 1988 * @fwrt: fw runtime struct 1989 * @list: list to add the dump tlv to 1990 * @reg_data: memory region 1991 * @ops: memory dump operations 1992 */ 1993 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1994 struct iwl_dump_ini_region_data *reg_data, 1995 const struct iwl_dump_ini_mem_ops *ops) 1996 { 1997 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1998 struct iwl_fw_ini_dump_entry *entry; 1999 struct iwl_fw_error_dump_data *tlv; 2000 struct iwl_fw_ini_error_dump_header *header; 2001 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id); 2002 u32 num_of_ranges, i, size; 2003 void *range; 2004 2005 /* 2006 * The higher part of the ID in version 2 is irrelevant for 2007 * us, so mask it out. 2008 */ 2009 if (le32_to_cpu(reg->hdr.version) == 2) 2010 id &= IWL_FW_INI_REGION_V2_MASK; 2011 2012 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2013 !ops->fill_range) 2014 return 0; 2015 2016 size = ops->get_size(fwrt, reg_data); 2017 if (!size) 2018 return 0; 2019 2020 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2021 if (!entry) 2022 return 0; 2023 2024 entry->size = sizeof(*tlv) + size; 2025 2026 tlv = (void *)entry->data; 2027 tlv->type = reg->type; 2028 tlv->len = cpu_to_le32(size); 2029 2030 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id, 2031 type); 2032 2033 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2034 2035 header = (void *)tlv->data; 2036 header->region_id = cpu_to_le32(id); 2037 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2038 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2039 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2040 2041 range = ops->fill_mem_hdr(fwrt, reg_data, header); 2042 if (!range) { 2043 IWL_ERR(fwrt, 2044 "WRT: Failed to fill region header: id=%d, type=%d\n", 2045 id, type); 2046 goto out_err; 2047 } 2048 2049 for (i = 0; i < num_of_ranges; i++) { 2050 int range_size = ops->fill_range(fwrt, reg_data, range, i); 2051 2052 if (range_size < 0) { 2053 IWL_ERR(fwrt, 2054 "WRT: Failed to dump region: id=%d, type=%d\n", 2055 id, type); 2056 goto out_err; 2057 } 2058 range = (u8 *)range + range_size; 2059 } 2060 2061 list_add_tail(&entry->list, list); 2062 2063 return entry->size; 2064 2065 out_err: 2066 vfree(entry); 2067 2068 return 0; 2069 } 2070 2071 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2072 struct iwl_fw_ini_trigger_tlv *trigger, 2073 struct list_head *list) 2074 { 2075 struct iwl_fw_ini_dump_entry *entry; 2076 struct iwl_fw_error_dump_data *tlv; 2077 struct iwl_fw_ini_dump_info *dump; 2078 struct iwl_dbg_tlv_node *node; 2079 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2080 u32 size = sizeof(*tlv) + sizeof(*dump); 2081 u32 num_of_cfg_names = 0; 2082 u32 hw_type; 2083 2084 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2085 size += sizeof(*cfg_name); 2086 num_of_cfg_names++; 2087 } 2088 2089 entry = vzalloc(sizeof(*entry) + size); 2090 if (!entry) 2091 return 0; 2092 2093 entry->size = size; 2094 2095 tlv = (void *)entry->data; 2096 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2097 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2098 2099 dump = (void *)tlv->data; 2100 2101 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2102 dump->time_point = trigger->time_point; 2103 dump->trigger_reason = trigger->trigger_reason; 2104 dump->external_cfg_state = 2105 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2106 2107 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2108 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2109 2110 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 2111 2112 /* 2113 * Several HWs all have type == 0x42, so we'll override this value 2114 * according to the detected HW 2115 */ 2116 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2117 if (hw_type == IWL_AX210_HW_TYPE) { 2118 u32 prph_val = iwl_read_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR_GEN2); 2119 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2120 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2121 u32 masked_bits = is_jacket | (is_cdb << 1); 2122 2123 /* 2124 * The HW type depends on certain bits in this case, so add 2125 * these bits to the HW type. We won't have collisions since we 2126 * add these bits after the highest possible bit in the mask. 2127 */ 2128 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2129 } 2130 dump->hw_type = cpu_to_le32(hw_type); 2131 2132 dump->rf_id_flavor = 2133 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2134 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2135 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2136 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2137 2138 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2139 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2140 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2141 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2142 2143 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2144 dump->regions_mask = trigger->regions_mask & 2145 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2146 2147 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2148 memcpy(dump->build_tag, fwrt->fw->human_readable, 2149 sizeof(dump->build_tag)); 2150 2151 cfg_name = dump->cfg_names; 2152 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2153 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2154 struct iwl_fw_ini_debug_info_tlv *debug_info = 2155 (void *)node->tlv.data; 2156 2157 cfg_name->image_type = debug_info->image_type; 2158 cfg_name->cfg_name_len = 2159 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2160 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2161 sizeof(cfg_name->cfg_name)); 2162 cfg_name++; 2163 } 2164 2165 /* add dump info TLV to the beginning of the list since it needs to be 2166 * the first TLV in the dump 2167 */ 2168 list_add(&entry->list, list); 2169 2170 return entry->size; 2171 } 2172 2173 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2174 [IWL_FW_INI_REGION_INVALID] = {}, 2175 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2176 .get_num_of_ranges = iwl_dump_ini_single_range, 2177 .get_size = iwl_dump_ini_mon_smem_get_size, 2178 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2179 .fill_range = iwl_dump_ini_mon_smem_iter, 2180 }, 2181 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2182 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2183 .get_size = iwl_dump_ini_mon_dram_get_size, 2184 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2185 .fill_range = iwl_dump_ini_mon_dram_iter, 2186 }, 2187 [IWL_FW_INI_REGION_TXF] = { 2188 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2189 .get_size = iwl_dump_ini_txf_get_size, 2190 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2191 .fill_range = iwl_dump_ini_txf_iter, 2192 }, 2193 [IWL_FW_INI_REGION_RXF] = { 2194 .get_num_of_ranges = iwl_dump_ini_single_range, 2195 .get_size = iwl_dump_ini_rxf_get_size, 2196 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2197 .fill_range = iwl_dump_ini_rxf_iter, 2198 }, 2199 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2200 .get_num_of_ranges = iwl_dump_ini_single_range, 2201 .get_size = iwl_dump_ini_err_table_get_size, 2202 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2203 .fill_range = iwl_dump_ini_err_table_iter, 2204 }, 2205 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2206 .get_num_of_ranges = iwl_dump_ini_single_range, 2207 .get_size = iwl_dump_ini_err_table_get_size, 2208 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2209 .fill_range = iwl_dump_ini_err_table_iter, 2210 }, 2211 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2212 .get_num_of_ranges = iwl_dump_ini_single_range, 2213 .get_size = iwl_dump_ini_fw_pkt_get_size, 2214 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2215 .fill_range = iwl_dump_ini_fw_pkt_iter, 2216 }, 2217 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2218 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2219 .get_size = iwl_dump_ini_mem_get_size, 2220 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2221 .fill_range = iwl_dump_ini_dev_mem_iter, 2222 }, 2223 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2224 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2225 .get_size = iwl_dump_ini_mem_get_size, 2226 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2227 .fill_range = iwl_dump_ini_prph_mac_iter, 2228 }, 2229 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2230 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2231 .get_size = iwl_dump_ini_mem_get_size, 2232 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2233 .fill_range = iwl_dump_ini_prph_phy_iter, 2234 }, 2235 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2236 [IWL_FW_INI_REGION_PAGING] = { 2237 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2238 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2239 .get_size = iwl_dump_ini_paging_get_size, 2240 .fill_range = iwl_dump_ini_paging_iter, 2241 }, 2242 [IWL_FW_INI_REGION_CSR] = { 2243 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2244 .get_size = iwl_dump_ini_mem_get_size, 2245 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2246 .fill_range = iwl_dump_ini_csr_iter, 2247 }, 2248 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 2249 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2250 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2251 .get_size = iwl_dump_ini_mem_get_size, 2252 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2253 .fill_range = iwl_dump_ini_config_iter, 2254 }, 2255 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2256 .get_num_of_ranges = iwl_dump_ini_single_range, 2257 .get_size = iwl_dump_ini_special_mem_get_size, 2258 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2259 .fill_range = iwl_dump_ini_special_mem_iter, 2260 }, 2261 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2262 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2263 .get_size = iwl_dump_ini_mem_get_size, 2264 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2265 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2266 }, 2267 }; 2268 2269 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2270 struct iwl_fwrt_dump_data *dump_data, 2271 struct list_head *list) 2272 { 2273 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2274 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2275 struct iwl_dump_ini_region_data reg_data = { 2276 .dump_data = dump_data, 2277 }; 2278 int i; 2279 u32 size = 0; 2280 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2281 ~(fwrt->trans->dbg.unsupported_region_msk); 2282 2283 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2284 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2285 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2286 2287 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2288 u32 reg_type; 2289 struct iwl_fw_ini_region_tlv *reg; 2290 2291 if (!(BIT_ULL(i) & regions_mask)) 2292 continue; 2293 2294 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2295 if (!reg_data.reg_tlv) { 2296 IWL_WARN(fwrt, 2297 "WRT: Unassigned region id %d, skipping\n", i); 2298 continue; 2299 } 2300 2301 reg = (void *)reg_data.reg_tlv->data; 2302 reg_type = le32_to_cpu(reg->type); 2303 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2304 continue; 2305 2306 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2307 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2308 IWL_WARN(fwrt, 2309 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2310 tp_id); 2311 continue; 2312 } 2313 2314 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2315 &iwl_dump_ini_region_ops[reg_type]); 2316 } 2317 2318 if (size) 2319 size += iwl_dump_ini_info(fwrt, trigger, list); 2320 2321 return size; 2322 } 2323 2324 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2325 struct iwl_fw_ini_trigger_tlv *trig) 2326 { 2327 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2328 u32 usec = le32_to_cpu(trig->ignore_consec); 2329 2330 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2331 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2332 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2333 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2334 return false; 2335 2336 return true; 2337 } 2338 2339 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2340 struct iwl_fwrt_dump_data *dump_data, 2341 struct list_head *list) 2342 { 2343 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2344 struct iwl_fw_ini_dump_entry *entry; 2345 struct iwl_fw_ini_dump_file_hdr *hdr; 2346 u32 size; 2347 2348 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2349 !le64_to_cpu(trigger->regions_mask)) 2350 return 0; 2351 2352 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2353 if (!entry) 2354 return 0; 2355 2356 entry->size = sizeof(*hdr); 2357 2358 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2359 if (!size) { 2360 vfree(entry); 2361 return 0; 2362 } 2363 2364 hdr = (void *)entry->data; 2365 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2366 hdr->file_len = cpu_to_le32(size + entry->size); 2367 2368 list_add(&entry->list, list); 2369 2370 return le32_to_cpu(hdr->file_len); 2371 } 2372 2373 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2374 const struct iwl_fw_dump_desc *desc) 2375 { 2376 if (desc && desc != &iwl_dump_desc_assert) 2377 kfree(desc); 2378 2379 fwrt->dump.lmac_err_id[0] = 0; 2380 if (fwrt->smem_cfg.num_lmacs > 1) 2381 fwrt->dump.lmac_err_id[1] = 0; 2382 fwrt->dump.umac_err_id = 0; 2383 } 2384 2385 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2386 struct iwl_fwrt_dump_data *dump_data) 2387 { 2388 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2389 struct iwl_fw_error_dump_file *dump_file; 2390 struct scatterlist *sg_dump_data; 2391 u32 file_len; 2392 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2393 2394 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2395 if (!dump_file) 2396 return; 2397 2398 if (dump_data->monitor_only) 2399 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2400 2401 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2402 fwrt->sanitize_ops, 2403 fwrt->sanitize_ctx); 2404 file_len = le32_to_cpu(dump_file->file_len); 2405 fw_error_dump.fwrt_len = file_len; 2406 2407 if (fw_error_dump.trans_ptr) { 2408 file_len += fw_error_dump.trans_ptr->len; 2409 dump_file->file_len = cpu_to_le32(file_len); 2410 } 2411 2412 sg_dump_data = alloc_sgtable(file_len); 2413 if (sg_dump_data) { 2414 sg_pcopy_from_buffer(sg_dump_data, 2415 sg_nents(sg_dump_data), 2416 fw_error_dump.fwrt_ptr, 2417 fw_error_dump.fwrt_len, 0); 2418 if (fw_error_dump.trans_ptr) 2419 sg_pcopy_from_buffer(sg_dump_data, 2420 sg_nents(sg_dump_data), 2421 fw_error_dump.trans_ptr->data, 2422 fw_error_dump.trans_ptr->len, 2423 fw_error_dump.fwrt_len); 2424 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2425 GFP_KERNEL); 2426 } 2427 vfree(fw_error_dump.fwrt_ptr); 2428 vfree(fw_error_dump.trans_ptr); 2429 } 2430 2431 static void iwl_dump_ini_list_free(struct list_head *list) 2432 { 2433 while (!list_empty(list)) { 2434 struct iwl_fw_ini_dump_entry *entry = 2435 list_entry(list->next, typeof(*entry), list); 2436 2437 list_del(&entry->list); 2438 vfree(entry); 2439 } 2440 } 2441 2442 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2443 { 2444 dump_data->trig = NULL; 2445 kfree(dump_data->fw_pkt); 2446 dump_data->fw_pkt = NULL; 2447 } 2448 2449 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2450 struct iwl_fwrt_dump_data *dump_data) 2451 { 2452 #if defined(__linux__) 2453 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2454 #elif defined(__FreeBSD__) 2455 struct list_head dump_list = LINUX_LIST_HEAD_INIT(dump_list); 2456 #endif 2457 struct scatterlist *sg_dump_data; 2458 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2459 2460 if (!file_len) 2461 return; 2462 2463 sg_dump_data = alloc_sgtable(file_len); 2464 if (sg_dump_data) { 2465 struct iwl_fw_ini_dump_entry *entry; 2466 int sg_entries = sg_nents(sg_dump_data); 2467 u32 offs = 0; 2468 2469 list_for_each_entry(entry, &dump_list, list) { 2470 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2471 entry->data, entry->size, offs); 2472 offs += entry->size; 2473 } 2474 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2475 GFP_KERNEL); 2476 } 2477 iwl_dump_ini_list_free(&dump_list); 2478 } 2479 2480 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2481 .trig_desc = { 2482 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2483 }, 2484 }; 2485 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2486 2487 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2488 const struct iwl_fw_dump_desc *desc, 2489 bool monitor_only, 2490 unsigned int delay) 2491 { 2492 struct iwl_fwrt_wk_data *wk_data; 2493 unsigned long idx; 2494 2495 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2496 iwl_fw_free_dump_desc(fwrt, desc); 2497 return 0; 2498 } 2499 2500 /* 2501 * Check there is an available worker. 2502 * ffz return value is undefined if no zero exists, 2503 * so check against ~0UL first. 2504 */ 2505 if (fwrt->dump.active_wks == ~0UL) 2506 return -EBUSY; 2507 2508 idx = ffz(fwrt->dump.active_wks); 2509 2510 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2511 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2512 return -EBUSY; 2513 2514 wk_data = &fwrt->dump.wks[idx]; 2515 2516 if (WARN_ON(wk_data->dump_data.desc)) 2517 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2518 2519 wk_data->dump_data.desc = desc; 2520 wk_data->dump_data.monitor_only = monitor_only; 2521 2522 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2523 le32_to_cpu(desc->trig_desc.type)); 2524 2525 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2526 2527 return 0; 2528 } 2529 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2530 2531 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2532 enum iwl_fw_dbg_trigger trig_type) 2533 { 2534 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2535 return -EIO; 2536 2537 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2538 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2539 trig_type != FW_DBG_TRIGGER_DRIVER) 2540 return -EIO; 2541 2542 iwl_dbg_tlv_time_point(fwrt, 2543 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2544 NULL); 2545 } else { 2546 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2547 int ret; 2548 2549 iwl_dump_error_desc = 2550 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2551 2552 if (!iwl_dump_error_desc) 2553 return -ENOMEM; 2554 2555 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2556 iwl_dump_error_desc->len = 0; 2557 2558 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2559 false, 0); 2560 if (ret) { 2561 kfree(iwl_dump_error_desc); 2562 return ret; 2563 } 2564 } 2565 2566 iwl_trans_sync_nmi(fwrt->trans); 2567 2568 return 0; 2569 } 2570 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2571 2572 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2573 enum iwl_fw_dbg_trigger trig, 2574 const char *str, size_t len, 2575 struct iwl_fw_dbg_trigger_tlv *trigger) 2576 { 2577 struct iwl_fw_dump_desc *desc; 2578 unsigned int delay = 0; 2579 bool monitor_only = false; 2580 2581 if (trigger) { 2582 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2583 2584 if (!le16_to_cpu(trigger->occurrences)) 2585 return 0; 2586 2587 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2588 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2589 trig); 2590 iwl_force_nmi(fwrt->trans); 2591 return 0; 2592 } 2593 2594 trigger->occurrences = cpu_to_le16(occurrences); 2595 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2596 2597 /* convert msec to usec */ 2598 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2599 } 2600 2601 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2602 if (!desc) 2603 return -ENOMEM; 2604 2605 2606 desc->len = len; 2607 desc->trig_desc.type = cpu_to_le32(trig); 2608 memcpy(desc->trig_desc.data, str, len); 2609 2610 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2611 } 2612 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2613 2614 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2615 struct iwl_fw_dbg_trigger_tlv *trigger, 2616 const char *fmt, ...) 2617 { 2618 int ret, len = 0; 2619 char buf[64]; 2620 2621 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2622 return 0; 2623 2624 if (fmt) { 2625 va_list ap; 2626 2627 buf[sizeof(buf) - 1] = '\0'; 2628 2629 va_start(ap, fmt); 2630 vsnprintf(buf, sizeof(buf), fmt, ap); 2631 va_end(ap); 2632 2633 /* check for truncation */ 2634 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2635 buf[sizeof(buf) - 1] = '\0'; 2636 2637 len = strlen(buf) + 1; 2638 } 2639 2640 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2641 trigger); 2642 2643 if (ret) 2644 return ret; 2645 2646 return 0; 2647 } 2648 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2649 2650 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2651 { 2652 u8 *ptr; 2653 int ret; 2654 int i; 2655 2656 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2657 "Invalid configuration %d\n", conf_id)) 2658 return -EINVAL; 2659 2660 /* EARLY START - firmware's configuration is hard coded */ 2661 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2662 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2663 conf_id == FW_DBG_START_FROM_ALIVE) 2664 return 0; 2665 2666 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2667 return -EINVAL; 2668 2669 if (fwrt->dump.conf != FW_DBG_INVALID) 2670 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2671 fwrt->dump.conf); 2672 2673 /* Send all HCMDs for configuring the FW debug */ 2674 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2675 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2676 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2677 struct iwl_host_cmd hcmd = { 2678 .id = cmd->id, 2679 .len = { le16_to_cpu(cmd->len), }, 2680 .data = { cmd->data, }, 2681 }; 2682 2683 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2684 if (ret) 2685 return ret; 2686 2687 ptr += sizeof(*cmd); 2688 ptr += le16_to_cpu(cmd->len); 2689 } 2690 2691 fwrt->dump.conf = conf_id; 2692 2693 return 0; 2694 } 2695 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2696 2697 /* this function assumes dump_start was called beforehand and dump_end will be 2698 * called afterwards 2699 */ 2700 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2701 { 2702 struct iwl_fw_dbg_params params = {0}; 2703 struct iwl_fwrt_dump_data *dump_data = 2704 &fwrt->dump.wks[wk_idx].dump_data; 2705 2706 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2707 return; 2708 2709 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2710 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2711 goto out; 2712 } 2713 2714 /* there's no point in fw dump if the bus is dead */ 2715 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2716 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2717 goto out; 2718 } 2719 2720 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2721 2722 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2723 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2724 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2725 else 2726 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2727 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2728 2729 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2730 2731 out: 2732 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2733 iwl_fw_error_dump_data_free(dump_data); 2734 } else { 2735 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 2736 dump_data->desc = NULL; 2737 } 2738 2739 clear_bit(wk_idx, &fwrt->dump.active_wks); 2740 } 2741 2742 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2743 struct iwl_fwrt_dump_data *dump_data, 2744 bool sync) 2745 { 2746 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2747 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2748 u32 occur, delay; 2749 unsigned long idx; 2750 2751 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 2752 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2753 tp_id); 2754 return -EINVAL; 2755 } 2756 2757 delay = le32_to_cpu(trig->dump_delay); 2758 occur = le32_to_cpu(trig->occurrences); 2759 if (!occur) 2760 return 0; 2761 2762 trig->occurrences = cpu_to_le32(--occur); 2763 2764 /* Check there is an available worker. 2765 * ffz return value is undefined if no zero exists, 2766 * so check against ~0UL first. 2767 */ 2768 if (fwrt->dump.active_wks == ~0UL) 2769 return -EBUSY; 2770 2771 idx = ffz(fwrt->dump.active_wks); 2772 2773 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2774 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2775 return -EBUSY; 2776 2777 fwrt->dump.wks[idx].dump_data = *dump_data; 2778 2779 if (sync) 2780 delay = 0; 2781 2782 IWL_WARN(fwrt, 2783 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 2784 tp_id, (u32)(delay / USEC_PER_MSEC)); 2785 2786 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2787 2788 if (sync) 2789 iwl_fw_dbg_collect_sync(fwrt, idx); 2790 2791 return 0; 2792 } 2793 2794 void iwl_fw_error_dump_wk(struct work_struct *work) 2795 { 2796 struct iwl_fwrt_wk_data *wks = 2797 container_of(work, typeof(*wks), wk.work); 2798 struct iwl_fw_runtime *fwrt = 2799 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 2800 2801 /* assumes the op mode mutex is locked in dump_start since 2802 * iwl_fw_dbg_collect_sync can't run in parallel 2803 */ 2804 if (fwrt->ops && fwrt->ops->dump_start && 2805 fwrt->ops->dump_start(fwrt->ops_ctx)) 2806 return; 2807 2808 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2809 2810 if (fwrt->ops && fwrt->ops->dump_end) 2811 fwrt->ops->dump_end(fwrt->ops_ctx); 2812 } 2813 2814 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2815 { 2816 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2817 2818 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2819 return; 2820 2821 if (!fwrt->dump.d3_debug_data) { 2822 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2823 GFP_KERNEL); 2824 if (!fwrt->dump.d3_debug_data) { 2825 IWL_ERR(fwrt, 2826 "failed to allocate memory for D3 debug data\n"); 2827 return; 2828 } 2829 } 2830 2831 /* if the buffer holds previous debug data it is overwritten */ 2832 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2833 fwrt->dump.d3_debug_data, 2834 cfg->d3_debug_data_length); 2835 2836 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 2837 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 2838 cfg->d3_debug_data_base_addr, 2839 fwrt->dump.d3_debug_data, 2840 cfg->d3_debug_data_length); 2841 } 2842 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2843 2844 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2845 { 2846 int i; 2847 2848 iwl_dbg_tlv_del_timers(fwrt->trans); 2849 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2850 iwl_fw_dbg_collect_sync(fwrt, i); 2851 2852 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2853 } 2854 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2855 2856 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2857 { 2858 struct iwl_dbg_suspend_resume_cmd cmd = { 2859 .operation = suspend ? 2860 cpu_to_le32(DBGC_SUSPEND_CMD) : 2861 cpu_to_le32(DBGC_RESUME_CMD), 2862 }; 2863 struct iwl_host_cmd hcmd = { 2864 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2865 .data[0] = &cmd, 2866 .len[0] = sizeof(cmd), 2867 }; 2868 2869 return iwl_trans_send_cmd(trans, &hcmd); 2870 } 2871 2872 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2873 struct iwl_fw_dbg_params *params) 2874 { 2875 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2876 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2877 return; 2878 } 2879 2880 if (params) { 2881 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2882 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2883 } 2884 2885 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2886 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2887 * avoid halting the HW while writing 2888 */ 2889 usleep_range(700, 1000); 2890 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2891 } 2892 2893 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2894 struct iwl_fw_dbg_params *params) 2895 { 2896 if (!params) 2897 return -EIO; 2898 2899 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2900 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2901 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2902 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2903 } else { 2904 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2905 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2906 } 2907 2908 return 0; 2909 } 2910 2911 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2912 struct iwl_fw_dbg_params *params, 2913 bool stop) 2914 { 2915 int ret __maybe_unused = 0; 2916 2917 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2918 return; 2919 2920 if (fw_has_capa(&fwrt->fw->ucode_capa, 2921 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2922 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2923 else if (stop) 2924 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2925 else 2926 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2927 #ifdef CONFIG_IWLWIFI_DEBUGFS 2928 if (!ret) { 2929 if (stop) 2930 fwrt->trans->dbg.rec_on = false; 2931 else 2932 iwl_fw_set_dbg_rec_on(fwrt); 2933 } 2934 #endif 2935 } 2936 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2937