1*bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*bfcc09ddSBjoern A. Zeeb /* 3*bfcc09ddSBjoern A. Zeeb * Copyright (C) 2012-2014 Intel Corporation 4*bfcc09ddSBjoern A. Zeeb * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5*bfcc09ddSBjoern A. Zeeb * Copyright (C) 2016-2017 Intel Deutschland GmbH 6*bfcc09ddSBjoern A. Zeeb */ 7*bfcc09ddSBjoern A. Zeeb #ifndef __iwl_fw_api_sf_h__ 8*bfcc09ddSBjoern A. Zeeb #define __iwl_fw_api_sf_h__ 9*bfcc09ddSBjoern A. Zeeb 10*bfcc09ddSBjoern A. Zeeb /* Smart Fifo state */ 11*bfcc09ddSBjoern A. Zeeb enum iwl_sf_state { 12*bfcc09ddSBjoern A. Zeeb SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 13*bfcc09ddSBjoern A. Zeeb SF_FULL_ON, 14*bfcc09ddSBjoern A. Zeeb SF_UNINIT, 15*bfcc09ddSBjoern A. Zeeb SF_INIT_OFF, 16*bfcc09ddSBjoern A. Zeeb SF_HW_NUM_STATES 17*bfcc09ddSBjoern A. Zeeb }; 18*bfcc09ddSBjoern A. Zeeb 19*bfcc09ddSBjoern A. Zeeb /* Smart Fifo possible scenario */ 20*bfcc09ddSBjoern A. Zeeb enum iwl_sf_scenario { 21*bfcc09ddSBjoern A. Zeeb SF_SCENARIO_SINGLE_UNICAST, 22*bfcc09ddSBjoern A. Zeeb SF_SCENARIO_AGG_UNICAST, 23*bfcc09ddSBjoern A. Zeeb SF_SCENARIO_MULTICAST, 24*bfcc09ddSBjoern A. Zeeb SF_SCENARIO_BA_RESP, 25*bfcc09ddSBjoern A. Zeeb SF_SCENARIO_TX_RESP, 26*bfcc09ddSBjoern A. Zeeb SF_NUM_SCENARIO 27*bfcc09ddSBjoern A. Zeeb }; 28*bfcc09ddSBjoern A. Zeeb 29*bfcc09ddSBjoern A. Zeeb #define SF_TRANSIENT_STATES_NUMBER 2 /* SF_LONG_DELAY_ON and SF_FULL_ON */ 30*bfcc09ddSBjoern A. Zeeb #define SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 31*bfcc09ddSBjoern A. Zeeb 32*bfcc09ddSBjoern A. Zeeb /* smart FIFO default values */ 33*bfcc09ddSBjoern A. Zeeb #define SF_W_MARK_SISO 6144 34*bfcc09ddSBjoern A. Zeeb #define SF_W_MARK_MIMO2 8192 35*bfcc09ddSBjoern A. Zeeb #define SF_W_MARK_MIMO3 6144 36*bfcc09ddSBjoern A. Zeeb #define SF_W_MARK_LEGACY 4096 37*bfcc09ddSBjoern A. Zeeb #define SF_W_MARK_SCAN 4096 38*bfcc09ddSBjoern A. Zeeb 39*bfcc09ddSBjoern A. Zeeb /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 40*bfcc09ddSBjoern A. Zeeb #define SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 41*bfcc09ddSBjoern A. Zeeb #define SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 42*bfcc09ddSBjoern A. Zeeb #define SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 43*bfcc09ddSBjoern A. Zeeb #define SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 44*bfcc09ddSBjoern A. Zeeb #define SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 45*bfcc09ddSBjoern A. Zeeb #define SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 46*bfcc09ddSBjoern A. Zeeb #define SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 47*bfcc09ddSBjoern A. Zeeb #define SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 48*bfcc09ddSBjoern A. Zeeb #define SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 49*bfcc09ddSBjoern A. Zeeb #define SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 50*bfcc09ddSBjoern A. Zeeb 51*bfcc09ddSBjoern A. Zeeb /* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */ 52*bfcc09ddSBjoern A. Zeeb #define SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 53*bfcc09ddSBjoern A. Zeeb #define SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 54*bfcc09ddSBjoern A. Zeeb #define SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 55*bfcc09ddSBjoern A. Zeeb #define SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 56*bfcc09ddSBjoern A. Zeeb #define SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 57*bfcc09ddSBjoern A. Zeeb #define SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 58*bfcc09ddSBjoern A. Zeeb #define SF_BA_IDLE_TIMER 320 /* 300 uSec */ 59*bfcc09ddSBjoern A. Zeeb #define SF_BA_AGING_TIMER 2016 /* 2 mSec */ 60*bfcc09ddSBjoern A. Zeeb #define SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 61*bfcc09ddSBjoern A. Zeeb #define SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 62*bfcc09ddSBjoern A. Zeeb 63*bfcc09ddSBjoern A. Zeeb #define SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 64*bfcc09ddSBjoern A. Zeeb 65*bfcc09ddSBjoern A. Zeeb #define SF_CFG_DUMMY_NOTIF_OFF BIT(16) 66*bfcc09ddSBjoern A. Zeeb 67*bfcc09ddSBjoern A. Zeeb /** 68*bfcc09ddSBjoern A. Zeeb * struct iwl_sf_cfg_cmd - Smart Fifo configuration command. 69*bfcc09ddSBjoern A. Zeeb * @state: smart fifo state, types listed in &enum iwl_sf_state. 70*bfcc09ddSBjoern A. Zeeb * @watermark: Minimum allowed available free space in RXF for transient state. 71*bfcc09ddSBjoern A. Zeeb * @long_delay_timeouts: aging and idle timer values for each scenario 72*bfcc09ddSBjoern A. Zeeb * in long delay state. 73*bfcc09ddSBjoern A. Zeeb * @full_on_timeouts: timer values for each scenario in full on state. 74*bfcc09ddSBjoern A. Zeeb */ 75*bfcc09ddSBjoern A. Zeeb struct iwl_sf_cfg_cmd { 76*bfcc09ddSBjoern A. Zeeb __le32 state; 77*bfcc09ddSBjoern A. Zeeb __le32 watermark[SF_TRANSIENT_STATES_NUMBER]; 78*bfcc09ddSBjoern A. Zeeb __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES]; 79*bfcc09ddSBjoern A. Zeeb __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES]; 80*bfcc09ddSBjoern A. Zeeb } __packed; /* SF_CFG_API_S_VER_2 */ 81*bfcc09ddSBjoern A. Zeeb 82*bfcc09ddSBjoern A. Zeeb #endif /* __iwl_fw_api_sf_h__ */ 83