1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 #define RX_MPDU_BAND_POS 6 197 #define RX_MPDU_BAND_MASK 0xC0 198 #define BAND_IN_RX_STATUS(_val) \ 199 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 200 201 enum iwl_rx_l3_proto_values { 202 IWL_RX_L3_TYPE_NONE, 203 IWL_RX_L3_TYPE_IPV4, 204 IWL_RX_L3_TYPE_IPV4_FRAG, 205 IWL_RX_L3_TYPE_IPV6_FRAG, 206 IWL_RX_L3_TYPE_IPV6, 207 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 208 IWL_RX_L3_TYPE_ARP, 209 IWL_RX_L3_TYPE_EAPOL, 210 }; 211 212 #define IWL_RX_L3_PROTO_POS 4 213 214 enum iwl_rx_l3l4_flags { 215 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 216 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 217 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 218 IWL_RX_L3L4_TCP_ACK = BIT(3), 219 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 220 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 221 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 222 }; 223 224 enum iwl_rx_mpdu_status { 225 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 226 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 227 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 228 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 229 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 230 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 231 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 232 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 233 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 234 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 235 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 236 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 237 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 238 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 239 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 240 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 241 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 242 #if defined(__FreeBSD__) 243 IWL_RX_MPDU_STATUS_SEC_ENC_ERR = 0x7 << 8, 244 #endif 245 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 246 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 247 248 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 249 250 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 251 }; 252 253 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 254 255 enum iwl_rx_mpdu_reorder_data { 256 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 257 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 258 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 259 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 260 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 261 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 262 }; 263 264 enum iwl_rx_mpdu_phy_info { 265 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 266 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 267 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 268 /* short preamble is only for CCK, for non-CCK overridden by this */ 269 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 270 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 271 }; 272 273 enum iwl_rx_mpdu_mac_info { 274 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 275 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 276 }; 277 278 /* TSF overload low dword */ 279 enum iwl_rx_phy_data0 { 280 /* info type: HE any */ 281 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 282 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 283 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 284 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 285 /* 1 bit reserved */ 286 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 287 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 288 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 289 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 290 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 291 /* 6 bits reserved */ 292 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 293 }; 294 295 enum iwl_rx_phy_info_type { 296 IWL_RX_PHY_INFO_TYPE_NONE = 0, 297 IWL_RX_PHY_INFO_TYPE_CCK = 1, 298 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 299 IWL_RX_PHY_INFO_TYPE_HT = 3, 300 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 301 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 302 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 303 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 304 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 305 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 306 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 307 }; 308 309 /* TSF overload high dword */ 310 enum iwl_rx_phy_data1 { 311 /* 312 * check this first - if TSF overload is set, 313 * see &enum iwl_rx_phy_info_type 314 */ 315 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 316 317 /* info type: HT/VHT/HE any */ 318 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 319 320 /* info type: HE MU/MU-EXT */ 321 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 322 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 323 324 /* info type: HE any */ 325 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 326 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 327 /* trigger encoded */ 328 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 329 330 /* info type: HE TB/TX-EXT */ 331 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 332 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 333 }; 334 335 /* goes into Metadata DW 7 */ 336 enum iwl_rx_phy_data2 { 337 /* info type: HE MU-EXT */ 338 /* the a1/a2/... is what the PHY/firmware calls the values */ 339 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 340 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 341 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 342 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 343 344 /* info type: HE TB-EXT */ 345 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 346 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 347 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 348 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 349 }; 350 351 /* goes into Metadata DW 8 */ 352 enum iwl_rx_phy_data3 { 353 /* info type: HE MU-EXT */ 354 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 355 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 356 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 357 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 358 }; 359 360 /* goes into Metadata DW 4 high 16 bits */ 361 enum iwl_rx_phy_data4 { 362 /* info type: HE MU-EXT */ 363 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 364 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 365 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 366 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 367 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 368 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 369 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 370 }; 371 372 /** 373 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 374 */ 375 struct iwl_rx_mpdu_desc_v1 { 376 /* DW7 - carries rss_hash only when rpa_en == 1 */ 377 union { 378 /** 379 * @rss_hash: RSS hash value 380 */ 381 __le32 rss_hash; 382 383 /** 384 * @phy_data2: depends on info type (see @phy_data1) 385 */ 386 __le32 phy_data2; 387 }; 388 389 /* DW8 - carries filter_match only when rpa_en == 1 */ 390 union { 391 /** 392 * @filter_match: filter match value 393 */ 394 __le32 filter_match; 395 396 /** 397 * @phy_data3: depends on info type (see @phy_data1) 398 */ 399 __le32 phy_data3; 400 }; 401 402 /* DW9 */ 403 /** 404 * @rate_n_flags: RX rate/flags encoding 405 */ 406 __le32 rate_n_flags; 407 /* DW10 */ 408 /** 409 * @energy_a: energy chain A 410 */ 411 u8 energy_a; 412 /** 413 * @energy_b: energy chain B 414 */ 415 u8 energy_b; 416 /** 417 * @channel: channel number 418 */ 419 u8 channel; 420 /** 421 * @mac_context: MAC context mask 422 */ 423 u8 mac_context; 424 /* DW11 */ 425 /** 426 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 427 */ 428 __le32 gp2_on_air_rise; 429 /* DW12 & DW13 */ 430 union { 431 /** 432 * @tsf_on_air_rise: 433 * TSF value on air rise (INA), only valid if 434 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 435 */ 436 __le64 tsf_on_air_rise; 437 438 struct { 439 /** 440 * @phy_data0: depends on info_type, see @phy_data1 441 */ 442 __le32 phy_data0; 443 /** 444 * @phy_data1: valid only if 445 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 446 * see &enum iwl_rx_phy_data1. 447 */ 448 __le32 phy_data1; 449 }; 450 }; 451 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 452 453 /** 454 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 455 */ 456 struct iwl_rx_mpdu_desc_v3 { 457 /* DW7 - carries filter_match only when rpa_en == 1 */ 458 union { 459 /** 460 * @filter_match: filter match value 461 */ 462 __le32 filter_match; 463 464 /** 465 * @phy_data3: depends on info type (see @phy_data1) 466 */ 467 __le32 phy_data3; 468 }; 469 470 /* DW8 - carries rss_hash only when rpa_en == 1 */ 471 union { 472 /** 473 * @rss_hash: RSS hash value 474 */ 475 __le32 rss_hash; 476 477 /** 478 * @phy_data2: depends on info type (see @phy_data1) 479 */ 480 __le32 phy_data2; 481 }; 482 /* DW9 */ 483 /** 484 * @partial_hash: 31:0 ip/tcp header hash 485 * w/o some fields (such as IP SRC addr) 486 */ 487 __le32 partial_hash; 488 /* DW10 */ 489 /** 490 * @raw_xsum: raw xsum value 491 */ 492 __be16 raw_xsum; 493 /** 494 * @reserved_xsum: reserved high bits in the raw checksum 495 */ 496 __le16 reserved_xsum; 497 /* DW11 */ 498 /** 499 * @rate_n_flags: RX rate/flags encoding 500 */ 501 __le32 rate_n_flags; 502 /* DW12 */ 503 /** 504 * @energy_a: energy chain A 505 */ 506 u8 energy_a; 507 /** 508 * @energy_b: energy chain B 509 */ 510 u8 energy_b; 511 /** 512 * @channel: channel number 513 */ 514 u8 channel; 515 /** 516 * @mac_context: MAC context mask 517 */ 518 u8 mac_context; 519 /* DW13 */ 520 /** 521 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 522 */ 523 __le32 gp2_on_air_rise; 524 /* DW14 & DW15 */ 525 union { 526 /** 527 * @tsf_on_air_rise: 528 * TSF value on air rise (INA), only valid if 529 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 530 */ 531 __le64 tsf_on_air_rise; 532 533 struct { 534 /** 535 * @phy_data0: depends on info_type, see @phy_data1 536 */ 537 __le32 phy_data0; 538 /** 539 * @phy_data1: valid only if 540 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 541 * see &enum iwl_rx_phy_data1. 542 */ 543 __le32 phy_data1; 544 }; 545 }; 546 /* DW16 & DW17 */ 547 /** 548 * @reserved: reserved 549 */ 550 __le32 reserved[2]; 551 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 552 RX_MPDU_RES_START_API_S_VER_5 */ 553 554 /** 555 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 556 */ 557 struct iwl_rx_mpdu_desc { 558 /* DW2 */ 559 /** 560 * @mpdu_len: MPDU length 561 */ 562 __le16 mpdu_len; 563 /** 564 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 565 */ 566 u8 mac_flags1; 567 /** 568 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 569 */ 570 u8 mac_flags2; 571 /* DW3 */ 572 /** 573 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 574 */ 575 u8 amsdu_info; 576 /** 577 * @phy_info: &enum iwl_rx_mpdu_phy_info 578 */ 579 __le16 phy_info; 580 /** 581 * @mac_phy_idx: MAC/PHY index 582 */ 583 u8 mac_phy_idx; 584 /* DW4 - carries csum data only when rpa_en == 1 */ 585 /** 586 * @raw_csum: raw checksum (alledgedly unreliable) 587 */ 588 __le16 raw_csum; 589 590 union { 591 /** 592 * @l3l4_flags: &enum iwl_rx_l3l4_flags 593 */ 594 __le16 l3l4_flags; 595 596 /** 597 * @phy_data4: depends on info type, see phy_data1 598 */ 599 __le16 phy_data4; 600 }; 601 /* DW5 */ 602 /** 603 * @status: &enum iwl_rx_mpdu_status 604 */ 605 __le32 status; 606 607 /* DW6 */ 608 /** 609 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 610 */ 611 __le32 reorder_data; 612 613 union { 614 struct iwl_rx_mpdu_desc_v1 v1; 615 struct iwl_rx_mpdu_desc_v3 v3; 616 }; 617 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 618 RX_MPDU_RES_START_API_S_VER_4, 619 RX_MPDU_RES_START_API_S_VER_5 */ 620 621 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 622 623 #define RX_NO_DATA_CHAIN_A_POS 0 624 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 625 #define RX_NO_DATA_CHAIN_B_POS 8 626 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 627 #define RX_NO_DATA_CHANNEL_POS 16 628 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 629 630 #define RX_NO_DATA_INFO_TYPE_POS 0 631 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 632 #define RX_NO_DATA_INFO_TYPE_NONE 0 633 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 634 #define RX_NO_DATA_INFO_TYPE_NDP 2 635 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 636 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 637 638 #define RX_NO_DATA_INFO_ERR_POS 8 639 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 640 #define RX_NO_DATA_INFO_ERR_NONE 0 641 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 642 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 643 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 644 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 645 646 #define RX_NO_DATA_FRAME_TIME_POS 0 647 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 648 649 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 650 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 651 652 /** 653 * struct iwl_rx_no_data - RX no data descriptor 654 * @info: 7:0 frame type, 15:8 RX error type 655 * @rssi: 7:0 energy chain-A, 656 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 657 * @on_air_rise_time: GP2 during on air rise 658 * @fr_time: frame time 659 * @rate: rate/mcs of frame 660 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 661 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 662 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 663 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 664 */ 665 struct iwl_rx_no_data { 666 __le32 info; 667 __le32 rssi; 668 __le32 on_air_rise_time; 669 __le32 fr_time; 670 __le32 rate; 671 __le32 phy_info[2]; 672 __le32 rx_vec[2]; 673 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 674 TX_NO_DATA_NTFY_API_S_VER_2 */ 675 676 struct iwl_frame_release { 677 u8 baid; 678 u8 reserved; 679 __le16 nssn; 680 }; 681 682 /** 683 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 684 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 685 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 686 */ 687 enum iwl_bar_frame_release_sta_tid { 688 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 689 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 690 }; 691 692 /** 693 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 694 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 695 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 696 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 697 */ 698 enum iwl_bar_frame_release_ba_info { 699 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 700 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 701 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 702 }; 703 704 /** 705 * struct iwl_bar_frame_release - frame release from BAR info 706 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 707 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 708 */ 709 struct iwl_bar_frame_release { 710 __le32 sta_tid; 711 __le32 ba_info; 712 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 713 714 enum iwl_rss_hash_func_en { 715 IWL_RSS_HASH_TYPE_IPV4_TCP, 716 IWL_RSS_HASH_TYPE_IPV4_UDP, 717 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 718 IWL_RSS_HASH_TYPE_IPV6_TCP, 719 IWL_RSS_HASH_TYPE_IPV6_UDP, 720 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 721 }; 722 723 #define IWL_RSS_HASH_KEY_CNT 10 724 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 725 #define IWL_RSS_ENABLE 1 726 727 /** 728 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 729 * 730 * @flags: 1 - enable, 0 - disable 731 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 732 * @reserved: reserved 733 * @secret_key: 320 bit input of random key configuration from driver 734 * @indirection_table: indirection table 735 */ 736 struct iwl_rss_config_cmd { 737 __le32 flags; 738 u8 hash_mask; 739 u8 reserved[3]; 740 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 741 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 742 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 743 744 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 745 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 746 747 /** 748 * struct iwl_rxq_sync_cmd - RXQ notification trigger 749 * 750 * @flags: flags of the notification. bit 0:3 are the sender queue 751 * @rxq_mask: rx queues to send the notification on 752 * @count: number of bytes in payload, should be DWORD aligned 753 * @payload: data to send to rx queues 754 */ 755 struct iwl_rxq_sync_cmd { 756 __le32 flags; 757 __le32 rxq_mask; 758 __le32 count; 759 u8 payload[0]; 760 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 761 762 /** 763 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 764 * sync command 765 * 766 * @count: number of bytes in payload 767 * @payload: data to send to rx queues 768 */ 769 struct iwl_rxq_sync_notification { 770 __le32 count; 771 u8 payload[0]; 772 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 773 774 /** 775 * enum iwl_mvm_pm_event - type of station PM event 776 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 777 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 778 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 779 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 780 */ 781 enum iwl_mvm_pm_event { 782 IWL_MVM_PM_EVENT_AWAKE, 783 IWL_MVM_PM_EVENT_ASLEEP, 784 IWL_MVM_PM_EVENT_UAPSD, 785 IWL_MVM_PM_EVENT_PS_POLL, 786 }; /* PEER_PM_NTFY_API_E_VER_1 */ 787 788 /** 789 * struct iwl_mvm_pm_state_notification - station PM state notification 790 * @sta_id: station ID of the station changing state 791 * @type: the new powersave state, see &enum iwl_mvm_pm_event 792 */ 793 struct iwl_mvm_pm_state_notification { 794 u8 sta_id; 795 u8 type; 796 /* private: */ 797 __le16 reserved; 798 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 799 800 #define BA_WINDOW_STREAMS_MAX 16 801 #define BA_WINDOW_STATUS_TID_MSK 0x000F 802 #define BA_WINDOW_STATUS_STA_ID_POS 4 803 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 804 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 805 806 /** 807 * struct iwl_ba_window_status_notif - reordering window's status notification 808 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 809 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 810 * @start_seq_num: the start sequence number of the bitmap 811 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 812 */ 813 struct iwl_ba_window_status_notif { 814 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 815 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 816 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 817 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 818 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 819 820 /** 821 * struct iwl_rfh_queue_config - RX queue configuration 822 * @q_num: Q num 823 * @enable: enable queue 824 * @reserved: alignment 825 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 826 * @fr_bd_cb: DMA address of freeRB table 827 * @ur_bd_cb: DMA address of used RB table 828 * @fr_bd_wid: Initial index of the free table 829 */ 830 struct iwl_rfh_queue_data { 831 u8 q_num; 832 u8 enable; 833 __le16 reserved; 834 __le64 urbd_stts_wrptr; 835 __le64 fr_bd_cb; 836 __le64 ur_bd_cb; 837 __le32 fr_bd_wid; 838 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 839 840 /** 841 * struct iwl_rfh_queue_config - RX queue configuration 842 * @num_queues: number of queues configured 843 * @reserved: alignment 844 * @data: DMA addresses per-queue 845 */ 846 struct iwl_rfh_queue_config { 847 u8 num_queues; 848 u8 reserved[3]; 849 struct iwl_rfh_queue_data data[0]; 850 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 851 852 #endif /* __iwl_fw_api_rx_h__ */ 853