1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 enum iwl_rx_mpdu_mac_phy_band { 197 /* whether or not this is MAC or LINK depends on the API */ 198 IWL_RX_MPDU_MAC_PHY_BAND_MAC_MASK = 0x0f, 199 IWL_RX_MPDU_MAC_PHY_BAND_LINK_MASK = 0x0f, 200 IWL_RX_MPDU_MAC_PHY_BAND_PHY_MASK = 0x30, 201 IWL_RX_MPDU_MAC_PHY_BAND_BAND_MASK = 0xc0, 202 }; 203 204 enum iwl_rx_l3_proto_values { 205 IWL_RX_L3_TYPE_NONE, 206 IWL_RX_L3_TYPE_IPV4, 207 IWL_RX_L3_TYPE_IPV4_FRAG, 208 IWL_RX_L3_TYPE_IPV6_FRAG, 209 IWL_RX_L3_TYPE_IPV6, 210 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 211 IWL_RX_L3_TYPE_ARP, 212 IWL_RX_L3_TYPE_EAPOL, 213 }; 214 215 #define IWL_RX_L3_PROTO_POS 4 216 217 enum iwl_rx_l3l4_flags { 218 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 219 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 220 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 221 IWL_RX_L3L4_TCP_ACK = BIT(3), 222 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 223 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 224 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 225 }; 226 227 enum iwl_rx_mpdu_status { 228 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 229 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 230 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 231 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 232 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 233 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 234 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 235 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 236 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 237 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 238 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 239 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 240 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 241 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 242 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 243 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 244 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 245 #if defined(__FreeBSD__) 246 IWL_RX_MPDU_STATUS_SEC_ENC_ERR = 0x7 << 8, 247 #endif 248 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 249 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 250 251 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 252 253 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 254 }; 255 256 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 257 258 enum iwl_rx_mpdu_reorder_data { 259 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 260 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 261 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 262 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 263 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 264 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 265 }; 266 267 enum iwl_rx_mpdu_phy_info { 268 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 269 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 270 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 271 /* short preamble is only for CCK, for non-CCK overridden by this */ 272 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 273 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 274 }; 275 276 enum iwl_rx_mpdu_mac_info { 277 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 278 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 279 }; 280 281 /* TSF overload low dword */ 282 enum iwl_rx_phy_he_data0 { 283 /* info type: HE any */ 284 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 285 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 286 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 287 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 288 /* 1 bit reserved */ 289 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 290 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 291 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 292 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 293 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 294 /* 6 bits reserved */ 295 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 296 }; 297 298 /* TSF overload low dword */ 299 enum iwl_rx_phy_eht_data0 { 300 /* info type: EHT any */ 301 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 302 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 303 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 304 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 305 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 306 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 307 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 308 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 309 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 310 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 311 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 312 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 313 /* 2 bits reserved */ 314 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 315 }; 316 317 enum iwl_rx_phy_info_type { 318 IWL_RX_PHY_INFO_TYPE_NONE = 0, 319 IWL_RX_PHY_INFO_TYPE_CCK = 1, 320 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 321 IWL_RX_PHY_INFO_TYPE_HT = 3, 322 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 323 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 324 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 325 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 326 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 327 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 328 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 329 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 330 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 331 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 332 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 333 }; 334 335 /* TSF overload high dword */ 336 enum iwl_rx_phy_common_data1 { 337 /* 338 * check this first - if TSF overload is set, 339 * see &enum iwl_rx_phy_info_type 340 */ 341 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 342 343 /* info type: HT/VHT/HE/EHT any */ 344 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 345 }; 346 347 /* TSF overload high dword For HE rates*/ 348 enum iwl_rx_phy_he_data1 { 349 /* info type: HE MU/MU-EXT */ 350 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 351 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 352 353 /* info type: HE any */ 354 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 355 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 356 /* trigger encoded */ 357 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 358 359 /* info type: HE TB/TX-EXT */ 360 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 361 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 362 }; 363 364 /* TSF overload high dword For EHT-MU/TB rates*/ 365 enum iwl_rx_phy_eht_data1 { 366 /* info type: EHT-MU */ 367 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 368 /* info type: EHT-TB */ 369 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 370 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 371 372 /* info type: EHT any */ 373 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 374 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 375 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 376 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 377 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 378 }; 379 380 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 381 enum iwl_rx_phy_he_data2 { 382 /* info type: HE MU-EXT */ 383 /* the a1/a2/... is what the PHY/firmware calls the values */ 384 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 385 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 386 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 387 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 388 389 /* info type: HE TB-EXT */ 390 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 391 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 392 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 393 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 394 }; 395 396 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 397 enum iwl_rx_phy_he_data3 { 398 /* info type: HE MU-EXT */ 399 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 400 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 401 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 402 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 403 }; 404 405 /* goes into Metadata DW 4 high 16 bits */ 406 enum iwl_rx_phy_he_he_data4 { 407 /* info type: HE MU-EXT */ 408 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 409 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 410 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 411 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 412 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 413 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 414 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 415 }; 416 417 /* goes into Metadata DW 8 (Qu has no EHT) */ 418 enum iwl_rx_phy_eht_data2 { 419 /* info type: EHT-MU-EXT */ 420 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 421 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 422 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 423 424 /* info type: EHT-TB-EXT */ 425 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 426 }; 427 428 /* goes into Metadata DW 7 (Qu has no EHT) */ 429 enum iwl_rx_phy_eht_data3 { 430 /* note: low 8 bits cannot be used */ 431 /* info type: EHT-MU-EXT */ 432 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 433 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 434 }; 435 436 /* goes into Metadata DW 4 */ 437 enum iwl_rx_phy_eht_data4 { 438 /* info type: EHT-MU-EXT */ 439 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 440 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 441 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 442 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 443 }; 444 445 /* goes into Metadata DW 16 */ 446 enum iwl_rx_phy_data5 { 447 /* info type: EHT any */ 448 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 449 /* info type: EHT-TB */ 450 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 451 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 452 /* info type: EHT-MU */ 453 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 454 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 455 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 456 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 457 }; 458 459 /** 460 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 461 */ 462 struct iwl_rx_mpdu_desc_v1 { 463 /* DW7 - carries rss_hash only when rpa_en == 1 */ 464 union { 465 /** 466 * @rss_hash: RSS hash value 467 */ 468 __le32 rss_hash; 469 470 /** 471 * @phy_data2: depends on info type (see @phy_data1) 472 */ 473 __le32 phy_data2; 474 }; 475 476 /* DW8 - carries filter_match only when rpa_en == 1 */ 477 union { 478 /** 479 * @filter_match: filter match value 480 */ 481 __le32 filter_match; 482 483 /** 484 * @phy_data3: depends on info type (see @phy_data1) 485 */ 486 __le32 phy_data3; 487 }; 488 489 /* DW9 */ 490 /** 491 * @rate_n_flags: RX rate/flags encoding 492 */ 493 __le32 rate_n_flags; 494 /* DW10 */ 495 /** 496 * @energy_a: energy chain A 497 */ 498 u8 energy_a; 499 /** 500 * @energy_b: energy chain B 501 */ 502 u8 energy_b; 503 /** 504 * @channel: channel number 505 */ 506 u8 channel; 507 /** 508 * @mac_context: MAC context mask 509 */ 510 u8 mac_context; 511 /* DW11 */ 512 /** 513 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 514 */ 515 __le32 gp2_on_air_rise; 516 /* DW12 & DW13 */ 517 union { 518 /** 519 * @tsf_on_air_rise: 520 * TSF value on air rise (INA), only valid if 521 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 522 */ 523 __le64 tsf_on_air_rise; 524 525 struct { 526 /** 527 * @phy_data0: depends on info_type, see @phy_data1 528 */ 529 __le32 phy_data0; 530 /** 531 * @phy_data1: valid only if 532 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 533 * see &enum iwl_rx_phy_common_data1 or 534 * &enum iwl_rx_phy_he_data1 or 535 * &enum iwl_rx_phy_eht_data1. 536 */ 537 __le32 phy_data1; 538 }; 539 }; 540 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 541 542 /** 543 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 544 */ 545 struct iwl_rx_mpdu_desc_v3 { 546 /* DW7 - carries filter_match only when rpa_en == 1 */ 547 union { 548 /** 549 * @filter_match: filter match value 550 */ 551 __le32 filter_match; 552 553 /** 554 * @phy_data3: depends on info type (see @phy_data1) 555 */ 556 __le32 phy_data3; 557 }; 558 559 /* DW8 - carries rss_hash only when rpa_en == 1 */ 560 union { 561 /** 562 * @rss_hash: RSS hash value 563 */ 564 __le32 rss_hash; 565 566 /** 567 * @phy_data2: depends on info type (see @phy_data1) 568 */ 569 __le32 phy_data2; 570 }; 571 /* DW9 */ 572 /** 573 * @partial_hash: 31:0 ip/tcp header hash 574 * w/o some fields (such as IP SRC addr) 575 */ 576 __le32 partial_hash; 577 /* DW10 */ 578 /** 579 * @raw_xsum: raw xsum value 580 */ 581 __be16 raw_xsum; 582 /** 583 * @reserved_xsum: reserved high bits in the raw checksum 584 */ 585 __le16 reserved_xsum; 586 /* DW11 */ 587 /** 588 * @rate_n_flags: RX rate/flags encoding 589 */ 590 __le32 rate_n_flags; 591 /* DW12 */ 592 /** 593 * @energy_a: energy chain A 594 */ 595 u8 energy_a; 596 /** 597 * @energy_b: energy chain B 598 */ 599 u8 energy_b; 600 /** 601 * @channel: channel number 602 */ 603 u8 channel; 604 /** 605 * @mac_context: MAC context mask 606 */ 607 u8 mac_context; 608 /* DW13 */ 609 /** 610 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 611 */ 612 __le32 gp2_on_air_rise; 613 /* DW14 & DW15 */ 614 union { 615 /** 616 * @tsf_on_air_rise: 617 * TSF value on air rise (INA), only valid if 618 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 619 */ 620 __le64 tsf_on_air_rise; 621 622 struct { 623 /** 624 * @phy_data0: depends on info_type, see @phy_data1 625 */ 626 __le32 phy_data0; 627 /** 628 * @phy_data1: valid only if 629 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 630 * see &enum iwl_rx_phy_data1. 631 */ 632 __le32 phy_data1; 633 }; 634 }; 635 /* DW16 */ 636 /** 637 * @phy_data5: valid only if 638 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 639 * see &enum iwl_rx_phy_data5. 640 */ 641 __le32 phy_data5; 642 /* DW17 */ 643 /** 644 * @reserved: reserved 645 */ 646 __le32 reserved[1]; 647 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 648 * RX_MPDU_RES_START_API_S_VER_5, 649 * RX_MPDU_RES_START_API_S_VER_6 650 */ 651 652 /** 653 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 654 */ 655 struct iwl_rx_mpdu_desc { 656 /* DW2 */ 657 /** 658 * @mpdu_len: MPDU length 659 */ 660 __le16 mpdu_len; 661 /** 662 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 663 */ 664 u8 mac_flags1; 665 /** 666 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 667 */ 668 u8 mac_flags2; 669 /* DW3 */ 670 /** 671 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 672 */ 673 u8 amsdu_info; 674 /** 675 * @phy_info: &enum iwl_rx_mpdu_phy_info 676 */ 677 __le16 phy_info; 678 /** 679 * @mac_phy_band: MAC/link ID, PHY ID, band; 680 * see &enum iwl_rx_mpdu_mac_phy_band 681 */ 682 u8 mac_phy_band; 683 /* DW4 */ 684 union { 685 struct { 686 /* carries csum data only when rpa_en == 1 */ 687 /** 688 * @raw_csum: raw checksum (alledgedly unreliable) 689 */ 690 __le16 raw_csum; 691 692 union { 693 /** 694 * @l3l4_flags: &enum iwl_rx_l3l4_flags 695 */ 696 __le16 l3l4_flags; 697 698 /** 699 * @phy_data4: depends on info type, see phy_data1 700 */ 701 __le16 phy_data4; 702 }; 703 }; 704 /** 705 * @phy_eht_data4: depends on info type, see phy_data1 706 */ 707 __le32 phy_eht_data4; 708 }; 709 /* DW5 */ 710 /** 711 * @status: &enum iwl_rx_mpdu_status 712 */ 713 __le32 status; 714 715 /* DW6 */ 716 /** 717 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 718 */ 719 __le32 reorder_data; 720 721 union { 722 /** 723 * @v1: version 1 of the remaining RX descriptor, 724 * see &struct iwl_rx_mpdu_desc_v1 725 */ 726 struct iwl_rx_mpdu_desc_v1 v1; 727 /** 728 * @v3: version 3 of the remaining RX descriptor, 729 * see &struct iwl_rx_mpdu_desc_v3 730 */ 731 struct iwl_rx_mpdu_desc_v3 v3; 732 }; 733 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 734 * RX_MPDU_RES_START_API_S_VER_4, 735 * RX_MPDU_RES_START_API_S_VER_5, 736 * RX_MPDU_RES_START_API_S_VER_6 737 */ 738 739 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 740 741 #define RX_NO_DATA_CHAIN_A_POS 0 742 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 743 #define RX_NO_DATA_CHAIN_B_POS 8 744 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 745 #define RX_NO_DATA_CHANNEL_POS 16 746 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 747 748 #define RX_NO_DATA_INFO_TYPE_POS 0 749 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 750 #define RX_NO_DATA_INFO_TYPE_NONE 0 751 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 752 #define RX_NO_DATA_INFO_TYPE_NDP 2 753 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 754 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 755 756 #define RX_NO_DATA_INFO_ERR_POS 8 757 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 758 #define RX_NO_DATA_INFO_ERR_NONE 0 759 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 760 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 761 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 762 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 763 #define RX_NO_DATA_INFO_LOW_ENERGY 5 764 765 #define RX_NO_DATA_FRAME_TIME_POS 0 766 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 767 768 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 769 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 770 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 771 772 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 773 enum iwl_rx_usig_a1 { 774 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 775 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 776 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 777 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 778 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 779 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 780 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 781 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 782 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 783 IWL_RX_USIG_A1_RDY = 0x80000000, 784 }; 785 786 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 787 enum iwl_rx_usig_a2_eht { 788 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 789 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 790 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 791 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 792 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 793 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 794 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 795 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 796 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 797 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 798 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 799 }; 800 801 /** 802 * struct iwl_rx_no_data - RX no data descriptor 803 * @info: 7:0 frame type, 15:8 RX error type 804 * @rssi: 7:0 energy chain-A, 805 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 806 * @on_air_rise_time: GP2 during on air rise 807 * @fr_time: frame time 808 * @rate: rate/mcs of frame 809 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 810 * based on &enum iwl_rx_phy_info_type 811 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 812 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 813 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 814 */ 815 struct iwl_rx_no_data { 816 __le32 info; 817 __le32 rssi; 818 __le32 on_air_rise_time; 819 __le32 fr_time; 820 __le32 rate; 821 __le32 phy_info[2]; 822 __le32 rx_vec[2]; 823 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 824 RX_NO_DATA_NTFY_API_S_VER_2 */ 825 826 /** 827 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 828 * @info: 7:0 frame type, 15:8 RX error type 829 * @rssi: 7:0 energy chain-A, 830 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 831 * @on_air_rise_time: GP2 during on air rise 832 * @fr_time: frame time 833 * @rate: rate/mcs of frame, format depends on the notification version 834 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 835 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 836 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 837 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 838 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 839 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 840 */ 841 struct iwl_rx_no_data_ver_3 { 842 __le32 info; 843 __le32 rssi; 844 __le32 on_air_rise_time; 845 __le32 fr_time; 846 __le32 rate; 847 __le32 phy_info[2]; 848 __le32 rx_vec[4]; 849 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_3, _VER_4 */ 850 851 struct iwl_frame_release { 852 u8 baid; 853 u8 reserved; 854 __le16 nssn; 855 }; 856 857 /** 858 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 859 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 860 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 861 */ 862 enum iwl_bar_frame_release_sta_tid { 863 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 864 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 865 }; 866 867 /** 868 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 869 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 870 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 871 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 872 */ 873 enum iwl_bar_frame_release_ba_info { 874 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 875 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 876 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 877 }; 878 879 /** 880 * struct iwl_bar_frame_release - frame release from BAR info 881 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 882 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 883 */ 884 struct iwl_bar_frame_release { 885 __le32 sta_tid; 886 __le32 ba_info; 887 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 888 889 enum iwl_rss_hash_func_en { 890 IWL_RSS_HASH_TYPE_IPV4_TCP, 891 IWL_RSS_HASH_TYPE_IPV4_UDP, 892 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 893 IWL_RSS_HASH_TYPE_IPV6_TCP, 894 IWL_RSS_HASH_TYPE_IPV6_UDP, 895 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 896 }; 897 898 #define IWL_RSS_HASH_KEY_CNT 10 899 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 900 #define IWL_RSS_ENABLE 1 901 902 /** 903 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 904 * 905 * @flags: 1 - enable, 0 - disable 906 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 907 * @reserved: reserved 908 * @secret_key: 320 bit input of random key configuration from driver 909 * @indirection_table: indirection table 910 */ 911 struct iwl_rss_config_cmd { 912 __le32 flags; 913 u8 hash_mask; 914 u8 reserved[3]; 915 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 916 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 917 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 918 919 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 920 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 921 922 /** 923 * struct iwl_rxq_sync_cmd - RXQ notification trigger 924 * 925 * @flags: flags of the notification. bit 0:3 are the sender queue 926 * @rxq_mask: rx queues to send the notification on 927 * @count: number of bytes in payload, should be DWORD aligned 928 * @payload: data to send to rx queues 929 */ 930 struct iwl_rxq_sync_cmd { 931 __le32 flags; 932 __le32 rxq_mask; 933 __le32 count; 934 #if defined(__linux__) 935 u8 payload[]; 936 #elif defined(__FreeBSD__) 937 u8 payload[0]; 938 #endif 939 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 940 941 /** 942 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 943 * sync command 944 * 945 * @count: number of bytes in payload 946 * @payload: data to send to rx queues 947 */ 948 struct iwl_rxq_sync_notification { 949 __le32 count; 950 #if defined(__linux__) 951 u8 payload[]; 952 #elif defined(__FreeBSD__) 953 u8 payload[0]; 954 #endif 955 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 956 957 /** 958 * enum iwl_mvm_pm_event - type of station PM event 959 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 960 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 961 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 962 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 963 */ 964 enum iwl_mvm_pm_event { 965 IWL_MVM_PM_EVENT_AWAKE, 966 IWL_MVM_PM_EVENT_ASLEEP, 967 IWL_MVM_PM_EVENT_UAPSD, 968 IWL_MVM_PM_EVENT_PS_POLL, 969 }; /* PEER_PM_NTFY_API_E_VER_1 */ 970 971 /** 972 * struct iwl_mvm_pm_state_notification - station PM state notification 973 * @sta_id: station ID of the station changing state 974 * @type: the new powersave state, see &enum iwl_mvm_pm_event 975 */ 976 struct iwl_mvm_pm_state_notification { 977 u8 sta_id; 978 u8 type; 979 /* private: */ 980 __le16 reserved; 981 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 982 983 #define BA_WINDOW_STREAMS_MAX 16 984 #define BA_WINDOW_STATUS_TID_MSK 0x000F 985 #define BA_WINDOW_STATUS_STA_ID_POS 4 986 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 987 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 988 989 /** 990 * struct iwl_ba_window_status_notif - reordering window's status notification 991 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 992 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 993 * @start_seq_num: the start sequence number of the bitmap 994 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 995 */ 996 struct iwl_ba_window_status_notif { 997 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 998 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 999 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 1000 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 1001 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 1002 1003 /** 1004 * struct iwl_rfh_queue_data - RX queue configuration 1005 * @q_num: Q num 1006 * @enable: enable queue 1007 * @reserved: alignment 1008 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 1009 * @fr_bd_cb: DMA address of freeRB table 1010 * @ur_bd_cb: DMA address of used RB table 1011 * @fr_bd_wid: Initial index of the free table 1012 */ 1013 struct iwl_rfh_queue_data { 1014 u8 q_num; 1015 u8 enable; 1016 __le16 reserved; 1017 __le64 urbd_stts_wrptr; 1018 __le64 fr_bd_cb; 1019 __le64 ur_bd_cb; 1020 __le32 fr_bd_wid; 1021 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1022 1023 /** 1024 * struct iwl_rfh_queue_config - RX queue configuration 1025 * @num_queues: number of queues configured 1026 * @reserved: alignment 1027 * @data: DMA addresses per-queue 1028 */ 1029 struct iwl_rfh_queue_config { 1030 u8 num_queues; 1031 u8 reserved[3]; 1032 #if defined(__linux__) 1033 struct iwl_rfh_queue_data data[]; 1034 #elif defined(__FreeBSD__) 1035 struct iwl_rfh_queue_data data[0]; 1036 #endif 1037 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1038 1039 /** 1040 * struct iwl_beacon_filter_notif_v1 - beacon filter notification 1041 * @average_energy: average energy for the received beacon 1042 * @mac_id: MAC ID the beacon was received for 1043 */ 1044 struct iwl_beacon_filter_notif_v1 { 1045 __le32 average_energy; 1046 __le32 mac_id; 1047 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_1 */ 1048 1049 /** 1050 * struct iwl_beacon_filter_notif - beacon filter notification 1051 * @average_energy: average energy for the received beacon 1052 * @link_id: link ID the beacon was received for 1053 */ 1054 struct iwl_beacon_filter_notif { 1055 __le32 average_energy; 1056 __le32 link_id; 1057 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_2 */ 1058 1059 #endif /* __iwl_fw_api_rx_h__ */ 1060