1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 #define RX_MPDU_BAND_POS 6 197 #define RX_MPDU_BAND_MASK 0xC0 198 #define BAND_IN_RX_STATUS(_val) \ 199 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 200 201 enum iwl_rx_l3_proto_values { 202 IWL_RX_L3_TYPE_NONE, 203 IWL_RX_L3_TYPE_IPV4, 204 IWL_RX_L3_TYPE_IPV4_FRAG, 205 IWL_RX_L3_TYPE_IPV6_FRAG, 206 IWL_RX_L3_TYPE_IPV6, 207 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 208 IWL_RX_L3_TYPE_ARP, 209 IWL_RX_L3_TYPE_EAPOL, 210 }; 211 212 #define IWL_RX_L3_PROTO_POS 4 213 214 enum iwl_rx_l3l4_flags { 215 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 216 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 217 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 218 IWL_RX_L3L4_TCP_ACK = BIT(3), 219 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 220 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 221 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 222 }; 223 224 enum iwl_rx_mpdu_status { 225 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 226 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 227 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 228 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 229 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 230 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 231 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 232 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 233 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 234 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 235 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 236 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 237 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 238 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 239 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 240 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 241 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 242 #if defined(__FreeBSD__) 243 IWL_RX_MPDU_STATUS_SEC_ENC_ERR = 0x7 << 8, 244 #endif 245 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 246 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 247 248 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 249 250 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 251 }; 252 253 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 254 255 enum iwl_rx_mpdu_reorder_data { 256 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 257 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 258 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 259 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 260 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 261 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 262 }; 263 264 enum iwl_rx_mpdu_phy_info { 265 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 266 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 267 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 268 /* short preamble is only for CCK, for non-CCK overridden by this */ 269 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 270 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 271 }; 272 273 enum iwl_rx_mpdu_mac_info { 274 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 275 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 276 }; 277 278 /* TSF overload low dword */ 279 enum iwl_rx_phy_he_data0 { 280 /* info type: HE any */ 281 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 282 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 283 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 284 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 285 /* 1 bit reserved */ 286 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 287 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 288 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 289 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 290 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 291 /* 6 bits reserved */ 292 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 293 }; 294 295 /* TSF overload low dword */ 296 enum iwl_rx_phy_eht_data0 { 297 /* info type: EHT any */ 298 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 299 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 300 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 301 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 302 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 303 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 304 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 305 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 306 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 307 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 308 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 309 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 310 /* 2 bits reserved */ 311 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 312 }; 313 314 enum iwl_rx_phy_info_type { 315 IWL_RX_PHY_INFO_TYPE_NONE = 0, 316 IWL_RX_PHY_INFO_TYPE_CCK = 1, 317 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 318 IWL_RX_PHY_INFO_TYPE_HT = 3, 319 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 320 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 321 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 322 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 323 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 324 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 325 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 326 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 327 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 328 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 329 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 330 }; 331 332 /* TSF overload high dword */ 333 enum iwl_rx_phy_common_data1 { 334 /* 335 * check this first - if TSF overload is set, 336 * see &enum iwl_rx_phy_info_type 337 */ 338 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 339 340 /* info type: HT/VHT/HE/EHT any */ 341 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 342 }; 343 344 /* TSF overload high dword For HE rates*/ 345 enum iwl_rx_phy_he_data1 { 346 /* info type: HE MU/MU-EXT */ 347 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 348 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 349 350 /* info type: HE any */ 351 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 352 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 353 /* trigger encoded */ 354 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 355 356 /* info type: HE TB/TX-EXT */ 357 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 358 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 359 }; 360 361 /* TSF overload high dword For EHT-MU/TB rates*/ 362 enum iwl_rx_phy_eht_data1 { 363 /* info type: EHT-MU */ 364 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 365 /* info type: EHT-TB */ 366 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 367 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 368 369 /* info type: EHT any */ 370 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 371 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 372 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 373 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 374 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 375 }; 376 377 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 378 enum iwl_rx_phy_he_data2 { 379 /* info type: HE MU-EXT */ 380 /* the a1/a2/... is what the PHY/firmware calls the values */ 381 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 382 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 383 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 384 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 385 386 /* info type: HE TB-EXT */ 387 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 388 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 389 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 390 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 391 }; 392 393 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 394 enum iwl_rx_phy_he_data3 { 395 /* info type: HE MU-EXT */ 396 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 397 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 398 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 399 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 400 }; 401 402 /* goes into Metadata DW 4 high 16 bits */ 403 enum iwl_rx_phy_he_he_data4 { 404 /* info type: HE MU-EXT */ 405 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 406 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 407 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 408 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 409 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 410 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 411 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 412 }; 413 414 /* goes into Metadata DW 8 (Qu has no EHT) */ 415 enum iwl_rx_phy_eht_data2 { 416 /* info type: EHT-MU-EXT */ 417 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 418 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 419 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 420 421 /* info type: EHT-TB-EXT */ 422 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 423 }; 424 425 /* goes into Metadata DW 7 (Qu has no EHT) */ 426 enum iwl_rx_phy_eht_data3 { 427 /* note: low 8 bits cannot be used */ 428 /* info type: EHT-MU-EXT */ 429 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 430 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 431 }; 432 433 /* goes into Metadata DW 4 */ 434 enum iwl_rx_phy_eht_data4 { 435 /* info type: EHT-MU-EXT */ 436 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 437 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 438 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 439 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 440 }; 441 442 /* goes into Metadata DW 16 */ 443 enum iwl_rx_phy_data5 { 444 /* info type: EHT any */ 445 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 446 /* info type: EHT-TB */ 447 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 448 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 449 /* info type: EHT-MU */ 450 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 451 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 452 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 453 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 454 }; 455 456 /** 457 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 458 */ 459 struct iwl_rx_mpdu_desc_v1 { 460 /* DW7 - carries rss_hash only when rpa_en == 1 */ 461 union { 462 /** 463 * @rss_hash: RSS hash value 464 */ 465 __le32 rss_hash; 466 467 /** 468 * @phy_data2: depends on info type (see @phy_data1) 469 */ 470 __le32 phy_data2; 471 }; 472 473 /* DW8 - carries filter_match only when rpa_en == 1 */ 474 union { 475 /** 476 * @filter_match: filter match value 477 */ 478 __le32 filter_match; 479 480 /** 481 * @phy_data3: depends on info type (see @phy_data1) 482 */ 483 __le32 phy_data3; 484 }; 485 486 /* DW9 */ 487 /** 488 * @rate_n_flags: RX rate/flags encoding 489 */ 490 __le32 rate_n_flags; 491 /* DW10 */ 492 /** 493 * @energy_a: energy chain A 494 */ 495 u8 energy_a; 496 /** 497 * @energy_b: energy chain B 498 */ 499 u8 energy_b; 500 /** 501 * @channel: channel number 502 */ 503 u8 channel; 504 /** 505 * @mac_context: MAC context mask 506 */ 507 u8 mac_context; 508 /* DW11 */ 509 /** 510 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 511 */ 512 __le32 gp2_on_air_rise; 513 /* DW12 & DW13 */ 514 union { 515 /** 516 * @tsf_on_air_rise: 517 * TSF value on air rise (INA), only valid if 518 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 519 */ 520 __le64 tsf_on_air_rise; 521 522 struct { 523 /** 524 * @phy_data0: depends on info_type, see @phy_data1 525 */ 526 __le32 phy_data0; 527 /** 528 * @phy_data1: valid only if 529 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 530 * see &enum iwl_rx_phy_common_data1 or 531 * &enum iwl_rx_phy_he_data1 or 532 * &enum iwl_rx_phy_eht_data1. 533 */ 534 __le32 phy_data1; 535 }; 536 }; 537 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 538 539 /** 540 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 541 */ 542 struct iwl_rx_mpdu_desc_v3 { 543 /* DW7 - carries filter_match only when rpa_en == 1 */ 544 union { 545 /** 546 * @filter_match: filter match value 547 */ 548 __le32 filter_match; 549 550 /** 551 * @phy_data3: depends on info type (see @phy_data1) 552 */ 553 __le32 phy_data3; 554 }; 555 556 /* DW8 - carries rss_hash only when rpa_en == 1 */ 557 union { 558 /** 559 * @rss_hash: RSS hash value 560 */ 561 __le32 rss_hash; 562 563 /** 564 * @phy_data2: depends on info type (see @phy_data1) 565 */ 566 __le32 phy_data2; 567 }; 568 /* DW9 */ 569 /** 570 * @partial_hash: 31:0 ip/tcp header hash 571 * w/o some fields (such as IP SRC addr) 572 */ 573 __le32 partial_hash; 574 /* DW10 */ 575 /** 576 * @raw_xsum: raw xsum value 577 */ 578 __be16 raw_xsum; 579 /** 580 * @reserved_xsum: reserved high bits in the raw checksum 581 */ 582 __le16 reserved_xsum; 583 /* DW11 */ 584 /** 585 * @rate_n_flags: RX rate/flags encoding 586 */ 587 __le32 rate_n_flags; 588 /* DW12 */ 589 /** 590 * @energy_a: energy chain A 591 */ 592 u8 energy_a; 593 /** 594 * @energy_b: energy chain B 595 */ 596 u8 energy_b; 597 /** 598 * @channel: channel number 599 */ 600 u8 channel; 601 /** 602 * @mac_context: MAC context mask 603 */ 604 u8 mac_context; 605 /* DW13 */ 606 /** 607 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 608 */ 609 __le32 gp2_on_air_rise; 610 /* DW14 & DW15 */ 611 union { 612 /** 613 * @tsf_on_air_rise: 614 * TSF value on air rise (INA), only valid if 615 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 616 */ 617 __le64 tsf_on_air_rise; 618 619 struct { 620 /** 621 * @phy_data0: depends on info_type, see @phy_data1 622 */ 623 __le32 phy_data0; 624 /** 625 * @phy_data1: valid only if 626 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 627 * see &enum iwl_rx_phy_data1. 628 */ 629 __le32 phy_data1; 630 }; 631 }; 632 /* DW16 */ 633 /** 634 * @phy_data5: valid only if 635 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 636 * see &enum iwl_rx_phy_data5. 637 */ 638 __le32 phy_data5; 639 /* DW17 */ 640 /** 641 * @reserved: reserved 642 */ 643 __le32 reserved[1]; 644 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 645 RX_MPDU_RES_START_API_S_VER_5 */ 646 647 /** 648 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 649 */ 650 struct iwl_rx_mpdu_desc { 651 /* DW2 */ 652 /** 653 * @mpdu_len: MPDU length 654 */ 655 __le16 mpdu_len; 656 /** 657 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 658 */ 659 u8 mac_flags1; 660 /** 661 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 662 */ 663 u8 mac_flags2; 664 /* DW3 */ 665 /** 666 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 667 */ 668 u8 amsdu_info; 669 /** 670 * @phy_info: &enum iwl_rx_mpdu_phy_info 671 */ 672 __le16 phy_info; 673 /** 674 * @mac_phy_idx: MAC/PHY index 675 */ 676 u8 mac_phy_idx; 677 /* DW4 */ 678 union { 679 struct { 680 /* carries csum data only when rpa_en == 1 */ 681 /** 682 * @raw_csum: raw checksum (alledgedly unreliable) 683 */ 684 __le16 raw_csum; 685 686 union { 687 /** 688 * @l3l4_flags: &enum iwl_rx_l3l4_flags 689 */ 690 __le16 l3l4_flags; 691 692 /** 693 * @phy_data4: depends on info type, see phy_data1 694 */ 695 __le16 phy_data4; 696 }; 697 }; 698 /** 699 * @phy_eht_data4: depends on info type, see phy_data1 700 */ 701 __le32 phy_eht_data4; 702 }; 703 /* DW5 */ 704 /** 705 * @status: &enum iwl_rx_mpdu_status 706 */ 707 __le32 status; 708 709 /* DW6 */ 710 /** 711 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 712 */ 713 __le32 reorder_data; 714 715 union { 716 /** 717 * @v1: version 1 of the remaining RX descriptor, 718 * see &struct iwl_rx_mpdu_desc_v1 719 */ 720 struct iwl_rx_mpdu_desc_v1 v1; 721 /** 722 * @v3: version 3 of the remaining RX descriptor, 723 * see &struct iwl_rx_mpdu_desc_v3 724 */ 725 struct iwl_rx_mpdu_desc_v3 v3; 726 }; 727 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 728 RX_MPDU_RES_START_API_S_VER_4, 729 RX_MPDU_RES_START_API_S_VER_5 */ 730 731 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 732 733 #define RX_NO_DATA_CHAIN_A_POS 0 734 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 735 #define RX_NO_DATA_CHAIN_B_POS 8 736 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 737 #define RX_NO_DATA_CHANNEL_POS 16 738 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 739 740 #define RX_NO_DATA_INFO_TYPE_POS 0 741 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 742 #define RX_NO_DATA_INFO_TYPE_NONE 0 743 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 744 #define RX_NO_DATA_INFO_TYPE_NDP 2 745 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 746 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 747 748 #define RX_NO_DATA_INFO_ERR_POS 8 749 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 750 #define RX_NO_DATA_INFO_ERR_NONE 0 751 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 752 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 753 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 754 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 755 #define RX_NO_DATA_INFO_LOW_ENERGY 5 756 757 #define RX_NO_DATA_FRAME_TIME_POS 0 758 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 759 760 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 761 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 762 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 763 764 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 765 enum iwl_rx_usig_a1 { 766 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 767 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 768 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 769 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 770 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 771 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 772 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 773 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 774 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 775 IWL_RX_USIG_A1_RDY = 0x80000000, 776 }; 777 778 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 779 enum iwl_rx_usig_a2_eht { 780 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 781 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 782 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 783 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 784 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 785 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 786 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 787 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 788 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 789 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 790 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 791 }; 792 793 /** 794 * struct iwl_rx_no_data - RX no data descriptor 795 * @info: 7:0 frame type, 15:8 RX error type 796 * @rssi: 7:0 energy chain-A, 797 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 798 * @on_air_rise_time: GP2 during on air rise 799 * @fr_time: frame time 800 * @rate: rate/mcs of frame 801 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 802 * based on &enum iwl_rx_phy_info_type 803 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 804 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 805 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 806 */ 807 struct iwl_rx_no_data { 808 __le32 info; 809 __le32 rssi; 810 __le32 on_air_rise_time; 811 __le32 fr_time; 812 __le32 rate; 813 __le32 phy_info[2]; 814 __le32 rx_vec[2]; 815 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 816 RX_NO_DATA_NTFY_API_S_VER_2 */ 817 818 /** 819 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 820 * @info: 7:0 frame type, 15:8 RX error type 821 * @rssi: 7:0 energy chain-A, 822 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 823 * @on_air_rise_time: GP2 during on air rise 824 * @fr_time: frame time 825 * @rate: rate/mcs of frame 826 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 827 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 828 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 829 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 830 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 831 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 832 */ 833 struct iwl_rx_no_data_ver_3 { 834 __le32 info; 835 __le32 rssi; 836 __le32 on_air_rise_time; 837 __le32 fr_time; 838 __le32 rate; 839 __le32 phy_info[2]; 840 __le32 rx_vec[4]; 841 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 842 RX_NO_DATA_NTFY_API_S_VER_2 843 RX_NO_DATA_NTFY_API_S_VER_3 */ 844 845 struct iwl_frame_release { 846 u8 baid; 847 u8 reserved; 848 __le16 nssn; 849 }; 850 851 /** 852 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 853 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 854 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 855 */ 856 enum iwl_bar_frame_release_sta_tid { 857 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 858 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 859 }; 860 861 /** 862 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 863 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 864 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 865 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 866 */ 867 enum iwl_bar_frame_release_ba_info { 868 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 869 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 870 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 871 }; 872 873 /** 874 * struct iwl_bar_frame_release - frame release from BAR info 875 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 876 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 877 */ 878 struct iwl_bar_frame_release { 879 __le32 sta_tid; 880 __le32 ba_info; 881 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 882 883 enum iwl_rss_hash_func_en { 884 IWL_RSS_HASH_TYPE_IPV4_TCP, 885 IWL_RSS_HASH_TYPE_IPV4_UDP, 886 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 887 IWL_RSS_HASH_TYPE_IPV6_TCP, 888 IWL_RSS_HASH_TYPE_IPV6_UDP, 889 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 890 }; 891 892 #define IWL_RSS_HASH_KEY_CNT 10 893 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 894 #define IWL_RSS_ENABLE 1 895 896 /** 897 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 898 * 899 * @flags: 1 - enable, 0 - disable 900 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 901 * @reserved: reserved 902 * @secret_key: 320 bit input of random key configuration from driver 903 * @indirection_table: indirection table 904 */ 905 struct iwl_rss_config_cmd { 906 __le32 flags; 907 u8 hash_mask; 908 u8 reserved[3]; 909 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 910 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 911 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 912 913 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 914 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 915 916 /** 917 * struct iwl_rxq_sync_cmd - RXQ notification trigger 918 * 919 * @flags: flags of the notification. bit 0:3 are the sender queue 920 * @rxq_mask: rx queues to send the notification on 921 * @count: number of bytes in payload, should be DWORD aligned 922 * @payload: data to send to rx queues 923 */ 924 struct iwl_rxq_sync_cmd { 925 __le32 flags; 926 __le32 rxq_mask; 927 __le32 count; 928 #if defined(__linux__) 929 u8 payload[]; 930 #elif defined(__FreeBSD__) 931 u8 payload[0]; 932 #endif 933 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 934 935 /** 936 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 937 * sync command 938 * 939 * @count: number of bytes in payload 940 * @payload: data to send to rx queues 941 */ 942 struct iwl_rxq_sync_notification { 943 __le32 count; 944 #if defined(__linux__) 945 u8 payload[]; 946 #elif defined(__FreeBSD__) 947 u8 payload[0]; 948 #endif 949 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 950 951 /** 952 * enum iwl_mvm_pm_event - type of station PM event 953 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 954 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 955 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 956 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 957 */ 958 enum iwl_mvm_pm_event { 959 IWL_MVM_PM_EVENT_AWAKE, 960 IWL_MVM_PM_EVENT_ASLEEP, 961 IWL_MVM_PM_EVENT_UAPSD, 962 IWL_MVM_PM_EVENT_PS_POLL, 963 }; /* PEER_PM_NTFY_API_E_VER_1 */ 964 965 /** 966 * struct iwl_mvm_pm_state_notification - station PM state notification 967 * @sta_id: station ID of the station changing state 968 * @type: the new powersave state, see &enum iwl_mvm_pm_event 969 */ 970 struct iwl_mvm_pm_state_notification { 971 u8 sta_id; 972 u8 type; 973 /* private: */ 974 __le16 reserved; 975 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 976 977 #define BA_WINDOW_STREAMS_MAX 16 978 #define BA_WINDOW_STATUS_TID_MSK 0x000F 979 #define BA_WINDOW_STATUS_STA_ID_POS 4 980 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 981 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 982 983 /** 984 * struct iwl_ba_window_status_notif - reordering window's status notification 985 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 986 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 987 * @start_seq_num: the start sequence number of the bitmap 988 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 989 */ 990 struct iwl_ba_window_status_notif { 991 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 992 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 993 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 994 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 995 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 996 997 /** 998 * struct iwl_rfh_queue_data - RX queue configuration 999 * @q_num: Q num 1000 * @enable: enable queue 1001 * @reserved: alignment 1002 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 1003 * @fr_bd_cb: DMA address of freeRB table 1004 * @ur_bd_cb: DMA address of used RB table 1005 * @fr_bd_wid: Initial index of the free table 1006 */ 1007 struct iwl_rfh_queue_data { 1008 u8 q_num; 1009 u8 enable; 1010 __le16 reserved; 1011 __le64 urbd_stts_wrptr; 1012 __le64 fr_bd_cb; 1013 __le64 ur_bd_cb; 1014 __le32 fr_bd_wid; 1015 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1016 1017 /** 1018 * struct iwl_rfh_queue_config - RX queue configuration 1019 * @num_queues: number of queues configured 1020 * @reserved: alignment 1021 * @data: DMA addresses per-queue 1022 */ 1023 struct iwl_rfh_queue_config { 1024 u8 num_queues; 1025 u8 reserved[3]; 1026 #if defined(__linux__) 1027 struct iwl_rfh_queue_data data[]; 1028 #elif defined(__FreeBSD__) 1029 struct iwl_rfh_queue_data data[0]; 1030 #endif 1031 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1032 1033 #endif /* __iwl_fw_api_rx_h__ */ 1034