1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 #define RX_MPDU_BAND_POS 6 197 #define RX_MPDU_BAND_MASK 0xC0 198 #define BAND_IN_RX_STATUS(_val) \ 199 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 200 201 enum iwl_rx_l3_proto_values { 202 IWL_RX_L3_TYPE_NONE, 203 IWL_RX_L3_TYPE_IPV4, 204 IWL_RX_L3_TYPE_IPV4_FRAG, 205 IWL_RX_L3_TYPE_IPV6_FRAG, 206 IWL_RX_L3_TYPE_IPV6, 207 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 208 IWL_RX_L3_TYPE_ARP, 209 IWL_RX_L3_TYPE_EAPOL, 210 }; 211 212 #define IWL_RX_L3_PROTO_POS 4 213 214 enum iwl_rx_l3l4_flags { 215 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 216 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 217 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 218 IWL_RX_L3L4_TCP_ACK = BIT(3), 219 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 220 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 221 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 222 }; 223 224 enum iwl_rx_mpdu_status { 225 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 226 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 227 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 228 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 229 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 230 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 231 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 232 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 233 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 234 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 235 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 236 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 237 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 238 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 239 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 240 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 241 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 242 #if defined(__FreeBSD__) 243 IWL_RX_MPDU_STATUS_SEC_ENC_ERR = 0x7 << 8, 244 #endif 245 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 246 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 247 248 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 249 250 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 251 }; 252 253 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 254 255 enum iwl_rx_mpdu_reorder_data { 256 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 257 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 258 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 259 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 260 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 261 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 262 }; 263 264 enum iwl_rx_mpdu_phy_info { 265 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 266 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 267 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 268 /* short preamble is only for CCK, for non-CCK overridden by this */ 269 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 270 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 271 }; 272 273 enum iwl_rx_mpdu_mac_info { 274 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 275 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 276 }; 277 278 /* TSF overload low dword */ 279 enum iwl_rx_phy_he_data0 { 280 /* info type: HE any */ 281 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 282 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 283 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 284 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 285 /* 1 bit reserved */ 286 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 287 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 288 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 289 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 290 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 291 /* 6 bits reserved */ 292 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 293 }; 294 295 /* TSF overload low dword */ 296 enum iwl_rx_phy_eht_data0 { 297 /* info type: EHT any */ 298 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 299 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 300 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 301 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 302 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 303 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 304 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 305 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 306 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 307 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 308 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 309 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 310 /* 2 bits reserved */ 311 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 312 }; 313 314 enum iwl_rx_phy_info_type { 315 IWL_RX_PHY_INFO_TYPE_NONE = 0, 316 IWL_RX_PHY_INFO_TYPE_CCK = 1, 317 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 318 IWL_RX_PHY_INFO_TYPE_HT = 3, 319 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 320 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 321 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 322 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 323 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 324 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 325 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 326 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 327 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 328 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 329 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 330 }; 331 332 /* TSF overload high dword */ 333 enum iwl_rx_phy_common_data1 { 334 /* 335 * check this first - if TSF overload is set, 336 * see &enum iwl_rx_phy_info_type 337 */ 338 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 339 340 /* info type: HT/VHT/HE/EHT any */ 341 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 342 }; 343 344 /* TSF overload high dword For HE rates*/ 345 enum iwl_rx_phy_he_data1 { 346 /* info type: HE MU/MU-EXT */ 347 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 348 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 349 350 /* info type: HE any */ 351 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 352 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 353 /* trigger encoded */ 354 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 355 356 /* info type: HE TB/TX-EXT */ 357 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 358 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 359 }; 360 361 /* TSF overload high dword For EHT-MU/TB rates*/ 362 enum iwl_rx_phy_eht_data1 { 363 /* info type: EHT-MU */ 364 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 365 /* info type: EHT-TB */ 366 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 367 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 368 369 /* info type: EHT any */ 370 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 371 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 372 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 373 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 374 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 375 }; 376 377 /* goes into Metadata DW 7 */ 378 enum iwl_rx_phy_he_data2 { 379 /* info type: HE MU-EXT */ 380 /* the a1/a2/... is what the PHY/firmware calls the values */ 381 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 382 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 383 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 384 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 385 386 /* info type: HE TB-EXT */ 387 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 388 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 389 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 390 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 391 }; 392 393 /* goes into Metadata DW 8 */ 394 enum iwl_rx_phy_he_data3 { 395 /* info type: HE MU-EXT */ 396 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 397 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 398 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 399 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 400 }; 401 402 /* goes into Metadata DW 4 high 16 bits */ 403 enum iwl_rx_phy_he_he_data4 { 404 /* info type: HE MU-EXT */ 405 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 406 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 407 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 408 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 409 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 410 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 411 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 412 }; 413 414 /* goes into Metadata DW 7 */ 415 enum iwl_rx_phy_eht_data2 { 416 /* info type: EHT-MU-EXT */ 417 /* OFDM_RX_VECTOR_COMMON_RU_ALLOC_0_OUT */ 418 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 419 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 420 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 421 422 /* info type: EHT-TB-EXT */ 423 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 424 }; 425 426 /* goes into Metadata DW 8 */ 427 enum iwl_rx_phy_eht_data3 { 428 /* info type: EHT-MU-EXT */ 429 /* OFDM_RX_VECTOR_COMMON_RU_ALLOC_1_OUT */ 430 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_B2 = 0x000001ff, 431 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 432 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 433 }; 434 435 /* goes into Metadata DW 4 */ 436 enum iwl_rx_phy_eht_data4 { 437 /* info type: EHT-MU-EXT */ 438 /* OFDM_RX_VECTOR_COMMON_RU_ALLOC_2_OUT */ 439 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 440 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 441 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 442 }; 443 444 /* goes into Metadata DW 16 */ 445 enum iwl_rx_phy_data5 { 446 /* info type: EHT any */ 447 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 448 /* info type: EHT-TB */ 449 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 450 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 451 /* info type: EHT-MU */ 452 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 453 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 454 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 455 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 456 }; 457 458 /** 459 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 460 */ 461 struct iwl_rx_mpdu_desc_v1 { 462 /* DW7 - carries rss_hash only when rpa_en == 1 */ 463 union { 464 /** 465 * @rss_hash: RSS hash value 466 */ 467 __le32 rss_hash; 468 469 /** 470 * @phy_data2: depends on info type (see @phy_data1) 471 */ 472 __le32 phy_data2; 473 }; 474 475 /* DW8 - carries filter_match only when rpa_en == 1 */ 476 union { 477 /** 478 * @filter_match: filter match value 479 */ 480 __le32 filter_match; 481 482 /** 483 * @phy_data3: depends on info type (see @phy_data1) 484 */ 485 __le32 phy_data3; 486 }; 487 488 /* DW9 */ 489 /** 490 * @rate_n_flags: RX rate/flags encoding 491 */ 492 __le32 rate_n_flags; 493 /* DW10 */ 494 /** 495 * @energy_a: energy chain A 496 */ 497 u8 energy_a; 498 /** 499 * @energy_b: energy chain B 500 */ 501 u8 energy_b; 502 /** 503 * @channel: channel number 504 */ 505 u8 channel; 506 /** 507 * @mac_context: MAC context mask 508 */ 509 u8 mac_context; 510 /* DW11 */ 511 /** 512 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 513 */ 514 __le32 gp2_on_air_rise; 515 /* DW12 & DW13 */ 516 union { 517 /** 518 * @tsf_on_air_rise: 519 * TSF value on air rise (INA), only valid if 520 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 521 */ 522 __le64 tsf_on_air_rise; 523 524 struct { 525 /** 526 * @phy_data0: depends on info_type, see @phy_data1 527 */ 528 __le32 phy_data0; 529 /** 530 * @phy_data1: valid only if 531 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 532 * see &enum iwl_rx_phy_common_data1 or 533 * &enum iwl_rx_phy_he_data1 or 534 * &enum iwl_rx_phy_eht_data1. 535 */ 536 __le32 phy_data1; 537 }; 538 }; 539 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 540 541 /** 542 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 543 */ 544 struct iwl_rx_mpdu_desc_v3 { 545 /* DW7 - carries filter_match only when rpa_en == 1 */ 546 union { 547 /** 548 * @filter_match: filter match value 549 */ 550 __le32 filter_match; 551 552 /** 553 * @phy_data3: depends on info type (see @phy_data1) 554 */ 555 __le32 phy_data3; 556 }; 557 558 /* DW8 - carries rss_hash only when rpa_en == 1 */ 559 union { 560 /** 561 * @rss_hash: RSS hash value 562 */ 563 __le32 rss_hash; 564 565 /** 566 * @phy_data2: depends on info type (see @phy_data1) 567 */ 568 __le32 phy_data2; 569 }; 570 /* DW9 */ 571 /** 572 * @partial_hash: 31:0 ip/tcp header hash 573 * w/o some fields (such as IP SRC addr) 574 */ 575 __le32 partial_hash; 576 /* DW10 */ 577 /** 578 * @raw_xsum: raw xsum value 579 */ 580 __be16 raw_xsum; 581 /** 582 * @reserved_xsum: reserved high bits in the raw checksum 583 */ 584 __le16 reserved_xsum; 585 /* DW11 */ 586 /** 587 * @rate_n_flags: RX rate/flags encoding 588 */ 589 __le32 rate_n_flags; 590 /* DW12 */ 591 /** 592 * @energy_a: energy chain A 593 */ 594 u8 energy_a; 595 /** 596 * @energy_b: energy chain B 597 */ 598 u8 energy_b; 599 /** 600 * @channel: channel number 601 */ 602 u8 channel; 603 /** 604 * @mac_context: MAC context mask 605 */ 606 u8 mac_context; 607 /* DW13 */ 608 /** 609 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 610 */ 611 __le32 gp2_on_air_rise; 612 /* DW14 & DW15 */ 613 union { 614 /** 615 * @tsf_on_air_rise: 616 * TSF value on air rise (INA), only valid if 617 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 618 */ 619 __le64 tsf_on_air_rise; 620 621 struct { 622 /** 623 * @phy_data0: depends on info_type, see @phy_data1 624 */ 625 __le32 phy_data0; 626 /** 627 * @phy_data1: valid only if 628 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 629 * see &enum iwl_rx_phy_data1. 630 */ 631 __le32 phy_data1; 632 }; 633 }; 634 /* DW16 */ 635 /** 636 * @phy_data5: valid only if 637 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 638 * see &enum iwl_rx_phy_data5. 639 */ 640 __le32 phy_data5; 641 /* DW17 */ 642 /** 643 * @reserved: reserved 644 */ 645 __le32 reserved[1]; 646 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 647 RX_MPDU_RES_START_API_S_VER_5 */ 648 649 /** 650 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 651 */ 652 struct iwl_rx_mpdu_desc { 653 /* DW2 */ 654 /** 655 * @mpdu_len: MPDU length 656 */ 657 __le16 mpdu_len; 658 /** 659 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 660 */ 661 u8 mac_flags1; 662 /** 663 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 664 */ 665 u8 mac_flags2; 666 /* DW3 */ 667 /** 668 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 669 */ 670 u8 amsdu_info; 671 /** 672 * @phy_info: &enum iwl_rx_mpdu_phy_info 673 */ 674 __le16 phy_info; 675 /** 676 * @mac_phy_idx: MAC/PHY index 677 */ 678 u8 mac_phy_idx; 679 /* DW4 */ 680 union { 681 struct { 682 /* carries csum data only when rpa_en == 1 */ 683 /** 684 * @raw_csum: raw checksum (alledgedly unreliable) 685 */ 686 __le16 raw_csum; 687 688 union { 689 /** 690 * @l3l4_flags: &enum iwl_rx_l3l4_flags 691 */ 692 __le16 l3l4_flags; 693 694 /** 695 * @phy_data4: depends on info type, see phy_data1 696 */ 697 __le16 phy_data4; 698 }; 699 }; 700 /** 701 * @phy_eht_data4: depends on info type, see phy_data1 702 */ 703 __le32 phy_eht_data4; 704 }; 705 /* DW5 */ 706 /** 707 * @status: &enum iwl_rx_mpdu_status 708 */ 709 __le32 status; 710 711 /* DW6 */ 712 /** 713 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 714 */ 715 __le32 reorder_data; 716 717 union { 718 struct iwl_rx_mpdu_desc_v1 v1; 719 struct iwl_rx_mpdu_desc_v3 v3; 720 }; 721 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 722 RX_MPDU_RES_START_API_S_VER_4, 723 RX_MPDU_RES_START_API_S_VER_5 */ 724 725 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 726 727 #define RX_NO_DATA_CHAIN_A_POS 0 728 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 729 #define RX_NO_DATA_CHAIN_B_POS 8 730 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 731 #define RX_NO_DATA_CHANNEL_POS 16 732 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 733 734 #define RX_NO_DATA_INFO_TYPE_POS 0 735 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 736 #define RX_NO_DATA_INFO_TYPE_NONE 0 737 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 738 #define RX_NO_DATA_INFO_TYPE_NDP 2 739 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 740 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 741 742 #define RX_NO_DATA_INFO_ERR_POS 8 743 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 744 #define RX_NO_DATA_INFO_ERR_NONE 0 745 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 746 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 747 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 748 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 749 #define RX_NO_DATA_INFO_LOW_ENERGY 5 750 751 #define RX_NO_DATA_FRAME_TIME_POS 0 752 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 753 754 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 755 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 756 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 757 758 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 759 enum iwl_rx_usig_a1 { 760 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 761 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 762 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 763 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 764 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 765 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 766 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 767 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 768 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 769 IWL_RX_USIG_A1_RDY = 0x80000000, 770 }; 771 772 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 773 enum iwl_rx_usig_a2_eht { 774 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 775 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 776 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 777 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 778 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 779 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 780 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 781 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 782 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 783 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 784 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 785 }; 786 787 /** 788 * struct iwl_rx_no_data - RX no data descriptor 789 * @info: 7:0 frame type, 15:8 RX error type 790 * @rssi: 7:0 energy chain-A, 791 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 792 * @on_air_rise_time: GP2 during on air rise 793 * @fr_time: frame time 794 * @rate: rate/mcs of frame 795 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 796 * based on &enum iwl_rx_phy_info_type 797 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 798 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 799 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 800 */ 801 struct iwl_rx_no_data { 802 __le32 info; 803 __le32 rssi; 804 __le32 on_air_rise_time; 805 __le32 fr_time; 806 __le32 rate; 807 __le32 phy_info[2]; 808 __le32 rx_vec[2]; 809 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 810 RX_NO_DATA_NTFY_API_S_VER_2 */ 811 812 /** 813 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 814 * @info: 7:0 frame type, 15:8 RX error type 815 * @rssi: 7:0 energy chain-A, 816 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 817 * @on_air_rise_time: GP2 during on air rise 818 * @fr_time: frame time 819 * @rate: rate/mcs of frame 820 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 821 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 822 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 823 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 824 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 825 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 826 */ 827 struct iwl_rx_no_data_ver_3 { 828 __le32 info; 829 __le32 rssi; 830 __le32 on_air_rise_time; 831 __le32 fr_time; 832 __le32 rate; 833 __le32 phy_info[2]; 834 __le32 rx_vec[4]; 835 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 836 RX_NO_DATA_NTFY_API_S_VER_2 837 RX_NO_DATA_NTFY_API_S_VER_3 */ 838 839 struct iwl_frame_release { 840 u8 baid; 841 u8 reserved; 842 __le16 nssn; 843 }; 844 845 /** 846 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 847 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 848 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 849 */ 850 enum iwl_bar_frame_release_sta_tid { 851 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 852 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 853 }; 854 855 /** 856 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 857 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 858 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 859 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 860 */ 861 enum iwl_bar_frame_release_ba_info { 862 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 863 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 864 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 865 }; 866 867 /** 868 * struct iwl_bar_frame_release - frame release from BAR info 869 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 870 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 871 */ 872 struct iwl_bar_frame_release { 873 __le32 sta_tid; 874 __le32 ba_info; 875 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 876 877 enum iwl_rss_hash_func_en { 878 IWL_RSS_HASH_TYPE_IPV4_TCP, 879 IWL_RSS_HASH_TYPE_IPV4_UDP, 880 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 881 IWL_RSS_HASH_TYPE_IPV6_TCP, 882 IWL_RSS_HASH_TYPE_IPV6_UDP, 883 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 884 }; 885 886 #define IWL_RSS_HASH_KEY_CNT 10 887 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 888 #define IWL_RSS_ENABLE 1 889 890 /** 891 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 892 * 893 * @flags: 1 - enable, 0 - disable 894 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 895 * @reserved: reserved 896 * @secret_key: 320 bit input of random key configuration from driver 897 * @indirection_table: indirection table 898 */ 899 struct iwl_rss_config_cmd { 900 __le32 flags; 901 u8 hash_mask; 902 u8 reserved[3]; 903 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 904 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 905 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 906 907 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 908 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 909 910 /** 911 * struct iwl_rxq_sync_cmd - RXQ notification trigger 912 * 913 * @flags: flags of the notification. bit 0:3 are the sender queue 914 * @rxq_mask: rx queues to send the notification on 915 * @count: number of bytes in payload, should be DWORD aligned 916 * @payload: data to send to rx queues 917 */ 918 struct iwl_rxq_sync_cmd { 919 __le32 flags; 920 __le32 rxq_mask; 921 __le32 count; 922 #if defined(__linux__) 923 u8 payload[]; 924 #elif defined(__FreeBSD__) 925 u8 payload[0]; 926 #endif 927 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 928 929 /** 930 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 931 * sync command 932 * 933 * @count: number of bytes in payload 934 * @payload: data to send to rx queues 935 */ 936 struct iwl_rxq_sync_notification { 937 __le32 count; 938 #if defined(__linux__) 939 u8 payload[]; 940 #elif defined(__FreeBSD__) 941 u8 payload[0]; 942 #endif 943 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 944 945 /** 946 * enum iwl_mvm_pm_event - type of station PM event 947 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 948 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 949 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 950 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 951 */ 952 enum iwl_mvm_pm_event { 953 IWL_MVM_PM_EVENT_AWAKE, 954 IWL_MVM_PM_EVENT_ASLEEP, 955 IWL_MVM_PM_EVENT_UAPSD, 956 IWL_MVM_PM_EVENT_PS_POLL, 957 }; /* PEER_PM_NTFY_API_E_VER_1 */ 958 959 /** 960 * struct iwl_mvm_pm_state_notification - station PM state notification 961 * @sta_id: station ID of the station changing state 962 * @type: the new powersave state, see &enum iwl_mvm_pm_event 963 */ 964 struct iwl_mvm_pm_state_notification { 965 u8 sta_id; 966 u8 type; 967 /* private: */ 968 __le16 reserved; 969 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 970 971 #define BA_WINDOW_STREAMS_MAX 16 972 #define BA_WINDOW_STATUS_TID_MSK 0x000F 973 #define BA_WINDOW_STATUS_STA_ID_POS 4 974 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 975 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 976 977 /** 978 * struct iwl_ba_window_status_notif - reordering window's status notification 979 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 980 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 981 * @start_seq_num: the start sequence number of the bitmap 982 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 983 */ 984 struct iwl_ba_window_status_notif { 985 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 986 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 987 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 988 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 989 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 990 991 /** 992 * struct iwl_rfh_queue_config - RX queue configuration 993 * @q_num: Q num 994 * @enable: enable queue 995 * @reserved: alignment 996 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 997 * @fr_bd_cb: DMA address of freeRB table 998 * @ur_bd_cb: DMA address of used RB table 999 * @fr_bd_wid: Initial index of the free table 1000 */ 1001 struct iwl_rfh_queue_data { 1002 u8 q_num; 1003 u8 enable; 1004 __le16 reserved; 1005 __le64 urbd_stts_wrptr; 1006 __le64 fr_bd_cb; 1007 __le64 ur_bd_cb; 1008 __le32 fr_bd_wid; 1009 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1010 1011 /** 1012 * struct iwl_rfh_queue_config - RX queue configuration 1013 * @num_queues: number of queues configured 1014 * @reserved: alignment 1015 * @data: DMA addresses per-queue 1016 */ 1017 struct iwl_rfh_queue_config { 1018 u8 num_queues; 1019 u8 reserved[3]; 1020 #if defined(__linux__) 1021 struct iwl_rfh_queue_data data[]; 1022 #elif defined(__FreeBSD__) 1023 struct iwl_rfh_queue_data data[0]; 1024 #endif 1025 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1026 1027 #endif /* __iwl_fw_api_rx_h__ */ 1028