1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_debug_h__ 8 #define __iwl_fw_api_debug_h__ 9 #include "dbg-tlv.h" 10 11 /** 12 * enum iwl_debug_cmds - debug commands 13 */ 14 enum iwl_debug_cmds { 15 /** 16 * @LMAC_RD_WR: 17 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 18 * &struct iwl_dbg_mem_access_rsp 19 */ 20 LMAC_RD_WR = 0x0, 21 /** 22 * @UMAC_RD_WR: 23 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 24 * &struct iwl_dbg_mem_access_rsp 25 */ 26 UMAC_RD_WR = 0x1, 27 /** 28 * @HOST_EVENT_CFG: 29 * updates the enabled event severities 30 * &struct iwl_dbg_host_event_cfg_cmd 31 */ 32 HOST_EVENT_CFG = 0x3, 33 /** 34 * @INVALID_WR_PTR_CMD: invalid write pointer, set in the TFD 35 * when it's not in use 36 */ 37 INVALID_WR_PTR_CMD = 0x6, 38 /** 39 * @DBGC_SUSPEND_RESUME: 40 * DBGC suspend/resume commad. Uses a single dword as data: 41 * 0 - resume DBGC recording 42 * 1 - suspend DBGC recording 43 */ 44 DBGC_SUSPEND_RESUME = 0x7, 45 /** 46 * @BUFFER_ALLOCATION: 47 * passes DRAM buffers to a DBGC 48 * &struct iwl_buf_alloc_cmd 49 */ 50 BUFFER_ALLOCATION = 0x8, 51 /** 52 * @GET_TAS_STATUS: 53 * sends command to fw to get TAS status 54 * the response is &struct iwl_mvm_tas_status_resp 55 */ 56 GET_TAS_STATUS = 0xA, 57 /** 58 * @FW_DUMP_COMPLETE_CMD: 59 * sends command to fw once dump collection completed 60 * &struct iwl_dbg_dump_complete_cmd 61 */ 62 FW_DUMP_COMPLETE_CMD = 0xB, 63 /** 64 * @FW_CLEAR_BUFFER: 65 * clears the firmware's internal buffer 66 * no payload 67 */ 68 FW_CLEAR_BUFFER = 0xD, 69 /** 70 * @MFU_ASSERT_DUMP_NTF: 71 * &struct iwl_mfu_assert_dump_notif 72 */ 73 MFU_ASSERT_DUMP_NTF = 0xFE, 74 }; 75 76 /* Error response/notification */ 77 enum { 78 FW_ERR_UNKNOWN_CMD = 0x0, 79 FW_ERR_INVALID_CMD_PARAM = 0x1, 80 FW_ERR_SERVICE = 0x2, 81 FW_ERR_ARC_MEMORY = 0x3, 82 FW_ERR_ARC_CODE = 0x4, 83 FW_ERR_WATCH_DOG = 0x5, 84 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 85 FW_ERR_WEP_KEY_SIZE = 0x11, 86 FW_ERR_OBSOLETE_FUNC = 0x12, 87 FW_ERR_UNEXPECTED = 0xFE, 88 FW_ERR_FATAL = 0xFF 89 }; 90 91 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 92 * dbgc suspend resume command operations 93 * @DBGC_RESUME_CMD: resume dbgc recording 94 * @DBGC_SUSPEND_CMD: stop dbgc recording 95 */ 96 enum iwl_dbg_suspend_resume_cmds { 97 DBGC_RESUME_CMD, 98 DBGC_SUSPEND_CMD, 99 }; 100 101 /** 102 * struct iwl_error_resp - FW error indication 103 * ( REPLY_ERROR = 0x2 ) 104 * @error_type: one of FW_ERR_* 105 * @cmd_id: the command ID for which the error occurred 106 * @reserved1: reserved 107 * @bad_cmd_seq_num: sequence number of the erroneous command 108 * @error_service: which service created the error, applicable only if 109 * error_type = 2, otherwise 0 110 * @timestamp: TSF in usecs. 111 */ 112 struct iwl_error_resp { 113 __le32 error_type; 114 u8 cmd_id; 115 u8 reserved1; 116 __le16 bad_cmd_seq_num; 117 __le32 error_service; 118 __le64 timestamp; 119 } __packed; 120 121 #define TX_FIFO_MAX_NUM_9000 8 122 #define TX_FIFO_MAX_NUM 15 123 #define RX_FIFO_MAX_NUM 2 124 #define TX_FIFO_INTERNAL_MAX_NUM 6 125 126 /** 127 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 128 * 129 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 130 * accessible) 131 * @shared_mem_size: shared memory size 132 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 133 * 0x0 as accessible only via DBGM RDAT) 134 * @sample_buff_size: internal sample buff size 135 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 136 * 8000 HW set to 0x0 as not accessible) 137 * @txfifo_size: size of TXF0 ... TXF7 138 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 139 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 140 * when paging is not supported this should be 0 141 * @page_buff_size: size of %page_buff_addr 142 * @rxfifo_addr: Start address of rxFifo 143 * @internal_txfifo_addr: start address of internalFifo 144 * @internal_txfifo_size: internal fifos' size 145 * 146 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 147 * set, the last 3 members don't exist. 148 */ 149 struct iwl_shared_mem_cfg_v2 { 150 __le32 shared_mem_addr; 151 __le32 shared_mem_size; 152 __le32 sample_buff_addr; 153 __le32 sample_buff_size; 154 __le32 txfifo_addr; 155 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 156 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 157 __le32 page_buff_addr; 158 __le32 page_buff_size; 159 __le32 rxfifo_addr; 160 __le32 internal_txfifo_addr; 161 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 162 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 163 164 /** 165 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 166 * 167 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 168 * @txfifo_size: size of TX FIFOs 169 * @rxfifo1_addr: RXF1 addr 170 * @rxfifo1_size: RXF1 size 171 */ 172 struct iwl_shared_mem_lmac_cfg { 173 __le32 txfifo_addr; 174 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 175 __le32 rxfifo1_addr; 176 __le32 rxfifo1_size; 177 178 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 179 180 /** 181 * struct iwl_shared_mem_cfg - Shared memory configuration information 182 * 183 * @shared_mem_addr: shared memory address 184 * @shared_mem_size: shared memory size 185 * @sample_buff_addr: internal sample (mon/adc) buff addr 186 * @sample_buff_size: internal sample buff size 187 * @rxfifo2_addr: start addr of RXF2 188 * @rxfifo2_size: size of RXF2 189 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 190 * when paging is not supported this should be 0 191 * @page_buff_size: size of %page_buff_addr 192 * @lmac_num: number of LMACs (1 or 2) 193 * @lmac_smem: per - LMAC smem data 194 * @rxfifo2_control_addr: start addr of RXF2C 195 * @rxfifo2_control_size: size of RXF2C 196 */ 197 struct iwl_shared_mem_cfg { 198 __le32 shared_mem_addr; 199 __le32 shared_mem_size; 200 __le32 sample_buff_addr; 201 __le32 sample_buff_size; 202 __le32 rxfifo2_addr; 203 __le32 rxfifo2_size; 204 __le32 page_buff_addr; 205 __le32 page_buff_size; 206 __le32 lmac_num; 207 struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 208 __le32 rxfifo2_control_addr; 209 __le32 rxfifo2_control_size; 210 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 211 212 /** 213 * struct iwl_mfuart_load_notif_v1 - mfuart image version & status 214 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 215 * @installed_ver: installed image version 216 * @external_ver: external image version 217 * @status: MFUART loading status 218 * @duration: MFUART loading time 219 */ 220 struct iwl_mfuart_load_notif_v1 { 221 __le32 installed_ver; 222 __le32 external_ver; 223 __le32 status; 224 __le32 duration; 225 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */ 226 227 /** 228 * struct iwl_mfuart_load_notif - mfuart image version & status 229 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 230 * @installed_ver: installed image version 231 * @external_ver: external image version 232 * @status: MFUART loading status 233 * @duration: MFUART loading time 234 * @image_size: MFUART image size in bytes 235 */ 236 struct iwl_mfuart_load_notif { 237 __le32 installed_ver; 238 __le32 external_ver; 239 __le32 status; 240 __le32 duration; 241 /* image size valid only in v2 of the command */ 242 __le32 image_size; 243 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 244 245 /** 246 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 247 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 248 * @assert_id: mfuart assert id that cause the notif 249 * @curr_reset_num: number of asserts since uptime 250 * @index_num: current chunk id 251 * @parts_num: total number of chunks 252 * @data_size: number of data bytes sent 253 * @data: data buffer 254 */ 255 struct iwl_mfu_assert_dump_notif { 256 __le32 assert_id; 257 __le32 curr_reset_num; 258 __le16 index_num; 259 __le16 parts_num; 260 __le32 data_size; 261 __le32 data[]; 262 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 263 264 /** 265 * enum iwl_mvm_marker_id - marker ids 266 * 267 * The ids for different type of markers to insert into the usniffer logs 268 * 269 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 270 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 271 */ 272 enum iwl_mvm_marker_id { 273 MARKER_ID_TX_FRAME_LATENCY = 1, 274 MARKER_ID_SYNC_CLOCK = 2, 275 }; /* MARKER_ID_API_E_VER_2 */ 276 277 /** 278 * struct iwl_mvm_marker - mark info into the usniffer logs 279 * 280 * (MARKER_CMD = 0xcb) 281 * 282 * Mark the UTC time stamp into the usniffer logs together with additional 283 * metadata, so the usniffer output can be parsed. 284 * In the command response the ucode will return the GP2 time. 285 * 286 * @dw_len: The amount of dwords following this byte including this byte. 287 * @marker_id: A unique marker id (iwl_mvm_marker_id). 288 * @reserved: reserved. 289 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 290 * @metadata: additional meta data that will be written to the unsiffer log 291 */ 292 struct iwl_mvm_marker { 293 u8 dw_len; 294 u8 marker_id; 295 __le16 reserved; 296 __le64 timestamp; 297 __le32 metadata[]; 298 } __packed; /* MARKER_API_S_VER_1 */ 299 300 /** 301 * struct iwl_mvm_marker_rsp - Response to marker cmd 302 * 303 * @gp2: The gp2 clock value in the FW 304 */ 305 struct iwl_mvm_marker_rsp { 306 __le32 gp2; 307 } __packed; 308 309 /* Operation types for the debug mem access */ 310 enum { 311 DEBUG_MEM_OP_READ = 0, 312 DEBUG_MEM_OP_WRITE = 1, 313 DEBUG_MEM_OP_WRITE_BYTES = 2, 314 }; 315 316 #define DEBUG_MEM_MAX_SIZE_DWORDS 32 317 318 /** 319 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 320 * @op: DEBUG_MEM_OP_* 321 * @addr: address to read/write from/to 322 * @len: in dwords, to read/write 323 * @data: for write opeations, contains the source buffer 324 */ 325 struct iwl_dbg_mem_access_cmd { 326 __le32 op; 327 __le32 addr; 328 __le32 len; 329 __le32 data[]; 330 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 331 332 /* Status responses for the debug mem access */ 333 enum { 334 DEBUG_MEM_STATUS_SUCCESS = 0x0, 335 DEBUG_MEM_STATUS_FAILED = 0x1, 336 DEBUG_MEM_STATUS_LOCKED = 0x2, 337 DEBUG_MEM_STATUS_HIDDEN = 0x3, 338 DEBUG_MEM_STATUS_LENGTH = 0x4, 339 }; 340 341 /** 342 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 343 * @status: DEBUG_MEM_STATUS_* 344 * @len: read dwords (0 for write operations) 345 * @data: contains the read DWs 346 */ 347 struct iwl_dbg_mem_access_rsp { 348 __le32 status; 349 __le32 len; 350 __le32 data[]; 351 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 352 353 /** 354 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 355 * @operation: suspend or resume operation, uses 356 * &enum iwl_dbg_suspend_resume_cmds 357 */ 358 struct iwl_dbg_suspend_resume_cmd { 359 __le32 operation; 360 } __packed; 361 362 #define BUF_ALLOC_MAX_NUM_FRAGS 16 363 364 /** 365 * struct iwl_buf_alloc_frag - a DBGC fragment 366 * @addr: base address of the fragment 367 * @size: size of the fragment 368 */ 369 struct iwl_buf_alloc_frag { 370 __le64 addr; 371 __le32 size; 372 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 373 374 /** 375 * struct iwl_buf_alloc_cmd - buffer allocation command 376 * @alloc_id: &enum iwl_fw_ini_allocation_id 377 * @buf_location: &enum iwl_fw_ini_buffer_location 378 * @num_frags: number of fragments 379 * @frags: fragments array 380 */ 381 struct iwl_buf_alloc_cmd { 382 __le32 alloc_id; 383 __le32 buf_location; 384 __le32 num_frags; 385 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 386 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 387 388 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210 389 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF 390 391 /** 392 * struct iwl_dram_info - DRAM fragments allocation struct 393 * 394 * Driver will fill in the first 1K(+) of the pointed DRAM fragment 395 * 396 * @first_word: magic word value 397 * @second_word: magic word value 398 * @dram_frags: DRAM fragmentaion detail 399 */ 400 struct iwl_dram_info { 401 __le32 first_word; 402 __le32 second_word; 403 struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1]; 404 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 405 406 /** 407 * struct iwl_dbgc1_info - DBGC1 address and size 408 * 409 * Driver will fill the dbcg1 address and size at address based on config TLV. 410 * 411 * @first_word: all 0 set as identifier 412 * @dbgc1_add_lsb: LSB bits of DBGC1 physical address 413 * @dbgc1_add_msb: MSB bits of DBGC1 physical address 414 * @dbgc1_size: DBGC1 size 415 */ 416 struct iwl_dbgc1_info { 417 __le32 first_word; 418 __le32 dbgc1_add_lsb; 419 __le32 dbgc1_add_msb; 420 __le32 dbgc1_size; 421 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 422 423 /** 424 * struct iwl_dbg_host_event_cfg_cmd 425 * @enabled_severities: enabled severities 426 */ 427 struct iwl_dbg_host_event_cfg_cmd { 428 __le32 enabled_severities; 429 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */ 430 431 /** 432 * struct iwl_dbg_dump_complete_cmd - dump complete cmd 433 * 434 * @tp: timepoint whose dump has completed 435 * @tp_data: timepoint data 436 */ 437 struct iwl_dbg_dump_complete_cmd { 438 __le32 tp; 439 __le32 tp_data; 440 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */ 441 442 #define TAS_LMAC_BAND_HB 0 443 #define TAS_LMAC_BAND_LB 1 444 #define TAS_LMAC_BAND_UHB 2 445 #define TAS_LMAC_BAND_INVALID 3 446 447 /** 448 * struct iwl_mvm_tas_status_per_mac - tas status per lmac 449 * @static_status: tas statically enabled or disabled per lmac - TRUE/FALSE 450 * @static_dis_reason: TAS static disable reason, uses 451 * &enum iwl_mvm_tas_statically_disabled_reason 452 * @dynamic_status: Current TAS status. uses 453 * &enum iwl_mvm_tas_dyna_status 454 * @near_disconnection: is TAS currently near disconnection per lmac? - TRUE/FALSE 455 * @max_reg_pwr_limit: Regulatory power limits in dBm 456 * @sar_limit: SAR limits per lmac in dBm 457 * @band: Band per lmac 458 * @reserved: reserved 459 */ 460 struct iwl_mvm_tas_status_per_mac { 461 u8 static_status; 462 u8 static_dis_reason; 463 u8 dynamic_status; 464 u8 near_disconnection; 465 __le16 max_reg_pwr_limit; 466 __le16 sar_limit; 467 u8 band; 468 u8 reserved[3]; 469 } __packed; /*DEBUG_GET_TAS_STATUS_PER_MAC_S_VER_1*/ 470 471 /** 472 * struct iwl_mvm_tas_status_resp - Response to GET_TAS_STATUS 473 * @tas_fw_version: TAS FW version 474 * @is_uhb_for_usa_enable: is UHB enabled in USA? - TRUE/FALSE 475 * @curr_mcc: current mcc 476 * @block_list: country block list 477 * @tas_status_mac: TAS status per lmac, uses 478 * &struct iwl_mvm_tas_status_per_mac 479 * @in_dual_radio: is TAS in dual radio? - TRUE/FALSE 480 * @reserved: reserved 481 */ 482 struct iwl_mvm_tas_status_resp { 483 u8 tas_fw_version; 484 u8 is_uhb_for_usa_enable; 485 __le16 curr_mcc; 486 __le16 block_list[16]; 487 struct iwl_mvm_tas_status_per_mac tas_status_mac[2]; 488 u8 in_dual_radio; 489 u8 reserved[3]; 490 } __packed; /*DEBUG_GET_TAS_STATUS_RSP_API_S_VER_3*/ 491 492 /** 493 * enum iwl_mvm_tas_dyna_status - TAS current running status 494 * @TAS_DYNA_INACTIVE: TAS status is inactive 495 * @TAS_DYNA_INACTIVE_MVM_MODE: TAS is disabled due because FW is in MVM mode 496 * or is in softap mode. 497 * @TAS_DYNA_INACTIVE_TRIGGER_MODE: TAS is disabled because FW is in 498 * multi user trigger mode 499 * @TAS_DYNA_INACTIVE_BLOCK_LISTED: TAS is disabled because current mcc 500 * is blocklisted mcc 501 * @TAS_DYNA_INACTIVE_UHB_NON_US: TAS is disabled because current band is UHB 502 * and current mcc is USA 503 * @TAS_DYNA_ACTIVE: TAS is currently active 504 * @TAS_DYNA_STATUS_MAX: TAS status max value 505 */ 506 enum iwl_mvm_tas_dyna_status { 507 TAS_DYNA_INACTIVE, 508 TAS_DYNA_INACTIVE_MVM_MODE, 509 TAS_DYNA_INACTIVE_TRIGGER_MODE, 510 TAS_DYNA_INACTIVE_BLOCK_LISTED, 511 TAS_DYNA_INACTIVE_UHB_NON_US, 512 TAS_DYNA_ACTIVE, 513 514 TAS_DYNA_STATUS_MAX, 515 }; /*_TAS_DYNA_STATUS_E*/ 516 517 /** 518 * enum iwl_mvm_tas_statically_disabled_reason - TAS statically disabled reason 519 * @TAS_DISABLED_DUE_TO_BIOS: TAS is disabled because TAS is disabled in BIOS 520 * @TAS_DISABLED_DUE_TO_SAR_6DBM: TAS is disabled because SAR limit is less than 6 Dbm 521 * @TAS_DISABLED_REASON_INVALID: TAS disable reason is invalid 522 * @TAS_DISABLED_REASON_MAX: TAS disable reason max value 523 */ 524 enum iwl_mvm_tas_statically_disabled_reason { 525 TAS_DISABLED_DUE_TO_BIOS, 526 TAS_DISABLED_DUE_TO_SAR_6DBM, 527 TAS_DISABLED_REASON_INVALID, 528 529 TAS_DISABLED_REASON_MAX, 530 }; /*_TAS_STATICALLY_DISABLED_REASON_E*/ 531 532 /** 533 * enum iwl_fw_dbg_config_cmd_type - types of FW debug config command 534 * @DEBUG_TOKEN_CONFIG_TYPE: token config type 535 */ 536 enum iwl_fw_dbg_config_cmd_type { 537 DEBUG_TOKEN_CONFIG_TYPE = 0x2B, 538 }; /* LDBG_CFG_CMD_TYPE_API_E_VER_1 */ 539 540 /* this token disables debug asserts in the firmware */ 541 #define IWL_FW_DBG_CONFIG_TOKEN 0x00010001 542 543 /** 544 * struct iwl_fw_dbg_config_cmd - configure FW debug 545 * 546 * @type: according to &enum iwl_fw_dbg_config_cmd_type 547 * @conf: FW configuration 548 */ 549 struct iwl_fw_dbg_config_cmd { 550 __le32 type; 551 __le32 conf; 552 } __packed; /* LDBG_CFG_CMD_API_S_VER_7 */ 553 554 #endif /* __iwl_fw_api_debug_h__ */ 555