1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_debug_h__ 8 #define __iwl_fw_api_debug_h__ 9 10 /** 11 * enum iwl_debug_cmds - debug commands 12 */ 13 enum iwl_debug_cmds { 14 /** 15 * @LMAC_RD_WR: 16 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 17 * &struct iwl_dbg_mem_access_rsp 18 */ 19 LMAC_RD_WR = 0x0, 20 /** 21 * @UMAC_RD_WR: 22 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 23 * &struct iwl_dbg_mem_access_rsp 24 */ 25 UMAC_RD_WR = 0x1, 26 /** 27 * @HOST_EVENT_CFG: 28 * updates the enabled event severities 29 * &struct iwl_dbg_host_event_cfg_cmd 30 */ 31 HOST_EVENT_CFG = 0x3, 32 /** 33 * @DBGC_SUSPEND_RESUME: 34 * DBGC suspend/resume commad. Uses a single dword as data: 35 * 0 - resume DBGC recording 36 * 1 - suspend DBGC recording 37 */ 38 DBGC_SUSPEND_RESUME = 0x7, 39 /** 40 * @BUFFER_ALLOCATION: 41 * passes DRAM buffers to a DBGC 42 * &struct iwl_buf_alloc_cmd 43 */ 44 BUFFER_ALLOCATION = 0x8, 45 /** 46 * @MFU_ASSERT_DUMP_NTF: 47 * &struct iwl_mfu_assert_dump_notif 48 */ 49 MFU_ASSERT_DUMP_NTF = 0xFE, 50 }; 51 52 /* Error response/notification */ 53 enum { 54 FW_ERR_UNKNOWN_CMD = 0x0, 55 FW_ERR_INVALID_CMD_PARAM = 0x1, 56 FW_ERR_SERVICE = 0x2, 57 FW_ERR_ARC_MEMORY = 0x3, 58 FW_ERR_ARC_CODE = 0x4, 59 FW_ERR_WATCH_DOG = 0x5, 60 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 61 FW_ERR_WEP_KEY_SIZE = 0x11, 62 FW_ERR_OBSOLETE_FUNC = 0x12, 63 FW_ERR_UNEXPECTED = 0xFE, 64 FW_ERR_FATAL = 0xFF 65 }; 66 67 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 68 * dbgc suspend resume command operations 69 * @DBGC_RESUME_CMD: resume dbgc recording 70 * @DBGC_SUSPEND_CMD: stop dbgc recording 71 */ 72 enum iwl_dbg_suspend_resume_cmds { 73 DBGC_RESUME_CMD, 74 DBGC_SUSPEND_CMD, 75 }; 76 77 /** 78 * struct iwl_error_resp - FW error indication 79 * ( REPLY_ERROR = 0x2 ) 80 * @error_type: one of FW_ERR_* 81 * @cmd_id: the command ID for which the error occurred 82 * @reserved1: reserved 83 * @bad_cmd_seq_num: sequence number of the erroneous command 84 * @error_service: which service created the error, applicable only if 85 * error_type = 2, otherwise 0 86 * @timestamp: TSF in usecs. 87 */ 88 struct iwl_error_resp { 89 __le32 error_type; 90 u8 cmd_id; 91 u8 reserved1; 92 __le16 bad_cmd_seq_num; 93 __le32 error_service; 94 __le64 timestamp; 95 } __packed; 96 97 #define TX_FIFO_MAX_NUM_9000 8 98 #define TX_FIFO_MAX_NUM 15 99 #define RX_FIFO_MAX_NUM 2 100 #define TX_FIFO_INTERNAL_MAX_NUM 6 101 102 /** 103 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 104 * 105 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 106 * accessible) 107 * @shared_mem_size: shared memory size 108 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 109 * 0x0 as accessible only via DBGM RDAT) 110 * @sample_buff_size: internal sample buff size 111 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 112 * 8000 HW set to 0x0 as not accessible) 113 * @txfifo_size: size of TXF0 ... TXF7 114 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 115 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 116 * when paging is not supported this should be 0 117 * @page_buff_size: size of %page_buff_addr 118 * @rxfifo_addr: Start address of rxFifo 119 * @internal_txfifo_addr: start address of internalFifo 120 * @internal_txfifo_size: internal fifos' size 121 * 122 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 123 * set, the last 3 members don't exist. 124 */ 125 struct iwl_shared_mem_cfg_v2 { 126 __le32 shared_mem_addr; 127 __le32 shared_mem_size; 128 __le32 sample_buff_addr; 129 __le32 sample_buff_size; 130 __le32 txfifo_addr; 131 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 132 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 133 __le32 page_buff_addr; 134 __le32 page_buff_size; 135 __le32 rxfifo_addr; 136 __le32 internal_txfifo_addr; 137 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 138 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 139 140 /** 141 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 142 * 143 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 144 * @txfifo_size: size of TX FIFOs 145 * @rxfifo1_addr: RXF1 addr 146 * @rxfifo1_size: RXF1 size 147 */ 148 struct iwl_shared_mem_lmac_cfg { 149 __le32 txfifo_addr; 150 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 151 __le32 rxfifo1_addr; 152 __le32 rxfifo1_size; 153 154 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 155 156 /** 157 * struct iwl_shared_mem_cfg - Shared memory configuration information 158 * 159 * @shared_mem_addr: shared memory address 160 * @shared_mem_size: shared memory size 161 * @sample_buff_addr: internal sample (mon/adc) buff addr 162 * @sample_buff_size: internal sample buff size 163 * @rxfifo2_addr: start addr of RXF2 164 * @rxfifo2_size: size of RXF2 165 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 166 * when paging is not supported this should be 0 167 * @page_buff_size: size of %page_buff_addr 168 * @lmac_num: number of LMACs (1 or 2) 169 * @lmac_smem: per - LMAC smem data 170 * @rxfifo2_control_addr: start addr of RXF2C 171 * @rxfifo2_control_size: size of RXF2C 172 */ 173 struct iwl_shared_mem_cfg { 174 __le32 shared_mem_addr; 175 __le32 shared_mem_size; 176 __le32 sample_buff_addr; 177 __le32 sample_buff_size; 178 __le32 rxfifo2_addr; 179 __le32 rxfifo2_size; 180 __le32 page_buff_addr; 181 __le32 page_buff_size; 182 __le32 lmac_num; 183 struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 184 __le32 rxfifo2_control_addr; 185 __le32 rxfifo2_control_size; 186 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 187 188 /** 189 * struct iwl_mfuart_load_notif_v1 - mfuart image version & status 190 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 191 * @installed_ver: installed image version 192 * @external_ver: external image version 193 * @status: MFUART loading status 194 * @duration: MFUART loading time 195 */ 196 struct iwl_mfuart_load_notif_v1 { 197 __le32 installed_ver; 198 __le32 external_ver; 199 __le32 status; 200 __le32 duration; 201 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */ 202 203 /** 204 * struct iwl_mfuart_load_notif - mfuart image version & status 205 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 206 * @installed_ver: installed image version 207 * @external_ver: external image version 208 * @status: MFUART loading status 209 * @duration: MFUART loading time 210 * @image_size: MFUART image size in bytes 211 */ 212 struct iwl_mfuart_load_notif { 213 __le32 installed_ver; 214 __le32 external_ver; 215 __le32 status; 216 __le32 duration; 217 /* image size valid only in v2 of the command */ 218 __le32 image_size; 219 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 220 221 /** 222 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 223 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 224 * @assert_id: mfuart assert id that cause the notif 225 * @curr_reset_num: number of asserts since uptime 226 * @index_num: current chunk id 227 * @parts_num: total number of chunks 228 * @data_size: number of data bytes sent 229 * @data: data buffer 230 */ 231 struct iwl_mfu_assert_dump_notif { 232 __le32 assert_id; 233 __le32 curr_reset_num; 234 __le16 index_num; 235 __le16 parts_num; 236 __le32 data_size; 237 __le32 data[0]; 238 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 239 240 /** 241 * enum iwl_mvm_marker_id - marker ids 242 * 243 * The ids for different type of markers to insert into the usniffer logs 244 * 245 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 246 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 247 */ 248 enum iwl_mvm_marker_id { 249 MARKER_ID_TX_FRAME_LATENCY = 1, 250 MARKER_ID_SYNC_CLOCK = 2, 251 }; /* MARKER_ID_API_E_VER_2 */ 252 253 /** 254 * struct iwl_mvm_marker - mark info into the usniffer logs 255 * 256 * (MARKER_CMD = 0xcb) 257 * 258 * Mark the UTC time stamp into the usniffer logs together with additional 259 * metadata, so the usniffer output can be parsed. 260 * In the command response the ucode will return the GP2 time. 261 * 262 * @dw_len: The amount of dwords following this byte including this byte. 263 * @marker_id: A unique marker id (iwl_mvm_marker_id). 264 * @reserved: reserved. 265 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 266 * @metadata: additional meta data that will be written to the unsiffer log 267 */ 268 struct iwl_mvm_marker { 269 u8 dw_len; 270 u8 marker_id; 271 __le16 reserved; 272 __le64 timestamp; 273 __le32 metadata[0]; 274 } __packed; /* MARKER_API_S_VER_1 */ 275 276 /** 277 * struct iwl_mvm_marker_rsp - Response to marker cmd 278 * 279 * @gp2: The gp2 clock value in the FW 280 */ 281 struct iwl_mvm_marker_rsp { 282 __le32 gp2; 283 } __packed; 284 285 /* Operation types for the debug mem access */ 286 enum { 287 DEBUG_MEM_OP_READ = 0, 288 DEBUG_MEM_OP_WRITE = 1, 289 DEBUG_MEM_OP_WRITE_BYTES = 2, 290 }; 291 292 #define DEBUG_MEM_MAX_SIZE_DWORDS 32 293 294 /** 295 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 296 * @op: DEBUG_MEM_OP_* 297 * @addr: address to read/write from/to 298 * @len: in dwords, to read/write 299 * @data: for write opeations, contains the source buffer 300 */ 301 struct iwl_dbg_mem_access_cmd { 302 __le32 op; 303 __le32 addr; 304 __le32 len; 305 __le32 data[]; 306 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 307 308 /* Status responses for the debug mem access */ 309 enum { 310 DEBUG_MEM_STATUS_SUCCESS = 0x0, 311 DEBUG_MEM_STATUS_FAILED = 0x1, 312 DEBUG_MEM_STATUS_LOCKED = 0x2, 313 DEBUG_MEM_STATUS_HIDDEN = 0x3, 314 DEBUG_MEM_STATUS_LENGTH = 0x4, 315 }; 316 317 /** 318 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 319 * @status: DEBUG_MEM_STATUS_* 320 * @len: read dwords (0 for write operations) 321 * @data: contains the read DWs 322 */ 323 struct iwl_dbg_mem_access_rsp { 324 __le32 status; 325 __le32 len; 326 __le32 data[]; 327 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 328 329 /** 330 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 331 * @operation: suspend or resume operation, uses 332 * &enum iwl_dbg_suspend_resume_cmds 333 */ 334 struct iwl_dbg_suspend_resume_cmd { 335 __le32 operation; 336 } __packed; 337 338 #define BUF_ALLOC_MAX_NUM_FRAGS 16 339 340 /** 341 * struct iwl_buf_alloc_frag - a DBGC fragment 342 * @addr: base address of the fragment 343 * @size: size of the fragment 344 */ 345 struct iwl_buf_alloc_frag { 346 __le64 addr; 347 __le32 size; 348 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 349 350 /** 351 * struct iwl_buf_alloc_cmd - buffer allocation command 352 * @alloc_id: &enum iwl_fw_ini_allocation_id 353 * @buf_location: &enum iwl_fw_ini_buffer_location 354 * @num_frags: number of fragments 355 * @frags: fragments array 356 */ 357 struct iwl_buf_alloc_cmd { 358 __le32 alloc_id; 359 __le32 buf_location; 360 __le32 num_frags; 361 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 362 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 363 364 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210 365 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF 366 367 /** 368 * struct iwL_dram_info - DRAM fragments allocation struct 369 * 370 * Driver will fill in the first 1K(+) of the pointed DRAM fragment 371 * 372 * @first_word: magic word value 373 * @second_word: magic word value 374 * @framfrags: DRAM fragmentaion detail 375 */ 376 struct iwl_dram_info { 377 __le32 first_word; 378 __le32 second_word; 379 struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1]; 380 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 381 382 /** 383 * struct iwl_dbgc1_info - DBGC1 address and size 384 * 385 * Driver will fill the dbcg1 address and size at address based on config TLV. 386 * 387 * @first_word: all 0 set as identifier 388 * @dbgc1_add_lsb: LSB bits of DBGC1 physical address 389 * @dbgc1_add_msb: MSB bits of DBGC1 physical address 390 * @dbgc1_size: DBGC1 size 391 */ 392 struct iwl_dbgc1_info { 393 __le32 first_word; 394 __le32 dbgc1_add_lsb; 395 __le32 dbgc1_add_msb; 396 __le32 dbgc1_size; 397 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 398 399 /** 400 * struct iwl_dbg_host_event_cfg_cmd 401 * @enabled_severities: enabled severities 402 */ 403 struct iwl_dbg_host_event_cfg_cmd { 404 __le32 enabled_severities; 405 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */ 406 407 #endif /* __iwl_fw_api_debug_h__ */ 408