xref: /freebsd/sys/contrib/dev/iwlwifi/cfg/bz.c (revision 9af1bba44e1ce9b0296ae56760b564d67ab7a1cf)
1*9af1bba4SBjoern A. Zeeb // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2*9af1bba4SBjoern A. Zeeb /*
3*9af1bba4SBjoern A. Zeeb  * Copyright (C) 2015-2017 Intel Deutschland GmbH
4*9af1bba4SBjoern A. Zeeb  * Copyright (C) 2018-2023 Intel Corporation
5*9af1bba4SBjoern A. Zeeb  */
6*9af1bba4SBjoern A. Zeeb #include <linux/module.h>
7*9af1bba4SBjoern A. Zeeb #include <linux/stringify.h>
8*9af1bba4SBjoern A. Zeeb #include "iwl-config.h"
9*9af1bba4SBjoern A. Zeeb #include "iwl-prph.h"
10*9af1bba4SBjoern A. Zeeb #include "fw/api/txq.h"
11*9af1bba4SBjoern A. Zeeb 
12*9af1bba4SBjoern A. Zeeb /* Highest firmware API version supported */
13*9af1bba4SBjoern A. Zeeb #define IWL_BZ_UCODE_API_MAX	83
14*9af1bba4SBjoern A. Zeeb 
15*9af1bba4SBjoern A. Zeeb /* Lowest firmware API version supported */
16*9af1bba4SBjoern A. Zeeb #define IWL_BZ_UCODE_API_MIN	80
17*9af1bba4SBjoern A. Zeeb 
18*9af1bba4SBjoern A. Zeeb /* NVM versions */
19*9af1bba4SBjoern A. Zeeb #define IWL_BZ_NVM_VERSION		0x0a1d
20*9af1bba4SBjoern A. Zeeb 
21*9af1bba4SBjoern A. Zeeb /* Memory offsets and lengths */
22*9af1bba4SBjoern A. Zeeb #define IWL_BZ_DCCM_OFFSET		0x800000 /* LMAC1 */
23*9af1bba4SBjoern A. Zeeb #define IWL_BZ_DCCM_LEN			0x10000 /* LMAC1 */
24*9af1bba4SBjoern A. Zeeb #define IWL_BZ_DCCM2_OFFSET		0x880000
25*9af1bba4SBjoern A. Zeeb #define IWL_BZ_DCCM2_LEN		0x8000
26*9af1bba4SBjoern A. Zeeb #define IWL_BZ_SMEM_OFFSET		0x400000
27*9af1bba4SBjoern A. Zeeb #define IWL_BZ_SMEM_LEN			0xD0000
28*9af1bba4SBjoern A. Zeeb 
29*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_HR_B_FW_PRE		"iwlwifi-bz-a0-hr-b0"
30*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_GF_A_FW_PRE		"iwlwifi-bz-a0-gf-a0"
31*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_GF4_A_FW_PRE		"iwlwifi-bz-a0-gf4-a0"
32*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM_B_FW_PRE		"iwlwifi-bz-a0-fm-b0"
33*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM_C_FW_PRE		"iwlwifi-bz-a0-fm-c0"
34*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM4_B_FW_PRE		"iwlwifi-bz-a0-fm4-b0"
35*9af1bba4SBjoern A. Zeeb #define IWL_GL_B_FM_B_FW_PRE		"iwlwifi-gl-b0-fm-b0"
36*9af1bba4SBjoern A. Zeeb #define IWL_GL_C_FM_C_FW_PRE		"iwlwifi-gl-c0-fm-c0"
37*9af1bba4SBjoern A. Zeeb 
38*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
39*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
40*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
41*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
42*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
43*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
44*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
45*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_FM_B_FW_PRE "-" __stringify(api) ".ucode"
46*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \
47*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_FM_C_FW_PRE "-" __stringify(api) ".ucode"
48*9af1bba4SBjoern A. Zeeb #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
49*9af1bba4SBjoern A. Zeeb 	IWL_BZ_A_FM4_B_FW_PRE "-" __stringify(api) ".ucode"
50*9af1bba4SBjoern A. Zeeb #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
51*9af1bba4SBjoern A. Zeeb 	IWL_GL_B_FM_B_FW_PRE "-" __stringify(api) ".ucode"
52*9af1bba4SBjoern A. Zeeb #define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \
53*9af1bba4SBjoern A. Zeeb 	IWL_GL_C_FM_C_FW_PRE "-" __stringify(api) ".ucode"
54*9af1bba4SBjoern A. Zeeb 
55*9af1bba4SBjoern A. Zeeb static const struct iwl_base_params iwl_bz_base_params = {
56*9af1bba4SBjoern A. Zeeb 	.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
57*9af1bba4SBjoern A. Zeeb 	.num_of_queues = 512,
58*9af1bba4SBjoern A. Zeeb 	.max_tfd_queue_size = 65536,
59*9af1bba4SBjoern A. Zeeb 	.shadow_ram_support = true,
60*9af1bba4SBjoern A. Zeeb 	.led_compensation = 57,
61*9af1bba4SBjoern A. Zeeb 	.wd_timeout = IWL_LONG_WD_TIMEOUT,
62*9af1bba4SBjoern A. Zeeb 	.max_event_log_size = 512,
63*9af1bba4SBjoern A. Zeeb 	.shadow_reg_enable = true,
64*9af1bba4SBjoern A. Zeeb 	.pcie_l1_allowed = true,
65*9af1bba4SBjoern A. Zeeb };
66*9af1bba4SBjoern A. Zeeb 
67*9af1bba4SBjoern A. Zeeb #define IWL_DEVICE_BZ_COMMON						\
68*9af1bba4SBjoern A. Zeeb 	.ucode_api_max = IWL_BZ_UCODE_API_MAX,			\
69*9af1bba4SBjoern A. Zeeb 	.ucode_api_min = IWL_BZ_UCODE_API_MIN,			\
70*9af1bba4SBjoern A. Zeeb 	.led_mode = IWL_LED_RF_STATE,					\
71*9af1bba4SBjoern A. Zeeb 	.nvm_hw_section_num = 10,					\
72*9af1bba4SBjoern A. Zeeb 	.non_shared_ant = ANT_B,					\
73*9af1bba4SBjoern A. Zeeb 	.dccm_offset = IWL_BZ_DCCM_OFFSET,				\
74*9af1bba4SBjoern A. Zeeb 	.dccm_len = IWL_BZ_DCCM_LEN,					\
75*9af1bba4SBjoern A. Zeeb 	.dccm2_offset = IWL_BZ_DCCM2_OFFSET,				\
76*9af1bba4SBjoern A. Zeeb 	.dccm2_len = IWL_BZ_DCCM2_LEN,				\
77*9af1bba4SBjoern A. Zeeb 	.smem_offset = IWL_BZ_SMEM_OFFSET,				\
78*9af1bba4SBjoern A. Zeeb 	.smem_len = IWL_BZ_SMEM_LEN,					\
79*9af1bba4SBjoern A. Zeeb 	.apmg_not_supported = true,					\
80*9af1bba4SBjoern A. Zeeb 	.trans.mq_rx_supported = true,					\
81*9af1bba4SBjoern A. Zeeb 	.vht_mu_mimo_supported = true,					\
82*9af1bba4SBjoern A. Zeeb 	.mac_addr_from_csr = 0x30,					\
83*9af1bba4SBjoern A. Zeeb 	.nvm_ver = IWL_BZ_NVM_VERSION,				\
84*9af1bba4SBjoern A. Zeeb 	.trans.rf_id = true,						\
85*9af1bba4SBjoern A. Zeeb 	.trans.gen2 = true,						\
86*9af1bba4SBjoern A. Zeeb 	.nvm_type = IWL_NVM_EXT,					\
87*9af1bba4SBjoern A. Zeeb 	.dbgc_supported = true,						\
88*9af1bba4SBjoern A. Zeeb 	.min_umac_error_event_table = 0xD0000,				\
89*9af1bba4SBjoern A. Zeeb 	.d3_debug_data_base_addr = 0x401000,				\
90*9af1bba4SBjoern A. Zeeb 	.d3_debug_data_length = 60 * 1024,				\
91*9af1bba4SBjoern A. Zeeb 	.mon_smem_regs = {						\
92*9af1bba4SBjoern A. Zeeb 		.write_ptr = {						\
93*9af1bba4SBjoern A. Zeeb 			.addr = LDBG_M2S_BUF_WPTR,			\
94*9af1bba4SBjoern A. Zeeb 			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,		\
95*9af1bba4SBjoern A. Zeeb 	},								\
96*9af1bba4SBjoern A. Zeeb 		.cycle_cnt = {						\
97*9af1bba4SBjoern A. Zeeb 			.addr = LDBG_M2S_BUF_WRAP_CNT,			\
98*9af1bba4SBjoern A. Zeeb 			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,		\
99*9af1bba4SBjoern A. Zeeb 		},							\
100*9af1bba4SBjoern A. Zeeb 	},								\
101*9af1bba4SBjoern A. Zeeb 	.trans.umac_prph_offset = 0x300000,				\
102*9af1bba4SBjoern A. Zeeb 	.trans.device_family = IWL_DEVICE_FAMILY_BZ,			\
103*9af1bba4SBjoern A. Zeeb 	.trans.base_params = &iwl_bz_base_params,			\
104*9af1bba4SBjoern A. Zeeb 	.min_txq_size = 128,						\
105*9af1bba4SBjoern A. Zeeb 	.gp2_reg_addr = 0xd02c68,					\
106*9af1bba4SBjoern A. Zeeb 	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,			\
107*9af1bba4SBjoern A. Zeeb 	.mon_dram_regs = {						\
108*9af1bba4SBjoern A. Zeeb 		.write_ptr = {						\
109*9af1bba4SBjoern A. Zeeb 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
110*9af1bba4SBjoern A. Zeeb 			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,	\
111*9af1bba4SBjoern A. Zeeb 		},							\
112*9af1bba4SBjoern A. Zeeb 		.cycle_cnt = {						\
113*9af1bba4SBjoern A. Zeeb 			.addr = DBGC_DBGBUF_WRAP_AROUND,		\
114*9af1bba4SBjoern A. Zeeb 			.mask = 0xffffffff,				\
115*9af1bba4SBjoern A. Zeeb 		},							\
116*9af1bba4SBjoern A. Zeeb 		.cur_frag = {						\
117*9af1bba4SBjoern A. Zeeb 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
118*9af1bba4SBjoern A. Zeeb 			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,		\
119*9af1bba4SBjoern A. Zeeb 		},							\
120*9af1bba4SBjoern A. Zeeb 	},								\
121*9af1bba4SBjoern A. Zeeb 	.mon_dbgi_regs = {						\
122*9af1bba4SBjoern A. Zeeb 		.write_ptr = {						\
123*9af1bba4SBjoern A. Zeeb 			.addr = DBGI_SRAM_FIFO_POINTERS,		\
124*9af1bba4SBjoern A. Zeeb 			.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,	\
125*9af1bba4SBjoern A. Zeeb 		},							\
126*9af1bba4SBjoern A. Zeeb 	}
127*9af1bba4SBjoern A. Zeeb 
128*9af1bba4SBjoern A. Zeeb #define IWL_DEVICE_BZ							\
129*9af1bba4SBjoern A. Zeeb 	IWL_DEVICE_BZ_COMMON,						\
130*9af1bba4SBjoern A. Zeeb 	.ht_params = &iwl_22000_ht_params
131*9af1bba4SBjoern A. Zeeb 
132*9af1bba4SBjoern A. Zeeb #define IWL_DEVICE_GL_A							\
133*9af1bba4SBjoern A. Zeeb 	IWL_DEVICE_BZ_COMMON,						\
134*9af1bba4SBjoern A. Zeeb 	.ht_params = &iwl_gl_a_ht_params
135*9af1bba4SBjoern A. Zeeb 
136*9af1bba4SBjoern A. Zeeb /*
137*9af1bba4SBjoern A. Zeeb  * If the device doesn't support HE, no need to have that many buffers.
138*9af1bba4SBjoern A. Zeeb  * These sizes were picked according to 8 MSDUs inside 256 A-MSDUs in an
139*9af1bba4SBjoern A. Zeeb  * A-MPDU, with additional overhead to account for processing time.
140*9af1bba4SBjoern A. Zeeb  */
141*9af1bba4SBjoern A. Zeeb #define IWL_NUM_RBDS_NON_HE		512
142*9af1bba4SBjoern A. Zeeb #define IWL_NUM_RBDS_BZ_HE		4096
143*9af1bba4SBjoern A. Zeeb 
144*9af1bba4SBjoern A. Zeeb const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
145*9af1bba4SBjoern A. Zeeb 	.device_family = IWL_DEVICE_FAMILY_BZ,
146*9af1bba4SBjoern A. Zeeb 	.base_params = &iwl_bz_base_params,
147*9af1bba4SBjoern A. Zeeb 	.mq_rx_supported = true,
148*9af1bba4SBjoern A. Zeeb 	.rf_id = true,
149*9af1bba4SBjoern A. Zeeb 	.gen2 = true,
150*9af1bba4SBjoern A. Zeeb 	.integrated = true,
151*9af1bba4SBjoern A. Zeeb 	.umac_prph_offset = 0x300000,
152*9af1bba4SBjoern A. Zeeb 	.xtal_latency = 12000,
153*9af1bba4SBjoern A. Zeeb 	.low_latency_xtal = true,
154*9af1bba4SBjoern A. Zeeb 	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
155*9af1bba4SBjoern A. Zeeb };
156*9af1bba4SBjoern A. Zeeb 
157*9af1bba4SBjoern A. Zeeb const char iwl_bz_name[] = "Intel(R) TBD Bz device";
158*9af1bba4SBjoern A. Zeeb 
159*9af1bba4SBjoern A. Zeeb const struct iwl_cfg iwl_cfg_bz = {
160*9af1bba4SBjoern A. Zeeb 	.fw_name_mac = "bz",
161*9af1bba4SBjoern A. Zeeb 	.uhb_supported = true,
162*9af1bba4SBjoern A. Zeeb 	IWL_DEVICE_BZ,
163*9af1bba4SBjoern A. Zeeb 	.features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
164*9af1bba4SBjoern A. Zeeb 	.num_rbds = IWL_NUM_RBDS_BZ_HE,
165*9af1bba4SBjoern A. Zeeb };
166*9af1bba4SBjoern A. Zeeb 
167*9af1bba4SBjoern A. Zeeb const struct iwl_cfg iwl_cfg_gl = {
168*9af1bba4SBjoern A. Zeeb 	.fw_name_mac = "gl",
169*9af1bba4SBjoern A. Zeeb 	.uhb_supported = true,
170*9af1bba4SBjoern A. Zeeb 	IWL_DEVICE_BZ,
171*9af1bba4SBjoern A. Zeeb 	.features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
172*9af1bba4SBjoern A. Zeeb 	.num_rbds = IWL_NUM_RBDS_BZ_HE,
173*9af1bba4SBjoern A. Zeeb };
174*9af1bba4SBjoern A. Zeeb 
175*9af1bba4SBjoern A. Zeeb 
176*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
177*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
178*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
179*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
180*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
181*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
182*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
183*9af1bba4SBjoern A. Zeeb MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
184