1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 70 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 60 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 61 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 62 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 63 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 64 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 65 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 66 67 68 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 69 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 70 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 71 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 72 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 73 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 75 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 76 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 77 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 79 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 81 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 82 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 83 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 84 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 85 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 86 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 87 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 88 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 89 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 90 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 91 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 92 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 93 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 94 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 95 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 96 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 97 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 98 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 99 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 100 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 101 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 102 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 103 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 104 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 105 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 106 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 107 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 109 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 110 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 111 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 112 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 113 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 114 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 115 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 116 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 117 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 118 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 119 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 120 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 121 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 122 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 123 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 124 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 125 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 126 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 127 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 128 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 129 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 130 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 131 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 132 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 133 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 134 135 static const struct iwl_base_params iwl_22000_base_params = { 136 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 137 .num_of_queues = 512, 138 .max_tfd_queue_size = 256, 139 .shadow_ram_support = true, 140 .led_compensation = 57, 141 .wd_timeout = IWL_LONG_WD_TIMEOUT, 142 .max_event_log_size = 512, 143 .shadow_reg_enable = true, 144 .pcie_l1_allowed = true, 145 }; 146 147 static const struct iwl_base_params iwl_ax210_base_params = { 148 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 149 .num_of_queues = 512, 150 .max_tfd_queue_size = 65536, 151 .shadow_ram_support = true, 152 .led_compensation = 57, 153 .wd_timeout = IWL_LONG_WD_TIMEOUT, 154 .max_event_log_size = 512, 155 .shadow_reg_enable = true, 156 .pcie_l1_allowed = true, 157 }; 158 159 static const struct iwl_ht_params iwl_22000_ht_params = { 160 .stbc = true, 161 .ldpc = true, 162 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 163 BIT(NL80211_BAND_6GHZ), 164 }; 165 166 #define IWL_DEVICE_22000_COMMON \ 167 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 168 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 169 .led_mode = IWL_LED_RF_STATE, \ 170 .nvm_hw_section_num = 10, \ 171 .non_shared_ant = ANT_B, \ 172 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 173 .dccm_len = IWL_22000_DCCM_LEN, \ 174 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 175 .dccm2_len = IWL_22000_DCCM2_LEN, \ 176 .smem_offset = IWL_22000_SMEM_OFFSET, \ 177 .smem_len = IWL_22000_SMEM_LEN, \ 178 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 179 .apmg_not_supported = true, \ 180 .trans.mq_rx_supported = true, \ 181 .vht_mu_mimo_supported = true, \ 182 .mac_addr_from_csr = 0x380, \ 183 .ht_params = &iwl_22000_ht_params, \ 184 .nvm_ver = IWL_22000_NVM_VERSION, \ 185 .trans.use_tfh = true, \ 186 .trans.rf_id = true, \ 187 .trans.gen2 = true, \ 188 .nvm_type = IWL_NVM_EXT, \ 189 .dbgc_supported = true, \ 190 .min_umac_error_event_table = 0x400000, \ 191 .d3_debug_data_base_addr = 0x401000, \ 192 .d3_debug_data_length = 60 * 1024, \ 193 .mon_smem_regs = { \ 194 .write_ptr = { \ 195 .addr = LDBG_M2S_BUF_WPTR, \ 196 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 197 }, \ 198 .cycle_cnt = { \ 199 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 200 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 201 }, \ 202 } 203 204 #define IWL_DEVICE_22500 \ 205 IWL_DEVICE_22000_COMMON, \ 206 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 207 .trans.base_params = &iwl_22000_base_params, \ 208 .gp2_reg_addr = 0xa02c68, \ 209 .mon_dram_regs = { \ 210 .write_ptr = { \ 211 .addr = MON_BUFF_WRPTR_VER2, \ 212 .mask = 0xffffffff, \ 213 }, \ 214 .cycle_cnt = { \ 215 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 216 .mask = 0xffffffff, \ 217 }, \ 218 } 219 220 #define IWL_DEVICE_AX210 \ 221 IWL_DEVICE_22000_COMMON, \ 222 .trans.umac_prph_offset = 0x300000, \ 223 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 224 .trans.base_params = &iwl_ax210_base_params, \ 225 .min_txq_size = 128, \ 226 .gp2_reg_addr = 0xd02c68, \ 227 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 228 .mon_dram_regs = { \ 229 .write_ptr = { \ 230 .addr = DBGC_CUR_DBGBUF_STATUS, \ 231 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 232 }, \ 233 .cycle_cnt = { \ 234 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 235 .mask = 0xffffffff, \ 236 }, \ 237 .cur_frag = { \ 238 .addr = DBGC_CUR_DBGBUF_STATUS, \ 239 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 240 }, \ 241 } 242 243 #define IWL_DEVICE_BZ_COMMON \ 244 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 245 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 246 .led_mode = IWL_LED_RF_STATE, \ 247 .nvm_hw_section_num = 10, \ 248 .non_shared_ant = ANT_B, \ 249 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 250 .dccm_len = IWL_22000_DCCM_LEN, \ 251 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 252 .dccm2_len = IWL_22000_DCCM2_LEN, \ 253 .smem_offset = IWL_22000_SMEM_OFFSET, \ 254 .smem_len = IWL_22000_SMEM_LEN, \ 255 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, \ 256 .apmg_not_supported = true, \ 257 .trans.mq_rx_supported = true, \ 258 .vht_mu_mimo_supported = true, \ 259 .mac_addr_from_csr = 0x30, \ 260 .ht_params = &iwl_22000_ht_params, \ 261 .nvm_ver = IWL_22000_NVM_VERSION, \ 262 .trans.use_tfh = true, \ 263 .trans.rf_id = true, \ 264 .trans.gen2 = true, \ 265 .nvm_type = IWL_NVM_EXT, \ 266 .dbgc_supported = true, \ 267 .min_umac_error_event_table = 0x400000, \ 268 .d3_debug_data_base_addr = 0x401000, \ 269 .d3_debug_data_length = 60 * 1024, \ 270 .mon_smem_regs = { \ 271 .write_ptr = { \ 272 .addr = LDBG_M2S_BUF_WPTR, \ 273 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 274 }, \ 275 .cycle_cnt = { \ 276 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 277 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 278 }, \ 279 } 280 281 #define IWL_DEVICE_BZ \ 282 IWL_DEVICE_BZ_COMMON, \ 283 .trans.umac_prph_offset = 0x300000, \ 284 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 285 .trans.base_params = &iwl_ax210_base_params, \ 286 .min_txq_size = 128, \ 287 .gp2_reg_addr = 0xd02c68, \ 288 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 289 .mon_dram_regs = { \ 290 .write_ptr = { \ 291 .addr = DBGC_CUR_DBGBUF_STATUS, \ 292 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 293 }, \ 294 .cycle_cnt = { \ 295 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 296 .mask = 0xffffffff, \ 297 }, \ 298 .cur_frag = { \ 299 .addr = DBGC_CUR_DBGBUF_STATUS, \ 300 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 301 }, \ 302 }, \ 303 .mon_dbgi_regs = { \ 304 .write_ptr = { \ 305 .addr = DBGI_SRAM_FIFO_POINTERS, \ 306 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 307 }, \ 308 } 309 310 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 311 .mq_rx_supported = true, 312 .use_tfh = true, 313 .rf_id = true, 314 .gen2 = true, 315 .device_family = IWL_DEVICE_FAMILY_22000, 316 .base_params = &iwl_22000_base_params, 317 }; 318 319 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 320 .mq_rx_supported = true, 321 .use_tfh = true, 322 .rf_id = true, 323 .gen2 = true, 324 .device_family = IWL_DEVICE_FAMILY_22000, 325 .base_params = &iwl_22000_base_params, 326 .integrated = true, 327 .xtal_latency = 500, 328 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 329 }; 330 331 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 332 .mq_rx_supported = true, 333 .use_tfh = true, 334 .rf_id = true, 335 .gen2 = true, 336 .device_family = IWL_DEVICE_FAMILY_22000, 337 .base_params = &iwl_22000_base_params, 338 .integrated = true, 339 .xtal_latency = 1820, 340 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 341 }; 342 343 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 344 .mq_rx_supported = true, 345 .use_tfh = true, 346 .rf_id = true, 347 .gen2 = true, 348 .device_family = IWL_DEVICE_FAMILY_22000, 349 .base_params = &iwl_22000_base_params, 350 .integrated = true, 351 .xtal_latency = 12000, 352 .low_latency_xtal = true, 353 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 354 }; 355 356 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 357 .mq_rx_supported = true, 358 .use_tfh = true, 359 .rf_id = true, 360 .gen2 = true, 361 .device_family = IWL_DEVICE_FAMILY_AX210, 362 .base_params = &iwl_ax210_base_params, 363 .umac_prph_offset = 0x300000, 364 }; 365 366 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 367 .mq_rx_supported = true, 368 .use_tfh = true, 369 .rf_id = true, 370 .gen2 = true, 371 .device_family = IWL_DEVICE_FAMILY_AX210, 372 .base_params = &iwl_ax210_base_params, 373 .umac_prph_offset = 0x300000, 374 .integrated = true, 375 /* TODO: the following values need to be checked */ 376 .xtal_latency = 500, 377 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 378 }; 379 380 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 381 .mq_rx_supported = true, 382 .use_tfh = true, 383 .rf_id = true, 384 .gen2 = true, 385 .device_family = IWL_DEVICE_FAMILY_AX210, 386 .base_params = &iwl_ax210_base_params, 387 .umac_prph_offset = 0x300000, 388 .integrated = true, 389 .low_latency_xtal = true, 390 .xtal_latency = 12000, 391 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 392 }; 393 394 /* 395 * If the device doesn't support HE, no need to have that many buffers. 396 * 22000 devices can split multiple frames into a single RB, so fewer are 397 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 398 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 399 * additional overhead to account for processing time. 400 */ 401 #define IWL_NUM_RBDS_NON_HE 512 402 #define IWL_NUM_RBDS_22000_HE 2048 403 #define IWL_NUM_RBDS_AX210_HE 4096 404 405 /* 406 * All JF radio modules are part of the 9000 series, but the MAC part 407 * looks more like 22000. That's why this device is here, but called 408 * 9560 nevertheless. 409 */ 410 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 411 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 412 IWL_DEVICE_22500, 413 .num_rbds = IWL_NUM_RBDS_NON_HE, 414 }; 415 416 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 417 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 418 IWL_DEVICE_22500, 419 .num_rbds = IWL_NUM_RBDS_NON_HE, 420 }; 421 422 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 423 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 424 IWL_DEVICE_22500, 425 /* 426 * This device doesn't support receiving BlockAck with a large bitmap 427 * so we need to restrict the size of transmitted aggregation to the 428 * HT size; mac80211 would otherwise pick the HE max (256) by default. 429 */ 430 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 431 .num_rbds = IWL_NUM_RBDS_NON_HE, 432 }; 433 434 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 435 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 436 IWL_DEVICE_22500, 437 /* 438 * This device doesn't support receiving BlockAck with a large bitmap 439 * so we need to restrict the size of transmitted aggregation to the 440 * HT size; mac80211 would otherwise pick the HE max (256) by default. 441 */ 442 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 443 .num_rbds = IWL_NUM_RBDS_NON_HE, 444 }; 445 446 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 447 .device_family = IWL_DEVICE_FAMILY_22000, 448 .base_params = &iwl_22000_base_params, 449 .mq_rx_supported = true, 450 .use_tfh = true, 451 .rf_id = true, 452 .gen2 = true, 453 .bisr_workaround = 1, 454 }; 455 456 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 457 .device_family = IWL_DEVICE_FAMILY_AX210, 458 .base_params = &iwl_ax210_base_params, 459 .mq_rx_supported = true, 460 .use_tfh = true, 461 .rf_id = true, 462 .gen2 = true, 463 .integrated = true, 464 .umac_prph_offset = 0x300000 465 }; 466 467 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 468 .device_family = IWL_DEVICE_FAMILY_BZ, 469 .base_params = &iwl_ax210_base_params, 470 .mq_rx_supported = true, 471 .use_tfh = true, 472 .rf_id = true, 473 .gen2 = true, 474 .integrated = true, 475 .umac_prph_offset = 0x300000, 476 .xtal_latency = 12000, 477 .low_latency_xtal = true, 478 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 479 }; 480 481 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 482 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 483 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 484 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 485 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 486 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 487 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 488 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 489 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 490 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 491 492 const char iwl_ax200_killer_1650w_name[] = 493 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 494 const char iwl_ax200_killer_1650x_name[] = 495 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 496 const char iwl_ax201_killer_1650s_name[] = 497 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 498 const char iwl_ax201_killer_1650i_name[] = 499 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 500 const char iwl_ax210_killer_1675w_name[] = 501 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 502 const char iwl_ax210_killer_1675x_name[] = 503 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 504 const char iwl_ax211_killer_1675s_name[] = 505 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 506 const char iwl_ax211_killer_1675i_name[] = 507 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 508 const char iwl_ax411_killer_1690s_name[] = 509 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 510 const char iwl_ax411_killer_1690i_name[] = 511 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 512 513 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 514 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 515 IWL_DEVICE_22500, 516 /* 517 * This device doesn't support receiving BlockAck with a large bitmap 518 * so we need to restrict the size of transmitted aggregation to the 519 * HT size; mac80211 would otherwise pick the HE max (256) by default. 520 */ 521 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 522 .tx_with_siso_diversity = true, 523 .num_rbds = IWL_NUM_RBDS_22000_HE, 524 }; 525 526 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 527 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 528 IWL_DEVICE_22500, 529 /* 530 * This device doesn't support receiving BlockAck with a large bitmap 531 * so we need to restrict the size of transmitted aggregation to the 532 * HT size; mac80211 would otherwise pick the HE max (256) by default. 533 */ 534 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 535 .num_rbds = IWL_NUM_RBDS_22000_HE, 536 }; 537 538 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 539 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 540 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 541 IWL_DEVICE_22500, 542 /* 543 * This device doesn't support receiving BlockAck with a large bitmap 544 * so we need to restrict the size of transmitted aggregation to the 545 * HT size; mac80211 would otherwise pick the HE max (256) by default. 546 */ 547 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 548 .num_rbds = IWL_NUM_RBDS_22000_HE, 549 }; 550 551 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 552 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 553 IWL_DEVICE_22500, 554 /* 555 * This device doesn't support receiving BlockAck with a large bitmap 556 * so we need to restrict the size of transmitted aggregation to the 557 * HT size; mac80211 would otherwise pick the HE max (256) by default. 558 */ 559 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 560 .tx_with_siso_diversity = true, 561 .num_rbds = IWL_NUM_RBDS_22000_HE, 562 }; 563 564 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 565 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 566 IWL_DEVICE_22500, 567 /* 568 * This device doesn't support receiving BlockAck with a large bitmap 569 * so we need to restrict the size of transmitted aggregation to the 570 * HT size; mac80211 would otherwise pick the HE max (256) by default. 571 */ 572 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 573 .num_rbds = IWL_NUM_RBDS_22000_HE, 574 }; 575 576 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 577 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 578 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 579 IWL_DEVICE_22500, 580 /* 581 * This device doesn't support receiving BlockAck with a large bitmap 582 * so we need to restrict the size of transmitted aggregation to the 583 * HT size; mac80211 would otherwise pick the HE max (256) by default. 584 */ 585 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 586 .num_rbds = IWL_NUM_RBDS_22000_HE, 587 }; 588 589 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 590 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 591 IWL_DEVICE_22500, 592 /* 593 * This device doesn't support receiving BlockAck with a large bitmap 594 * so we need to restrict the size of transmitted aggregation to the 595 * HT size; mac80211 would otherwise pick the HE max (256) by default. 596 */ 597 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 598 .tx_with_siso_diversity = true, 599 .num_rbds = IWL_NUM_RBDS_22000_HE, 600 }; 601 602 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 603 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 604 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 605 IWL_DEVICE_22500, 606 /* 607 * This device doesn't support receiving BlockAck with a large bitmap 608 * so we need to restrict the size of transmitted aggregation to the 609 * HT size; mac80211 would otherwise pick the HE max (256) by default. 610 */ 611 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 612 .num_rbds = IWL_NUM_RBDS_22000_HE, 613 }; 614 615 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 616 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 617 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 618 IWL_DEVICE_22500, 619 /* 620 * This device doesn't support receiving BlockAck with a large bitmap 621 * so we need to restrict the size of transmitted aggregation to the 622 * HT size; mac80211 would otherwise pick the HE max (256) by default. 623 */ 624 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 625 .num_rbds = IWL_NUM_RBDS_22000_HE, 626 }; 627 628 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 629 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 630 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 631 IWL_DEVICE_22500, 632 /* 633 * This device doesn't support receiving BlockAck with a large bitmap 634 * so we need to restrict the size of transmitted aggregation to the 635 * HT size; mac80211 would otherwise pick the HE max (256) by default. 636 */ 637 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 638 .num_rbds = IWL_NUM_RBDS_22000_HE, 639 }; 640 641 const struct iwl_cfg iwl_ax200_cfg_cc = { 642 .fw_name_pre = IWL_CC_A_FW_PRE, 643 IWL_DEVICE_22500, 644 /* 645 * This device doesn't support receiving BlockAck with a large bitmap 646 * so we need to restrict the size of transmitted aggregation to the 647 * HT size; mac80211 would otherwise pick the HE max (256) by default. 648 */ 649 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 650 .num_rbds = IWL_NUM_RBDS_22000_HE, 651 }; 652 653 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 654 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 655 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 656 IWL_DEVICE_22500, 657 /* 658 * This device doesn't support receiving BlockAck with a large bitmap 659 * so we need to restrict the size of transmitted aggregation to the 660 * HT size; mac80211 would otherwise pick the HE max (256) by default. 661 */ 662 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 663 .num_rbds = IWL_NUM_RBDS_22000_HE, 664 }; 665 666 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 667 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 668 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 669 IWL_DEVICE_22500, 670 /* 671 * This device doesn't support receiving BlockAck with a large bitmap 672 * so we need to restrict the size of transmitted aggregation to the 673 * HT size; mac80211 would otherwise pick the HE max (256) by default. 674 */ 675 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 676 .num_rbds = IWL_NUM_RBDS_22000_HE, 677 }; 678 679 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 680 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 681 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 682 IWL_DEVICE_22500, 683 /* 684 * This device doesn't support receiving BlockAck with a large bitmap 685 * so we need to restrict the size of transmitted aggregation to the 686 * HT size; mac80211 would otherwise pick the HE max (256) by default. 687 */ 688 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 689 .num_rbds = IWL_NUM_RBDS_22000_HE, 690 }; 691 692 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 693 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 694 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 695 IWL_DEVICE_22500, 696 /* 697 * This device doesn't support receiving BlockAck with a large bitmap 698 * so we need to restrict the size of transmitted aggregation to the 699 * HT size; mac80211 would otherwise pick the HE max (256) by default. 700 */ 701 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 702 .num_rbds = IWL_NUM_RBDS_22000_HE, 703 }; 704 705 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 706 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 707 IWL_DEVICE_22500, 708 /* 709 * This device doesn't support receiving BlockAck with a large bitmap 710 * so we need to restrict the size of transmitted aggregation to the 711 * HT size; mac80211 would otherwise pick the HE max (256) by default. 712 */ 713 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 714 .num_rbds = IWL_NUM_RBDS_22000_HE, 715 }; 716 717 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 718 .name = "Intel(R) Wireless-AC 9560 160MHz", 719 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 720 IWL_DEVICE_AX210, 721 .num_rbds = IWL_NUM_RBDS_NON_HE, 722 }; 723 724 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 725 .name = iwl_ax211_name, 726 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 727 .uhb_supported = true, 728 IWL_DEVICE_AX210, 729 .num_rbds = IWL_NUM_RBDS_AX210_HE, 730 }; 731 732 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 733 .name = iwl_ax211_name, 734 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 735 .uhb_supported = true, 736 IWL_DEVICE_AX210, 737 .num_rbds = IWL_NUM_RBDS_AX210_HE, 738 .trans.xtal_latency = 12000, 739 .trans.low_latency_xtal = true, 740 }; 741 742 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 743 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 744 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 745 .uhb_supported = true, 746 IWL_DEVICE_AX210, 747 .num_rbds = IWL_NUM_RBDS_AX210_HE, 748 }; 749 750 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 751 .name = iwl_ax411_name, 752 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 753 .uhb_supported = true, 754 IWL_DEVICE_AX210, 755 .num_rbds = IWL_NUM_RBDS_AX210_HE, 756 }; 757 758 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 759 .name = iwl_ax411_name, 760 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 761 .uhb_supported = true, 762 IWL_DEVICE_AX210, 763 .num_rbds = IWL_NUM_RBDS_AX210_HE, 764 .trans.xtal_latency = 12000, 765 .trans.low_latency_xtal = true, 766 }; 767 768 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 769 .name = iwl_ax411_name, 770 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 771 .uhb_supported = true, 772 IWL_DEVICE_AX210, 773 .num_rbds = IWL_NUM_RBDS_AX210_HE, 774 }; 775 776 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 777 .name = iwl_ax211_name, 778 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 779 .uhb_supported = true, 780 IWL_DEVICE_AX210, 781 .num_rbds = IWL_NUM_RBDS_AX210_HE, 782 }; 783 784 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 785 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 786 .uhb_supported = true, 787 IWL_DEVICE_AX210, 788 .num_rbds = IWL_NUM_RBDS_AX210_HE, 789 }; 790 791 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 792 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 793 .uhb_supported = true, 794 IWL_DEVICE_AX210, 795 .num_rbds = IWL_NUM_RBDS_AX210_HE, 796 }; 797 798 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 799 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 800 .uhb_supported = true, 801 IWL_DEVICE_AX210, 802 .num_rbds = IWL_NUM_RBDS_AX210_HE, 803 }; 804 805 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 806 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 807 .uhb_supported = true, 808 IWL_DEVICE_AX210, 809 .num_rbds = IWL_NUM_RBDS_AX210_HE, 810 }; 811 812 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 813 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 814 .uhb_supported = true, 815 IWL_DEVICE_AX210, 816 .num_rbds = IWL_NUM_RBDS_AX210_HE, 817 }; 818 819 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 820 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 821 .uhb_supported = true, 822 IWL_DEVICE_AX210, 823 .num_rbds = IWL_NUM_RBDS_AX210_HE, 824 }; 825 826 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 827 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 828 .uhb_supported = false, 829 IWL_DEVICE_AX210, 830 .num_rbds = IWL_NUM_RBDS_AX210_HE, 831 }; 832 833 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 834 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 835 .uhb_supported = false, 836 IWL_DEVICE_AX210, 837 .num_rbds = IWL_NUM_RBDS_AX210_HE, 838 }; 839 840 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 841 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 842 .uhb_supported = true, 843 IWL_DEVICE_AX210, 844 .num_rbds = IWL_NUM_RBDS_AX210_HE, 845 }; 846 847 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 848 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 849 .uhb_supported = true, 850 IWL_DEVICE_AX210, 851 .num_rbds = IWL_NUM_RBDS_AX210_HE, 852 }; 853 854 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 855 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 856 .uhb_supported = false, 857 IWL_DEVICE_AX210, 858 .num_rbds = IWL_NUM_RBDS_AX210_HE, 859 }; 860 861 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 862 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 863 IWL_DEVICE_AX210, 864 .num_rbds = IWL_NUM_RBDS_AX210_HE, 865 }; 866 867 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 868 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 869 IWL_DEVICE_22500, 870 /* 871 * This device doesn't support receiving BlockAck with a large bitmap 872 * so we need to restrict the size of transmitted aggregation to the 873 * HT size; mac80211 would otherwise pick the HE max (256) by default. 874 */ 875 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 876 .num_rbds = IWL_NUM_RBDS_22000_HE, 877 }; 878 879 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 880 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 881 .uhb_supported = true, 882 IWL_DEVICE_BZ, 883 .num_rbds = IWL_NUM_RBDS_AX210_HE, 884 }; 885 886 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 887 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 888 .uhb_supported = true, 889 IWL_DEVICE_BZ, 890 .num_rbds = IWL_NUM_RBDS_AX210_HE, 891 }; 892 893 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 894 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 895 .uhb_supported = true, 896 IWL_DEVICE_BZ, 897 .num_rbds = IWL_NUM_RBDS_AX210_HE, 898 }; 899 900 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 901 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 902 .uhb_supported = true, 903 IWL_DEVICE_BZ, 904 .num_rbds = IWL_NUM_RBDS_AX210_HE, 905 }; 906 907 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 908 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 909 .uhb_supported = true, 910 IWL_DEVICE_BZ, 911 .num_rbds = IWL_NUM_RBDS_AX210_HE, 912 }; 913 914 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 915 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 916 .uhb_supported = true, 917 IWL_DEVICE_BZ, 918 .num_rbds = IWL_NUM_RBDS_AX210_HE, 919 }; 920 921 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 922 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 923 .uhb_supported = true, 924 IWL_DEVICE_BZ, 925 .num_rbds = IWL_NUM_RBDS_AX210_HE, 926 }; 927 928 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 929 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 930 .uhb_supported = true, 931 IWL_DEVICE_BZ, 932 .num_rbds = IWL_NUM_RBDS_AX210_HE, 933 }; 934 935 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 936 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 937 .uhb_supported = true, 938 IWL_DEVICE_BZ, 939 .num_rbds = IWL_NUM_RBDS_AX210_HE, 940 }; 941 942 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 943 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 944 .uhb_supported = true, 945 IWL_DEVICE_BZ, 946 .num_rbds = IWL_NUM_RBDS_AX210_HE, 947 }; 948 949 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 950 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 951 .uhb_supported = true, 952 IWL_DEVICE_BZ, 953 .num_rbds = IWL_NUM_RBDS_AX210_HE, 954 }; 955 956 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 957 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 958 .uhb_supported = true, 959 IWL_DEVICE_BZ, 960 .num_rbds = IWL_NUM_RBDS_AX210_HE, 961 }; 962 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 963 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 964 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 965 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 966 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 967 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 968 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 969 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 970 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 971 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 972 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 973 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 974 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 975 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 976 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 977 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 978 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 979 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 980 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 981 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 982 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 983 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 984 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 985 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 986 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 987 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 988 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 989 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 990 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 991 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 992 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 993 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 994 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 995