1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "dp_mon.h" 8 #include "debug.h" 9 #include "dp_rx.h" 10 #include "dp_tx.h" 11 #include "peer.h" 12 13 static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv, 14 struct hal_rx_user_status *rx_user_status) 15 { 16 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 17 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 18 19 rx_user_status->ul_ofdma_user_v0_word0 = 20 __le32_to_cpu(ppdu_end_user->usr_resp_ref); 21 rx_user_status->ul_ofdma_user_v0_word1 = 22 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext); 23 } 24 25 static void 26 ath12k_dp_mon_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 27 struct hal_rx_user_status *rx_user_status) 28 { 29 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 30 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 31 u32 mpdu_ok_byte_count = __le32_to_cpu(ppdu_end_user->mpdu_ok_cnt); 32 u32 mpdu_err_byte_count = __le32_to_cpu(ppdu_end_user->mpdu_err_cnt); 33 34 rx_user_status->mpdu_ok_byte_count = 35 u32_get_bits(mpdu_ok_byte_count, 36 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT); 37 rx_user_status->mpdu_err_byte_count = 38 u32_get_bits(mpdu_err_byte_count, 39 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT); 40 } 41 42 static void 43 ath12k_dp_mon_rx_populate_mu_user_info(void *rx_tlv, 44 struct hal_rx_mon_ppdu_info *ppdu_info, 45 struct hal_rx_user_status *rx_user_status) 46 { 47 rx_user_status->ast_index = ppdu_info->ast_index; 48 rx_user_status->tid = ppdu_info->tid; 49 rx_user_status->tcp_ack_msdu_count = 50 ppdu_info->tcp_ack_msdu_count; 51 rx_user_status->tcp_msdu_count = 52 ppdu_info->tcp_msdu_count; 53 rx_user_status->udp_msdu_count = 54 ppdu_info->udp_msdu_count; 55 rx_user_status->other_msdu_count = 56 ppdu_info->other_msdu_count; 57 rx_user_status->frame_control = ppdu_info->frame_control; 58 rx_user_status->frame_control_info_valid = 59 ppdu_info->frame_control_info_valid; 60 rx_user_status->data_sequence_control_info_valid = 61 ppdu_info->data_sequence_control_info_valid; 62 rx_user_status->first_data_seq_ctrl = 63 ppdu_info->first_data_seq_ctrl; 64 rx_user_status->preamble_type = ppdu_info->preamble_type; 65 rx_user_status->ht_flags = ppdu_info->ht_flags; 66 rx_user_status->vht_flags = ppdu_info->vht_flags; 67 rx_user_status->he_flags = ppdu_info->he_flags; 68 rx_user_status->rs_flags = ppdu_info->rs_flags; 69 70 rx_user_status->mpdu_cnt_fcs_ok = 71 ppdu_info->num_mpdu_fcs_ok; 72 rx_user_status->mpdu_cnt_fcs_err = 73 ppdu_info->num_mpdu_fcs_err; 74 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0], 75 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 76 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 77 78 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 79 } 80 81 static void ath12k_dp_mon_parse_vht_sig_a(u8 *tlv_data, 82 struct hal_rx_mon_ppdu_info *ppdu_info) 83 { 84 struct hal_rx_vht_sig_a_info *vht_sig = 85 (struct hal_rx_vht_sig_a_info *)tlv_data; 86 u32 nsts, group_id, info0, info1; 87 u8 gi_setting; 88 89 info0 = __le32_to_cpu(vht_sig->info0); 90 info1 = __le32_to_cpu(vht_sig->info1); 91 92 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 93 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS); 94 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING); 95 switch (gi_setting) { 96 case HAL_RX_VHT_SIG_A_NORMAL_GI: 97 ppdu_info->gi = HAL_RX_GI_0_8_US; 98 break; 99 case HAL_RX_VHT_SIG_A_SHORT_GI: 100 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 101 ppdu_info->gi = HAL_RX_GI_0_4_US; 102 break; 103 } 104 105 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC); 106 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS); 107 if (ppdu_info->is_stbc && nsts > 0) 108 nsts = ((nsts + 1) >> 1) - 1; 109 110 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK); 111 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW); 112 ppdu_info->beamformed = u32_get_bits(info1, 113 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED); 114 group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID); 115 if (group_id == 0 || group_id == 63) 116 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 117 else 118 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 119 ppdu_info->vht_flag_values5 = group_id; 120 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 121 ppdu_info->nss); 122 ppdu_info->vht_flag_values2 = ppdu_info->bw; 123 ppdu_info->vht_flag_values4 = 124 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 125 } 126 127 static void ath12k_dp_mon_parse_ht_sig(u8 *tlv_data, 128 struct hal_rx_mon_ppdu_info *ppdu_info) 129 { 130 struct hal_rx_ht_sig_info *ht_sig = 131 (struct hal_rx_ht_sig_info *)tlv_data; 132 u32 info0 = __le32_to_cpu(ht_sig->info0); 133 u32 info1 = __le32_to_cpu(ht_sig->info1); 134 135 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS); 136 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW); 137 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC); 138 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING); 139 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI); 140 ppdu_info->nss = (ppdu_info->mcs >> 3); 141 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 142 } 143 144 static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data, 145 struct hal_rx_mon_ppdu_info *ppdu_info) 146 { 147 struct hal_rx_lsig_b_info *lsigb = 148 (struct hal_rx_lsig_b_info *)tlv_data; 149 u32 info0 = __le32_to_cpu(lsigb->info0); 150 u8 rate; 151 152 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE); 153 switch (rate) { 154 case 1: 155 rate = HAL_RX_LEGACY_RATE_1_MBPS; 156 break; 157 case 2: 158 case 5: 159 rate = HAL_RX_LEGACY_RATE_2_MBPS; 160 break; 161 case 3: 162 case 6: 163 rate = HAL_RX_LEGACY_RATE_5_5_MBPS; 164 break; 165 case 4: 166 case 7: 167 rate = HAL_RX_LEGACY_RATE_11_MBPS; 168 break; 169 default: 170 rate = HAL_RX_LEGACY_RATE_INVALID; 171 } 172 173 ppdu_info->rate = rate; 174 ppdu_info->cck_flag = 1; 175 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 176 } 177 178 static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data, 179 struct hal_rx_mon_ppdu_info *ppdu_info) 180 { 181 struct hal_rx_lsig_a_info *lsiga = 182 (struct hal_rx_lsig_a_info *)tlv_data; 183 u32 info0 = __le32_to_cpu(lsiga->info0); 184 u8 rate; 185 186 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE); 187 switch (rate) { 188 case 8: 189 rate = HAL_RX_LEGACY_RATE_48_MBPS; 190 break; 191 case 9: 192 rate = HAL_RX_LEGACY_RATE_24_MBPS; 193 break; 194 case 10: 195 rate = HAL_RX_LEGACY_RATE_12_MBPS; 196 break; 197 case 11: 198 rate = HAL_RX_LEGACY_RATE_6_MBPS; 199 break; 200 case 12: 201 rate = HAL_RX_LEGACY_RATE_54_MBPS; 202 break; 203 case 13: 204 rate = HAL_RX_LEGACY_RATE_36_MBPS; 205 break; 206 case 14: 207 rate = HAL_RX_LEGACY_RATE_18_MBPS; 208 break; 209 case 15: 210 rate = HAL_RX_LEGACY_RATE_9_MBPS; 211 break; 212 default: 213 rate = HAL_RX_LEGACY_RATE_INVALID; 214 } 215 216 ppdu_info->rate = rate; 217 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 218 } 219 220 static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data, 221 struct hal_rx_mon_ppdu_info *ppdu_info) 222 { 223 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma = 224 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data; 225 u32 info0, value; 226 227 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0); 228 229 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN; 230 231 /* HE-data2 */ 232 ppdu_info->he_data2 |= HE_TXBF_KNOWN; 233 234 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS); 235 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 236 ppdu_info->he_data3 |= value; 237 238 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM); 239 value = value << HE_DCM_SHIFT; 240 ppdu_info->he_data3 |= value; 241 242 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING); 243 ppdu_info->ldpc = value; 244 value = value << HE_CODING_SHIFT; 245 ppdu_info->he_data3 |= value; 246 247 /* HE-data4 */ 248 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID); 249 value = value << HE_STA_ID_SHIFT; 250 ppdu_info->he_data4 |= value; 251 252 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS); 253 ppdu_info->beamformed = u32_get_bits(info0, 254 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF); 255 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 256 } 257 258 static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data, 259 struct hal_rx_mon_ppdu_info *ppdu_info) 260 { 261 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu = 262 (struct hal_rx_he_sig_b2_mu_info *)tlv_data; 263 u32 info0, value; 264 265 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 266 267 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN; 268 269 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS); 270 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 271 ppdu_info->he_data3 |= value; 272 273 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING); 274 ppdu_info->ldpc = value; 275 value = value << HE_CODING_SHIFT; 276 ppdu_info->he_data3 |= value; 277 278 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID); 279 value = value << HE_STA_ID_SHIFT; 280 ppdu_info->he_data4 |= value; 281 282 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS); 283 } 284 285 static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data, 286 struct hal_rx_mon_ppdu_info *ppdu_info) 287 { 288 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu = 289 (struct hal_rx_he_sig_b1_mu_info *)tlv_data; 290 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 291 u16 ru_tones; 292 293 ru_tones = u32_get_bits(info0, 294 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION); 295 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 296 ppdu_info->he_RU[0] = ru_tones; 297 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 298 } 299 300 static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data, 301 struct hal_rx_mon_ppdu_info *ppdu_info) 302 { 303 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl = 304 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data; 305 u32 info0, info1, value; 306 u16 he_gi = 0, he_ltf = 0; 307 308 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 309 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 310 311 ppdu_info->he_mu_flags = 1; 312 313 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE; 314 ppdu_info->he_data1 |= 315 HE_BSS_COLOR_KNOWN | 316 HE_DL_UL_KNOWN | 317 HE_LDPC_EXTRA_SYMBOL_KNOWN | 318 HE_STBC_KNOWN | 319 HE_DATA_BW_RU_KNOWN | 320 HE_DOPPLER_KNOWN; 321 322 ppdu_info->he_data2 = 323 HE_GI_KNOWN | 324 HE_LTF_SYMBOLS_KNOWN | 325 HE_PRE_FEC_PADDING_KNOWN | 326 HE_PE_DISAMBIGUITY_KNOWN | 327 HE_TXOP_KNOWN | 328 HE_MIDABLE_PERIODICITY_KNOWN; 329 330 /* data3 */ 331 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR); 332 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG); 333 value = value << HE_DL_UL_SHIFT; 334 ppdu_info->he_data3 |= value; 335 336 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA); 337 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 338 ppdu_info->he_data3 |= value; 339 340 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC); 341 value = value << HE_STBC_SHIFT; 342 ppdu_info->he_data3 |= value; 343 344 /* data4 */ 345 ppdu_info->he_data4 = u32_get_bits(info0, 346 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE); 347 ppdu_info->he_data4 = value; 348 349 /* data5 */ 350 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 351 ppdu_info->he_data5 = value; 352 ppdu_info->bw = value; 353 354 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE); 355 switch (value) { 356 case 0: 357 he_gi = HE_GI_0_8; 358 he_ltf = HE_LTF_4_X; 359 break; 360 case 1: 361 he_gi = HE_GI_0_8; 362 he_ltf = HE_LTF_2_X; 363 break; 364 case 2: 365 he_gi = HE_GI_1_6; 366 he_ltf = HE_LTF_2_X; 367 break; 368 case 3: 369 he_gi = HE_GI_3_2; 370 he_ltf = HE_LTF_4_X; 371 break; 372 } 373 374 ppdu_info->gi = he_gi; 375 value = he_gi << HE_GI_SHIFT; 376 ppdu_info->he_data5 |= value; 377 378 value = he_ltf << HE_LTF_SIZE_SHIFT; 379 ppdu_info->he_data5 |= value; 380 381 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB); 382 value = (value << HE_LTF_SYM_SHIFT); 383 ppdu_info->he_data5 |= value; 384 385 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR); 386 value = value << HE_PRE_FEC_PAD_SHIFT; 387 ppdu_info->he_data5 |= value; 388 389 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM); 390 value = value << HE_PE_DISAMBIGUITY_SHIFT; 391 ppdu_info->he_data5 |= value; 392 393 /*data6*/ 394 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION); 395 value = value << HE_DOPPLER_SHIFT; 396 ppdu_info->he_data6 |= value; 397 398 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION); 399 value = value << HE_TXOP_SHIFT; 400 ppdu_info->he_data6 |= value; 401 402 /* HE-MU Flags */ 403 /* HE-MU-flags1 */ 404 ppdu_info->he_flags1 = 405 HE_SIG_B_MCS_KNOWN | 406 HE_SIG_B_DCM_KNOWN | 407 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN | 408 HE_SIG_B_SYM_NUM_KNOWN | 409 HE_RU_0_KNOWN; 410 411 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB); 412 ppdu_info->he_flags1 |= value; 413 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB); 414 value = value << HE_DCM_FLAG_1_SHIFT; 415 ppdu_info->he_flags1 |= value; 416 417 /* HE-MU-flags2 */ 418 ppdu_info->he_flags2 = HE_BW_KNOWN; 419 420 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 421 ppdu_info->he_flags2 |= value; 422 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB); 423 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT; 424 ppdu_info->he_flags2 |= value; 425 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB); 426 value = value - 1; 427 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT; 428 ppdu_info->he_flags2 |= value; 429 430 ppdu_info->is_stbc = info1 & 431 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC; 432 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 433 } 434 435 static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data, 436 struct hal_rx_mon_ppdu_info *ppdu_info) 437 { 438 struct hal_rx_he_sig_a_su_info *he_sig_a = 439 (struct hal_rx_he_sig_a_su_info *)tlv_data; 440 u32 info0, info1, value; 441 u32 dcm; 442 u8 he_dcm = 0, he_stbc = 0; 443 u16 he_gi = 0, he_ltf = 0; 444 445 ppdu_info->he_flags = 1; 446 447 info0 = __le32_to_cpu(he_sig_a->info0); 448 info1 = __le32_to_cpu(he_sig_a->info1); 449 450 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND); 451 if (value == 0) 452 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE; 453 else 454 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE; 455 456 ppdu_info->he_data1 |= 457 HE_BSS_COLOR_KNOWN | 458 HE_BEAM_CHANGE_KNOWN | 459 HE_DL_UL_KNOWN | 460 HE_MCS_KNOWN | 461 HE_DCM_KNOWN | 462 HE_CODING_KNOWN | 463 HE_LDPC_EXTRA_SYMBOL_KNOWN | 464 HE_STBC_KNOWN | 465 HE_DATA_BW_RU_KNOWN | 466 HE_DOPPLER_KNOWN; 467 468 ppdu_info->he_data2 |= 469 HE_GI_KNOWN | 470 HE_TXBF_KNOWN | 471 HE_PE_DISAMBIGUITY_KNOWN | 472 HE_TXOP_KNOWN | 473 HE_LTF_SYMBOLS_KNOWN | 474 HE_PRE_FEC_PADDING_KNOWN | 475 HE_MIDABLE_PERIODICITY_KNOWN; 476 477 ppdu_info->he_data3 = u32_get_bits(info0, 478 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR); 479 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE); 480 value = value << HE_BEAM_CHANGE_SHIFT; 481 ppdu_info->he_data3 |= value; 482 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG); 483 value = value << HE_DL_UL_SHIFT; 484 ppdu_info->he_data3 |= value; 485 486 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 487 ppdu_info->mcs = value; 488 value = value << HE_TRANSMIT_MCS_SHIFT; 489 ppdu_info->he_data3 |= value; 490 491 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 492 he_dcm = value; 493 value = value << HE_DCM_SHIFT; 494 ppdu_info->he_data3 |= value; 495 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 496 value = value << HE_CODING_SHIFT; 497 ppdu_info->he_data3 |= value; 498 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA); 499 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 500 ppdu_info->he_data3 |= value; 501 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 502 he_stbc = value; 503 value = value << HE_STBC_SHIFT; 504 ppdu_info->he_data3 |= value; 505 506 /* data4 */ 507 ppdu_info->he_data4 = u32_get_bits(info0, 508 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE); 509 510 /* data5 */ 511 value = u32_get_bits(info0, 512 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 513 ppdu_info->he_data5 = value; 514 ppdu_info->bw = value; 515 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE); 516 switch (value) { 517 case 0: 518 he_gi = HE_GI_0_8; 519 he_ltf = HE_LTF_1_X; 520 break; 521 case 1: 522 he_gi = HE_GI_0_8; 523 he_ltf = HE_LTF_2_X; 524 break; 525 case 2: 526 he_gi = HE_GI_1_6; 527 he_ltf = HE_LTF_2_X; 528 break; 529 case 3: 530 if (he_dcm && he_stbc) { 531 he_gi = HE_GI_0_8; 532 he_ltf = HE_LTF_4_X; 533 } else { 534 he_gi = HE_GI_3_2; 535 he_ltf = HE_LTF_4_X; 536 } 537 break; 538 } 539 ppdu_info->gi = he_gi; 540 value = he_gi << HE_GI_SHIFT; 541 ppdu_info->he_data5 |= value; 542 value = he_ltf << HE_LTF_SIZE_SHIFT; 543 ppdu_info->ltf_size = he_ltf; 544 ppdu_info->he_data5 |= value; 545 546 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 547 value = (value << HE_LTF_SYM_SHIFT); 548 ppdu_info->he_data5 |= value; 549 550 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR); 551 value = value << HE_PRE_FEC_PAD_SHIFT; 552 ppdu_info->he_data5 |= value; 553 554 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 555 value = value << HE_TXBF_SHIFT; 556 ppdu_info->he_data5 |= value; 557 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM); 558 value = value << HE_PE_DISAMBIGUITY_SHIFT; 559 ppdu_info->he_data5 |= value; 560 561 /* data6 */ 562 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 563 value++; 564 ppdu_info->he_data6 = value; 565 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND); 566 value = value << HE_DOPPLER_SHIFT; 567 ppdu_info->he_data6 |= value; 568 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION); 569 value = value << HE_TXOP_SHIFT; 570 ppdu_info->he_data6 |= value; 571 572 ppdu_info->mcs = 573 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 574 ppdu_info->bw = 575 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 576 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 577 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 578 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 579 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 580 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 581 ppdu_info->dcm = dcm; 582 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 583 } 584 585 static enum hal_rx_mon_status 586 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab, 587 struct ath12k_mon_data *pmon, 588 u32 tlv_tag, u8 *tlv_data, u32 userid) 589 { 590 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 591 u32 info[7]; 592 593 switch (tlv_tag) { 594 case HAL_RX_PPDU_START: { 595 struct hal_rx_ppdu_start *ppdu_start = 596 (struct hal_rx_ppdu_start *)tlv_data; 597 598 info[0] = __le32_to_cpu(ppdu_start->info0); 599 600 ppdu_info->ppdu_id = 601 u32_get_bits(info[0], HAL_RX_PPDU_START_INFO0_PPDU_ID); 602 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); 603 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); 604 605 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) { 606 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id; 607 ppdu_info->num_users = 0; 608 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0, 609 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 610 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 611 } 612 break; 613 } 614 case HAL_RX_PPDU_END_USER_STATS: { 615 struct hal_rx_ppdu_end_user_stats *eu_stats = 616 (struct hal_rx_ppdu_end_user_stats *)tlv_data; 617 618 info[0] = __le32_to_cpu(eu_stats->info0); 619 info[1] = __le32_to_cpu(eu_stats->info1); 620 info[2] = __le32_to_cpu(eu_stats->info2); 621 info[4] = __le32_to_cpu(eu_stats->info4); 622 info[5] = __le32_to_cpu(eu_stats->info5); 623 info[6] = __le32_to_cpu(eu_stats->info6); 624 625 ppdu_info->ast_index = 626 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX); 627 ppdu_info->fc_valid = 628 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID); 629 ppdu_info->tid = 630 ffs(u32_get_bits(info[6], 631 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP) 632 - 1); 633 ppdu_info->tcp_msdu_count = 634 u32_get_bits(info[4], 635 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT); 636 ppdu_info->udp_msdu_count = 637 u32_get_bits(info[4], 638 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT); 639 ppdu_info->other_msdu_count = 640 u32_get_bits(info[5], 641 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT); 642 ppdu_info->tcp_ack_msdu_count = 643 u32_get_bits(info[5], 644 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT); 645 ppdu_info->preamble_type = 646 u32_get_bits(info[1], 647 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE); 648 ppdu_info->num_mpdu_fcs_ok = 649 u32_get_bits(info[1], 650 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK); 651 ppdu_info->num_mpdu_fcs_err = 652 u32_get_bits(info[0], 653 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR); 654 switch (ppdu_info->preamble_type) { 655 case HAL_RX_PREAMBLE_11N: 656 ppdu_info->ht_flags = 1; 657 break; 658 case HAL_RX_PREAMBLE_11AC: 659 ppdu_info->vht_flags = 1; 660 break; 661 case HAL_RX_PREAMBLE_11AX: 662 ppdu_info->he_flags = 1; 663 break; 664 default: 665 break; 666 } 667 668 if (userid < HAL_MAX_UL_MU_USERS) { 669 struct hal_rx_user_status *rxuser_stats = 670 &ppdu_info->userstats[userid]; 671 ppdu_info->num_users += 1; 672 673 ath12k_dp_mon_rx_handle_ofdma_info(tlv_data, rxuser_stats); 674 ath12k_dp_mon_rx_populate_mu_user_info(tlv_data, ppdu_info, 675 rxuser_stats); 676 } 677 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]); 678 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]); 679 break; 680 } 681 case HAL_RX_PPDU_END_USER_STATS_EXT: { 682 struct hal_rx_ppdu_end_user_stats_ext *eu_stats = 683 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data; 684 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1); 685 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2); 686 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3); 687 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4); 688 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5); 689 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6); 690 break; 691 } 692 case HAL_PHYRX_HT_SIG: 693 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info); 694 break; 695 696 case HAL_PHYRX_L_SIG_B: 697 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info); 698 break; 699 700 case HAL_PHYRX_L_SIG_A: 701 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info); 702 break; 703 704 case HAL_PHYRX_VHT_SIG_A: 705 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info); 706 break; 707 708 case HAL_PHYRX_HE_SIG_A_SU: 709 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info); 710 break; 711 712 case HAL_PHYRX_HE_SIG_A_MU_DL: 713 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info); 714 break; 715 716 case HAL_PHYRX_HE_SIG_B1_MU: 717 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info); 718 break; 719 720 case HAL_PHYRX_HE_SIG_B2_MU: 721 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info); 722 break; 723 724 case HAL_PHYRX_HE_SIG_B2_OFDMA: 725 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info); 726 break; 727 728 case HAL_PHYRX_RSSI_LEGACY: { 729 struct hal_rx_phyrx_rssi_legacy_info *rssi = 730 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; 731 u32 reception_type = 0; 732 u32 rssi_legacy_info = __le32_to_cpu(rssi->rsvd[0]); 733 734 info[0] = __le32_to_cpu(rssi->info0); 735 736 /* TODO: Please note that the combined rssi will not be accurate 737 * in MU case. Rssi in MU needs to be retrieved from 738 * PHYRX_OTHER_RECEIVE_INFO TLV. 739 */ 740 ppdu_info->rssi_comb = 741 u32_get_bits(info[0], 742 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB); 743 reception_type = 744 u32_get_bits(rssi_legacy_info, 745 HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION); 746 747 switch (reception_type) { 748 case HAL_RECEPTION_TYPE_ULOFMDA: 749 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 750 break; 751 case HAL_RECEPTION_TYPE_ULMIMO: 752 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 753 break; 754 default: 755 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 756 break; 757 } 758 break; 759 } 760 case HAL_RXPCU_PPDU_END_INFO: { 761 struct hal_rx_ppdu_end_duration *ppdu_rx_duration = 762 (struct hal_rx_ppdu_end_duration *)tlv_data; 763 764 info[0] = __le32_to_cpu(ppdu_rx_duration->info0); 765 ppdu_info->rx_duration = 766 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION); 767 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 768 ppdu_info->tsft = (ppdu_info->tsft << 32) | 769 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 770 break; 771 } 772 case HAL_RX_MPDU_START: { 773 struct hal_rx_mpdu_start *mpdu_start = 774 (struct hal_rx_mpdu_start *)tlv_data; 775 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 776 u16 peer_id; 777 778 info[1] = __le32_to_cpu(mpdu_start->info1); 779 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); 780 if (peer_id) 781 ppdu_info->peer_id = peer_id; 782 783 ppdu_info->mpdu_len += u32_get_bits(info[1], 784 HAL_RX_MPDU_START_INFO2_MPDU_LEN); 785 if (userid < HAL_MAX_UL_MU_USERS) { 786 info[0] = __le32_to_cpu(mpdu_start->info0); 787 ppdu_info->userid = userid; 788 ppdu_info->ampdu_id[userid] = 789 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID); 790 } 791 792 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 793 if (!mon_mpdu) 794 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 795 796 break; 797 } 798 case HAL_RX_MSDU_START: 799 /* TODO: add msdu start parsing logic */ 800 break; 801 case HAL_MON_BUF_ADDR: { 802 struct dp_rxdma_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring; 803 struct dp_mon_packet_info *packet_info = 804 (struct dp_mon_packet_info *)tlv_data; 805 int buf_id = u32_get_bits(packet_info->cookie, 806 DP_RXDMA_BUF_COOKIE_BUF_ID); 807 struct sk_buff *msdu; 808 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 809 struct ath12k_skb_rxcb *rxcb; 810 811 spin_lock_bh(&buf_ring->idr_lock); 812 msdu = idr_remove(&buf_ring->bufs_idr, buf_id); 813 spin_unlock_bh(&buf_ring->idr_lock); 814 815 if (unlikely(!msdu)) { 816 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 817 buf_id); 818 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 819 } 820 821 rxcb = ATH12K_SKB_RXCB(msdu); 822 dma_unmap_single(ab->dev, rxcb->paddr, 823 msdu->len + skb_tailroom(msdu), 824 DMA_FROM_DEVICE); 825 826 if (mon_mpdu->tail) 827 mon_mpdu->tail->next = msdu; 828 else 829 mon_mpdu->tail = msdu; 830 831 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 832 833 break; 834 } 835 case HAL_RX_MSDU_END: { 836 struct rx_msdu_end_qcn9274 *msdu_end = 837 (struct rx_msdu_end_qcn9274 *)tlv_data; 838 bool is_first_msdu_in_mpdu; 839 u16 msdu_end_info; 840 841 msdu_end_info = __le16_to_cpu(msdu_end->info5); 842 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info, 843 RX_MSDU_END_INFO5_FIRST_MSDU); 844 if (is_first_msdu_in_mpdu) { 845 pmon->mon_mpdu->head = pmon->mon_mpdu->tail; 846 pmon->mon_mpdu->tail = NULL; 847 } 848 break; 849 } 850 case HAL_RX_MPDU_END: 851 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list); 852 break; 853 case HAL_DUMMY: 854 return HAL_RX_MON_STATUS_BUF_DONE; 855 case HAL_RX_PPDU_END_STATUS_DONE: 856 case 0: 857 return HAL_RX_MON_STATUS_PPDU_DONE; 858 default: 859 break; 860 } 861 862 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 863 } 864 865 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, struct sk_buff *msdu) 866 { 867 u32 rx_pkt_offset, l2_hdr_offset; 868 869 rx_pkt_offset = ar->ab->hw_params->hal_desc_sz; 870 l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab, 871 (struct hal_rx_desc *)msdu->data); 872 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 873 } 874 875 static struct sk_buff * 876 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, 877 u32 mac_id, struct sk_buff *head_msdu, 878 struct ieee80211_rx_status *rxs, bool *fcs_err) 879 { 880 struct ath12k_base *ab = ar->ab; 881 struct sk_buff *msdu, *mpdu_buf, *prev_buf; 882 struct hal_rx_desc *rx_desc; 883 u8 *hdr_desc, *dest, decap_format; 884 struct ieee80211_hdr_3addr *wh; 885 u32 err_bitmap; 886 887 mpdu_buf = NULL; 888 889 if (!head_msdu) 890 goto err_merge_fail; 891 892 rx_desc = (struct hal_rx_desc *)head_msdu->data; 893 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 894 895 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 896 *fcs_err = true; 897 898 decap_format = ath12k_dp_rx_h_decap_type(ab, rx_desc); 899 900 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 901 902 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 903 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu); 904 905 prev_buf = head_msdu; 906 msdu = head_msdu->next; 907 908 while (msdu) { 909 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); 910 911 prev_buf = msdu; 912 msdu = msdu->next; 913 } 914 915 prev_buf->next = NULL; 916 917 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 918 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 919 u8 qos_pkt = 0; 920 921 rx_desc = (struct hal_rx_desc *)head_msdu->data; 922 hdr_desc = ab->hw_params->hal_ops->rx_desc_get_msdu_payload(rx_desc); 923 924 /* Base size */ 925 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 926 927 if (ieee80211_is_data_qos(wh->frame_control)) 928 qos_pkt = 1; 929 930 msdu = head_msdu; 931 932 while (msdu) { 933 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); 934 if (qos_pkt) { 935 dest = skb_push(msdu, sizeof(__le16)); 936 if (!dest) 937 goto err_merge_fail; 938 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 939 } 940 prev_buf = msdu; 941 msdu = msdu->next; 942 } 943 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 944 if (!dest) 945 goto err_merge_fail; 946 947 ath12k_dbg(ab, ATH12K_DBG_DATA, 948 "mpdu_buf %pK mpdu_buf->len %u", 949 prev_buf, prev_buf->len); 950 } else { 951 ath12k_dbg(ab, ATH12K_DBG_DATA, 952 "decap format %d is not supported!\n", 953 decap_format); 954 goto err_merge_fail; 955 } 956 957 return head_msdu; 958 959 err_merge_fail: 960 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) { 961 ath12k_dbg(ab, ATH12K_DBG_DATA, 962 "err_merge_fail mpdu_buf %pK", mpdu_buf); 963 /* Free the head buffer */ 964 dev_kfree_skb_any(mpdu_buf); 965 } 966 return NULL; 967 } 968 969 static void 970 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 971 u8 *rtap_buf) 972 { 973 u32 rtap_len = 0; 974 975 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 976 rtap_len += 2; 977 978 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 979 rtap_len += 2; 980 981 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 982 rtap_len += 2; 983 984 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 985 rtap_len += 2; 986 987 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 988 rtap_len += 2; 989 990 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 991 } 992 993 static void 994 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 995 u8 *rtap_buf) 996 { 997 u32 rtap_len = 0; 998 999 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 1000 rtap_len += 2; 1001 1002 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 1003 rtap_len += 2; 1004 1005 rtap_buf[rtap_len] = rx_status->he_RU[0]; 1006 rtap_len += 1; 1007 1008 rtap_buf[rtap_len] = rx_status->he_RU[1]; 1009 rtap_len += 1; 1010 1011 rtap_buf[rtap_len] = rx_status->he_RU[2]; 1012 rtap_len += 1; 1013 1014 rtap_buf[rtap_len] = rx_status->he_RU[3]; 1015 } 1016 1017 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar, 1018 struct hal_rx_mon_ppdu_info *ppduinfo, 1019 struct sk_buff *mon_skb, 1020 struct ieee80211_rx_status *rxs) 1021 { 1022 struct ieee80211_supported_band *sband; 1023 u8 *ptr = NULL; 1024 u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid]; 1025 1026 rxs->flag |= RX_FLAG_MACTIME_START; 1027 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR; 1028 rxs->nss = ppduinfo->nss + 1; 1029 1030 if (ampdu_id) { 1031 rxs->flag |= RX_FLAG_AMPDU_DETAILS; 1032 rxs->ampdu_reference = ampdu_id; 1033 } 1034 1035 if (ppduinfo->he_mu_flags) { 1036 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 1037 rxs->encoding = RX_ENC_HE; 1038 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 1039 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr); 1040 } else if (ppduinfo->he_flags) { 1041 rxs->flag |= RX_FLAG_RADIOTAP_HE; 1042 rxs->encoding = RX_ENC_HE; 1043 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 1044 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr); 1045 rxs->rate_idx = ppduinfo->rate; 1046 } else if (ppduinfo->vht_flags) { 1047 rxs->encoding = RX_ENC_VHT; 1048 rxs->rate_idx = ppduinfo->rate; 1049 } else if (ppduinfo->ht_flags) { 1050 rxs->encoding = RX_ENC_HT; 1051 rxs->rate_idx = ppduinfo->rate; 1052 } else { 1053 rxs->encoding = RX_ENC_LEGACY; 1054 sband = &ar->mac.sbands[rxs->band]; 1055 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate, 1056 ppduinfo->cck_flag); 1057 } 1058 1059 rxs->mactime = ppduinfo->tsft; 1060 } 1061 1062 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 1063 struct sk_buff *msdu, 1064 struct ieee80211_rx_status *status) 1065 { 1066 static const struct ieee80211_radiotap_he known = { 1067 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1068 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1069 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1070 }; 1071 struct ieee80211_rx_status *rx_status; 1072 struct ieee80211_radiotap_he *he = NULL; 1073 struct ieee80211_sta *pubsta = NULL; 1074 struct ath12k_peer *peer; 1075 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1076 u8 decap = DP_RX_DECAP_TYPE_RAW; 1077 bool is_mcbc = rxcb->is_mcbc; 1078 bool is_eapol_tkip = rxcb->is_eapol; 1079 1080 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) && 1081 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 1082 he = skb_push(msdu, sizeof(known)); 1083 memcpy(he, &known, sizeof(known)); 1084 status->flag |= RX_FLAG_RADIOTAP_HE; 1085 } 1086 1087 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 1088 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc); 1089 spin_lock_bh(&ar->ab->base_lock); 1090 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 1091 if (peer && peer->sta) 1092 pubsta = peer->sta; 1093 spin_unlock_bh(&ar->ab->base_lock); 1094 1095 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 1096 "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 1097 msdu, 1098 msdu->len, 1099 peer ? peer->addr : NULL, 1100 rxcb->tid, 1101 (is_mcbc) ? "mcast" : "ucast", 1102 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 1103 (status->encoding == RX_ENC_HT) ? "ht" : "", 1104 (status->encoding == RX_ENC_VHT) ? "vht" : "", 1105 (status->encoding == RX_ENC_HE) ? "he" : "", 1106 (status->bw == RATE_INFO_BW_40) ? "40" : "", 1107 (status->bw == RATE_INFO_BW_80) ? "80" : "", 1108 (status->bw == RATE_INFO_BW_160) ? "160" : "", 1109 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 1110 status->rate_idx, 1111 status->nss, 1112 status->freq, 1113 status->band, status->flag, 1114 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 1115 !!(status->flag & RX_FLAG_MMIC_ERROR), 1116 !!(status->flag & RX_FLAG_AMSDU_MORE)); 1117 1118 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 1119 msdu->data, msdu->len); 1120 rx_status = IEEE80211_SKB_RXCB(msdu); 1121 *rx_status = *status; 1122 1123 /* TODO: trace rx packet */ 1124 1125 /* PN for multicast packets are not validate in HW, 1126 * so skip 802.3 rx path 1127 * Also, fast_rx expects the STA to be authorized, hence 1128 * eapol packets are sent in slow path. 1129 */ 1130 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip && 1131 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 1132 rx_status->flag |= RX_FLAG_8023; 1133 1134 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 1135 } 1136 1137 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id, 1138 struct sk_buff *head_msdu, 1139 struct hal_rx_mon_ppdu_info *ppduinfo, 1140 struct napi_struct *napi) 1141 { 1142 struct ath12k_pdev_dp *dp = &ar->dp; 1143 struct sk_buff *mon_skb, *skb_next, *header; 1144 struct ieee80211_rx_status *rxs = &dp->rx_status; 1145 bool fcs_err = false; 1146 1147 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, head_msdu, 1148 rxs, &fcs_err); 1149 if (!mon_skb) 1150 goto mon_deliver_fail; 1151 1152 header = mon_skb; 1153 rxs->flag = 0; 1154 1155 if (fcs_err) 1156 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 1157 1158 do { 1159 skb_next = mon_skb->next; 1160 if (!skb_next) 1161 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 1162 else 1163 rxs->flag |= RX_FLAG_AMSDU_MORE; 1164 1165 if (mon_skb == header) { 1166 header = NULL; 1167 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 1168 } else { 1169 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 1170 } 1171 rxs->flag |= RX_FLAG_ONLY_MONITOR; 1172 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs); 1173 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs); 1174 mon_skb = skb_next; 1175 } while (mon_skb); 1176 rxs->flag = 0; 1177 1178 return 0; 1179 1180 mon_deliver_fail: 1181 mon_skb = head_msdu; 1182 while (mon_skb) { 1183 skb_next = mon_skb->next; 1184 dev_kfree_skb_any(mon_skb); 1185 mon_skb = skb_next; 1186 } 1187 return -EINVAL; 1188 } 1189 1190 static enum hal_rx_mon_status 1191 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon, 1192 struct sk_buff *skb) 1193 { 1194 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1195 struct hal_tlv_hdr *tlv; 1196 enum hal_rx_mon_status hal_status; 1197 u32 tlv_userid = 0; 1198 u16 tlv_tag, tlv_len; 1199 u8 *ptr = skb->data; 1200 1201 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); 1202 1203 do { 1204 tlv = (struct hal_tlv_hdr *)ptr; 1205 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 1206 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 1207 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 1208 ptr += sizeof(*tlv); 1209 1210 /* The actual length of PPDU_END is the combined length of many PHY 1211 * TLVs that follow. Skip the TLV header and 1212 * rx_rxpcu_classification_overview that follows the header to get to 1213 * next TLV. 1214 */ 1215 1216 if (tlv_tag == HAL_RX_PPDU_END) 1217 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1218 1219 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon, 1220 tlv_tag, ptr, tlv_userid); 1221 ptr += tlv_len; 1222 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1223 1224 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1225 break; 1226 1227 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1228 1229 return hal_status; 1230 } 1231 1232 enum hal_rx_mon_status 1233 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, 1234 struct ath12k_mon_data *pmon, 1235 int mac_id, 1236 struct sk_buff *skb, 1237 struct napi_struct *napi) 1238 { 1239 struct ath12k_base *ab = ar->ab; 1240 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1241 struct dp_mon_mpdu *tmp; 1242 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 1243 struct sk_buff *head_msdu, *tail_msdu; 1244 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1245 1246 ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 1247 1248 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) { 1249 list_del(&mon_mpdu->list); 1250 head_msdu = mon_mpdu->head; 1251 tail_msdu = mon_mpdu->tail; 1252 1253 if (head_msdu && tail_msdu) { 1254 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, 1255 ppdu_info, napi); 1256 } 1257 1258 kfree(mon_mpdu); 1259 } 1260 return hal_status; 1261 } 1262 1263 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab, 1264 struct dp_rxdma_ring *buf_ring, 1265 int req_entries) 1266 { 1267 struct hal_mon_buf_ring *mon_buf; 1268 struct sk_buff *skb; 1269 struct hal_srng *srng; 1270 dma_addr_t paddr; 1271 u32 cookie; 1272 int buf_id; 1273 1274 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id]; 1275 spin_lock_bh(&srng->lock); 1276 ath12k_hal_srng_access_begin(ab, srng); 1277 1278 while (req_entries > 0) { 1279 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE); 1280 if (unlikely(!skb)) 1281 goto fail_alloc_skb; 1282 1283 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) { 1284 skb_pull(skb, 1285 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 1286 skb->data); 1287 } 1288 1289 paddr = dma_map_single(ab->dev, skb->data, 1290 skb->len + skb_tailroom(skb), 1291 DMA_FROM_DEVICE); 1292 1293 if (unlikely(dma_mapping_error(ab->dev, paddr))) 1294 goto fail_free_skb; 1295 1296 spin_lock_bh(&buf_ring->idr_lock); 1297 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0, 1298 buf_ring->bufs_max * 3, GFP_ATOMIC); 1299 spin_unlock_bh(&buf_ring->idr_lock); 1300 1301 if (unlikely(buf_id < 0)) 1302 goto fail_dma_unmap; 1303 1304 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng); 1305 if (unlikely(!mon_buf)) 1306 goto fail_idr_remove; 1307 1308 ATH12K_SKB_RXCB(skb)->paddr = paddr; 1309 1310 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID); 1311 1312 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr)); 1313 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr)); 1314 mon_buf->cookie = cpu_to_le64(cookie); 1315 1316 req_entries--; 1317 } 1318 1319 ath12k_hal_srng_access_end(ab, srng); 1320 spin_unlock_bh(&srng->lock); 1321 return 0; 1322 1323 fail_idr_remove: 1324 spin_lock_bh(&buf_ring->idr_lock); 1325 idr_remove(&buf_ring->bufs_idr, buf_id); 1326 spin_unlock_bh(&buf_ring->idr_lock); 1327 fail_dma_unmap: 1328 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 1329 DMA_FROM_DEVICE); 1330 fail_free_skb: 1331 dev_kfree_skb_any(skb); 1332 fail_alloc_skb: 1333 ath12k_hal_srng_access_end(ab, srng); 1334 spin_unlock_bh(&srng->lock); 1335 return -ENOMEM; 1336 } 1337 1338 static struct dp_mon_tx_ppdu_info * 1339 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon, 1340 unsigned int ppdu_id, 1341 enum dp_mon_tx_ppdu_info_type type) 1342 { 1343 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1344 1345 if (type == DP_MON_TX_PROT_PPDU_INFO) { 1346 tx_ppdu_info = pmon->tx_prot_ppdu_info; 1347 1348 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1349 return tx_ppdu_info; 1350 kfree(tx_ppdu_info); 1351 } else { 1352 tx_ppdu_info = pmon->tx_data_ppdu_info; 1353 1354 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1355 return tx_ppdu_info; 1356 kfree(tx_ppdu_info); 1357 } 1358 1359 /* allocate new tx_ppdu_info */ 1360 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC); 1361 if (!tx_ppdu_info) 1362 return NULL; 1363 1364 tx_ppdu_info->is_used = 0; 1365 tx_ppdu_info->ppdu_id = ppdu_id; 1366 1367 if (type == DP_MON_TX_PROT_PPDU_INFO) 1368 pmon->tx_prot_ppdu_info = tx_ppdu_info; 1369 else 1370 pmon->tx_data_ppdu_info = tx_ppdu_info; 1371 1372 return tx_ppdu_info; 1373 } 1374 1375 static struct dp_mon_tx_ppdu_info * 1376 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon, 1377 u16 tlv_tag) 1378 { 1379 switch (tlv_tag) { 1380 case HAL_TX_FES_SETUP: 1381 case HAL_TX_FLUSH: 1382 case HAL_PCU_PPDU_SETUP_INIT: 1383 case HAL_TX_PEER_ENTRY: 1384 case HAL_TX_QUEUE_EXTENSION: 1385 case HAL_TX_MPDU_START: 1386 case HAL_TX_MSDU_START: 1387 case HAL_TX_DATA: 1388 case HAL_MON_BUF_ADDR: 1389 case HAL_TX_MPDU_END: 1390 case HAL_TX_LAST_MPDU_FETCHED: 1391 case HAL_TX_LAST_MPDU_END: 1392 case HAL_COEX_TX_REQ: 1393 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP: 1394 case HAL_SCH_CRITICAL_TLV_REFERENCE: 1395 case HAL_TX_FES_SETUP_COMPLETE: 1396 case HAL_TQM_MPDU_GLOBAL_START: 1397 case HAL_SCHEDULER_END: 1398 case HAL_TX_FES_STATUS_USER_PPDU: 1399 break; 1400 case HAL_TX_FES_STATUS_PROT: { 1401 if (!pmon->tx_prot_ppdu_info->is_used) 1402 pmon->tx_prot_ppdu_info->is_used = true; 1403 1404 return pmon->tx_prot_ppdu_info; 1405 } 1406 } 1407 1408 if (!pmon->tx_data_ppdu_info->is_used) 1409 pmon->tx_data_ppdu_info->is_used = true; 1410 1411 return pmon->tx_data_ppdu_info; 1412 } 1413 1414 #define MAX_MONITOR_HEADER 512 1415 #define MAX_DUMMY_FRM_BODY 128 1416 1417 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void) 1418 { 1419 struct sk_buff *skb; 1420 1421 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY); 1422 if (!skb) 1423 return NULL; 1424 1425 skb_reserve(skb, MAX_MONITOR_HEADER); 1426 1427 if (!IS_ALIGNED((unsigned long)skb->data, 4)) 1428 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data); 1429 1430 return skb; 1431 } 1432 1433 static int 1434 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1435 { 1436 struct sk_buff *skb; 1437 struct ieee80211_cts *cts; 1438 1439 skb = ath12k_dp_mon_tx_alloc_skb(); 1440 if (!skb) 1441 return -ENOMEM; 1442 1443 cts = (struct ieee80211_cts *)skb->data; 1444 memset(cts, 0, MAX_DUMMY_FRM_BODY); 1445 cts->frame_control = 1446 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS); 1447 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1448 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra)); 1449 1450 skb_put(skb, sizeof(*cts)); 1451 tx_ppdu_info->tx_mon_mpdu->head = skb; 1452 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1453 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1454 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1455 1456 return 0; 1457 } 1458 1459 static int 1460 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1461 { 1462 struct sk_buff *skb; 1463 struct ieee80211_rts *rts; 1464 1465 skb = ath12k_dp_mon_tx_alloc_skb(); 1466 if (!skb) 1467 return -ENOMEM; 1468 1469 rts = (struct ieee80211_rts *)skb->data; 1470 memset(rts, 0, MAX_DUMMY_FRM_BODY); 1471 rts->frame_control = 1472 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); 1473 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1474 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra)); 1475 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta)); 1476 1477 skb_put(skb, sizeof(*rts)); 1478 tx_ppdu_info->tx_mon_mpdu->head = skb; 1479 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1480 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1481 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1482 1483 return 0; 1484 } 1485 1486 static int 1487 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1488 { 1489 struct sk_buff *skb; 1490 struct ieee80211_qos_hdr *qhdr; 1491 1492 skb = ath12k_dp_mon_tx_alloc_skb(); 1493 if (!skb) 1494 return -ENOMEM; 1495 1496 qhdr = (struct ieee80211_qos_hdr *)skb->data; 1497 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1498 qhdr->frame_control = 1499 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1500 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1501 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1502 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1503 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1504 1505 skb_put(skb, sizeof(*qhdr)); 1506 tx_ppdu_info->tx_mon_mpdu->head = skb; 1507 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1508 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1509 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1510 1511 return 0; 1512 } 1513 1514 static int 1515 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1516 { 1517 struct sk_buff *skb; 1518 struct dp_mon_qosframe_addr4 *qhdr; 1519 1520 skb = ath12k_dp_mon_tx_alloc_skb(); 1521 if (!skb) 1522 return -ENOMEM; 1523 1524 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data; 1525 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1526 qhdr->frame_control = 1527 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1528 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1529 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1530 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1531 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1532 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN); 1533 1534 skb_put(skb, sizeof(*qhdr)); 1535 tx_ppdu_info->tx_mon_mpdu->head = skb; 1536 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1537 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1538 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1539 1540 return 0; 1541 } 1542 1543 static int 1544 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1545 { 1546 struct sk_buff *skb; 1547 struct dp_mon_frame_min_one *fbmhdr; 1548 1549 skb = ath12k_dp_mon_tx_alloc_skb(); 1550 if (!skb) 1551 return -ENOMEM; 1552 1553 fbmhdr = (struct dp_mon_frame_min_one *)skb->data; 1554 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY); 1555 fbmhdr->frame_control = 1556 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK); 1557 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1558 1559 /* set duration zero for ack frame */ 1560 fbmhdr->duration = 0; 1561 1562 skb_put(skb, sizeof(*fbmhdr)); 1563 tx_ppdu_info->tx_mon_mpdu->head = skb; 1564 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1565 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1566 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1567 1568 return 0; 1569 } 1570 1571 static int 1572 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1573 { 1574 int ret = 0; 1575 1576 switch (tx_ppdu_info->rx_status.medium_prot_type) { 1577 case DP_MON_TX_MEDIUM_RTS_LEGACY: 1578 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW: 1579 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW: 1580 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info); 1581 break; 1582 case DP_MON_TX_MEDIUM_CTS2SELF: 1583 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1584 break; 1585 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR: 1586 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info); 1587 break; 1588 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR: 1589 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info); 1590 break; 1591 } 1592 1593 return ret; 1594 } 1595 1596 static enum dp_mon_tx_tlv_status 1597 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab, 1598 struct ath12k_mon_data *pmon, 1599 u16 tlv_tag, u8 *tlv_data, u32 userid) 1600 { 1601 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1602 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1603 u32 info[7]; 1604 1605 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag); 1606 1607 switch (tlv_tag) { 1608 case HAL_TX_FES_SETUP: { 1609 struct hal_tx_fes_setup *tx_fes_setup = 1610 (struct hal_tx_fes_setup *)tlv_data; 1611 1612 info[0] = __le32_to_cpu(tx_fes_setup->info0); 1613 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id); 1614 tx_ppdu_info->num_users = 1615 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1616 status = DP_MON_TX_FES_SETUP; 1617 break; 1618 } 1619 1620 case HAL_TX_FES_STATUS_END: { 1621 struct hal_tx_fes_status_end *tx_fes_status_end = 1622 (struct hal_tx_fes_status_end *)tlv_data; 1623 u32 tst_15_0, tst_31_16; 1624 1625 info[0] = __le32_to_cpu(tx_fes_status_end->info0); 1626 tst_15_0 = 1627 u32_get_bits(info[0], 1628 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0); 1629 tst_31_16 = 1630 u32_get_bits(info[0], 1631 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16); 1632 1633 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16)); 1634 status = DP_MON_TX_FES_STATUS_END; 1635 break; 1636 } 1637 1638 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1639 struct hal_rx_resp_req_info *rx_resp_req_info = 1640 (struct hal_rx_resp_req_info *)tlv_data; 1641 u32 addr_32; 1642 u16 addr_16; 1643 1644 info[0] = __le32_to_cpu(rx_resp_req_info->info0); 1645 info[1] = __le32_to_cpu(rx_resp_req_info->info1); 1646 info[2] = __le32_to_cpu(rx_resp_req_info->info2); 1647 info[3] = __le32_to_cpu(rx_resp_req_info->info3); 1648 info[4] = __le32_to_cpu(rx_resp_req_info->info4); 1649 info[5] = __le32_to_cpu(rx_resp_req_info->info5); 1650 1651 tx_ppdu_info->rx_status.ppdu_id = 1652 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID); 1653 tx_ppdu_info->rx_status.reception_type = 1654 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE); 1655 tx_ppdu_info->rx_status.rx_duration = 1656 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION); 1657 tx_ppdu_info->rx_status.mcs = 1658 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS); 1659 tx_ppdu_info->rx_status.sgi = 1660 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI); 1661 tx_ppdu_info->rx_status.is_stbc = 1662 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC); 1663 tx_ppdu_info->rx_status.ldpc = 1664 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC); 1665 tx_ppdu_info->rx_status.is_ampdu = 1666 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU); 1667 tx_ppdu_info->rx_status.num_users = 1668 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER); 1669 1670 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0); 1671 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32); 1672 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1673 1674 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0); 1675 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16); 1676 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1677 1678 if (tx_ppdu_info->rx_status.reception_type == 0) 1679 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1680 status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1681 break; 1682 } 1683 1684 case HAL_PCU_PPDU_SETUP_INIT: { 1685 struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = 1686 (struct hal_tx_pcu_ppdu_setup_init *)tlv_data; 1687 u32 addr_32; 1688 u16 addr_16; 1689 1690 info[0] = __le32_to_cpu(ppdu_setup->info0); 1691 info[1] = __le32_to_cpu(ppdu_setup->info1); 1692 info[2] = __le32_to_cpu(ppdu_setup->info2); 1693 info[3] = __le32_to_cpu(ppdu_setup->info3); 1694 info[4] = __le32_to_cpu(ppdu_setup->info4); 1695 info[5] = __le32_to_cpu(ppdu_setup->info5); 1696 info[6] = __le32_to_cpu(ppdu_setup->info6); 1697 1698 /* protection frame address 1 */ 1699 addr_32 = u32_get_bits(info[1], 1700 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0); 1701 addr_16 = u32_get_bits(info[2], 1702 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32); 1703 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1704 1705 /* protection frame address 2 */ 1706 addr_16 = u32_get_bits(info[2], 1707 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0); 1708 addr_32 = u32_get_bits(info[3], 1709 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16); 1710 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1711 1712 /* protection frame address 3 */ 1713 addr_32 = u32_get_bits(info[4], 1714 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0); 1715 addr_16 = u32_get_bits(info[5], 1716 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32); 1717 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3); 1718 1719 /* protection frame address 4 */ 1720 addr_16 = u32_get_bits(info[5], 1721 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0); 1722 addr_32 = u32_get_bits(info[6], 1723 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16); 1724 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4); 1725 1726 status = u32_get_bits(info[0], 1727 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE); 1728 break; 1729 } 1730 1731 case HAL_TX_QUEUE_EXTENSION: { 1732 struct hal_tx_queue_exten *tx_q_exten = 1733 (struct hal_tx_queue_exten *)tlv_data; 1734 1735 info[0] = __le32_to_cpu(tx_q_exten->info0); 1736 1737 tx_ppdu_info->rx_status.frame_control = 1738 u32_get_bits(info[0], 1739 HAL_TX_Q_EXT_INFO0_FRAME_CTRL); 1740 tx_ppdu_info->rx_status.fc_valid = true; 1741 break; 1742 } 1743 1744 case HAL_TX_FES_STATUS_START: { 1745 struct hal_tx_fes_status_start *tx_fes_start = 1746 (struct hal_tx_fes_status_start *)tlv_data; 1747 1748 info[0] = __le32_to_cpu(tx_fes_start->info0); 1749 1750 tx_ppdu_info->rx_status.medium_prot_type = 1751 u32_get_bits(info[0], 1752 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE); 1753 break; 1754 } 1755 1756 case HAL_TX_FES_STATUS_PROT: { 1757 struct hal_tx_fes_status_prot *tx_fes_status = 1758 (struct hal_tx_fes_status_prot *)tlv_data; 1759 u32 start_timestamp; 1760 u32 end_timestamp; 1761 1762 info[0] = __le32_to_cpu(tx_fes_status->info0); 1763 info[1] = __le32_to_cpu(tx_fes_status->info1); 1764 1765 start_timestamp = 1766 u32_get_bits(info[0], 1767 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0); 1768 start_timestamp |= 1769 u32_get_bits(info[0], 1770 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15; 1771 end_timestamp = 1772 u32_get_bits(info[1], 1773 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0); 1774 end_timestamp |= 1775 u32_get_bits(info[1], 1776 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15; 1777 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp; 1778 1779 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info); 1780 break; 1781 } 1782 1783 case HAL_TX_FES_STATUS_START_PPDU: 1784 case HAL_TX_FES_STATUS_START_PROT: { 1785 struct hal_tx_fes_status_start_prot *tx_fes_stat_start = 1786 (struct hal_tx_fes_status_start_prot *)tlv_data; 1787 u64 ppdu_ts; 1788 1789 info[0] = __le32_to_cpu(tx_fes_stat_start->info0); 1790 1791 tx_ppdu_info->rx_status.ppdu_ts = 1792 u32_get_bits(info[0], 1793 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32); 1794 ppdu_ts = (u32_get_bits(info[1], 1795 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32)); 1796 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32; 1797 break; 1798 } 1799 1800 case HAL_TX_FES_STATUS_USER_PPDU: { 1801 struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = 1802 (struct hal_tx_fes_status_user_ppdu *)tlv_data; 1803 1804 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0); 1805 1806 tx_ppdu_info->rx_status.rx_duration = 1807 u32_get_bits(info[0], 1808 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION); 1809 break; 1810 } 1811 1812 case HAL_MACTX_HE_SIG_A_SU: 1813 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status); 1814 break; 1815 1816 case HAL_MACTX_HE_SIG_A_MU_DL: 1817 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status); 1818 break; 1819 1820 case HAL_MACTX_HE_SIG_B1_MU: 1821 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status); 1822 break; 1823 1824 case HAL_MACTX_HE_SIG_B2_MU: 1825 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status); 1826 break; 1827 1828 case HAL_MACTX_HE_SIG_B2_OFDMA: 1829 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status); 1830 break; 1831 1832 case HAL_MACTX_VHT_SIG_A: 1833 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1834 break; 1835 1836 case HAL_MACTX_L_SIG_A: 1837 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1838 break; 1839 1840 case HAL_MACTX_L_SIG_B: 1841 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status); 1842 break; 1843 1844 case HAL_RX_FRAME_BITMAP_ACK: { 1845 struct hal_rx_frame_bitmap_ack *fbm_ack = 1846 (struct hal_rx_frame_bitmap_ack *)tlv_data; 1847 u32 addr_32; 1848 u16 addr_16; 1849 1850 info[0] = __le32_to_cpu(fbm_ack->info0); 1851 info[1] = __le32_to_cpu(fbm_ack->info1); 1852 1853 addr_32 = u32_get_bits(info[0], 1854 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0); 1855 addr_16 = u32_get_bits(info[1], 1856 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32); 1857 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1858 1859 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info); 1860 break; 1861 } 1862 1863 case HAL_MACTX_PHY_DESC: { 1864 struct hal_tx_phy_desc *tx_phy_desc = 1865 (struct hal_tx_phy_desc *)tlv_data; 1866 1867 info[0] = __le32_to_cpu(tx_phy_desc->info0); 1868 info[1] = __le32_to_cpu(tx_phy_desc->info1); 1869 info[2] = __le32_to_cpu(tx_phy_desc->info2); 1870 info[3] = __le32_to_cpu(tx_phy_desc->info3); 1871 1872 tx_ppdu_info->rx_status.beamformed = 1873 u32_get_bits(info[0], 1874 HAL_TX_PHY_DESC_INFO0_BF_TYPE); 1875 tx_ppdu_info->rx_status.preamble_type = 1876 u32_get_bits(info[0], 1877 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B); 1878 tx_ppdu_info->rx_status.mcs = 1879 u32_get_bits(info[1], 1880 HAL_TX_PHY_DESC_INFO1_MCS); 1881 tx_ppdu_info->rx_status.ltf_size = 1882 u32_get_bits(info[3], 1883 HAL_TX_PHY_DESC_INFO3_LTF_SIZE); 1884 tx_ppdu_info->rx_status.nss = 1885 u32_get_bits(info[2], 1886 HAL_TX_PHY_DESC_INFO2_NSS); 1887 tx_ppdu_info->rx_status.chan_num = 1888 u32_get_bits(info[3], 1889 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL); 1890 tx_ppdu_info->rx_status.bw = 1891 u32_get_bits(info[0], 1892 HAL_TX_PHY_DESC_INFO0_BANDWIDTH); 1893 break; 1894 } 1895 1896 case HAL_TX_MPDU_START: { 1897 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 1898 1899 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 1900 if (!mon_mpdu) 1901 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 1902 status = DP_MON_TX_MPDU_START; 1903 break; 1904 } 1905 1906 case HAL_MON_BUF_ADDR: { 1907 struct dp_rxdma_ring *buf_ring = &ab->dp.tx_mon_buf_ring; 1908 struct dp_mon_packet_info *packet_info = 1909 (struct dp_mon_packet_info *)tlv_data; 1910 int buf_id = u32_get_bits(packet_info->cookie, 1911 DP_RXDMA_BUF_COOKIE_BUF_ID); 1912 struct sk_buff *msdu; 1913 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 1914 struct ath12k_skb_rxcb *rxcb; 1915 1916 spin_lock_bh(&buf_ring->idr_lock); 1917 msdu = idr_remove(&buf_ring->bufs_idr, buf_id); 1918 spin_unlock_bh(&buf_ring->idr_lock); 1919 1920 if (unlikely(!msdu)) { 1921 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 1922 buf_id); 1923 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 1924 } 1925 1926 rxcb = ATH12K_SKB_RXCB(msdu); 1927 dma_unmap_single(ab->dev, rxcb->paddr, 1928 msdu->len + skb_tailroom(msdu), 1929 DMA_FROM_DEVICE); 1930 1931 if (!mon_mpdu->head) 1932 mon_mpdu->head = msdu; 1933 else if (mon_mpdu->tail) 1934 mon_mpdu->tail->next = msdu; 1935 1936 mon_mpdu->tail = msdu; 1937 1938 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 1939 status = DP_MON_TX_BUFFER_ADDR; 1940 break; 1941 } 1942 1943 case HAL_TX_MPDU_END: 1944 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1945 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1946 break; 1947 } 1948 1949 return status; 1950 } 1951 1952 enum dp_mon_tx_tlv_status 1953 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag, 1954 struct hal_tlv_hdr *tx_tlv, 1955 u8 *num_users) 1956 { 1957 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1958 u32 info0; 1959 1960 switch (tlv_tag) { 1961 case HAL_TX_FES_SETUP: { 1962 struct hal_tx_fes_setup *tx_fes_setup = 1963 (struct hal_tx_fes_setup *)tx_tlv; 1964 1965 info0 = __le32_to_cpu(tx_fes_setup->info0); 1966 1967 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1968 tlv_status = DP_MON_TX_FES_SETUP; 1969 break; 1970 } 1971 1972 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1973 /* TODO: need to update *num_users */ 1974 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1975 break; 1976 } 1977 } 1978 1979 return tlv_status; 1980 } 1981 1982 static void 1983 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id, 1984 struct napi_struct *napi, 1985 struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1986 { 1987 struct dp_mon_mpdu *tmp, *mon_mpdu; 1988 struct sk_buff *head_msdu; 1989 1990 list_for_each_entry_safe(mon_mpdu, tmp, 1991 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) { 1992 list_del(&mon_mpdu->list); 1993 head_msdu = mon_mpdu->head; 1994 1995 if (head_msdu) 1996 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, 1997 &tx_ppdu_info->rx_status, napi); 1998 1999 kfree(mon_mpdu); 2000 } 2001 } 2002 2003 enum hal_rx_mon_status 2004 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar, 2005 struct ath12k_mon_data *pmon, 2006 int mac_id, 2007 struct sk_buff *skb, 2008 struct napi_struct *napi, 2009 u32 ppdu_id) 2010 { 2011 struct ath12k_base *ab = ar->ab; 2012 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info; 2013 struct hal_tlv_hdr *tlv; 2014 u8 *ptr = skb->data; 2015 u16 tlv_tag; 2016 u16 tlv_len; 2017 u32 tlv_userid = 0; 2018 u8 num_user; 2019 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 2020 2021 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2022 DP_MON_TX_PROT_PPDU_INFO); 2023 if (!tx_prot_ppdu_info) 2024 return -ENOMEM; 2025 2026 tlv = (struct hal_tlv_hdr *)ptr; 2027 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2028 2029 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user); 2030 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user) 2031 return -EINVAL; 2032 2033 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2034 DP_MON_TX_DATA_PPDU_INFO); 2035 if (!tx_data_ppdu_info) 2036 return -ENOMEM; 2037 2038 do { 2039 tlv = (struct hal_tlv_hdr *)ptr; 2040 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2041 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 2042 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 2043 2044 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon, 2045 tlv_tag, ptr, 2046 tlv_userid); 2047 ptr += tlv_len; 2048 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 2049 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE) 2050 break; 2051 } while (tlv_status != DP_MON_TX_FES_STATUS_END); 2052 2053 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info); 2054 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info); 2055 2056 return tlv_status; 2057 } 2058 2059 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget, 2060 enum dp_monitor_mode monitor_mode, 2061 struct napi_struct *napi) 2062 { 2063 struct hal_mon_dest_desc *mon_dst_desc; 2064 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2065 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2066 struct ath12k_base *ab = ar->ab; 2067 struct ath12k_dp *dp = &ab->dp; 2068 struct sk_buff *skb; 2069 struct ath12k_skb_rxcb *rxcb; 2070 struct dp_srng *mon_dst_ring; 2071 struct hal_srng *srng; 2072 struct dp_rxdma_ring *buf_ring; 2073 u64 cookie; 2074 u32 ppdu_id; 2075 int num_buffs_reaped = 0, srng_id, buf_id; 2076 u8 dest_idx = 0, i; 2077 bool end_of_ppdu; 2078 struct hal_rx_mon_ppdu_info *ppdu_info; 2079 struct ath12k_peer *peer = NULL; 2080 2081 ppdu_info = &pmon->mon_ppdu_info; 2082 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2083 ppdu_info->peer_id = HAL_INVALID_PEERID; 2084 2085 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2086 2087 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) { 2088 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2089 buf_ring = &dp->rxdma_mon_buf_ring; 2090 } else { 2091 mon_dst_ring = &pdev_dp->tx_mon_dst_ring[srng_id]; 2092 buf_ring = &dp->tx_mon_buf_ring; 2093 } 2094 2095 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2096 2097 spin_lock_bh(&srng->lock); 2098 ath12k_hal_srng_access_begin(ab, srng); 2099 2100 while (likely(*budget)) { 2101 *budget -= 1; 2102 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2103 if (unlikely(!mon_dst_desc)) 2104 break; 2105 2106 cookie = le32_to_cpu(mon_dst_desc->cookie); 2107 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2108 2109 spin_lock_bh(&buf_ring->idr_lock); 2110 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2111 spin_unlock_bh(&buf_ring->idr_lock); 2112 2113 if (unlikely(!skb)) { 2114 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 2115 buf_id); 2116 goto move_next; 2117 } 2118 2119 rxcb = ATH12K_SKB_RXCB(skb); 2120 dma_unmap_single(ab->dev, rxcb->paddr, 2121 skb->len + skb_tailroom(skb), 2122 DMA_FROM_DEVICE); 2123 2124 pmon->dest_skb_q[dest_idx] = skb; 2125 dest_idx++; 2126 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id); 2127 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2128 HAL_MON_DEST_INFO0_END_OF_PPDU); 2129 if (!end_of_ppdu) 2130 continue; 2131 2132 for (i = 0; i < dest_idx; i++) { 2133 skb = pmon->dest_skb_q[i]; 2134 2135 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) 2136 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id, 2137 skb, napi); 2138 else 2139 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id, 2140 skb, napi, ppdu_id); 2141 2142 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2143 2144 if (!peer || !peer->sta) { 2145 ath12k_dbg(ab, ATH12K_DBG_DATA, 2146 "failed to find the peer with peer_id %d\n", 2147 ppdu_info->peer_id); 2148 dev_kfree_skb_any(skb); 2149 continue; 2150 } 2151 2152 dev_kfree_skb_any(skb); 2153 pmon->dest_skb_q[i] = NULL; 2154 } 2155 2156 dest_idx = 0; 2157 move_next: 2158 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2159 ath12k_hal_srng_src_get_next_entry(ab, srng); 2160 num_buffs_reaped++; 2161 } 2162 2163 ath12k_hal_srng_access_end(ab, srng); 2164 spin_unlock_bh(&srng->lock); 2165 2166 return num_buffs_reaped; 2167 } 2168 2169 static void 2170 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats, 2171 struct hal_rx_mon_ppdu_info *ppdu_info, 2172 struct hal_rx_user_status *user_stats, 2173 u32 num_msdu) 2174 { 2175 u32 rate_idx = 0; 2176 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs; 2177 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1; 2178 u32 bw_idx = ppdu_info->bw; 2179 u32 gi_idx = ppdu_info->gi; 2180 2181 if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) || 2182 (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) { 2183 return; 2184 } 2185 2186 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N || 2187 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) { 2188 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx; 2189 rate_idx += bw_idx * 2 + gi_idx; 2190 } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) { 2191 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi); 2192 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx; 2193 rate_idx += bw_idx * 3 + gi_idx; 2194 } else { 2195 return; 2196 } 2197 2198 rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu; 2199 if (user_stats) 2200 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count; 2201 else 2202 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len; 2203 } 2204 2205 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar, 2206 struct ath12k_sta *arsta, 2207 struct hal_rx_mon_ppdu_info *ppdu_info) 2208 { 2209 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats; 2210 u32 num_msdu; 2211 2212 if (!rx_stats) 2213 return; 2214 2215 arsta->rssi_comb = ppdu_info->rssi_comb; 2216 2217 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2218 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2219 2220 rx_stats->num_msdu += num_msdu; 2221 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2222 ppdu_info->tcp_ack_msdu_count; 2223 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2224 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2225 2226 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2227 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2228 ppdu_info->nss = 1; 2229 ppdu_info->mcs = HAL_RX_MAX_MCS; 2230 ppdu_info->tid = IEEE80211_NUM_TIDS; 2231 } 2232 2233 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2234 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2235 2236 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2237 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2238 2239 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2240 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2241 2242 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2243 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2244 2245 if (ppdu_info->is_stbc) 2246 rx_stats->stbc_count += num_msdu; 2247 2248 if (ppdu_info->beamformed) 2249 rx_stats->beamformed_count += num_msdu; 2250 2251 if (ppdu_info->num_mpdu_fcs_ok > 1) 2252 rx_stats->ampdu_msdu_count += num_msdu; 2253 else 2254 rx_stats->non_ampdu_msdu_count += num_msdu; 2255 2256 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2257 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2258 rx_stats->dcm_count += ppdu_info->dcm; 2259 2260 rx_stats->rx_duration += ppdu_info->rx_duration; 2261 arsta->rx_duration = rx_stats->rx_duration; 2262 2263 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) { 2264 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu; 2265 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len; 2266 } 2267 2268 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N && 2269 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) { 2270 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu; 2271 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2272 /* To fit into rate table for HT packets */ 2273 ppdu_info->mcs = ppdu_info->mcs % 8; 2274 } 2275 2276 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC && 2277 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) { 2278 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu; 2279 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2280 } 2281 2282 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX && 2283 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) { 2284 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu; 2285 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2286 } 2287 2288 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2289 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) && 2290 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) { 2291 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu; 2292 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len; 2293 } 2294 2295 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2296 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2297 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len; 2298 } 2299 2300 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2301 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2302 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len; 2303 } 2304 2305 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2306 NULL, num_msdu); 2307 } 2308 2309 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info) 2310 { 2311 struct hal_rx_user_status *rx_user_status; 2312 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size; 2313 2314 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO || 2315 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2316 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)) 2317 return; 2318 2319 num_users = ppdu_info->num_users; 2320 if (num_users > HAL_MAX_UL_MU_USERS) 2321 num_users = HAL_MAX_UL_MU_USERS; 2322 2323 for (i = 0; i < num_users; i++) { 2324 rx_user_status = &ppdu_info->userstats[i]; 2325 mu_ul_user_v0_word0 = 2326 rx_user_status->ul_ofdma_user_v0_word0; 2327 mu_ul_user_v0_word1 = 2328 rx_user_status->ul_ofdma_user_v0_word1; 2329 2330 if (u32_get_bits(mu_ul_user_v0_word0, 2331 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) && 2332 !u32_get_bits(mu_ul_user_v0_word0, 2333 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) { 2334 rx_user_status->mcs = 2335 u32_get_bits(mu_ul_user_v0_word1, 2336 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS); 2337 rx_user_status->nss = 2338 u32_get_bits(mu_ul_user_v0_word1, 2339 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1; 2340 2341 rx_user_status->ofdma_info_valid = 1; 2342 rx_user_status->ul_ofdma_ru_start_index = 2343 u32_get_bits(mu_ul_user_v0_word1, 2344 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START); 2345 2346 ru_size = u32_get_bits(mu_ul_user_v0_word1, 2347 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE); 2348 rx_user_status->ul_ofdma_ru_width = ru_size; 2349 rx_user_status->ul_ofdma_ru_size = ru_size; 2350 } 2351 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1, 2352 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC); 2353 } 2354 ppdu_info->ldpc = 1; 2355 } 2356 2357 static void 2358 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar, 2359 struct hal_rx_mon_ppdu_info *ppdu_info, 2360 u32 uid) 2361 { 2362 struct ath12k_sta *arsta = NULL; 2363 struct ath12k_rx_peer_stats *rx_stats = NULL; 2364 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid]; 2365 struct ath12k_peer *peer; 2366 u32 num_msdu; 2367 2368 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF) 2369 return; 2370 2371 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index); 2372 2373 if (!peer) { 2374 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n", 2375 user_stats->ast_index); 2376 return; 2377 } 2378 2379 arsta = (struct ath12k_sta *)peer->sta->drv_priv; 2380 rx_stats = arsta->rx_stats; 2381 2382 if (!rx_stats) 2383 return; 2384 2385 arsta->rssi_comb = ppdu_info->rssi_comb; 2386 2387 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count + 2388 user_stats->udp_msdu_count + user_stats->other_msdu_count; 2389 2390 rx_stats->num_msdu += num_msdu; 2391 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count + 2392 user_stats->tcp_ack_msdu_count; 2393 rx_stats->udp_msdu_count += user_stats->udp_msdu_count; 2394 rx_stats->other_msdu_count += user_stats->other_msdu_count; 2395 2396 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2397 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2398 2399 if (user_stats->tid <= IEEE80211_NUM_TIDS) 2400 rx_stats->tid_count[user_stats->tid] += num_msdu; 2401 2402 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX) 2403 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu; 2404 2405 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2406 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2407 2408 if (ppdu_info->is_stbc) 2409 rx_stats->stbc_count += num_msdu; 2410 2411 if (ppdu_info->beamformed) 2412 rx_stats->beamformed_count += num_msdu; 2413 2414 if (user_stats->mpdu_cnt_fcs_ok > 1) 2415 rx_stats->ampdu_msdu_count += num_msdu; 2416 else 2417 rx_stats->non_ampdu_msdu_count += num_msdu; 2418 2419 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok; 2420 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err; 2421 rx_stats->dcm_count += ppdu_info->dcm; 2422 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2423 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO) 2424 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu; 2425 2426 rx_stats->rx_duration += ppdu_info->rx_duration; 2427 arsta->rx_duration = rx_stats->rx_duration; 2428 2429 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) { 2430 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu; 2431 rx_stats->byte_stats.nss_count[user_stats->nss - 1] += 2432 user_stats->mpdu_ok_byte_count; 2433 } 2434 2435 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX && 2436 user_stats->mcs <= HAL_RX_MAX_MCS_HE) { 2437 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu; 2438 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] += 2439 user_stats->mpdu_ok_byte_count; 2440 } 2441 2442 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2443 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2444 rx_stats->byte_stats.gi_count[ppdu_info->gi] += 2445 user_stats->mpdu_ok_byte_count; 2446 } 2447 2448 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2449 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2450 rx_stats->byte_stats.bw_count[ppdu_info->bw] += 2451 user_stats->mpdu_ok_byte_count; 2452 } 2453 2454 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2455 user_stats, num_msdu); 2456 } 2457 2458 static void 2459 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar, 2460 struct hal_rx_mon_ppdu_info *ppdu_info) 2461 { 2462 u32 num_users, i; 2463 2464 num_users = ppdu_info->num_users; 2465 if (num_users > HAL_MAX_UL_MU_USERS) 2466 num_users = HAL_MAX_UL_MU_USERS; 2467 2468 for (i = 0; i < num_users; i++) 2469 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i); 2470 } 2471 2472 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id, 2473 struct napi_struct *napi, int *budget) 2474 { 2475 struct ath12k_base *ab = ar->ab; 2476 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2477 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2478 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 2479 struct ath12k_dp *dp = &ab->dp; 2480 struct hal_mon_dest_desc *mon_dst_desc; 2481 struct sk_buff *skb; 2482 struct ath12k_skb_rxcb *rxcb; 2483 struct dp_srng *mon_dst_ring; 2484 struct hal_srng *srng; 2485 struct dp_rxdma_ring *buf_ring; 2486 struct ath12k_sta *arsta = NULL; 2487 struct ath12k_peer *peer; 2488 u64 cookie; 2489 int num_buffs_reaped = 0, srng_id, buf_id; 2490 u8 dest_idx = 0, i; 2491 bool end_of_ppdu; 2492 u32 hal_status; 2493 2494 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2495 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2496 buf_ring = &dp->rxdma_mon_buf_ring; 2497 2498 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2499 spin_lock_bh(&srng->lock); 2500 ath12k_hal_srng_access_begin(ab, srng); 2501 2502 while (likely(*budget)) { 2503 *budget -= 1; 2504 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2505 if (unlikely(!mon_dst_desc)) 2506 break; 2507 cookie = le32_to_cpu(mon_dst_desc->cookie); 2508 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2509 2510 spin_lock_bh(&buf_ring->idr_lock); 2511 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2512 spin_unlock_bh(&buf_ring->idr_lock); 2513 2514 if (unlikely(!skb)) { 2515 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 2516 buf_id); 2517 goto move_next; 2518 } 2519 2520 rxcb = ATH12K_SKB_RXCB(skb); 2521 dma_unmap_single(ab->dev, rxcb->paddr, 2522 skb->len + skb_tailroom(skb), 2523 DMA_FROM_DEVICE); 2524 pmon->dest_skb_q[dest_idx] = skb; 2525 dest_idx++; 2526 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2527 HAL_MON_DEST_INFO0_END_OF_PPDU); 2528 if (!end_of_ppdu) 2529 continue; 2530 2531 for (i = 0; i < dest_idx; i++) { 2532 skb = pmon->dest_skb_q[i]; 2533 hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 2534 2535 if (ppdu_info->peer_id == HAL_INVALID_PEERID || 2536 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 2537 dev_kfree_skb_any(skb); 2538 continue; 2539 } 2540 2541 rcu_read_lock(); 2542 spin_lock_bh(&ab->base_lock); 2543 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2544 if (!peer || !peer->sta) { 2545 ath12k_dbg(ab, ATH12K_DBG_DATA, 2546 "failed to find the peer with peer_id %d\n", 2547 ppdu_info->peer_id); 2548 spin_unlock_bh(&ab->base_lock); 2549 rcu_read_unlock(); 2550 dev_kfree_skb_any(skb); 2551 continue; 2552 } 2553 2554 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { 2555 arsta = (struct ath12k_sta *)peer->sta->drv_priv; 2556 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta, 2557 ppdu_info); 2558 } else if ((ppdu_info->fc_valid) && 2559 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { 2560 ath12k_dp_mon_rx_process_ulofdma(ppdu_info); 2561 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info); 2562 } 2563 2564 spin_unlock_bh(&ab->base_lock); 2565 rcu_read_unlock(); 2566 dev_kfree_skb_any(skb); 2567 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2568 ppdu_info->peer_id = HAL_INVALID_PEERID; 2569 } 2570 2571 dest_idx = 0; 2572 move_next: 2573 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2574 ath12k_hal_srng_src_get_next_entry(ab, srng); 2575 num_buffs_reaped++; 2576 } 2577 2578 ath12k_hal_srng_access_end(ab, srng); 2579 spin_unlock_bh(&srng->lock); 2580 return num_buffs_reaped; 2581 } 2582 2583 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id, 2584 struct napi_struct *napi, int budget, 2585 enum dp_monitor_mode monitor_mode) 2586 { 2587 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id); 2588 int num_buffs_reaped = 0; 2589 2590 if (!ar->monitor_started) 2591 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget); 2592 else 2593 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget, 2594 monitor_mode, napi); 2595 2596 return num_buffs_reaped; 2597 } 2598