1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_rx.h" 11 #include "hw.h" 12 13 #define MAX_RXDMA_PER_PDEV 2 14 15 struct ath12k_base; 16 struct ath12k_peer; 17 struct ath12k_dp; 18 struct ath12k_vif; 19 struct hal_tcl_status_ring; 20 struct ath12k_ext_irq_grp; 21 22 #define DP_MON_PURGE_TIMEOUT_MS 100 23 #define DP_MON_SERVICE_BUDGET 128 24 25 struct dp_srng { 26 u32 *vaddr_unaligned; 27 u32 *vaddr; 28 dma_addr_t paddr_unaligned; 29 dma_addr_t paddr; 30 int size; 31 u32 ring_id; 32 }; 33 34 struct dp_rxdma_ring { 35 struct dp_srng refill_buf_ring; 36 struct idr bufs_idr; 37 /* Protects bufs_idr */ 38 spinlock_t idr_lock; 39 int bufs_max; 40 }; 41 42 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 43 44 struct dp_tx_ring { 45 u8 tcl_data_ring_id; 46 struct dp_srng tcl_data_ring; 47 struct dp_srng tcl_comp_ring; 48 struct hal_wbm_completion_ring_tx *tx_status; 49 int tx_status_head; 50 int tx_status_tail; 51 }; 52 53 struct ath12k_pdev_mon_stats { 54 u32 status_ppdu_state; 55 u32 status_ppdu_start; 56 u32 status_ppdu_end; 57 u32 status_ppdu_compl; 58 u32 status_ppdu_start_mis; 59 u32 status_ppdu_end_mis; 60 u32 status_ppdu_done; 61 u32 dest_ppdu_done; 62 u32 dest_mpdu_done; 63 u32 dest_mpdu_drop; 64 u32 dup_mon_linkdesc_cnt; 65 u32 dup_mon_buf_cnt; 66 }; 67 68 struct dp_link_desc_bank { 69 void *vaddr_unaligned; 70 void *vaddr; 71 dma_addr_t paddr_unaligned; 72 dma_addr_t paddr; 73 u32 size; 74 }; 75 76 /* Size to enforce scatter idle list mode */ 77 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 78 #define DP_LINK_DESC_BANKS_MAX 8 79 80 #define DP_LINK_DESC_START 0x4000 81 #define DP_LINK_DESC_SHIFT 3 82 83 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 84 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 85 86 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 87 88 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 89 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 90 #define DP_RX_DESC_COOKIE_MAX \ 91 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 92 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 93 94 enum ath12k_dp_ppdu_state { 95 DP_PPDU_STATUS_START, 96 DP_PPDU_STATUS_DONE, 97 }; 98 99 struct dp_mon_mpdu { 100 struct list_head list; 101 struct sk_buff *head; 102 struct sk_buff *tail; 103 }; 104 105 #define DP_MON_MAX_STATUS_BUF 32 106 107 struct ath12k_mon_data { 108 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 109 struct hal_rx_mon_ppdu_info mon_ppdu_info; 110 111 u32 mon_ppdu_status; 112 u32 mon_last_buf_cookie; 113 u64 mon_last_linkdesc_paddr; 114 u16 chan_noise_floor; 115 116 struct ath12k_pdev_mon_stats rx_mon_stats; 117 /* lock for monitor data */ 118 spinlock_t mon_lock; 119 struct sk_buff_head rx_status_q; 120 struct dp_mon_mpdu *mon_mpdu; 121 struct list_head dp_rx_mon_mpdu_list; 122 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF]; 123 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 124 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 125 }; 126 127 struct ath12k_pdev_dp { 128 u32 mac_id; 129 atomic_t num_tx_pending; 130 wait_queue_head_t tx_empty_waitq; 131 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 132 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 133 134 struct ieee80211_rx_status rx_status; 135 struct ath12k_mon_data mon_data; 136 }; 137 138 #define DP_NUM_CLIENTS_MAX 64 139 #define DP_AVG_TIDS_PER_CLIENT 2 140 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 141 #define DP_AVG_MSDUS_PER_FLOW 128 142 #define DP_AVG_FLOWS_PER_TID 2 143 #define DP_AVG_MPDUS_PER_TID_MAX 128 144 #define DP_AVG_MSDUS_PER_MPDU 4 145 146 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 147 148 #define DP_BA_WIN_SZ_MAX 256 149 150 #define DP_TCL_NUM_RING_MAX 4 151 152 #define DP_IDLE_SCATTER_BUFS_MAX 16 153 154 #define DP_WBM_RELEASE_RING_SIZE 64 155 #define DP_TCL_DATA_RING_SIZE 512 156 #define DP_TX_COMP_RING_SIZE 32768 157 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 158 #define DP_TCL_CMD_RING_SIZE 32 159 #define DP_TCL_STATUS_RING_SIZE 32 160 #define DP_REO_DST_RING_MAX 8 161 #define DP_REO_DST_RING_SIZE 2048 162 #define DP_REO_REINJECT_RING_SIZE 32 163 #define DP_RX_RELEASE_RING_SIZE 1024 164 #define DP_REO_EXCEPTION_RING_SIZE 128 165 #define DP_REO_CMD_RING_SIZE 128 166 #define DP_REO_STATUS_RING_SIZE 2048 167 #define DP_RXDMA_BUF_RING_SIZE 4096 168 #define DP_RXDMA_REFILL_RING_SIZE 2048 169 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 170 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 171 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 172 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 173 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 174 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 175 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 176 177 #define DP_TX_MONITOR_BUF_SIZE 2048 178 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 179 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 180 181 #define DP_RX_BUFFER_SIZE 2048 182 #define DP_RX_BUFFER_SIZE_LITE 1024 183 #define DP_RX_BUFFER_ALIGN_SIZE 128 184 185 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 186 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 187 188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 189 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 190 191 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 192 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 193 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 194 195 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 196 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 197 198 #define ATH12K_NUM_POOL_TX_DESC 32768 199 200 /* TODO: revisit this count during testing */ 201 #define ATH12K_RX_DESC_COUNT (12288) 202 203 #define ATH12K_PAGE_SIZE PAGE_SIZE 204 205 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 206 * SPT pages which makes lower 12bits 0 207 */ 208 #define ATH12K_MAX_PPT_ENTRIES 1024 209 210 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 211 #define ATH12K_MAX_SPT_ENTRIES 512 212 213 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 214 215 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 216 ATH12K_MAX_SPT_ENTRIES) 217 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 218 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 219 220 /* The SPT pages are divided for RX and TX, first block for RX 221 * and remaining for TX 222 */ 223 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 224 225 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 226 227 /* 4K aligned address have last 12 bits set to 0, this check is done 228 * so that two spt pages address can be stored per 8bytes 229 * of CMEM (PPT) 230 */ 231 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 232 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 233 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 234 235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 236 #define ATH12K_CMEM_ADDR_MSB 0x10 237 238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 239 #define ATH12K_CC_SPT_MSB 8 240 #define ATH12K_CC_PPT_MSB 19 241 #define ATH12K_CC_PPT_SHIFT 9 242 #define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0) 243 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 244 245 #define DP_REO_QREF_NUM GENMASK(31, 16) 246 #define DP_MAX_PEER_ID 2047 247 248 /* Total size of the LUT is based on 2K peers, each having reference 249 * for 17tids, note each entry is of type ath12k_reo_queue_ref 250 * hence total size is 2048 * 17 * 8 = 278528 251 */ 252 #define DP_REOQ_LUT_SIZE 278528 253 254 /* Invalid TX Bank ID value */ 255 #define DP_INVALID_BANK_ID -1 256 257 struct ath12k_dp_tx_bank_profile { 258 u8 is_configured; 259 u32 num_users; 260 u32 bank_config; 261 }; 262 263 struct ath12k_hp_update_timer { 264 struct timer_list timer; 265 bool started; 266 bool init; 267 u32 tx_num; 268 u32 timer_tx_num; 269 u32 ring_id; 270 u32 interval; 271 struct ath12k_base *ab; 272 }; 273 274 struct ath12k_rx_desc_info { 275 struct list_head list; 276 struct sk_buff *skb; 277 u32 cookie; 278 u32 magic; 279 }; 280 281 struct ath12k_tx_desc_info { 282 struct list_head list; 283 struct sk_buff *skb; 284 u32 desc_id; /* Cookie */ 285 u8 mac_id; 286 u8 pool_id; 287 }; 288 289 struct ath12k_spt_info { 290 dma_addr_t paddr; 291 u64 *vaddr; 292 }; 293 294 struct ath12k_reo_queue_ref { 295 u32 info0; 296 u32 info1; 297 } __packed; 298 299 struct ath12k_reo_q_addr_lut { 300 dma_addr_t paddr; 301 u32 *vaddr; 302 }; 303 304 struct ath12k_dp { 305 struct ath12k_base *ab; 306 u8 num_bank_profiles; 307 /* protects the access and update of bank_profiles */ 308 spinlock_t tx_bank_lock; 309 struct ath12k_dp_tx_bank_profile *bank_profiles; 310 enum ath12k_htc_ep_id eid; 311 struct completion htt_tgt_version_received; 312 u8 htt_tgt_ver_major; 313 u8 htt_tgt_ver_minor; 314 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 315 struct dp_srng wbm_idle_ring; 316 struct dp_srng wbm_desc_rel_ring; 317 struct dp_srng tcl_cmd_ring; 318 struct dp_srng tcl_status_ring; 319 struct dp_srng reo_reinject_ring; 320 struct dp_srng rx_rel_ring; 321 struct dp_srng reo_except_ring; 322 struct dp_srng reo_cmd_ring; 323 struct dp_srng reo_status_ring; 324 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 325 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 326 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 327 struct list_head reo_cmd_list; 328 struct list_head reo_cmd_cache_flush_list; 329 u32 reo_cmd_cache_flush_count; 330 331 /* protects access to below fields, 332 * - reo_cmd_list 333 * - reo_cmd_cache_flush_list 334 * - reo_cmd_cache_flush_count 335 */ 336 spinlock_t reo_cmd_lock; 337 struct ath12k_hp_update_timer reo_cmd_timer; 338 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 339 struct ath12k_spt_info *spt_info; 340 u32 num_spt_pages; 341 struct list_head rx_desc_free_list; 342 struct list_head rx_desc_used_list; 343 /* protects the free and used desc list */ 344 spinlock_t rx_desc_lock; 345 346 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 347 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 348 /* protects the free and used desc lists */ 349 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 350 351 struct dp_rxdma_ring rx_refill_buf_ring; 352 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 353 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 354 struct dp_rxdma_ring rxdma_mon_buf_ring; 355 struct dp_rxdma_ring tx_mon_buf_ring; 356 struct ath12k_reo_q_addr_lut reoq_lut; 357 }; 358 359 /* HTT definitions */ 360 361 #define HTT_TCL_META_DATA_TYPE BIT(0) 362 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 363 364 /* vdev meta data */ 365 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 366 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 367 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 368 369 /* peer meta data */ 370 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 371 372 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 373 374 /* HTT tx completion is overlaid in wbm_release_ring */ 375 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 376 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 377 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 378 379 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 380 381 struct htt_tx_wbm_completion { 382 __le32 rsvd0[2]; 383 __le32 info0; 384 __le32 info1; 385 __le32 info2; 386 __le32 info3; 387 __le32 info4; 388 __le32 rsvd1; 389 390 } __packed; 391 392 enum htt_h2t_msg_type { 393 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 394 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 395 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 396 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 397 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 398 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 399 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 400 }; 401 402 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 403 404 struct htt_ver_req_cmd { 405 __le32 ver_reg_info; 406 } __packed; 407 408 enum htt_srng_ring_type { 409 HTT_HW_TO_SW_RING, 410 HTT_SW_TO_HW_RING, 411 HTT_SW_TO_SW_RING, 412 }; 413 414 enum htt_srng_ring_id { 415 HTT_RXDMA_HOST_BUF_RING, 416 HTT_RXDMA_MONITOR_STATUS_RING, 417 HTT_RXDMA_MONITOR_BUF_RING, 418 HTT_RXDMA_MONITOR_DESC_RING, 419 HTT_RXDMA_MONITOR_DEST_RING, 420 HTT_HOST1_TO_FW_RXBUF_RING, 421 HTT_HOST2_TO_FW_RXBUF_RING, 422 HTT_RXDMA_NON_MONITOR_DEST_RING, 423 HTT_TX_MON_HOST2MON_BUF_RING, 424 HTT_TX_MON_MON2HOST_DEST_RING, 425 }; 426 427 /* host -> target HTT_SRING_SETUP message 428 * 429 * After target is booted up, Host can send SRING setup message for 430 * each host facing LMAC SRING. Target setups up HW registers based 431 * on setup message and confirms back to Host if response_required is set. 432 * Host should wait for confirmation message before sending new SRING 433 * setup message 434 * 435 * The message would appear as follows: 436 * 437 * |31 24|23 20|19|18 16|15|14 8|7 0| 438 * |--------------- +-----------------+----------------+------------------| 439 * | ring_type | ring_id | pdev_id | msg_type | 440 * |----------------------------------------------------------------------| 441 * | ring_base_addr_lo | 442 * |----------------------------------------------------------------------| 443 * | ring_base_addr_hi | 444 * |----------------------------------------------------------------------| 445 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 446 * |----------------------------------------------------------------------| 447 * | ring_head_offset32_remote_addr_lo | 448 * |----------------------------------------------------------------------| 449 * | ring_head_offset32_remote_addr_hi | 450 * |----------------------------------------------------------------------| 451 * | ring_tail_offset32_remote_addr_lo | 452 * |----------------------------------------------------------------------| 453 * | ring_tail_offset32_remote_addr_hi | 454 * |----------------------------------------------------------------------| 455 * | ring_msi_addr_lo | 456 * |----------------------------------------------------------------------| 457 * | ring_msi_addr_hi | 458 * |----------------------------------------------------------------------| 459 * | ring_msi_data | 460 * |----------------------------------------------------------------------| 461 * | intr_timer_th |IM| intr_batch_counter_th | 462 * |----------------------------------------------------------------------| 463 * | reserved |RR|PTCF| intr_low_threshold | 464 * |----------------------------------------------------------------------| 465 * Where 466 * IM = sw_intr_mode 467 * RR = response_required 468 * PTCF = prefetch_timer_cfg 469 * 470 * The message is interpreted as follows: 471 * dword0 - b'0:7 - msg_type: This will be set to 472 * HTT_H2T_MSG_TYPE_SRING_SETUP 473 * b'8:15 - pdev_id: 474 * 0 (for rings at SOC/UMAC level), 475 * 1/2/3 mac id (for rings at LMAC level) 476 * b'16:23 - ring_id: identify which ring is to setup, 477 * more details can be got from enum htt_srng_ring_id 478 * b'24:31 - ring_type: identify type of host rings, 479 * more details can be got from enum htt_srng_ring_type 480 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 481 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 482 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 483 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 484 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 485 * SW_TO_HW_RING. 486 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 487 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 488 * Lower 32 bits of memory address of the remote variable 489 * storing the 4-byte word offset that identifies the head 490 * element within the ring. 491 * (The head offset variable has type u32.) 492 * Valid for HW_TO_SW and SW_TO_SW rings. 493 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 494 * Upper 32 bits of memory address of the remote variable 495 * storing the 4-byte word offset that identifies the head 496 * element within the ring. 497 * (The head offset variable has type u32.) 498 * Valid for HW_TO_SW and SW_TO_SW rings. 499 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 500 * Lower 32 bits of memory address of the remote variable 501 * storing the 4-byte word offset that identifies the tail 502 * element within the ring. 503 * (The tail offset variable has type u32.) 504 * Valid for HW_TO_SW and SW_TO_SW rings. 505 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 506 * Upper 32 bits of memory address of the remote variable 507 * storing the 4-byte word offset that identifies the tail 508 * element within the ring. 509 * (The tail offset variable has type u32.) 510 * Valid for HW_TO_SW and SW_TO_SW rings. 511 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 512 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 513 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 514 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 515 * dword10 - b'0:31 - ring_msi_data: MSI data 516 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 517 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 518 * dword11 - b'0:14 - intr_batch_counter_th: 519 * batch counter threshold is in units of 4-byte words. 520 * HW internally maintains and increments batch count. 521 * (see SRING spec for detail description). 522 * When batch count reaches threshold value, an interrupt 523 * is generated by HW. 524 * b'15 - sw_intr_mode: 525 * This configuration shall be static. 526 * Only programmed at power up. 527 * 0: generate pulse style sw interrupts 528 * 1: generate level style sw interrupts 529 * b'16:31 - intr_timer_th: 530 * The timer init value when timer is idle or is 531 * initialized to start downcounting. 532 * In 8us units (to cover a range of 0 to 524 ms) 533 * dword12 - b'0:15 - intr_low_threshold: 534 * Used only by Consumer ring to generate ring_sw_int_p. 535 * Ring entries low threshold water mark, that is used 536 * in combination with the interrupt timer as well as 537 * the clearing of the level interrupt. 538 * b'16:18 - prefetch_timer_cfg: 539 * Used only by Consumer ring to set timer mode to 540 * support Application prefetch handling. 541 * The external tail offset/pointer will be updated 542 * at following intervals: 543 * 3'b000: (Prefetch feature disabled; used only for debug) 544 * 3'b001: 1 usec 545 * 3'b010: 4 usec 546 * 3'b011: 8 usec (default) 547 * 3'b100: 16 usec 548 * Others: Reserved 549 * b'19 - response_required: 550 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 551 * b'20:31 - reserved: reserved for future use 552 */ 553 554 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 555 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 556 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 557 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 558 559 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 560 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 561 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 562 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 563 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 564 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 565 566 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 567 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 568 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 569 570 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 571 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 572 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 573 574 struct htt_srng_setup_cmd { 575 __le32 info0; 576 __le32 ring_base_addr_lo; 577 __le32 ring_base_addr_hi; 578 __le32 info1; 579 __le32 ring_head_off32_remote_addr_lo; 580 __le32 ring_head_off32_remote_addr_hi; 581 __le32 ring_tail_off32_remote_addr_lo; 582 __le32 ring_tail_off32_remote_addr_hi; 583 __le32 ring_msi_addr_lo; 584 __le32 ring_msi_addr_hi; 585 __le32 msi_data; 586 __le32 intr_info; 587 __le32 info2; 588 } __packed; 589 590 /* host -> target FW PPDU_STATS config message 591 * 592 * @details 593 * The following field definitions describe the format of the HTT host 594 * to target FW for PPDU_STATS_CFG msg. 595 * The message allows the host to configure the PPDU_STATS_IND messages 596 * produced by the target. 597 * 598 * |31 24|23 16|15 8|7 0| 599 * |-----------------------------------------------------------| 600 * | REQ bit mask | pdev_mask | msg type | 601 * |-----------------------------------------------------------| 602 * Header fields: 603 * - MSG_TYPE 604 * Bits 7:0 605 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 606 * Value: 0x11 607 * - PDEV_MASK 608 * Bits 8:15 609 * Purpose: identifies which pdevs this PPDU stats configuration applies to 610 * Value: This is a overloaded field, refer to usage and interpretation of 611 * PDEV in interface document. 612 * Bit 8 : Reserved for SOC stats 613 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 614 * Indicates MACID_MASK in DBS 615 * - REQ_TLV_BIT_MASK 616 * Bits 16:31 617 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 618 * needs to be included in the target's PPDU_STATS_IND messages. 619 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 620 * 621 */ 622 623 struct htt_ppdu_stats_cfg_cmd { 624 __le32 msg; 625 } __packed; 626 627 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 628 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 629 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 630 631 enum htt_ppdu_stats_tag_type { 632 HTT_PPDU_STATS_TAG_COMMON, 633 HTT_PPDU_STATS_TAG_USR_COMMON, 634 HTT_PPDU_STATS_TAG_USR_RATE, 635 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 636 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 637 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 638 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 639 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 640 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 641 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 642 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 643 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 644 HTT_PPDU_STATS_TAG_INFO, 645 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 646 647 /* New TLV's are added above to this line */ 648 HTT_PPDU_STATS_TAG_MAX, 649 }; 650 651 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 652 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 653 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 654 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 655 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 656 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 657 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 658 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 659 660 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 661 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 662 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 663 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 664 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 665 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 666 HTT_PPDU_STATS_TAG_DEFAULT) 667 668 enum htt_stats_internal_ppdu_frametype { 669 HTT_STATS_PPDU_FTYPE_CTRL, 670 HTT_STATS_PPDU_FTYPE_DATA, 671 HTT_STATS_PPDU_FTYPE_BAR, 672 HTT_STATS_PPDU_FTYPE_MAX 673 }; 674 675 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 676 * 677 * details: 678 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 679 * configure RXDMA rings. 680 * The configuration is per ring based and includes both packet subtypes 681 * and PPDU/MPDU TLVs. 682 * 683 * The message would appear as follows: 684 * 685 * |31 26|25|24|23 16|15 8|7 0| 686 * |-----------------+----------------+----------------+---------------| 687 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 688 * |-------------------------------------------------------------------| 689 * | rsvd2 | ring_buffer_size | 690 * |-------------------------------------------------------------------| 691 * | packet_type_enable_flags_0 | 692 * |-------------------------------------------------------------------| 693 * | packet_type_enable_flags_1 | 694 * |-------------------------------------------------------------------| 695 * | packet_type_enable_flags_2 | 696 * |-------------------------------------------------------------------| 697 * | packet_type_enable_flags_3 | 698 * |-------------------------------------------------------------------| 699 * | tlv_filter_in_flags | 700 * |-------------------------------------------------------------------| 701 * Where: 702 * PS = pkt_swap 703 * SS = status_swap 704 * The message is interpreted as follows: 705 * dword0 - b'0:7 - msg_type: This will be set to 706 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 707 * b'8:15 - pdev_id: 708 * 0 (for rings at SOC/UMAC level), 709 * 1/2/3 mac id (for rings at LMAC level) 710 * b'16:23 - ring_id : Identify the ring to configure. 711 * More details can be got from enum htt_srng_ring_id 712 * b'24 - status_swap: 1 is to swap status TLV 713 * b'25 - pkt_swap: 1 is to swap packet TLV 714 * b'26:31 - rsvd1: reserved for future use 715 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 716 * in byte units. 717 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 718 * - b'16:31 - rsvd2: Reserved for future use 719 * dword2 - b'0:31 - packet_type_enable_flags_0: 720 * Enable MGMT packet from 0b0000 to 0b1001 721 * bits from low to high: FP, MD, MO - 3 bits 722 * FP: Filter_Pass 723 * MD: Monitor_Direct 724 * MO: Monitor_Other 725 * 10 mgmt subtypes * 3 bits -> 30 bits 726 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 727 * dword3 - b'0:31 - packet_type_enable_flags_1: 728 * Enable MGMT packet from 0b1010 to 0b1111 729 * bits from low to high: FP, MD, MO - 3 bits 730 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 731 * dword4 - b'0:31 - packet_type_enable_flags_2: 732 * Enable CTRL packet from 0b0000 to 0b1001 733 * bits from low to high: FP, MD, MO - 3 bits 734 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 735 * dword5 - b'0:31 - packet_type_enable_flags_3: 736 * Enable CTRL packet from 0b1010 to 0b1111, 737 * MCAST_DATA, UCAST_DATA, NULL_DATA 738 * bits from low to high: FP, MD, MO - 3 bits 739 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 740 * dword6 - b'0:31 - tlv_filter_in_flags: 741 * Filter in Attention/MPDU/PPDU/Header/User tlvs 742 * Refer to CFG_TLV_FILTER_IN_FLAG defs 743 */ 744 745 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 746 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 747 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 748 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 749 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 750 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 751 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26) 752 753 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 754 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 755 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 756 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 757 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 758 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 759 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 760 761 enum htt_rx_filter_tlv_flags { 762 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 763 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 764 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 765 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 766 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 767 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 768 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 769 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 770 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 771 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 772 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 773 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 774 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 775 }; 776 777 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 778 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 779 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 780 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 781 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 782 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 783 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 784 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 785 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 786 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 787 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 788 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 789 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 790 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 791 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 792 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 793 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 794 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 795 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 796 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 797 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 798 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 799 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 800 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 801 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 802 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 803 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 804 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 805 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 806 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 807 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 808 }; 809 810 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 811 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 812 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 813 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 814 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 815 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 816 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 817 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 818 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 819 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 820 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 821 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 822 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 823 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 824 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 825 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 826 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 827 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 828 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 829 }; 830 831 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 832 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 833 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 834 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 835 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 836 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 837 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 838 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 839 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 840 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 841 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 842 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 843 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 844 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 845 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 846 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 847 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 848 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 849 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 850 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 851 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 852 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 853 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 854 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 855 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 856 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 857 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 858 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 859 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 860 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 861 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 862 }; 863 864 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 865 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 866 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 867 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 868 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 869 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 870 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 871 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 872 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 873 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 874 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 875 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 876 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 877 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 878 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 879 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 880 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 881 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 882 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 883 }; 884 885 enum htt_rx_data_pkt_filter_tlv_flasg3 { 886 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 887 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 888 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 889 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 890 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 891 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 892 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 893 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 894 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 895 }; 896 897 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 898 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 899 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 900 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 901 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 902 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 903 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 904 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 905 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 906 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 907 908 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 909 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 910 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 911 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 912 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 913 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 914 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 915 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 916 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 917 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 918 919 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 920 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 921 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 922 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 923 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 924 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 925 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 926 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 927 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 928 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 929 930 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 931 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 932 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 933 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 934 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 935 936 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 937 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 938 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 939 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 940 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 941 942 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 943 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 944 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 945 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 946 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 947 948 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 949 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 950 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 951 952 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 953 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 954 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 955 956 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 957 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 958 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 959 960 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 961 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 962 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 963 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 964 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 965 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 966 967 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 968 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 969 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 970 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 971 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 972 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 973 974 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 975 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 976 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 977 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 978 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 979 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 980 981 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 982 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 983 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 984 985 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 986 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 987 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 988 989 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 990 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 991 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 992 993 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 994 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 995 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 996 997 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 998 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 999 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1000 1001 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1002 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1003 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1004 1005 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1006 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1007 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1008 1009 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1010 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1011 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1012 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1013 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1014 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1015 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1016 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1017 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1018 1019 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1020 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1021 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1022 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1023 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1024 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1025 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1026 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1027 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1028 1029 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1030 1031 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1032 1033 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1034 1035 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1036 1037 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1038 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1039 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1040 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1041 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1042 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1043 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1044 1045 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1046 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1047 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1048 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1049 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1050 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1051 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1052 1053 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1054 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1055 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1056 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1057 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1058 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1059 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1060 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1061 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1062 1063 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1064 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1065 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1066 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1067 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1068 1069 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1070 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1071 1072 struct htt_rx_ring_selection_cfg_cmd { 1073 __le32 info0; 1074 __le32 info1; 1075 __le32 pkt_type_en_flags0; 1076 __le32 pkt_type_en_flags1; 1077 __le32 pkt_type_en_flags2; 1078 __le32 pkt_type_en_flags3; 1079 __le32 rx_filter_tlv; 1080 __le32 rx_packet_offset; 1081 __le32 rx_mpdu_offset; 1082 __le32 rx_msdu_offset; 1083 __le32 rx_attn_offset; 1084 } __packed; 1085 1086 struct htt_rx_ring_tlv_filter { 1087 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1088 u32 pkt_filter_flags0; /* MGMT */ 1089 u32 pkt_filter_flags1; /* MGMT */ 1090 u32 pkt_filter_flags2; /* CTRL */ 1091 u32 pkt_filter_flags3; /* DATA */ 1092 bool offset_valid; 1093 u16 rx_packet_offset; 1094 u16 rx_header_offset; 1095 u16 rx_mpdu_end_offset; 1096 u16 rx_mpdu_start_offset; 1097 u16 rx_msdu_end_offset; 1098 u16 rx_msdu_start_offset; 1099 u16 rx_attn_offset; 1100 }; 1101 1102 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1103 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1104 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1105 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1106 1107 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1108 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1109 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1110 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1111 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1112 1113 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1114 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1115 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1116 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1117 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1118 1119 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1120 1121 struct htt_tx_ring_selection_cfg_cmd { 1122 __le32 info0; 1123 __le32 info1; 1124 __le32 info2; 1125 __le32 tlv_filter_mask_in0; 1126 __le32 tlv_filter_mask_in1; 1127 __le32 tlv_filter_mask_in2; 1128 __le32 tlv_filter_mask_in3; 1129 __le32 reserved[3]; 1130 } __packed; 1131 1132 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1133 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1134 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1135 1136 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1137 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1138 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1139 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1140 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1141 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1142 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1143 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1144 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1145 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1146 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1147 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1148 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1149 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1150 1151 struct htt_tx_ring_tlv_filter { 1152 u32 tx_mon_downstream_tlv_flags; 1153 u32 tx_mon_upstream_tlv_flags0; 1154 u32 tx_mon_upstream_tlv_flags1; 1155 u32 tx_mon_upstream_tlv_flags2; 1156 bool tx_mon_mgmt_filter; 1157 bool tx_mon_data_filter; 1158 bool tx_mon_ctrl_filter; 1159 u16 tx_mon_pkt_dma_len; 1160 } __packed; 1161 1162 enum htt_tx_mon_upstream_tlv_flags0 { 1163 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1164 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1165 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1166 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1167 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1168 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1169 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1170 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1171 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1172 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1173 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1174 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1175 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1176 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1177 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1178 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1179 }; 1180 1181 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1182 1183 /* HTT message target->host */ 1184 1185 enum htt_t2h_msg_type { 1186 HTT_T2H_MSG_TYPE_VERSION_CONF, 1187 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1188 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1189 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1190 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1191 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1192 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1193 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1194 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1195 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1196 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1197 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1198 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1199 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1200 }; 1201 1202 #define HTT_TARGET_VERSION_MAJOR 3 1203 1204 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1205 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1206 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1207 1208 struct htt_t2h_version_conf_msg { 1209 __le32 version; 1210 } __packed; 1211 1212 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1213 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1214 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1215 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1216 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1217 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1218 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1219 1220 struct htt_t2h_peer_map_event { 1221 __le32 info; 1222 __le32 mac_addr_l32; 1223 __le32 info1; 1224 __le32 info2; 1225 } __packed; 1226 1227 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1228 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1229 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1230 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1231 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1232 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1233 1234 struct htt_t2h_peer_unmap_event { 1235 __le32 info; 1236 __le32 mac_addr_l32; 1237 __le32 info1; 1238 } __packed; 1239 1240 struct htt_resp_msg { 1241 union { 1242 struct htt_t2h_version_conf_msg version_msg; 1243 struct htt_t2h_peer_map_event peer_map_ev; 1244 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1245 }; 1246 } __packed; 1247 1248 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1249 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1250 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1251 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1252 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1253 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1254 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1255 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1256 1257 struct htt_t2h_vdev_txrx_stats_ind { 1258 __le32 vdev_id; 1259 __le32 rx_msdu_byte_cnt_lo; 1260 __le32 rx_msdu_byte_cnt_hi; 1261 __le32 rx_msdu_cnt_lo; 1262 __le32 rx_msdu_cnt_hi; 1263 __le32 tx_msdu_byte_cnt_lo; 1264 __le32 tx_msdu_byte_cnt_hi; 1265 __le32 tx_msdu_cnt_lo; 1266 __le32 tx_msdu_cnt_hi; 1267 __le32 tx_retry_cnt_lo; 1268 __le32 tx_retry_cnt_hi; 1269 __le32 tx_retry_byte_cnt_lo; 1270 __le32 tx_retry_byte_cnt_hi; 1271 __le32 tx_drop_cnt_lo; 1272 __le32 tx_drop_cnt_hi; 1273 __le32 tx_drop_byte_cnt_lo; 1274 __le32 tx_drop_byte_cnt_hi; 1275 __le32 msdu_ttl_cnt_lo; 1276 __le32 msdu_ttl_cnt_hi; 1277 __le32 msdu_ttl_byte_cnt_lo; 1278 __le32 msdu_ttl_byte_cnt_hi; 1279 } __packed; 1280 1281 struct htt_t2h_vdev_common_stats_tlv { 1282 __le32 soc_drop_count_lo; 1283 __le32 soc_drop_count_hi; 1284 } __packed; 1285 1286 /* ppdu stats 1287 * 1288 * @details 1289 * The following field definitions describe the format of the HTT target 1290 * to host ppdu stats indication message. 1291 * 1292 * 1293 * |31 16|15 12|11 10|9 8|7 0 | 1294 * |----------------------------------------------------------------------| 1295 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1296 * |----------------------------------------------------------------------| 1297 * | ppdu_id | 1298 * |----------------------------------------------------------------------| 1299 * | Timestamp in us | 1300 * |----------------------------------------------------------------------| 1301 * | reserved | 1302 * |----------------------------------------------------------------------| 1303 * | type-specific stats info | 1304 * | (see htt_ppdu_stats.h) | 1305 * |----------------------------------------------------------------------| 1306 * Header fields: 1307 * - MSG_TYPE 1308 * Bits 7:0 1309 * Purpose: Identifies this is a PPDU STATS indication 1310 * message. 1311 * Value: 0x1d 1312 * - mac_id 1313 * Bits 9:8 1314 * Purpose: mac_id of this ppdu_id 1315 * Value: 0-3 1316 * - pdev_id 1317 * Bits 11:10 1318 * Purpose: pdev_id of this ppdu_id 1319 * Value: 0-3 1320 * 0 (for rings at SOC level), 1321 * 1/2/3 PDEV -> 0/1/2 1322 * - payload_size 1323 * Bits 31:16 1324 * Purpose: total tlv size 1325 * Value: payload_size in bytes 1326 */ 1327 1328 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1329 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1330 1331 struct ath12k_htt_ppdu_stats_msg { 1332 __le32 info; 1333 __le32 ppdu_id; 1334 __le32 timestamp; 1335 __le32 rsvd; 1336 u8 data[]; 1337 } __packed; 1338 1339 struct htt_tlv { 1340 __le32 header; 1341 #if defined(__linux__) 1342 u8 value[]; 1343 #elif defined(__FreeBSD__) 1344 u8 value[0]; 1345 #endif 1346 } __packed; 1347 1348 #define HTT_TLV_TAG GENMASK(11, 0) 1349 #define HTT_TLV_LEN GENMASK(23, 12) 1350 1351 enum HTT_PPDU_STATS_BW { 1352 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1353 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1354 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1355 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1356 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1357 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1358 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1359 }; 1360 1361 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1362 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1363 /* bw - HTT_PPDU_STATS_BW */ 1364 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1365 1366 struct htt_ppdu_stats_common { 1367 __le32 ppdu_id; 1368 __le16 sched_cmdid; 1369 u8 ring_id; 1370 u8 num_users; 1371 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1372 __le32 chain_mask; 1373 __le32 fes_duration_us; /* frame exchange sequence */ 1374 __le32 ppdu_sch_eval_start_tstmp_us; 1375 __le32 ppdu_sch_end_tstmp_us; 1376 __le32 ppdu_start_tstmp_us; 1377 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1378 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1379 */ 1380 __le16 phy_mode; 1381 __le16 bw_mhz; 1382 } __packed; 1383 1384 enum htt_ppdu_stats_gi { 1385 HTT_PPDU_STATS_SGI_0_8_US, 1386 HTT_PPDU_STATS_SGI_0_4_US, 1387 HTT_PPDU_STATS_SGI_1_6_US, 1388 HTT_PPDU_STATS_SGI_3_2_US, 1389 }; 1390 1391 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1392 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1393 1394 enum HTT_PPDU_STATS_PPDU_TYPE { 1395 HTT_PPDU_STATS_PPDU_TYPE_SU, 1396 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1397 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1398 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1399 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1400 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1401 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1402 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1403 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1404 HTT_PPDU_STATS_PPDU_TYPE_MAX 1405 }; 1406 1407 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1408 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1409 1410 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1411 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1412 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1413 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1414 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1415 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1416 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1417 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1418 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1419 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1420 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1421 1422 #define HTT_USR_RATE_PREAMBLE(_val) \ 1423 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1424 #define HTT_USR_RATE_BW(_val) \ 1425 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1426 #define HTT_USR_RATE_NSS(_val) \ 1427 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1428 #define HTT_USR_RATE_MCS(_val) \ 1429 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1430 #define HTT_USR_RATE_GI(_val) \ 1431 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1432 #define HTT_USR_RATE_DCM(_val) \ 1433 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1434 1435 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1436 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1437 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1438 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1439 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1440 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1441 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1442 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1443 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1444 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1445 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1446 1447 struct htt_ppdu_stats_user_rate { 1448 u8 tid_num; 1449 u8 reserved0; 1450 __le16 sw_peer_id; 1451 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1452 __le16 ru_end; 1453 __le16 ru_start; 1454 __le16 resp_ru_end; 1455 __le16 resp_ru_start; 1456 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1457 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1458 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1459 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1460 } __packed; 1461 1462 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1463 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1464 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1465 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1466 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1467 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1468 1469 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1470 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1471 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1472 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1473 #define HTT_TX_INFO_RATECODE(_flags) \ 1474 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1475 #define HTT_TX_INFO_PEERID(_flags) \ 1476 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1477 1478 struct htt_tx_ppdu_stats_info { 1479 struct htt_tlv tlv_hdr; 1480 __le32 tx_success_bytes; 1481 __le32 tx_retry_bytes; 1482 __le32 tx_failed_bytes; 1483 __le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1484 __le16 tx_success_msdus; 1485 __le16 tx_retry_msdus; 1486 __le16 tx_failed_msdus; 1487 __le16 tx_duration; /* united in us */ 1488 } __packed; 1489 1490 enum htt_ppdu_stats_usr_compln_status { 1491 HTT_PPDU_STATS_USER_STATUS_OK, 1492 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1493 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1494 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1495 HTT_PPDU_STATS_USER_STATUS_ABORT, 1496 }; 1497 1498 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1499 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1500 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1501 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1502 1503 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1504 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1505 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1506 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1507 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1508 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1509 1510 struct htt_ppdu_stats_usr_cmpltn_cmn { 1511 u8 status; 1512 u8 tid_num; 1513 __le16 sw_peer_id; 1514 /* RSSI value of last ack packet (units = dB above noise floor) */ 1515 __le32 ack_rssi; 1516 __le16 mpdu_tried; 1517 __le16 mpdu_success; 1518 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1519 } __packed; 1520 1521 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1522 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1523 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1524 1525 #define HTT_PPDU_STATS_NON_QOS_TID 16 1526 1527 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1528 __le32 ppdu_id; 1529 __le16 sw_peer_id; 1530 __le16 reserved0; 1531 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1532 __le16 current_seq; 1533 __le16 start_seq; 1534 __le32 success_bytes; 1535 } __packed; 1536 1537 struct htt_ppdu_user_stats { 1538 u16 peer_id; 1539 u16 delay_ba; 1540 u32 tlv_flags; 1541 bool is_valid_peer_id; 1542 struct htt_ppdu_stats_user_rate rate; 1543 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1544 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1545 }; 1546 1547 #define HTT_PPDU_STATS_MAX_USERS 8 1548 #define HTT_PPDU_DESC_MAX_DEPTH 16 1549 1550 struct htt_ppdu_stats { 1551 struct htt_ppdu_stats_common common; 1552 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1553 }; 1554 1555 struct htt_ppdu_stats_info { 1556 u32 tlv_bitmap; 1557 u32 ppdu_id; 1558 u32 frame_type; 1559 u32 frame_ctrl; 1560 u32 delay_ba; 1561 u32 bar_num_users; 1562 struct htt_ppdu_stats ppdu_stats; 1563 struct list_head list; 1564 }; 1565 1566 /* @brief target -> host MLO offset indiciation message 1567 * 1568 * @details 1569 * The following field definitions describe the format of the HTT target 1570 * to host mlo offset indication message. 1571 * 1572 * 1573 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1574 * |---------------------------------------------------------------------| 1575 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1576 * |---------------------------------------------------------------------| 1577 * | sync_timestamp_lo_us | 1578 * |---------------------------------------------------------------------| 1579 * | sync_timestamp_hi_us | 1580 * |---------------------------------------------------------------------| 1581 * | mlo_offset_lo | 1582 * |---------------------------------------------------------------------| 1583 * | mlo_offset_hi | 1584 * |---------------------------------------------------------------------| 1585 * | mlo_offset_clcks | 1586 * |---------------------------------------------------------------------| 1587 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1588 * |---------------------------------------------------------------------| 1589 * | rsvd3 |mlo_comp_timer | 1590 * |---------------------------------------------------------------------| 1591 * Header fields 1592 * - MSG_TYPE 1593 * Bits 7:0 1594 * Purpose: Identifies this is a MLO offset indication msg 1595 * - PDEV_ID 1596 * Bits 9:8 1597 * Purpose: Pdev of this MLO offset 1598 * - CHIP_ID 1599 * Bits 12:10 1600 * Purpose: chip_id of this MLO offset 1601 * - MAC_FREQ 1602 * Bits 28:13 1603 * - SYNC_TIMESTAMP_LO_US 1604 * Purpose: clock frequency of the mac HW block in MHz 1605 * Bits: 31:0 1606 * Purpose: lower 32 bits of the WLAN global time stamp at which 1607 * last sync interrupt was received 1608 * - SYNC_TIMESTAMP_HI_US 1609 * Bits: 31:0 1610 * Purpose: upper 32 bits of WLAN global time stamp at which 1611 * last sync interrupt was received 1612 * - MLO_OFFSET_LO 1613 * Bits: 31:0 1614 * Purpose: lower 32 bits of the MLO offset in us 1615 * - MLO_OFFSET_HI 1616 * Bits: 31:0 1617 * Purpose: upper 32 bits of the MLO offset in us 1618 * - MLO_COMP_US 1619 * Bits: 15:0 1620 * Purpose: MLO time stamp compensation applied in us 1621 * - MLO_COMP_CLCKS 1622 * Bits: 25:16 1623 * Purpose: MLO time stamp compensation applied in clock ticks 1624 * - MLO_COMP_TIMER 1625 * Bits: 21:0 1626 * Purpose: Periodic timer at which compensation is applied 1627 */ 1628 1629 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1630 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1631 1632 struct ath12k_htt_mlo_offset_msg { 1633 __le32 info; 1634 __le32 sync_timestamp_lo_us; 1635 __le32 sync_timestamp_hi_us; 1636 __le32 mlo_offset_hi; 1637 __le32 mlo_offset_lo; 1638 __le32 mlo_offset_clks; 1639 __le32 mlo_comp_clks; 1640 __le32 mlo_comp_timer; 1641 } __packed; 1642 1643 /* @brief host -> target FW extended statistics retrieve 1644 * 1645 * @details 1646 * The following field definitions describe the format of the HTT host 1647 * to target FW extended stats retrieve message. 1648 * The message specifies the type of stats the host wants to retrieve. 1649 * 1650 * |31 24|23 16|15 8|7 0| 1651 * |-----------------------------------------------------------| 1652 * | reserved | stats type | pdev_mask | msg type | 1653 * |-----------------------------------------------------------| 1654 * | config param [0] | 1655 * |-----------------------------------------------------------| 1656 * | config param [1] | 1657 * |-----------------------------------------------------------| 1658 * | config param [2] | 1659 * |-----------------------------------------------------------| 1660 * | config param [3] | 1661 * |-----------------------------------------------------------| 1662 * | reserved | 1663 * |-----------------------------------------------------------| 1664 * | cookie LSBs | 1665 * |-----------------------------------------------------------| 1666 * | cookie MSBs | 1667 * |-----------------------------------------------------------| 1668 * Header fields: 1669 * - MSG_TYPE 1670 * Bits 7:0 1671 * Purpose: identifies this is a extended stats upload request message 1672 * Value: 0x10 1673 * - PDEV_MASK 1674 * Bits 8:15 1675 * Purpose: identifies the mask of PDEVs to retrieve stats from 1676 * Value: This is a overloaded field, refer to usage and interpretation of 1677 * PDEV in interface document. 1678 * Bit 8 : Reserved for SOC stats 1679 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1680 * Indicates MACID_MASK in DBS 1681 * - STATS_TYPE 1682 * Bits 23:16 1683 * Purpose: identifies which FW statistics to upload 1684 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1685 * - Reserved 1686 * Bits 31:24 1687 * - CONFIG_PARAM [0] 1688 * Bits 31:0 1689 * Purpose: give an opaque configuration value to the specified stats type 1690 * Value: stats-type specific configuration value 1691 * Refer to htt_stats.h for interpretation for each stats sub_type 1692 * - CONFIG_PARAM [1] 1693 * Bits 31:0 1694 * Purpose: give an opaque configuration value to the specified stats type 1695 * Value: stats-type specific configuration value 1696 * Refer to htt_stats.h for interpretation for each stats sub_type 1697 * - CONFIG_PARAM [2] 1698 * Bits 31:0 1699 * Purpose: give an opaque configuration value to the specified stats type 1700 * Value: stats-type specific configuration value 1701 * Refer to htt_stats.h for interpretation for each stats sub_type 1702 * - CONFIG_PARAM [3] 1703 * Bits 31:0 1704 * Purpose: give an opaque configuration value to the specified stats type 1705 * Value: stats-type specific configuration value 1706 * Refer to htt_stats.h for interpretation for each stats sub_type 1707 * - Reserved [31:0] for future use. 1708 * - COOKIE_LSBS 1709 * Bits 31:0 1710 * Purpose: Provide a mechanism to match a target->host stats confirmation 1711 * message with its preceding host->target stats request message. 1712 * Value: LSBs of the opaque cookie specified by the host-side requestor 1713 * - COOKIE_MSBS 1714 * Bits 31:0 1715 * Purpose: Provide a mechanism to match a target->host stats confirmation 1716 * message with its preceding host->target stats request message. 1717 * Value: MSBs of the opaque cookie specified by the host-side requestor 1718 */ 1719 1720 struct htt_ext_stats_cfg_hdr { 1721 u8 msg_type; 1722 u8 pdev_mask; 1723 u8 stats_type; 1724 u8 reserved; 1725 } __packed; 1726 1727 struct htt_ext_stats_cfg_cmd { 1728 struct htt_ext_stats_cfg_hdr hdr; 1729 __le32 cfg_param0; 1730 __le32 cfg_param1; 1731 __le32 cfg_param2; 1732 __le32 cfg_param3; 1733 __le32 reserved; 1734 __le32 cookie_lsb; 1735 __le32 cookie_msb; 1736 } __packed; 1737 1738 /* htt stats config default params */ 1739 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1740 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1741 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1742 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1743 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1744 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1745 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1746 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1747 1748 /* HTT_DBG_EXT_STATS_PEER_INFO 1749 * PARAMS: 1750 * @config_param0: 1751 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1752 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1753 * [Bit31 : Bit16] sw_peer_id 1754 * @config_param1: 1755 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1756 * 0 bit htt_peer_stats_cmn_tlv 1757 * 1 bit htt_peer_details_tlv 1758 * 2 bit htt_tx_peer_rate_stats_tlv 1759 * 3 bit htt_rx_peer_rate_stats_tlv 1760 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1761 * 5 bit htt_rx_tid_stats_tlv 1762 * 6 bit htt_msdu_flow_stats_tlv 1763 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1764 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1765 * [Bit31 : Bit16] reserved 1766 */ 1767 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1768 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1769 1770 /* Used to set different configs to the specified stats type.*/ 1771 struct htt_ext_stats_cfg_params { 1772 u32 cfg0; 1773 u32 cfg1; 1774 u32 cfg2; 1775 u32 cfg3; 1776 }; 1777 1778 enum vdev_stats_offload_timer_duration { 1779 ATH12K_STATS_TIMER_DUR_500MS = 1, 1780 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1781 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1782 }; 1783 1784 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1785 { 1786 memcpy(addr, &addr_l32, 4); 1787 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1788 } 1789 1790 int ath12k_dp_service_srng(struct ath12k_base *ab, 1791 struct ath12k_ext_irq_grp *irq_grp, 1792 int budget); 1793 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1794 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif); 1795 void ath12k_dp_free(struct ath12k_base *ab); 1796 int ath12k_dp_alloc(struct ath12k_base *ab); 1797 void ath12k_dp_cc_config(struct ath12k_base *ab); 1798 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1799 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab); 1800 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1801 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1802 int mac_id, enum hal_ring_type ring_type); 1803 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1804 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1805 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1806 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1807 enum hal_ring_type type, int ring_num, 1808 int mac_id, int num_entries); 1809 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1810 struct dp_link_desc_bank *desc_bank, 1811 u32 ring_type, struct dp_srng *ring); 1812 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1813 struct dp_link_desc_bank *link_desc_banks, 1814 u32 ring_type, struct hal_srng *srng, 1815 u32 n_link_desc); 1816 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1817 u32 cookie); 1818 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1819 u32 desc_id); 1820 #endif 1821