1*28348caeSBjoern A. Zeeb /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*28348caeSBjoern A. Zeeb /* 3*28348caeSBjoern A. Zeeb * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4*28348caeSBjoern A. Zeeb * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 5*28348caeSBjoern A. Zeeb */ 6*28348caeSBjoern A. Zeeb 7*28348caeSBjoern A. Zeeb #ifndef _ATH11K_PCI_CMN_H 8*28348caeSBjoern A. Zeeb #define _ATH11K_PCI_CMN_H 9*28348caeSBjoern A. Zeeb 10*28348caeSBjoern A. Zeeb #include "core.h" 11*28348caeSBjoern A. Zeeb 12*28348caeSBjoern A. Zeeb #define ATH11K_PCI_IRQ_CE0_OFFSET 3 13*28348caeSBjoern A. Zeeb #define ATH11K_PCI_IRQ_DP_OFFSET 14 14*28348caeSBjoern A. Zeeb 15*28348caeSBjoern A. Zeeb #define ATH11K_PCI_CE_WAKE_IRQ 2 16*28348caeSBjoern A. Zeeb 17*28348caeSBjoern A. Zeeb #define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000 18*28348caeSBjoern A. Zeeb #define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c 19*28348caeSBjoern A. Zeeb #define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19) 20*28348caeSBjoern A. Zeeb #define ATH11K_PCI_WINDOW_START 0x80000 21*28348caeSBjoern A. Zeeb #define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0) 22*28348caeSBjoern A. Zeeb 23*28348caeSBjoern A. Zeeb /* BAR0 + 4k is always accessible, and no 24*28348caeSBjoern A. Zeeb * need to force wakeup. 25*28348caeSBjoern A. Zeeb * 4K - 32 = 0xFE0 26*28348caeSBjoern A. Zeeb */ 27*28348caeSBjoern A. Zeeb #define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0 28*28348caeSBjoern A. Zeeb 29*28348caeSBjoern A. Zeeb int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 30*28348caeSBjoern A. Zeeb int *num_vectors, u32 *user_base_data, 31*28348caeSBjoern A. Zeeb u32 *base_vector); 32*28348caeSBjoern A. Zeeb void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value); 33*28348caeSBjoern A. Zeeb u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset); 34*28348caeSBjoern A. Zeeb void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 35*28348caeSBjoern A. Zeeb u32 *msi_addr_hi); 36*28348caeSBjoern A. Zeeb void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx); 37*28348caeSBjoern A. Zeeb void ath11k_pcic_free_irq(struct ath11k_base *ab); 38*28348caeSBjoern A. Zeeb int ath11k_pcic_config_irq(struct ath11k_base *ab); 39*28348caeSBjoern A. Zeeb void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab); 40*28348caeSBjoern A. Zeeb void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab); 41*28348caeSBjoern A. Zeeb void ath11k_pcic_stop(struct ath11k_base *ab); 42*28348caeSBjoern A. Zeeb int ath11k_pcic_start(struct ath11k_base *ab); 43*28348caeSBjoern A. Zeeb int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 44*28348caeSBjoern A. Zeeb u8 *ul_pipe, u8 *dl_pipe); 45*28348caeSBjoern A. Zeeb void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab); 46*28348caeSBjoern A. Zeeb void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab); 47*28348caeSBjoern A. Zeeb int ath11k_pcic_init_msi_config(struct ath11k_base *ab); 48*28348caeSBjoern A. Zeeb int ath11k_pcic_register_pci_ops(struct ath11k_base *ab, 49*28348caeSBjoern A. Zeeb const struct ath11k_pci_ops *pci_ops); 50*28348caeSBjoern A. Zeeb int ath11k_pcic_read(struct ath11k_base *ab, void *buf, u32 start, u32 end); 51*28348caeSBjoern A. Zeeb void ath11k_pci_enable_ce_irqs_except_wake_irq(struct ath11k_base *ab); 52*28348caeSBjoern A. Zeeb void ath11k_pci_disable_ce_irqs_except_wake_irq(struct ath11k_base *ab); 53*28348caeSBjoern A. Zeeb 54*28348caeSBjoern A. Zeeb #endif 55