1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 #if defined(CONFIG_OF) 10 #include <linux/of.h> 11 #endif 12 #include <linux/of_address.h> 13 #include <linux/ioport.h> 14 #if defined(__FreeBSD__) 15 #include <linux/delay.h> 16 #endif 17 18 #include "core.h" 19 #include "debug.h" 20 #include "mhi.h" 21 #include "pci.h" 22 #include "pcic.h" 23 24 #define MHI_TIMEOUT_DEFAULT_MS 20000 25 #define RDDM_DUMP_SIZE 0x420000 26 27 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 28 { 29 .num = 0, 30 .name = "LOOPBACK", 31 .num_elements = 32, 32 .event_ring = 0, 33 .dir = DMA_TO_DEVICE, 34 .ee_mask = 0x4, 35 .pollcfg = 0, 36 .doorbell = MHI_DB_BRST_DISABLE, 37 .lpm_notify = false, 38 .offload_channel = false, 39 .doorbell_mode_switch = false, 40 .auto_queue = false, 41 }, 42 { 43 .num = 1, 44 .name = "LOOPBACK", 45 .num_elements = 32, 46 .event_ring = 0, 47 .dir = DMA_FROM_DEVICE, 48 .ee_mask = 0x4, 49 .pollcfg = 0, 50 .doorbell = MHI_DB_BRST_DISABLE, 51 .lpm_notify = false, 52 .offload_channel = false, 53 .doorbell_mode_switch = false, 54 .auto_queue = false, 55 }, 56 { 57 .num = 20, 58 .name = "IPCR", 59 .num_elements = 64, 60 .event_ring = 1, 61 .dir = DMA_TO_DEVICE, 62 .ee_mask = 0x4, 63 .pollcfg = 0, 64 .doorbell = MHI_DB_BRST_DISABLE, 65 .lpm_notify = false, 66 .offload_channel = false, 67 .doorbell_mode_switch = false, 68 .auto_queue = false, 69 }, 70 { 71 .num = 21, 72 .name = "IPCR", 73 .num_elements = 64, 74 .event_ring = 1, 75 .dir = DMA_FROM_DEVICE, 76 .ee_mask = 0x4, 77 .pollcfg = 0, 78 .doorbell = MHI_DB_BRST_DISABLE, 79 .lpm_notify = false, 80 .offload_channel = false, 81 .doorbell_mode_switch = false, 82 .auto_queue = true, 83 }, 84 }; 85 86 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 87 { 88 .num_elements = 32, 89 .irq_moderation_ms = 0, 90 .irq = 1, 91 .mode = MHI_DB_BRST_DISABLE, 92 .data_type = MHI_ER_CTRL, 93 .hardware_event = false, 94 .client_managed = false, 95 .offload_channel = false, 96 }, 97 { 98 .num_elements = 256, 99 .irq_moderation_ms = 1, 100 .irq = 2, 101 .mode = MHI_DB_BRST_DISABLE, 102 .priority = 1, 103 .hardware_event = false, 104 .client_managed = false, 105 .offload_channel = false, 106 }, 107 }; 108 109 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 110 .max_channels = 128, 111 .timeout_ms = 2000, 112 .use_bounce_buf = false, 113 .buf_len = 0, 114 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 115 .ch_cfg = ath11k_mhi_channels_qca6390, 116 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 117 .event_cfg = ath11k_mhi_events_qca6390, 118 }; 119 120 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 121 { 122 .num = 0, 123 .name = "LOOPBACK", 124 .num_elements = 32, 125 .event_ring = 1, 126 .dir = DMA_TO_DEVICE, 127 .ee_mask = 0x14, 128 .pollcfg = 0, 129 .doorbell = MHI_DB_BRST_DISABLE, 130 .lpm_notify = false, 131 .offload_channel = false, 132 .doorbell_mode_switch = false, 133 .auto_queue = false, 134 }, 135 { 136 .num = 1, 137 .name = "LOOPBACK", 138 .num_elements = 32, 139 .event_ring = 1, 140 .dir = DMA_FROM_DEVICE, 141 .ee_mask = 0x14, 142 .pollcfg = 0, 143 .doorbell = MHI_DB_BRST_DISABLE, 144 .lpm_notify = false, 145 .offload_channel = false, 146 .doorbell_mode_switch = false, 147 .auto_queue = false, 148 }, 149 { 150 .num = 20, 151 .name = "IPCR", 152 .num_elements = 32, 153 .event_ring = 1, 154 .dir = DMA_TO_DEVICE, 155 .ee_mask = 0x14, 156 .pollcfg = 0, 157 .doorbell = MHI_DB_BRST_DISABLE, 158 .lpm_notify = false, 159 .offload_channel = false, 160 .doorbell_mode_switch = false, 161 .auto_queue = false, 162 }, 163 { 164 .num = 21, 165 .name = "IPCR", 166 .num_elements = 32, 167 .event_ring = 1, 168 .dir = DMA_FROM_DEVICE, 169 .ee_mask = 0x14, 170 .pollcfg = 0, 171 .doorbell = MHI_DB_BRST_DISABLE, 172 .lpm_notify = false, 173 .offload_channel = false, 174 .doorbell_mode_switch = false, 175 .auto_queue = true, 176 }, 177 }; 178 179 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 180 { 181 .num_elements = 32, 182 .irq_moderation_ms = 0, 183 .irq = 1, 184 .data_type = MHI_ER_CTRL, 185 .mode = MHI_DB_BRST_DISABLE, 186 .hardware_event = false, 187 .client_managed = false, 188 .offload_channel = false, 189 }, 190 { 191 .num_elements = 256, 192 .irq_moderation_ms = 1, 193 .irq = 2, 194 .mode = MHI_DB_BRST_DISABLE, 195 .priority = 1, 196 .hardware_event = false, 197 .client_managed = false, 198 .offload_channel = false, 199 }, 200 }; 201 202 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 203 .max_channels = 30, 204 .timeout_ms = 10000, 205 .use_bounce_buf = false, 206 .buf_len = 0, 207 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 208 .ch_cfg = ath11k_mhi_channels_qcn9074, 209 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 210 .event_cfg = ath11k_mhi_events_qcn9074, 211 }; 212 213 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 214 { 215 u32 val; 216 217 val = ath11k_pcic_read32(ab, MHISTATUS); 218 219 ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val); 220 221 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 222 * has SYSERR bit set and thus need to set MHICTRL_RESET 223 * to clear SYSERR. 224 */ 225 ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 226 227 mdelay(10); 228 } 229 230 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 231 { 232 ath11k_pcic_write32(ab, PCIE_TXVECDB, 0); 233 } 234 235 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 236 { 237 ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0); 238 } 239 240 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 241 { 242 ath11k_pcic_write32(ab, PCIE_RXVECDB, 0); 243 } 244 245 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 246 { 247 ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0); 248 } 249 250 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 251 { 252 ath11k_mhi_reset_txvecdb(ab); 253 ath11k_mhi_reset_txvecstatus(ab); 254 ath11k_mhi_reset_rxvecdb(ab); 255 ath11k_mhi_reset_rxvecstatus(ab); 256 } 257 258 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 259 { 260 struct ath11k_base *ab = ab_pci->ab; 261 u32 user_base_data, base_vector; 262 int ret, num_vectors, i; 263 int *irq; 264 unsigned int msi_data; 265 266 ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors, 267 &user_base_data, &base_vector); 268 if (ret) 269 return ret; 270 271 ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n", 272 num_vectors, base_vector); 273 274 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 275 if (!irq) 276 return -ENOMEM; 277 278 for (i = 0; i < num_vectors; i++) { 279 msi_data = base_vector; 280 281 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 282 msi_data += i; 283 284 irq[i] = ath11k_pci_get_msi_irq(ab, msi_data); 285 } 286 287 ab_pci->mhi_ctrl->irq = irq; 288 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 289 290 return 0; 291 } 292 293 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 294 { 295 return 0; 296 } 297 298 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 299 { 300 } 301 302 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason) 303 { 304 switch (reason) { 305 case MHI_CB_IDLE: 306 return "MHI_CB_IDLE"; 307 case MHI_CB_PENDING_DATA: 308 return "MHI_CB_PENDING_DATA"; 309 case MHI_CB_LPM_ENTER: 310 return "MHI_CB_LPM_ENTER"; 311 case MHI_CB_LPM_EXIT: 312 return "MHI_CB_LPM_EXIT"; 313 case MHI_CB_EE_RDDM: 314 return "MHI_CB_EE_RDDM"; 315 case MHI_CB_EE_MISSION_MODE: 316 return "MHI_CB_EE_MISSION_MODE"; 317 case MHI_CB_SYS_ERROR: 318 return "MHI_CB_SYS_ERROR"; 319 case MHI_CB_FATAL_ERROR: 320 return "MHI_CB_FATAL_ERROR"; 321 case MHI_CB_BW_REQ: 322 return "MHI_CB_BW_REQ"; 323 default: 324 return "UNKNOWN"; 325 } 326 }; 327 328 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 329 enum mhi_callback cb) 330 { 331 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 332 333 ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n", 334 ath11k_mhi_op_callback_to_str(cb)); 335 336 switch (cb) { 337 case MHI_CB_SYS_ERROR: 338 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 339 break; 340 case MHI_CB_EE_RDDM: 341 if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) 342 queue_work(ab->workqueue_aux, &ab->reset_work); 343 break; 344 default: 345 break; 346 } 347 } 348 349 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 350 void __iomem *addr, 351 u32 *out) 352 { 353 *out = readl(addr); 354 355 return 0; 356 } 357 358 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 359 void __iomem *addr, 360 u32 val) 361 { 362 writel(val, addr); 363 } 364 365 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 366 { 367 #if defined(__linux__) 368 struct device_node *np; 369 struct resource res; 370 int ret; 371 372 np = of_find_node_by_type(NULL, "memory"); 373 if (!np) 374 return -ENOENT; 375 376 ret = of_address_to_resource(np, 0, &res); 377 of_node_put(np); 378 if (ret) 379 return ret; 380 381 mhi_ctrl->iova_start = res.start + 0x1000000; 382 mhi_ctrl->iova_stop = res.end; 383 384 return 0; 385 #elif defined(__FreeBSD__) 386 return -ENOENT; 387 #endif 388 } 389 390 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 391 { 392 struct ath11k_base *ab = ab_pci->ab; 393 struct mhi_controller *mhi_ctrl; 394 struct mhi_controller_config *ath11k_mhi_config; 395 int ret; 396 397 mhi_ctrl = mhi_alloc_controller(); 398 if (!mhi_ctrl) 399 return -ENOMEM; 400 401 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 402 ab_pci->amss_path, 403 sizeof(ab_pci->amss_path)); 404 405 ab_pci->mhi_ctrl = mhi_ctrl; 406 mhi_ctrl->cntrl_dev = ab->dev; 407 mhi_ctrl->fw_image = ab_pci->amss_path; 408 mhi_ctrl->regs = ab->mem; 409 mhi_ctrl->reg_len = ab->mem_len; 410 411 ret = ath11k_mhi_get_msi(ab_pci); 412 if (ret) { 413 ath11k_err(ab, "failed to get msi for mhi\n"); 414 goto free_controller; 415 } 416 417 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 418 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 419 420 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 421 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 422 if (ret < 0) 423 goto free_controller; 424 } else { 425 mhi_ctrl->iova_start = 0; 426 mhi_ctrl->iova_stop = 0xFFFFFFFF; 427 } 428 429 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE; 430 mhi_ctrl->sbl_size = SZ_512K; 431 mhi_ctrl->seg_len = SZ_512K; 432 mhi_ctrl->fbc_download = true; 433 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 434 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 435 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 436 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 437 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 438 439 switch (ab->hw_rev) { 440 case ATH11K_HW_QCN9074_HW10: 441 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 442 break; 443 case ATH11K_HW_QCA6390_HW20: 444 case ATH11K_HW_WCN6855_HW20: 445 case ATH11K_HW_WCN6855_HW21: 446 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 447 break; 448 default: 449 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 450 ab->hw_rev); 451 ret = -EINVAL; 452 goto free_controller; 453 } 454 455 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 456 if (ret) { 457 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 458 goto free_controller; 459 } 460 461 return 0; 462 463 free_controller: 464 mhi_free_controller(mhi_ctrl); 465 ab_pci->mhi_ctrl = NULL; 466 return ret; 467 } 468 469 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 470 { 471 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 472 473 mhi_unregister_controller(mhi_ctrl); 474 kfree(mhi_ctrl->irq); 475 mhi_free_controller(mhi_ctrl); 476 } 477 478 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 479 { 480 struct ath11k_base *ab = ab_pci->ab; 481 int ret; 482 483 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 484 485 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 486 if (ret) { 487 ath11k_warn(ab, "failed to prepare mhi: %d", ret); 488 return ret; 489 } 490 491 ret = mhi_sync_power_up(ab_pci->mhi_ctrl); 492 if (ret) { 493 ath11k_warn(ab, "failed to power up mhi: %d", ret); 494 return ret; 495 } 496 497 return 0; 498 } 499 500 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 501 { 502 mhi_power_down(ab_pci->mhi_ctrl, true); 503 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 504 } 505 506 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 507 { 508 struct ath11k_base *ab = ab_pci->ab; 509 int ret; 510 511 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 512 if (ret) { 513 ath11k_warn(ab, "failed to suspend mhi: %d", ret); 514 return ret; 515 } 516 517 return 0; 518 } 519 520 int ath11k_mhi_resume(struct ath11k_pci *ab_pci) 521 { 522 struct ath11k_base *ab = ab_pci->ab; 523 int ret; 524 525 /* Do force MHI resume as some devices like QCA6390, WCN6855 526 * are not in M3 state but they are functional. So just ignore 527 * the MHI state while resuming. 528 */ 529 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 530 if (ret) { 531 ath11k_warn(ab, "failed to resume mhi: %d", ret); 532 return ret; 533 } 534 535 return 0; 536 } 537