1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HW_H 7 #define ATH11K_HW_H 8 9 #include "hal.h" 10 #include "wmi.h" 11 12 /* Target configuration defines */ 13 14 /* Num VDEVS per radio */ 15 #define TARGET_NUM_VDEVS(ab) (ab->hw_params.num_vdevs) 16 17 #define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab)) 18 19 /* Num of peers for Single Radio mode */ 20 #define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab)) 21 22 /* Num of peers for DBS */ 23 #define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab)) 24 25 /* Num of peers for DBS_SBS */ 26 #define TARGET_NUM_PEERS_DBS_SBS(ab) (3 * TARGET_NUM_PEERS_PDEV(ab)) 27 28 /* Max num of stations (per radio) */ 29 #define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers) 30 31 #define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab) 32 #define TARGET_NUM_PEER_KEYS 2 33 #define TARGET_NUM_TIDS(ab, x) (2 * TARGET_NUM_PEERS(ab, x) + \ 34 4 * TARGET_NUM_VDEVS(ab) + 8) 35 36 #define TARGET_AST_SKID_LIMIT 16 37 #define TARGET_NUM_OFFLD_PEERS 4 38 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 39 40 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 41 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 42 #define TARGET_RX_TIMEOUT_LO_PRI 100 43 #define TARGET_RX_TIMEOUT_HI_PRI 40 44 45 #define TARGET_DECAP_MODE_RAW 0 46 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 47 #define TARGET_DECAP_MODE_ETH 2 48 49 #define TARGET_SCAN_MAX_PENDING_REQS 4 50 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 51 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 52 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 53 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 54 #define TARGET_NUM_MCAST_GROUPS 12 55 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 56 #define TARGET_MCAST2UCAST_MODE 2 57 #define TARGET_TX_DBG_LOG_SIZE 1024 58 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 59 #define TARGET_VOW_CONFIG 0 60 #define TARGET_NUM_MSDU_DESC (2500) 61 #define TARGET_MAX_FRAG_ENTRIES 6 62 #define TARGET_MAX_BCN_OFFLD 16 63 #define TARGET_NUM_WDS_ENTRIES 32 64 #define TARGET_DMA_BURST_SIZE 1 65 #define TARGET_RX_BATCHMODE 1 66 67 #define ATH11K_HW_MAX_QUEUES 4 68 #define ATH11K_QUEUE_LEN 4096 69 70 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 71 72 #define ATH11K_FW_DIR "ath11k" 73 74 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD" 75 #define ATH11K_BOARD_API2_FILE "board-2.bin" 76 #define ATH11K_DEFAULT_BOARD_FILE "board.bin" 77 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin" 78 #define ATH11K_AMSS_FILE "amss.bin" 79 #define ATH11K_M3_FILE "m3.bin" 80 #define ATH11K_REGDB_FILE_NAME "regdb.bin" 81 82 enum ath11k_hw_rate_cck { 83 ATH11K_HW_RATE_CCK_LP_11M = 0, 84 ATH11K_HW_RATE_CCK_LP_5_5M, 85 ATH11K_HW_RATE_CCK_LP_2M, 86 ATH11K_HW_RATE_CCK_LP_1M, 87 ATH11K_HW_RATE_CCK_SP_11M, 88 ATH11K_HW_RATE_CCK_SP_5_5M, 89 ATH11K_HW_RATE_CCK_SP_2M, 90 }; 91 92 enum ath11k_hw_rate_ofdm { 93 ATH11K_HW_RATE_OFDM_48M = 0, 94 ATH11K_HW_RATE_OFDM_24M, 95 ATH11K_HW_RATE_OFDM_12M, 96 ATH11K_HW_RATE_OFDM_6M, 97 ATH11K_HW_RATE_OFDM_54M, 98 ATH11K_HW_RATE_OFDM_36M, 99 ATH11K_HW_RATE_OFDM_18M, 100 ATH11K_HW_RATE_OFDM_9M, 101 }; 102 103 enum ath11k_bus { 104 ATH11K_BUS_AHB, 105 ATH11K_BUS_PCI, 106 }; 107 108 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11 109 110 struct hal_rx_desc; 111 struct hal_tcl_data_cmd; 112 113 struct ath11k_hw_ring_mask { 114 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 115 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 116 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 117 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 118 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 119 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 120 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 121 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 122 }; 123 124 struct ath11k_hw_hal_params { 125 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 126 }; 127 128 struct ath11k_hw_params { 129 const char *name; 130 u16 hw_rev; 131 u8 max_radios; 132 u32 bdf_addr; 133 134 struct { 135 const char *dir; 136 size_t board_size; 137 size_t cal_offset; 138 } fw; 139 140 const struct ath11k_hw_ops *hw_ops; 141 const struct ath11k_hw_ring_mask *ring_mask; 142 143 bool internal_sleep_clock; 144 145 const struct ath11k_hw_regs *regs; 146 u32 qmi_service_ins_id; 147 const struct ce_attr *host_ce_config; 148 u32 ce_count; 149 const struct ce_pipe_config *target_ce_config; 150 u32 target_ce_count; 151 const struct service_to_pipe *svc_to_ce_map; 152 u32 svc_to_ce_map_len; 153 154 bool single_pdev_only; 155 u32 rfkill_pin; 156 u32 rfkill_cfg; 157 u32 rfkill_on_level; 158 159 bool rxdma1_enable; 160 int num_rxmda_per_pdev; 161 bool rx_mac_buf_ring; 162 bool vdev_start_delay; 163 bool htt_peer_map_v2; 164 165 struct { 166 u8 fft_sz; 167 u8 fft_pad_sz; 168 u8 summary_pad_sz; 169 u8 fft_hdr_len; 170 u16 max_fft_bins; 171 } spectral; 172 173 u16 interface_modes; 174 bool supports_monitor; 175 bool full_monitor_mode; 176 bool supports_shadow_regs; 177 bool idle_ps; 178 bool supports_sta_ps; 179 bool cold_boot_calib; 180 int fw_mem_mode; 181 u32 num_vdevs; 182 u32 num_peers; 183 bool supports_suspend; 184 u32 hal_desc_sz; 185 bool supports_regdb; 186 bool fix_l1ss; 187 bool credit_flow; 188 u8 max_tx_ring; 189 const struct ath11k_hw_hal_params *hal_params; 190 bool supports_dynamic_smps_6ghz; 191 bool alloc_cacheable_memory; 192 bool wakeup_mhi; 193 bool supports_rssi_stats; 194 bool fw_wmi_diag_event; 195 }; 196 197 struct ath11k_hw_ops { 198 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 199 void (*wmi_init_config)(struct ath11k_base *ab, 200 struct target_resource_config *config); 201 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id); 202 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id); 203 void (*tx_mesh_enable)(struct ath11k_base *ab, 204 struct hal_tcl_data_cmd *tcl_cmd); 205 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc); 206 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc); 207 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 208 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc); 209 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc); 210 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc); 211 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc); 212 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc); 213 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc); 214 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc); 215 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc); 216 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc); 217 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc); 218 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc); 219 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc); 220 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc); 221 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc); 222 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc); 223 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc); 224 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc); 225 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc); 226 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc, 227 struct hal_rx_desc *ldesc); 228 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 229 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 230 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 231 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc); 232 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 233 void (*reo_setup)(struct ath11k_base *ab); 234 u16 (*mpdu_info_get_peerid)(u8 *tlv_data); 235 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); 236 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); 237 }; 238 239 extern const struct ath11k_hw_ops ipq8074_ops; 240 extern const struct ath11k_hw_ops ipq6018_ops; 241 extern const struct ath11k_hw_ops qca6390_ops; 242 extern const struct ath11k_hw_ops qcn9074_ops; 243 extern const struct ath11k_hw_ops wcn6855_ops; 244 245 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074; 246 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390; 247 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074; 248 249 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074; 250 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390; 251 252 static inline 253 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw, 254 int pdev_idx) 255 { 256 if (hw->hw_ops->get_hw_mac_from_pdev_id) 257 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 258 259 return 0; 260 } 261 262 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw, 263 int mac_id) 264 { 265 if (hw->hw_ops->mac_id_to_pdev_id) 266 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 267 268 return 0; 269 } 270 271 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw, 272 int mac_id) 273 { 274 if (hw->hw_ops->mac_id_to_srng_id) 275 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 276 277 return 0; 278 } 279 280 struct ath11k_fw_ie { 281 __le32 id; 282 __le32 len; 283 u8 data[]; 284 }; 285 286 enum ath11k_bd_ie_board_type { 287 ATH11K_BD_IE_BOARD_NAME = 0, 288 ATH11K_BD_IE_BOARD_DATA = 1, 289 }; 290 291 enum ath11k_bd_ie_type { 292 /* contains sub IEs of enum ath11k_bd_ie_board_type */ 293 ATH11K_BD_IE_BOARD = 0, 294 ATH11K_BD_IE_BOARD_EXT = 1, 295 }; 296 297 struct ath11k_hw_regs { 298 u32 hal_tcl1_ring_base_lsb; 299 u32 hal_tcl1_ring_base_msb; 300 u32 hal_tcl1_ring_id; 301 u32 hal_tcl1_ring_misc; 302 u32 hal_tcl1_ring_tp_addr_lsb; 303 u32 hal_tcl1_ring_tp_addr_msb; 304 u32 hal_tcl1_ring_consumer_int_setup_ix0; 305 u32 hal_tcl1_ring_consumer_int_setup_ix1; 306 u32 hal_tcl1_ring_msi1_base_lsb; 307 u32 hal_tcl1_ring_msi1_base_msb; 308 u32 hal_tcl1_ring_msi1_data; 309 u32 hal_tcl2_ring_base_lsb; 310 u32 hal_tcl_ring_base_lsb; 311 312 u32 hal_tcl_status_ring_base_lsb; 313 314 u32 hal_reo1_ring_base_lsb; 315 u32 hal_reo1_ring_base_msb; 316 u32 hal_reo1_ring_id; 317 u32 hal_reo1_ring_misc; 318 u32 hal_reo1_ring_hp_addr_lsb; 319 u32 hal_reo1_ring_hp_addr_msb; 320 u32 hal_reo1_ring_producer_int_setup; 321 u32 hal_reo1_ring_msi1_base_lsb; 322 u32 hal_reo1_ring_msi1_base_msb; 323 u32 hal_reo1_ring_msi1_data; 324 u32 hal_reo2_ring_base_lsb; 325 u32 hal_reo1_aging_thresh_ix_0; 326 u32 hal_reo1_aging_thresh_ix_1; 327 u32 hal_reo1_aging_thresh_ix_2; 328 u32 hal_reo1_aging_thresh_ix_3; 329 330 u32 hal_reo1_ring_hp; 331 u32 hal_reo1_ring_tp; 332 u32 hal_reo2_ring_hp; 333 334 u32 hal_reo_tcl_ring_base_lsb; 335 u32 hal_reo_tcl_ring_hp; 336 337 u32 hal_reo_status_ring_base_lsb; 338 u32 hal_reo_status_hp; 339 340 u32 hal_seq_wcss_umac_ce0_src_reg; 341 u32 hal_seq_wcss_umac_ce0_dst_reg; 342 u32 hal_seq_wcss_umac_ce1_src_reg; 343 u32 hal_seq_wcss_umac_ce1_dst_reg; 344 345 u32 hal_wbm_idle_link_ring_base_lsb; 346 u32 hal_wbm_idle_link_ring_misc; 347 348 u32 hal_wbm_release_ring_base_lsb; 349 350 u32 hal_wbm0_release_ring_base_lsb; 351 u32 hal_wbm1_release_ring_base_lsb; 352 353 u32 pcie_qserdes_sysclk_en_sel; 354 u32 pcie_pcs_osc_dtct_config_base; 355 }; 356 357 extern const struct ath11k_hw_regs ipq8074_regs; 358 extern const struct ath11k_hw_regs qca6390_regs; 359 extern const struct ath11k_hw_regs qcn9074_regs; 360 extern const struct ath11k_hw_regs wcn6855_regs; 361 362 #endif 363