1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "core.h" 11 #include "ce.h" 12 #include "hif.h" 13 #include "hal.h" 14 #include "hw.h" 15 16 /* Map from pdev index to hw mac index */ 17 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 18 { 19 switch (pdev_idx) { 20 case 0: 21 return 0; 22 case 1: 23 return 2; 24 case 2: 25 return 1; 26 default: 27 return ATH11K_INVALID_HW_MAC_ID; 28 } 29 } 30 31 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 32 { 33 return pdev_idx; 34 } 35 36 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 37 struct hal_tcl_data_cmd *tcl_cmd) 38 { 39 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 40 true); 41 } 42 43 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 44 struct hal_tcl_data_cmd *tcl_cmd) 45 { 46 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 47 true); 48 } 49 50 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 51 struct hal_tcl_data_cmd *tcl_cmd) 52 { 53 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 54 true); 55 } 56 57 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 58 struct target_resource_config *config) 59 { 60 config->num_vdevs = 4; 61 config->num_peers = 16; 62 config->num_tids = 32; 63 64 config->num_offload_peers = 3; 65 config->num_offload_reorder_buffs = 3; 66 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 67 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 68 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 69 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 71 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 74 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 75 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 76 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 77 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 79 config->num_mcast_groups = 0; 80 config->num_mcast_table_elems = 0; 81 config->mcast2ucast_mode = 0; 82 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 83 config->num_wds_entries = 0; 84 config->dma_burst_size = 0; 85 config->rx_skip_defrag_timeout_dup_detection_check = 0; 86 config->vow_config = TARGET_VOW_CONFIG; 87 config->gtk_offload_max_vdev = 2; 88 config->num_msdu_desc = 0x400; 89 config->beacon_tx_offload_max_vdev = 2; 90 config->rx_batchmode = TARGET_RX_BATCHMODE; 91 92 config->peer_map_unmap_v2_support = 0; 93 config->use_pdev_id = 1; 94 config->max_frag_entries = 0xa; 95 config->num_tdls_vdevs = 0x1; 96 config->num_tdls_conn_table_entries = 8; 97 config->beacon_tx_offload_max_vdev = 0x2; 98 config->num_multicast_filter_entries = 0x20; 99 config->num_wow_filters = 0x16; 100 config->num_keep_alive_pattern = 0; 101 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 102 } 103 104 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 105 { 106 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 107 u32 val; 108 /* Each hash entry uses three bits to map to a particular ring. */ 109 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 110 HAL_HASH_ROUTING_RING_SW2 << 3 | 111 HAL_HASH_ROUTING_RING_SW3 << 6 | 112 HAL_HASH_ROUTING_RING_SW4 << 9 | 113 HAL_HASH_ROUTING_RING_SW1 << 12 | 114 HAL_HASH_ROUTING_RING_SW2 << 15 | 115 HAL_HASH_ROUTING_RING_SW3 << 18 | 116 HAL_HASH_ROUTING_RING_SW4 << 21; 117 118 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 119 120 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 121 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 122 HAL_SRNG_RING_ID_REO2SW1) | 123 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 125 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 126 127 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 128 HAL_DEFAULT_REO_TIMEOUT_USEC); 129 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 130 HAL_DEFAULT_REO_TIMEOUT_USEC); 131 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 132 HAL_DEFAULT_REO_TIMEOUT_USEC); 133 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 134 HAL_DEFAULT_REO_TIMEOUT_USEC); 135 136 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 137 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 138 ring_hash_map)); 139 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 140 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 141 ring_hash_map)); 142 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 143 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 144 ring_hash_map)); 145 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 146 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 147 ring_hash_map)); 148 } 149 150 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 151 struct target_resource_config *config) 152 { 153 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 154 155 if (ab->num_radios == 2) { 156 config->num_peers = TARGET_NUM_PEERS(ab, DBS); 157 config->num_tids = TARGET_NUM_TIDS(ab, DBS); 158 } else if (ab->num_radios == 3) { 159 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 160 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 161 } else { 162 /* Control should not reach here */ 163 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 164 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 165 } 166 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 167 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 168 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 169 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 170 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 171 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 173 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 176 177 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 178 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 179 else 180 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 181 182 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 183 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 184 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 186 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 187 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 188 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 189 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 190 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 191 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 192 config->rx_skip_defrag_timeout_dup_detection_check = 193 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 194 config->vow_config = TARGET_VOW_CONFIG; 195 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 196 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 197 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 198 config->rx_batchmode = TARGET_RX_BATCHMODE; 199 config->peer_map_unmap_v2_support = 1; 200 config->twt_ap_pdev_count = ab->num_radios; 201 config->twt_ap_sta_count = 1000; 202 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 203 } 204 205 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 206 int mac_id) 207 { 208 return mac_id; 209 } 210 211 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 212 int mac_id) 213 { 214 return 0; 215 } 216 217 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 218 int mac_id) 219 { 220 return 0; 221 } 222 223 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 224 int mac_id) 225 { 226 return mac_id; 227 } 228 229 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 230 { 231 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 232 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 233 } 234 235 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 236 { 237 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 238 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 239 } 240 241 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 242 { 243 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 244 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 245 } 246 247 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 248 { 249 return desc->u.ipq8074.hdr_status; 250 } 251 252 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 253 { 254 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 255 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 256 } 257 258 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 259 { 260 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 261 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 262 } 263 264 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 265 { 266 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 267 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 268 } 269 270 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 271 { 272 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 273 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 274 } 275 276 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 277 { 278 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 279 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 280 } 281 282 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 283 { 284 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 285 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 286 } 287 288 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 289 { 290 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 291 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 292 } 293 294 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 295 { 296 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 297 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 298 } 299 300 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 301 { 302 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 303 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 304 } 305 306 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 307 { 308 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 309 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 310 } 311 312 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 313 { 314 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 315 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 316 } 317 318 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 319 { 320 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 321 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 322 } 323 324 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 325 { 326 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 327 } 328 329 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 330 { 331 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 332 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 333 } 334 335 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 336 { 337 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 338 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 339 } 340 341 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 342 { 343 return FIELD_GET(RX_MPDU_START_INFO2_TID, 344 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 345 } 346 347 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 348 { 349 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 350 } 351 352 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 353 struct hal_rx_desc *ldesc) 354 { 355 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 356 sizeof(struct rx_msdu_end_ipq8074)); 357 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 358 sizeof(struct rx_attention)); 359 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 360 sizeof(struct rx_mpdu_end)); 361 } 362 363 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 364 { 365 return FIELD_GET(HAL_TLV_HDR_TAG, 366 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 367 } 368 369 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 370 { 371 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 372 } 373 374 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 375 { 376 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 377 378 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 379 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 380 381 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 382 } 383 384 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 385 { 386 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 387 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 388 } 389 390 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 391 { 392 return desc->u.ipq8074.mpdu_start.addr2; 393 } 394 395 static 396 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 397 { 398 return &desc->u.ipq8074.attention; 399 } 400 401 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 402 { 403 return &desc->u.ipq8074.msdu_payload[0]; 404 } 405 406 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 407 { 408 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 409 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 410 } 411 412 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 413 { 414 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 415 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 416 } 417 418 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 419 { 420 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 421 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 422 } 423 424 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 425 { 426 return desc->u.qcn9074.hdr_status; 427 } 428 429 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 430 { 431 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 432 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 433 } 434 435 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 436 { 437 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 438 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 439 } 440 441 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 442 { 443 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 444 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 445 } 446 447 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 448 { 449 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 450 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 451 } 452 453 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 454 { 455 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 456 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 457 } 458 459 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 460 { 461 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 462 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 463 } 464 465 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 466 { 467 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 468 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 469 } 470 471 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 472 { 473 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 474 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 475 } 476 477 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 478 { 479 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 480 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 481 } 482 483 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 484 { 485 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 486 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 487 } 488 489 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 490 { 491 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 492 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 493 } 494 495 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 496 { 497 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 498 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 499 } 500 501 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 502 { 503 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 504 } 505 506 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 507 { 508 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 509 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 510 } 511 512 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 513 { 514 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 515 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 516 } 517 518 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 519 { 520 return FIELD_GET(RX_MPDU_START_INFO9_TID, 521 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 522 } 523 524 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 525 { 526 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 527 } 528 529 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 530 struct hal_rx_desc *ldesc) 531 { 532 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 533 sizeof(struct rx_msdu_end_qcn9074)); 534 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 535 sizeof(struct rx_attention)); 536 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 537 sizeof(struct rx_mpdu_end)); 538 } 539 540 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 541 { 542 return FIELD_GET(HAL_TLV_HDR_TAG, 543 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 544 } 545 546 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 547 { 548 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 549 } 550 551 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 552 { 553 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 554 555 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 556 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 557 558 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 559 } 560 561 static 562 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 563 { 564 return &desc->u.qcn9074.attention; 565 } 566 567 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 568 { 569 return &desc->u.qcn9074.msdu_payload[0]; 570 } 571 572 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 573 { 574 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 575 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 576 } 577 578 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 579 { 580 return desc->u.qcn9074.mpdu_start.addr2; 581 } 582 583 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 584 { 585 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 586 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 587 } 588 589 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 590 { 591 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 592 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 593 } 594 595 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 596 { 597 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 598 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 599 } 600 601 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 602 { 603 return desc->u.wcn6855.hdr_status; 604 } 605 606 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 607 { 608 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 609 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 610 } 611 612 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 613 { 614 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 615 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 616 } 617 618 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 619 { 620 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 621 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 622 } 623 624 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 625 { 626 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 627 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 628 } 629 630 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 631 { 632 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 633 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 634 } 635 636 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 637 { 638 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 639 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 640 } 641 642 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 643 { 644 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 645 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 646 } 647 648 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 649 { 650 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 651 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 652 } 653 654 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 655 { 656 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 657 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 658 } 659 660 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 661 { 662 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 663 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 664 } 665 666 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 667 { 668 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 669 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 670 } 671 672 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 673 { 674 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 675 } 676 677 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 678 { 679 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 680 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 681 } 682 683 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 684 { 685 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 686 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 687 } 688 689 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 690 { 691 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 692 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 693 } 694 695 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 696 { 697 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 698 } 699 700 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 701 struct hal_rx_desc *ldesc) 702 { 703 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 704 sizeof(struct rx_msdu_end_wcn6855)); 705 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 706 sizeof(struct rx_attention)); 707 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 708 sizeof(struct rx_mpdu_end)); 709 } 710 711 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 712 { 713 return FIELD_GET(HAL_TLV_HDR_TAG, 714 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 715 } 716 717 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 718 { 719 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 720 } 721 722 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 723 { 724 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 725 726 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 727 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 728 729 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 730 } 731 732 static 733 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 734 { 735 return &desc->u.wcn6855.attention; 736 } 737 738 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 739 { 740 return &desc->u.wcn6855.msdu_payload[0]; 741 } 742 743 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 744 { 745 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 746 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 747 } 748 749 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 750 { 751 return desc->u.wcn6855.mpdu_start.addr2; 752 } 753 754 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 755 { 756 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 757 u32 val; 758 /* Each hash entry uses four bits to map to a particular ring. */ 759 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 760 HAL_HASH_ROUTING_RING_SW2 << 4 | 761 HAL_HASH_ROUTING_RING_SW3 << 8 | 762 HAL_HASH_ROUTING_RING_SW4 << 12 | 763 HAL_HASH_ROUTING_RING_SW1 << 16 | 764 HAL_HASH_ROUTING_RING_SW2 << 20 | 765 HAL_HASH_ROUTING_RING_SW3 << 24 | 766 HAL_HASH_ROUTING_RING_SW4 << 28; 767 768 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 769 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 770 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 771 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 772 773 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL); 774 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 775 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 776 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val); 777 778 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 779 HAL_DEFAULT_REO_TIMEOUT_USEC); 780 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 781 HAL_DEFAULT_REO_TIMEOUT_USEC); 782 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 783 HAL_DEFAULT_REO_TIMEOUT_USEC); 784 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 785 HAL_DEFAULT_REO_TIMEOUT_USEC); 786 787 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 788 ring_hash_map); 789 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 790 ring_hash_map); 791 } 792 793 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 794 { 795 u16 peer_id = 0; 796 struct hal_rx_mpdu_info *mpdu_info = 797 (struct hal_rx_mpdu_info *)tlv_data; 798 799 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 800 __le32_to_cpu(mpdu_info->info0)); 801 802 return peer_id; 803 } 804 805 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 806 { 807 u16 peer_id = 0; 808 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 809 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 810 811 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 812 __le32_to_cpu(mpdu_info->info0)); 813 return peer_id; 814 } 815 816 const struct ath11k_hw_ops ipq8074_ops = { 817 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 818 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 819 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 820 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 821 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 822 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 823 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 824 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 825 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 826 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 827 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 828 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 829 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 830 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 831 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 832 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 833 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 834 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 835 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 836 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 837 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 838 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 839 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 840 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 841 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 842 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 843 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 844 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 845 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 846 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 847 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 848 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 849 .reo_setup = ath11k_hw_ipq8074_reo_setup, 850 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 851 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 852 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 853 }; 854 855 const struct ath11k_hw_ops ipq6018_ops = { 856 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 857 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 858 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 859 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 860 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 861 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 862 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 863 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 864 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 865 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 866 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 867 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 868 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 869 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 870 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 871 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 872 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 873 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 874 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 875 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 876 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 877 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 878 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 879 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 880 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 881 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 882 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 883 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 884 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 885 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 886 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 887 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 888 .reo_setup = ath11k_hw_ipq8074_reo_setup, 889 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 890 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 891 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 892 }; 893 894 const struct ath11k_hw_ops qca6390_ops = { 895 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 896 .wmi_init_config = ath11k_init_wmi_config_qca6390, 897 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 898 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 899 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 900 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 901 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 902 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 903 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 904 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 905 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 906 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 907 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 908 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 909 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 910 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 911 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 912 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 913 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 914 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 915 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 916 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 917 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 918 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 919 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 920 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 921 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 922 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 923 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 924 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 925 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 926 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 927 .reo_setup = ath11k_hw_ipq8074_reo_setup, 928 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 929 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 930 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 931 }; 932 933 const struct ath11k_hw_ops qcn9074_ops = { 934 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 935 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 936 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 937 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 938 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 939 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 940 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 941 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 942 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 943 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 944 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 945 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 946 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 947 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 948 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 949 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 950 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 951 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 952 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 953 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 954 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 955 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 956 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 957 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 958 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 959 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 960 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 961 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 962 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 963 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 964 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 965 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 966 .reo_setup = ath11k_hw_ipq8074_reo_setup, 967 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 968 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 969 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 970 }; 971 972 const struct ath11k_hw_ops wcn6855_ops = { 973 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 974 .wmi_init_config = ath11k_init_wmi_config_qca6390, 975 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 976 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 977 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 978 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 979 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 980 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 981 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 982 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 983 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 984 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 985 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 986 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 987 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 988 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 989 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 990 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 991 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 992 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 993 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 994 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 995 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 996 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 997 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 998 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 999 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1000 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1001 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1002 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1003 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 1004 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1005 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 1006 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 1007 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 1008 }; 1009 1010 #define ATH11K_TX_RING_MASK_0 0x1 1011 #define ATH11K_TX_RING_MASK_1 0x2 1012 #define ATH11K_TX_RING_MASK_2 0x4 1013 1014 #define ATH11K_RX_RING_MASK_0 0x1 1015 #define ATH11K_RX_RING_MASK_1 0x2 1016 #define ATH11K_RX_RING_MASK_2 0x4 1017 #define ATH11K_RX_RING_MASK_3 0x8 1018 1019 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1020 1021 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1022 1023 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1024 1025 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1026 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1027 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1028 1029 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1030 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1031 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1032 1033 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1034 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1035 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1036 1037 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1038 .tx = { 1039 ATH11K_TX_RING_MASK_0, 1040 ATH11K_TX_RING_MASK_1, 1041 ATH11K_TX_RING_MASK_2, 1042 }, 1043 .rx_mon_status = { 1044 0, 0, 0, 0, 1045 ATH11K_RX_MON_STATUS_RING_MASK_0, 1046 ATH11K_RX_MON_STATUS_RING_MASK_1, 1047 ATH11K_RX_MON_STATUS_RING_MASK_2, 1048 }, 1049 .rx = { 1050 0, 0, 0, 0, 0, 0, 0, 1051 ATH11K_RX_RING_MASK_0, 1052 ATH11K_RX_RING_MASK_1, 1053 ATH11K_RX_RING_MASK_2, 1054 ATH11K_RX_RING_MASK_3, 1055 }, 1056 .rx_err = { 1057 ATH11K_RX_ERR_RING_MASK_0, 1058 }, 1059 .rx_wbm_rel = { 1060 ATH11K_RX_WBM_REL_RING_MASK_0, 1061 }, 1062 .reo_status = { 1063 ATH11K_REO_STATUS_RING_MASK_0, 1064 }, 1065 .rxdma2host = { 1066 ATH11K_RXDMA2HOST_RING_MASK_0, 1067 ATH11K_RXDMA2HOST_RING_MASK_1, 1068 ATH11K_RXDMA2HOST_RING_MASK_2, 1069 }, 1070 .host2rxdma = { 1071 ATH11K_HOST2RXDMA_RING_MASK_0, 1072 ATH11K_HOST2RXDMA_RING_MASK_1, 1073 ATH11K_HOST2RXDMA_RING_MASK_2, 1074 }, 1075 }; 1076 1077 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1078 .tx = { 1079 ATH11K_TX_RING_MASK_0, 1080 }, 1081 .rx_mon_status = { 1082 0, 0, 0, 0, 1083 ATH11K_RX_MON_STATUS_RING_MASK_0, 1084 ATH11K_RX_MON_STATUS_RING_MASK_1, 1085 ATH11K_RX_MON_STATUS_RING_MASK_2, 1086 }, 1087 .rx = { 1088 0, 0, 0, 0, 0, 0, 0, 1089 ATH11K_RX_RING_MASK_0, 1090 ATH11K_RX_RING_MASK_1, 1091 ATH11K_RX_RING_MASK_2, 1092 ATH11K_RX_RING_MASK_3, 1093 }, 1094 .rx_err = { 1095 ATH11K_RX_ERR_RING_MASK_0, 1096 }, 1097 .rx_wbm_rel = { 1098 ATH11K_RX_WBM_REL_RING_MASK_0, 1099 }, 1100 .reo_status = { 1101 ATH11K_REO_STATUS_RING_MASK_0, 1102 }, 1103 .rxdma2host = { 1104 ATH11K_RXDMA2HOST_RING_MASK_0, 1105 ATH11K_RXDMA2HOST_RING_MASK_1, 1106 ATH11K_RXDMA2HOST_RING_MASK_2, 1107 }, 1108 .host2rxdma = { 1109 }, 1110 }; 1111 1112 /* Target firmware's Copy Engine configuration. */ 1113 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1114 /* CE0: host->target HTC control and raw streams */ 1115 { 1116 .pipenum = __cpu_to_le32(0), 1117 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1118 .nentries = __cpu_to_le32(32), 1119 .nbytes_max = __cpu_to_le32(2048), 1120 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1121 .reserved = __cpu_to_le32(0), 1122 }, 1123 1124 /* CE1: target->host HTT + HTC control */ 1125 { 1126 .pipenum = __cpu_to_le32(1), 1127 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1128 .nentries = __cpu_to_le32(32), 1129 .nbytes_max = __cpu_to_le32(2048), 1130 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1131 .reserved = __cpu_to_le32(0), 1132 }, 1133 1134 /* CE2: target->host WMI */ 1135 { 1136 .pipenum = __cpu_to_le32(2), 1137 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1138 .nentries = __cpu_to_le32(32), 1139 .nbytes_max = __cpu_to_le32(2048), 1140 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1141 .reserved = __cpu_to_le32(0), 1142 }, 1143 1144 /* CE3: host->target WMI */ 1145 { 1146 .pipenum = __cpu_to_le32(3), 1147 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1148 .nentries = __cpu_to_le32(32), 1149 .nbytes_max = __cpu_to_le32(2048), 1150 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1151 .reserved = __cpu_to_le32(0), 1152 }, 1153 1154 /* CE4: host->target HTT */ 1155 { 1156 .pipenum = __cpu_to_le32(4), 1157 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1158 .nentries = __cpu_to_le32(256), 1159 .nbytes_max = __cpu_to_le32(256), 1160 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1161 .reserved = __cpu_to_le32(0), 1162 }, 1163 1164 /* CE5: target->host Pktlog */ 1165 { 1166 .pipenum = __cpu_to_le32(5), 1167 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1168 .nentries = __cpu_to_le32(32), 1169 .nbytes_max = __cpu_to_le32(2048), 1170 .flags = __cpu_to_le32(0), 1171 .reserved = __cpu_to_le32(0), 1172 }, 1173 1174 /* CE6: Reserved for target autonomous hif_memcpy */ 1175 { 1176 .pipenum = __cpu_to_le32(6), 1177 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1178 .nentries = __cpu_to_le32(32), 1179 .nbytes_max = __cpu_to_le32(65535), 1180 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1181 .reserved = __cpu_to_le32(0), 1182 }, 1183 1184 /* CE7 used only by Host */ 1185 { 1186 .pipenum = __cpu_to_le32(7), 1187 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1188 .nentries = __cpu_to_le32(32), 1189 .nbytes_max = __cpu_to_le32(2048), 1190 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1191 .reserved = __cpu_to_le32(0), 1192 }, 1193 1194 /* CE8 target->host used only by IPA */ 1195 { 1196 .pipenum = __cpu_to_le32(8), 1197 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1198 .nentries = __cpu_to_le32(32), 1199 .nbytes_max = __cpu_to_le32(65535), 1200 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1201 .reserved = __cpu_to_le32(0), 1202 }, 1203 1204 /* CE9 host->target HTT */ 1205 { 1206 .pipenum = __cpu_to_le32(9), 1207 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1208 .nentries = __cpu_to_le32(32), 1209 .nbytes_max = __cpu_to_le32(2048), 1210 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1211 .reserved = __cpu_to_le32(0), 1212 }, 1213 1214 /* CE10 target->host HTT */ 1215 { 1216 .pipenum = __cpu_to_le32(10), 1217 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1218 .nentries = __cpu_to_le32(0), 1219 .nbytes_max = __cpu_to_le32(0), 1220 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1221 .reserved = __cpu_to_le32(0), 1222 }, 1223 1224 /* CE11 Not used */ 1225 }; 1226 1227 /* Map from service/endpoint to Copy Engine. 1228 * This table is derived from the CE_PCI TABLE, above. 1229 * It is passed to the Target at startup for use by firmware. 1230 */ 1231 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1232 { 1233 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1234 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1235 .pipenum = __cpu_to_le32(3), 1236 }, 1237 { 1238 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1239 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1240 .pipenum = __cpu_to_le32(2), 1241 }, 1242 { 1243 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1244 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1245 .pipenum = __cpu_to_le32(3), 1246 }, 1247 { 1248 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1249 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1250 .pipenum = __cpu_to_le32(2), 1251 }, 1252 { 1253 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1254 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1255 .pipenum = __cpu_to_le32(3), 1256 }, 1257 { 1258 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1259 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1260 .pipenum = __cpu_to_le32(2), 1261 }, 1262 { 1263 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1264 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1265 .pipenum = __cpu_to_le32(3), 1266 }, 1267 { 1268 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1269 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1270 .pipenum = __cpu_to_le32(2), 1271 }, 1272 { 1273 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1274 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1275 .pipenum = __cpu_to_le32(3), 1276 }, 1277 { 1278 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1279 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1280 .pipenum = __cpu_to_le32(2), 1281 }, 1282 { 1283 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1284 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1285 .pipenum = __cpu_to_le32(7), 1286 }, 1287 { 1288 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1289 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1290 .pipenum = __cpu_to_le32(2), 1291 }, 1292 { 1293 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1294 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1295 .pipenum = __cpu_to_le32(9), 1296 }, 1297 { 1298 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1299 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1300 .pipenum = __cpu_to_le32(2), 1301 }, 1302 { 1303 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1304 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1305 .pipenum = __cpu_to_le32(0), 1306 }, 1307 { 1308 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1309 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1310 .pipenum = __cpu_to_le32(1), 1311 }, 1312 { /* not used */ 1313 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1314 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1315 .pipenum = __cpu_to_le32(0), 1316 }, 1317 { /* not used */ 1318 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1319 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1320 .pipenum = __cpu_to_le32(1), 1321 }, 1322 { 1323 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1324 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1325 .pipenum = __cpu_to_le32(4), 1326 }, 1327 { 1328 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1329 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1330 .pipenum = __cpu_to_le32(1), 1331 }, 1332 { 1333 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1334 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1335 .pipenum = __cpu_to_le32(5), 1336 }, 1337 1338 /* (Additions here) */ 1339 1340 { /* terminator entry */ } 1341 }; 1342 1343 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1344 { 1345 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1346 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1347 .pipenum = __cpu_to_le32(3), 1348 }, 1349 { 1350 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1351 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1352 .pipenum = __cpu_to_le32(2), 1353 }, 1354 { 1355 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1356 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1357 .pipenum = __cpu_to_le32(3), 1358 }, 1359 { 1360 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1361 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1362 .pipenum = __cpu_to_le32(2), 1363 }, 1364 { 1365 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1366 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1367 .pipenum = __cpu_to_le32(3), 1368 }, 1369 { 1370 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1371 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1372 .pipenum = __cpu_to_le32(2), 1373 }, 1374 { 1375 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1376 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1377 .pipenum = __cpu_to_le32(3), 1378 }, 1379 { 1380 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1381 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1382 .pipenum = __cpu_to_le32(2), 1383 }, 1384 { 1385 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1386 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1387 .pipenum = __cpu_to_le32(3), 1388 }, 1389 { 1390 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1391 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1392 .pipenum = __cpu_to_le32(2), 1393 }, 1394 { 1395 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1396 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1397 .pipenum = __cpu_to_le32(7), 1398 }, 1399 { 1400 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1401 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1402 .pipenum = __cpu_to_le32(2), 1403 }, 1404 { 1405 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1406 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1407 .pipenum = __cpu_to_le32(0), 1408 }, 1409 { 1410 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1411 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1412 .pipenum = __cpu_to_le32(1), 1413 }, 1414 { /* not used */ 1415 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1416 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1417 .pipenum = __cpu_to_le32(0), 1418 }, 1419 { /* not used */ 1420 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1421 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1422 .pipenum = __cpu_to_le32(1), 1423 }, 1424 { 1425 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1426 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1427 .pipenum = __cpu_to_le32(4), 1428 }, 1429 { 1430 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1431 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1432 .pipenum = __cpu_to_le32(1), 1433 }, 1434 { 1435 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1436 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1437 .pipenum = __cpu_to_le32(5), 1438 }, 1439 1440 /* (Additions here) */ 1441 1442 { /* terminator entry */ } 1443 }; 1444 1445 /* Target firmware's Copy Engine configuration. */ 1446 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1447 /* CE0: host->target HTC control and raw streams */ 1448 { 1449 .pipenum = __cpu_to_le32(0), 1450 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1451 .nentries = __cpu_to_le32(32), 1452 .nbytes_max = __cpu_to_le32(2048), 1453 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1454 .reserved = __cpu_to_le32(0), 1455 }, 1456 1457 /* CE1: target->host HTT + HTC control */ 1458 { 1459 .pipenum = __cpu_to_le32(1), 1460 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1461 .nentries = __cpu_to_le32(32), 1462 .nbytes_max = __cpu_to_le32(2048), 1463 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1464 .reserved = __cpu_to_le32(0), 1465 }, 1466 1467 /* CE2: target->host WMI */ 1468 { 1469 .pipenum = __cpu_to_le32(2), 1470 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1471 .nentries = __cpu_to_le32(32), 1472 .nbytes_max = __cpu_to_le32(2048), 1473 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1474 .reserved = __cpu_to_le32(0), 1475 }, 1476 1477 /* CE3: host->target WMI */ 1478 { 1479 .pipenum = __cpu_to_le32(3), 1480 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1481 .nentries = __cpu_to_le32(32), 1482 .nbytes_max = __cpu_to_le32(2048), 1483 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1484 .reserved = __cpu_to_le32(0), 1485 }, 1486 1487 /* CE4: host->target HTT */ 1488 { 1489 .pipenum = __cpu_to_le32(4), 1490 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1491 .nentries = __cpu_to_le32(256), 1492 .nbytes_max = __cpu_to_le32(256), 1493 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1494 .reserved = __cpu_to_le32(0), 1495 }, 1496 1497 /* CE5: target->host Pktlog */ 1498 { 1499 .pipenum = __cpu_to_le32(5), 1500 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1501 .nentries = __cpu_to_le32(32), 1502 .nbytes_max = __cpu_to_le32(2048), 1503 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1504 .reserved = __cpu_to_le32(0), 1505 }, 1506 1507 /* CE6: Reserved for target autonomous hif_memcpy */ 1508 { 1509 .pipenum = __cpu_to_le32(6), 1510 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1511 .nentries = __cpu_to_le32(32), 1512 .nbytes_max = __cpu_to_le32(16384), 1513 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1514 .reserved = __cpu_to_le32(0), 1515 }, 1516 1517 /* CE7 used only by Host */ 1518 { 1519 .pipenum = __cpu_to_le32(7), 1520 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1521 .nentries = __cpu_to_le32(0), 1522 .nbytes_max = __cpu_to_le32(0), 1523 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1524 .reserved = __cpu_to_le32(0), 1525 }, 1526 1527 /* CE8 target->host used only by IPA */ 1528 { 1529 .pipenum = __cpu_to_le32(8), 1530 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1531 .nentries = __cpu_to_le32(32), 1532 .nbytes_max = __cpu_to_le32(16384), 1533 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1534 .reserved = __cpu_to_le32(0), 1535 }, 1536 /* CE 9, 10, 11 are used by MHI driver */ 1537 }; 1538 1539 /* Map from service/endpoint to Copy Engine. 1540 * This table is derived from the CE_PCI TABLE, above. 1541 * It is passed to the Target at startup for use by firmware. 1542 */ 1543 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1544 { 1545 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1546 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1547 __cpu_to_le32(3), 1548 }, 1549 { 1550 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1551 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1552 __cpu_to_le32(2), 1553 }, 1554 { 1555 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1556 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1557 __cpu_to_le32(3), 1558 }, 1559 { 1560 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1561 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1562 __cpu_to_le32(2), 1563 }, 1564 { 1565 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1566 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1567 __cpu_to_le32(3), 1568 }, 1569 { 1570 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1571 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1572 __cpu_to_le32(2), 1573 }, 1574 { 1575 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1576 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1577 __cpu_to_le32(3), 1578 }, 1579 { 1580 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1581 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1582 __cpu_to_le32(2), 1583 }, 1584 { 1585 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1586 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1587 __cpu_to_le32(3), 1588 }, 1589 { 1590 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1591 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1592 __cpu_to_le32(2), 1593 }, 1594 { 1595 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1596 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1597 __cpu_to_le32(0), 1598 }, 1599 { 1600 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1601 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1602 __cpu_to_le32(2), 1603 }, 1604 { 1605 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1606 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1607 __cpu_to_le32(4), 1608 }, 1609 { 1610 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1611 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1612 __cpu_to_le32(1), 1613 }, 1614 1615 /* (Additions here) */ 1616 1617 { /* must be last */ 1618 __cpu_to_le32(0), 1619 __cpu_to_le32(0), 1620 __cpu_to_le32(0), 1621 }, 1622 }; 1623 1624 /* Target firmware's Copy Engine configuration. */ 1625 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1626 /* CE0: host->target HTC control and raw streams */ 1627 { 1628 .pipenum = __cpu_to_le32(0), 1629 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1630 .nentries = __cpu_to_le32(32), 1631 .nbytes_max = __cpu_to_le32(2048), 1632 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1633 .reserved = __cpu_to_le32(0), 1634 }, 1635 1636 /* CE1: target->host HTT + HTC control */ 1637 { 1638 .pipenum = __cpu_to_le32(1), 1639 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1640 .nentries = __cpu_to_le32(32), 1641 .nbytes_max = __cpu_to_le32(2048), 1642 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1643 .reserved = __cpu_to_le32(0), 1644 }, 1645 1646 /* CE2: target->host WMI */ 1647 { 1648 .pipenum = __cpu_to_le32(2), 1649 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1650 .nentries = __cpu_to_le32(32), 1651 .nbytes_max = __cpu_to_le32(2048), 1652 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1653 .reserved = __cpu_to_le32(0), 1654 }, 1655 1656 /* CE3: host->target WMI */ 1657 { 1658 .pipenum = __cpu_to_le32(3), 1659 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1660 .nentries = __cpu_to_le32(32), 1661 .nbytes_max = __cpu_to_le32(2048), 1662 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1663 .reserved = __cpu_to_le32(0), 1664 }, 1665 1666 /* CE4: host->target HTT */ 1667 { 1668 .pipenum = __cpu_to_le32(4), 1669 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1670 .nentries = __cpu_to_le32(256), 1671 .nbytes_max = __cpu_to_le32(256), 1672 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1673 .reserved = __cpu_to_le32(0), 1674 }, 1675 1676 /* CE5: target->host Pktlog */ 1677 { 1678 .pipenum = __cpu_to_le32(5), 1679 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1680 .nentries = __cpu_to_le32(32), 1681 .nbytes_max = __cpu_to_le32(2048), 1682 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1683 .reserved = __cpu_to_le32(0), 1684 }, 1685 1686 /* CE6: Reserved for target autonomous hif_memcpy */ 1687 { 1688 .pipenum = __cpu_to_le32(6), 1689 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1690 .nentries = __cpu_to_le32(32), 1691 .nbytes_max = __cpu_to_le32(16384), 1692 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1693 .reserved = __cpu_to_le32(0), 1694 }, 1695 1696 /* CE7 used only by Host */ 1697 { 1698 .pipenum = __cpu_to_le32(7), 1699 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1700 .nentries = __cpu_to_le32(0), 1701 .nbytes_max = __cpu_to_le32(0), 1702 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1703 .reserved = __cpu_to_le32(0), 1704 }, 1705 1706 /* CE8 target->host used only by IPA */ 1707 { 1708 .pipenum = __cpu_to_le32(8), 1709 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1710 .nentries = __cpu_to_le32(32), 1711 .nbytes_max = __cpu_to_le32(16384), 1712 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1713 .reserved = __cpu_to_le32(0), 1714 }, 1715 /* CE 9, 10, 11 are used by MHI driver */ 1716 }; 1717 1718 /* Map from service/endpoint to Copy Engine. 1719 * This table is derived from the CE_PCI TABLE, above. 1720 * It is passed to the Target at startup for use by firmware. 1721 */ 1722 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1723 { 1724 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1725 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1726 __cpu_to_le32(3), 1727 }, 1728 { 1729 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1730 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1731 __cpu_to_le32(2), 1732 }, 1733 { 1734 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1735 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1736 __cpu_to_le32(3), 1737 }, 1738 { 1739 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1740 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1741 __cpu_to_le32(2), 1742 }, 1743 { 1744 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1745 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1746 __cpu_to_le32(3), 1747 }, 1748 { 1749 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1750 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1751 __cpu_to_le32(2), 1752 }, 1753 { 1754 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1755 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1756 __cpu_to_le32(3), 1757 }, 1758 { 1759 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1760 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1761 __cpu_to_le32(2), 1762 }, 1763 { 1764 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1765 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1766 __cpu_to_le32(3), 1767 }, 1768 { 1769 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1770 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1771 __cpu_to_le32(2), 1772 }, 1773 { 1774 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1775 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1776 __cpu_to_le32(0), 1777 }, 1778 { 1779 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1780 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1781 __cpu_to_le32(1), 1782 }, 1783 { 1784 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1785 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1786 __cpu_to_le32(0), 1787 }, 1788 { 1789 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1790 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1791 __cpu_to_le32(1), 1792 }, 1793 { 1794 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1795 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1796 __cpu_to_le32(4), 1797 }, 1798 { 1799 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1800 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1801 __cpu_to_le32(1), 1802 }, 1803 { 1804 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1805 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1806 __cpu_to_le32(5), 1807 }, 1808 1809 /* (Additions here) */ 1810 1811 { /* must be last */ 1812 __cpu_to_le32(0), 1813 __cpu_to_le32(0), 1814 __cpu_to_le32(0), 1815 }, 1816 }; 1817 1818 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1819 .tx = { 1820 ATH11K_TX_RING_MASK_0, 1821 ATH11K_TX_RING_MASK_1, 1822 ATH11K_TX_RING_MASK_2, 1823 }, 1824 .rx_mon_status = { 1825 0, 0, 0, 1826 ATH11K_RX_MON_STATUS_RING_MASK_0, 1827 ATH11K_RX_MON_STATUS_RING_MASK_1, 1828 ATH11K_RX_MON_STATUS_RING_MASK_2, 1829 }, 1830 .rx = { 1831 0, 0, 0, 0, 1832 ATH11K_RX_RING_MASK_0, 1833 ATH11K_RX_RING_MASK_1, 1834 ATH11K_RX_RING_MASK_2, 1835 ATH11K_RX_RING_MASK_3, 1836 }, 1837 .rx_err = { 1838 0, 0, 0, 1839 ATH11K_RX_ERR_RING_MASK_0, 1840 }, 1841 .rx_wbm_rel = { 1842 0, 0, 0, 1843 ATH11K_RX_WBM_REL_RING_MASK_0, 1844 }, 1845 .reo_status = { 1846 0, 0, 0, 1847 ATH11K_REO_STATUS_RING_MASK_0, 1848 }, 1849 .rxdma2host = { 1850 0, 0, 0, 1851 ATH11K_RXDMA2HOST_RING_MASK_0, 1852 }, 1853 .host2rxdma = { 1854 0, 0, 0, 1855 ATH11K_HOST2RXDMA_RING_MASK_0, 1856 }, 1857 }; 1858 1859 const struct ath11k_hw_regs ipq8074_regs = { 1860 /* SW2TCL(x) R0 ring configuration address */ 1861 .hal_tcl1_ring_base_lsb = 0x00000510, 1862 .hal_tcl1_ring_base_msb = 0x00000514, 1863 .hal_tcl1_ring_id = 0x00000518, 1864 .hal_tcl1_ring_misc = 0x00000520, 1865 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1866 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1867 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1868 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1869 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1870 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1871 .hal_tcl1_ring_msi1_data = 0x00000560, 1872 .hal_tcl2_ring_base_lsb = 0x00000568, 1873 .hal_tcl_ring_base_lsb = 0x00000618, 1874 1875 /* TCL STATUS ring address */ 1876 .hal_tcl_status_ring_base_lsb = 0x00000720, 1877 1878 /* REO2SW(x) R0 ring configuration address */ 1879 .hal_reo1_ring_base_lsb = 0x0000029c, 1880 .hal_reo1_ring_base_msb = 0x000002a0, 1881 .hal_reo1_ring_id = 0x000002a4, 1882 .hal_reo1_ring_misc = 0x000002ac, 1883 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1884 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1885 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1886 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1887 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1888 .hal_reo1_ring_msi1_data = 0x000002ec, 1889 .hal_reo2_ring_base_lsb = 0x000002f4, 1890 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1891 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1892 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1893 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1894 1895 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1896 .hal_reo1_ring_hp = 0x00003038, 1897 .hal_reo1_ring_tp = 0x0000303c, 1898 .hal_reo2_ring_hp = 0x00003040, 1899 1900 /* REO2TCL R0 ring configuration address */ 1901 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1902 .hal_reo_tcl_ring_hp = 0x00003058, 1903 1904 /* REO status address */ 1905 .hal_reo_status_ring_base_lsb = 0x00000504, 1906 .hal_reo_status_hp = 0x00003070, 1907 1908 /* WCSS relative address */ 1909 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1910 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1911 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1912 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1913 1914 /* WBM Idle address */ 1915 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1916 .hal_wbm_idle_link_ring_misc = 0x00000870, 1917 1918 /* SW2WBM release address */ 1919 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1920 1921 /* WBM2SW release address */ 1922 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1923 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1924 1925 /* PCIe base address */ 1926 .pcie_qserdes_sysclk_en_sel = 0x0, 1927 .pcie_pcs_osc_dtct_config_base = 0x0, 1928 }; 1929 1930 const struct ath11k_hw_regs qca6390_regs = { 1931 /* SW2TCL(x) R0 ring configuration address */ 1932 .hal_tcl1_ring_base_lsb = 0x00000684, 1933 .hal_tcl1_ring_base_msb = 0x00000688, 1934 .hal_tcl1_ring_id = 0x0000068c, 1935 .hal_tcl1_ring_misc = 0x00000694, 1936 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1937 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1938 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1939 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1940 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1941 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1942 .hal_tcl1_ring_msi1_data = 0x000006d4, 1943 .hal_tcl2_ring_base_lsb = 0x000006dc, 1944 .hal_tcl_ring_base_lsb = 0x0000078c, 1945 1946 /* TCL STATUS ring address */ 1947 .hal_tcl_status_ring_base_lsb = 0x00000894, 1948 1949 /* REO2SW(x) R0 ring configuration address */ 1950 .hal_reo1_ring_base_lsb = 0x00000244, 1951 .hal_reo1_ring_base_msb = 0x00000248, 1952 .hal_reo1_ring_id = 0x0000024c, 1953 .hal_reo1_ring_misc = 0x00000254, 1954 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1955 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1956 .hal_reo1_ring_producer_int_setup = 0x00000268, 1957 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1958 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1959 .hal_reo1_ring_msi1_data = 0x00000294, 1960 .hal_reo2_ring_base_lsb = 0x0000029c, 1961 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1962 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1963 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1964 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1965 1966 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1967 .hal_reo1_ring_hp = 0x00003030, 1968 .hal_reo1_ring_tp = 0x00003034, 1969 .hal_reo2_ring_hp = 0x00003038, 1970 1971 /* REO2TCL R0 ring configuration address */ 1972 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1973 .hal_reo_tcl_ring_hp = 0x00003050, 1974 1975 /* REO status address */ 1976 .hal_reo_status_ring_base_lsb = 0x000004ac, 1977 .hal_reo_status_hp = 0x00003068, 1978 1979 /* WCSS relative address */ 1980 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1981 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1982 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1983 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1984 1985 /* WBM Idle address */ 1986 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1987 .hal_wbm_idle_link_ring_misc = 0x00000870, 1988 1989 /* SW2WBM release address */ 1990 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1991 1992 /* WBM2SW release address */ 1993 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1994 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1995 1996 /* PCIe base address */ 1997 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 1998 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 1999 }; 2000 2001 const struct ath11k_hw_regs qcn9074_regs = { 2002 /* SW2TCL(x) R0 ring configuration address */ 2003 .hal_tcl1_ring_base_lsb = 0x000004f0, 2004 .hal_tcl1_ring_base_msb = 0x000004f4, 2005 .hal_tcl1_ring_id = 0x000004f8, 2006 .hal_tcl1_ring_misc = 0x00000500, 2007 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 2008 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 2009 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 2010 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 2011 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 2012 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 2013 .hal_tcl1_ring_msi1_data = 0x00000540, 2014 .hal_tcl2_ring_base_lsb = 0x00000548, 2015 .hal_tcl_ring_base_lsb = 0x000005f8, 2016 2017 /* TCL STATUS ring address */ 2018 .hal_tcl_status_ring_base_lsb = 0x00000700, 2019 2020 /* REO2SW(x) R0 ring configuration address */ 2021 .hal_reo1_ring_base_lsb = 0x0000029c, 2022 .hal_reo1_ring_base_msb = 0x000002a0, 2023 .hal_reo1_ring_id = 0x000002a4, 2024 .hal_reo1_ring_misc = 0x000002ac, 2025 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2026 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2027 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2028 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2029 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2030 .hal_reo1_ring_msi1_data = 0x000002ec, 2031 .hal_reo2_ring_base_lsb = 0x000002f4, 2032 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2033 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2034 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2035 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2036 2037 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2038 .hal_reo1_ring_hp = 0x00003038, 2039 .hal_reo1_ring_tp = 0x0000303c, 2040 .hal_reo2_ring_hp = 0x00003040, 2041 2042 /* REO2TCL R0 ring configuration address */ 2043 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2044 .hal_reo_tcl_ring_hp = 0x00003058, 2045 2046 /* REO status address */ 2047 .hal_reo_status_ring_base_lsb = 0x00000504, 2048 .hal_reo_status_hp = 0x00003070, 2049 2050 /* WCSS relative address */ 2051 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2052 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2053 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2054 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2055 2056 /* WBM Idle address */ 2057 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2058 .hal_wbm_idle_link_ring_misc = 0x00000884, 2059 2060 /* SW2WBM release address */ 2061 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2062 2063 /* WBM2SW release address */ 2064 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2065 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2066 2067 /* PCIe base address */ 2068 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2069 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2070 }; 2071 2072 const struct ath11k_hw_regs wcn6855_regs = { 2073 /* SW2TCL(x) R0 ring configuration address */ 2074 .hal_tcl1_ring_base_lsb = 0x00000690, 2075 .hal_tcl1_ring_base_msb = 0x00000694, 2076 .hal_tcl1_ring_id = 0x00000698, 2077 .hal_tcl1_ring_misc = 0x000006a0, 2078 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2079 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2080 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2081 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2082 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2083 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2084 .hal_tcl1_ring_msi1_data = 0x000006e0, 2085 .hal_tcl2_ring_base_lsb = 0x000006e8, 2086 .hal_tcl_ring_base_lsb = 0x00000798, 2087 2088 /* TCL STATUS ring address */ 2089 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2090 2091 /* REO2SW(x) R0 ring configuration address */ 2092 .hal_reo1_ring_base_lsb = 0x00000244, 2093 .hal_reo1_ring_base_msb = 0x00000248, 2094 .hal_reo1_ring_id = 0x0000024c, 2095 .hal_reo1_ring_misc = 0x00000254, 2096 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2097 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2098 .hal_reo1_ring_producer_int_setup = 0x00000268, 2099 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2100 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2101 .hal_reo1_ring_msi1_data = 0x00000294, 2102 .hal_reo2_ring_base_lsb = 0x0000029c, 2103 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2104 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2105 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2106 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2107 2108 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2109 .hal_reo1_ring_hp = 0x00003030, 2110 .hal_reo1_ring_tp = 0x00003034, 2111 .hal_reo2_ring_hp = 0x00003038, 2112 2113 /* REO2TCL R0 ring configuration address */ 2114 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2115 .hal_reo_tcl_ring_hp = 0x00003060, 2116 2117 /* REO status address */ 2118 .hal_reo_status_ring_base_lsb = 0x0000055c, 2119 .hal_reo_status_hp = 0x00003078, 2120 2121 /* WCSS relative address */ 2122 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2123 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2124 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2125 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2126 2127 /* WBM Idle address */ 2128 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2129 .hal_wbm_idle_link_ring_misc = 0x00000880, 2130 2131 /* SW2WBM release address */ 2132 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2133 2134 /* WBM2SW release address */ 2135 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2136 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2137 2138 /* PCIe base address */ 2139 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2140 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2141 }; 2142 2143 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2144 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2145 }; 2146 2147 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2148 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2149 }; 2150