1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "core.h" 12 #include "ce.h" 13 #include "hif.h" 14 #include "hal.h" 15 #include "hw.h" 16 17 /* Map from pdev index to hw mac index */ 18 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 19 { 20 switch (pdev_idx) { 21 case 0: 22 return 0; 23 case 1: 24 return 2; 25 case 2: 26 return 1; 27 default: 28 return ATH11K_INVALID_HW_MAC_ID; 29 } 30 } 31 32 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 33 { 34 return pdev_idx; 35 } 36 37 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 38 struct hal_tcl_data_cmd *tcl_cmd) 39 { 40 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 41 true); 42 } 43 44 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 45 struct hal_tcl_data_cmd *tcl_cmd) 46 { 47 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 48 true); 49 } 50 51 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 52 struct hal_tcl_data_cmd *tcl_cmd) 53 { 54 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 55 true); 56 } 57 58 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 59 struct target_resource_config *config) 60 { 61 config->num_vdevs = 4; 62 config->num_peers = 16; 63 config->num_tids = 32; 64 65 config->num_offload_peers = 3; 66 config->num_offload_reorder_buffs = 3; 67 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 68 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 69 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 74 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 75 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 76 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 77 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 79 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 80 config->num_mcast_groups = 0; 81 config->num_mcast_table_elems = 0; 82 config->mcast2ucast_mode = 0; 83 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 84 config->num_wds_entries = 0; 85 config->dma_burst_size = 0; 86 config->rx_skip_defrag_timeout_dup_detection_check = 0; 87 config->vow_config = TARGET_VOW_CONFIG; 88 config->gtk_offload_max_vdev = 2; 89 config->num_msdu_desc = 0x400; 90 config->beacon_tx_offload_max_vdev = 2; 91 config->rx_batchmode = TARGET_RX_BATCHMODE; 92 93 config->peer_map_unmap_v2_support = 0; 94 config->use_pdev_id = 1; 95 config->max_frag_entries = 0xa; 96 config->num_tdls_vdevs = 0x1; 97 config->num_tdls_conn_table_entries = 8; 98 config->beacon_tx_offload_max_vdev = 0x2; 99 config->num_multicast_filter_entries = 0x20; 100 config->num_wow_filters = 0x16; 101 config->num_keep_alive_pattern = 0; 102 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 103 } 104 105 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 106 { 107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 108 u32 val; 109 /* Each hash entry uses three bits to map to a particular ring. */ 110 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 111 HAL_HASH_ROUTING_RING_SW2 << 3 | 112 HAL_HASH_ROUTING_RING_SW3 << 6 | 113 HAL_HASH_ROUTING_RING_SW4 << 9 | 114 HAL_HASH_ROUTING_RING_SW1 << 12 | 115 HAL_HASH_ROUTING_RING_SW2 << 15 | 116 HAL_HASH_ROUTING_RING_SW3 << 18 | 117 HAL_HASH_ROUTING_RING_SW4 << 21; 118 119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 120 121 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 122 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 123 HAL_SRNG_RING_ID_REO2SW1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 125 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 127 128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 129 HAL_DEFAULT_REO_TIMEOUT_USEC); 130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 131 HAL_DEFAULT_REO_TIMEOUT_USEC); 132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 133 HAL_DEFAULT_REO_TIMEOUT_USEC); 134 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 135 HAL_DEFAULT_REO_TIMEOUT_USEC); 136 137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 139 ring_hash_map)); 140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 142 ring_hash_map)); 143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 145 ring_hash_map)); 146 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 147 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 148 ring_hash_map)); 149 } 150 151 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 152 struct target_resource_config *config) 153 { 154 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 155 156 if (ab->num_radios == 2) { 157 config->num_peers = TARGET_NUM_PEERS(ab, DBS); 158 config->num_tids = TARGET_NUM_TIDS(ab, DBS); 159 } else if (ab->num_radios == 3) { 160 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 161 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 162 } else { 163 /* Control should not reach here */ 164 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 165 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 166 } 167 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 168 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 169 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 170 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 171 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 173 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 176 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 177 178 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 179 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 180 else 181 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 182 183 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 184 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 186 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 187 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 188 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 189 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 190 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 191 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 192 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 193 config->rx_skip_defrag_timeout_dup_detection_check = 194 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 195 config->vow_config = TARGET_VOW_CONFIG; 196 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 197 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 198 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 199 config->rx_batchmode = TARGET_RX_BATCHMODE; 200 config->peer_map_unmap_v2_support = 1; 201 config->twt_ap_pdev_count = ab->num_radios; 202 config->twt_ap_sta_count = 1000; 203 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 204 config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI; 205 config->ema_max_vap_cnt = ab->num_radios; 206 config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD; 207 config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt; 208 } 209 210 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 211 int mac_id) 212 { 213 return mac_id; 214 } 215 216 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 217 int mac_id) 218 { 219 return 0; 220 } 221 222 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 223 int mac_id) 224 { 225 return 0; 226 } 227 228 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 229 int mac_id) 230 { 231 return mac_id; 232 } 233 234 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 235 { 236 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 237 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 238 } 239 240 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 241 { 242 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 243 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 244 } 245 246 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 247 { 248 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 249 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 250 } 251 252 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 253 { 254 return desc->u.ipq8074.hdr_status; 255 } 256 257 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 258 { 259 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 260 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 261 } 262 263 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 264 { 265 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 266 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 267 } 268 269 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 270 { 271 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 272 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 273 } 274 275 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 276 { 277 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 278 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 279 } 280 281 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 282 { 283 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 284 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 285 } 286 287 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 288 { 289 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 290 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 291 } 292 293 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 294 { 295 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 296 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 297 } 298 299 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 300 { 301 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 302 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 303 } 304 305 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 306 { 307 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 308 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 309 } 310 311 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 312 { 313 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 314 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 315 } 316 317 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 318 { 319 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 320 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 321 } 322 323 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 324 { 325 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 326 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 327 } 328 329 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 330 { 331 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 332 } 333 334 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 335 { 336 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 337 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 338 } 339 340 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 341 { 342 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 343 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 344 } 345 346 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 347 { 348 return FIELD_GET(RX_MPDU_START_INFO2_TID, 349 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 350 } 351 352 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 353 { 354 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 355 } 356 357 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 358 struct hal_rx_desc *ldesc) 359 { 360 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 361 sizeof(struct rx_msdu_end_ipq8074)); 362 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 363 sizeof(struct rx_attention)); 364 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 365 sizeof(struct rx_mpdu_end)); 366 } 367 368 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 369 { 370 return FIELD_GET(HAL_TLV_HDR_TAG, 371 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 372 } 373 374 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 375 { 376 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 377 } 378 379 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 380 { 381 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 382 383 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 384 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 385 386 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 387 } 388 389 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 390 { 391 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 392 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 393 } 394 395 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 396 { 397 return desc->u.ipq8074.mpdu_start.addr2; 398 } 399 400 static 401 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 402 { 403 return &desc->u.ipq8074.attention; 404 } 405 406 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 407 { 408 return &desc->u.ipq8074.msdu_payload[0]; 409 } 410 411 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 412 { 413 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 414 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 415 } 416 417 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 418 { 419 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 420 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 421 } 422 423 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 424 { 425 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 426 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 427 } 428 429 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 430 { 431 return desc->u.qcn9074.hdr_status; 432 } 433 434 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 435 { 436 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 437 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 438 } 439 440 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 441 { 442 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 443 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 444 } 445 446 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 447 { 448 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 449 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 450 } 451 452 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 453 { 454 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 455 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 456 } 457 458 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 459 { 460 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 461 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 462 } 463 464 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 465 { 466 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 467 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 468 } 469 470 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 471 { 472 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 473 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 474 } 475 476 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 477 { 478 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 479 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 480 } 481 482 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 483 { 484 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 485 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 486 } 487 488 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 489 { 490 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 491 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 492 } 493 494 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 495 { 496 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 497 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 498 } 499 500 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 501 { 502 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 503 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 504 } 505 506 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 507 { 508 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 509 } 510 511 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 512 { 513 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 514 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 515 } 516 517 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 518 { 519 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 520 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 521 } 522 523 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 524 { 525 return FIELD_GET(RX_MPDU_START_INFO9_TID, 526 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 527 } 528 529 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 530 { 531 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 532 } 533 534 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 535 struct hal_rx_desc *ldesc) 536 { 537 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 538 sizeof(struct rx_msdu_end_qcn9074)); 539 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 540 sizeof(struct rx_attention)); 541 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 542 sizeof(struct rx_mpdu_end)); 543 } 544 545 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 546 { 547 return FIELD_GET(HAL_TLV_HDR_TAG, 548 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 549 } 550 551 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 552 { 553 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 554 } 555 556 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 557 { 558 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 559 560 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 561 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 562 563 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 564 } 565 566 static 567 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 568 { 569 return &desc->u.qcn9074.attention; 570 } 571 572 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 573 { 574 return &desc->u.qcn9074.msdu_payload[0]; 575 } 576 577 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 578 { 579 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 580 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 581 } 582 583 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 584 { 585 return desc->u.qcn9074.mpdu_start.addr2; 586 } 587 588 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 589 { 590 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 591 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 592 } 593 594 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 595 { 596 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 597 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 598 } 599 600 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 601 { 602 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 603 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 604 } 605 606 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 607 { 608 return desc->u.wcn6855.hdr_status; 609 } 610 611 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 612 { 613 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 614 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 615 } 616 617 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 618 { 619 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 620 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 621 } 622 623 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 624 { 625 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 626 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 627 } 628 629 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 630 { 631 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 632 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 633 } 634 635 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 636 { 637 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 638 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 639 } 640 641 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 642 { 643 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 644 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 645 } 646 647 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 648 { 649 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 650 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 651 } 652 653 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 654 { 655 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 656 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 657 } 658 659 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 660 { 661 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 662 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 663 } 664 665 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 666 { 667 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 668 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 669 } 670 671 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 672 { 673 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 674 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 675 } 676 677 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 678 { 679 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 680 } 681 682 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 683 { 684 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 685 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 686 } 687 688 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 689 { 690 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 691 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 692 } 693 694 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 695 { 696 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 697 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 698 } 699 700 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 701 { 702 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 703 } 704 705 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 706 struct hal_rx_desc *ldesc) 707 { 708 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 709 sizeof(struct rx_msdu_end_wcn6855)); 710 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 711 sizeof(struct rx_attention)); 712 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 713 sizeof(struct rx_mpdu_end)); 714 } 715 716 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 717 { 718 return FIELD_GET(HAL_TLV_HDR_TAG, 719 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 720 } 721 722 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 723 { 724 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 725 } 726 727 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 728 { 729 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 730 731 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 732 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 733 734 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 735 } 736 737 static 738 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 739 { 740 return &desc->u.wcn6855.attention; 741 } 742 743 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 744 { 745 return &desc->u.wcn6855.msdu_payload[0]; 746 } 747 748 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 749 { 750 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 751 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 752 } 753 754 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 755 { 756 return desc->u.wcn6855.mpdu_start.addr2; 757 } 758 759 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 760 { 761 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 762 u32 val; 763 /* Each hash entry uses four bits to map to a particular ring. */ 764 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 765 HAL_HASH_ROUTING_RING_SW2 << 4 | 766 HAL_HASH_ROUTING_RING_SW3 << 8 | 767 HAL_HASH_ROUTING_RING_SW4 << 12 | 768 HAL_HASH_ROUTING_RING_SW1 << 16 | 769 HAL_HASH_ROUTING_RING_SW2 << 20 | 770 HAL_HASH_ROUTING_RING_SW3 << 24 | 771 HAL_HASH_ROUTING_RING_SW4 << 28; 772 773 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 774 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 775 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 776 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 777 778 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab)); 779 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 780 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 781 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val); 782 783 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 784 HAL_DEFAULT_REO_TIMEOUT_USEC); 785 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 786 HAL_DEFAULT_REO_TIMEOUT_USEC); 787 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 788 HAL_DEFAULT_REO_TIMEOUT_USEC); 789 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 790 HAL_DEFAULT_REO_TIMEOUT_USEC); 791 792 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 793 ring_hash_map); 794 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 795 ring_hash_map); 796 } 797 798 static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab) 799 { 800 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 801 u32 val; 802 803 /* Each hash entry uses three bits to map to a particular ring. */ 804 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 805 HAL_HASH_ROUTING_RING_SW2 << 4 | 806 HAL_HASH_ROUTING_RING_SW3 << 8 | 807 HAL_HASH_ROUTING_RING_SW4 << 12 | 808 HAL_HASH_ROUTING_RING_SW1 << 16 | 809 HAL_HASH_ROUTING_RING_SW2 << 20 | 810 HAL_HASH_ROUTING_RING_SW3 << 24 | 811 HAL_HASH_ROUTING_RING_SW4 << 28; 812 813 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 814 815 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 816 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 817 HAL_SRNG_RING_ID_REO2SW1) | 818 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 819 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 820 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 821 822 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 823 HAL_DEFAULT_REO_TIMEOUT_USEC); 824 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 825 HAL_DEFAULT_REO_TIMEOUT_USEC); 826 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 827 HAL_DEFAULT_REO_TIMEOUT_USEC); 828 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 829 HAL_DEFAULT_REO_TIMEOUT_USEC); 830 831 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 832 ring_hash_map); 833 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 834 ring_hash_map); 835 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 836 ring_hash_map); 837 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 838 ring_hash_map); 839 } 840 841 static u16 842 ath11k_hw_ipq8074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) 843 { 844 u16 peer_id = 0; 845 846 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 847 __le32_to_cpu(mpdu_info->u.ipq8074.info0)); 848 849 return peer_id; 850 } 851 852 static u16 853 ath11k_hw_qcn9074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) 854 { 855 u16 peer_id = 0; 856 857 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 858 __le32_to_cpu(mpdu_info->u.qcn9074.info0)); 859 860 return peer_id; 861 } 862 863 static u16 864 ath11k_hw_wcn6855_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) 865 { 866 u16 peer_id = 0; 867 868 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 869 __le32_to_cpu(mpdu_info->u.wcn6855.info0)); 870 return peer_id; 871 } 872 873 static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 874 { 875 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 876 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 877 } 878 879 static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb) 880 { 881 /* Let the default ring selection be based on current processor 882 * number, where one of the 3 tcl rings are selected based on 883 * the smp_processor_id(). In case that ring 884 * is full/busy, we resort to other available rings. 885 * If all rings are full, we drop the packet. 886 * 887 * TODO: Add throttling logic when all rings are full 888 */ 889 return smp_processor_id(); 890 } 891 892 static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb) 893 { 894 /* Select the TCL ring based on the flow hash of the SKB instead 895 * of CPU ID. Since applications pumping the traffic can be scheduled 896 * on multiple CPUs, there is a chance that packets of the same flow 897 * could end on different TCL rings, this could sometimes results in 898 * an out of order arrival of the packets at the receiver. 899 */ 900 return skb_get_hash(skb); 901 } 902 903 const struct ath11k_hw_ops ipq8074_ops = { 904 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 905 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 906 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 907 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 908 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 909 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 910 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 911 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 912 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 913 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 914 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 915 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 916 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 917 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 918 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 919 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 920 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 921 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 922 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 923 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 924 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 925 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 926 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 927 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 928 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 929 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 930 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 931 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 932 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 933 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 934 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 935 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 936 .reo_setup = ath11k_hw_ipq8074_reo_setup, 937 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 938 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 939 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 940 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 941 }; 942 943 const struct ath11k_hw_ops ipq6018_ops = { 944 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 945 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 946 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 947 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 948 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 949 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 950 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 951 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 952 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 953 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 954 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 955 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 956 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 957 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 958 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 959 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 960 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 961 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 962 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 963 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 964 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 965 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 966 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 967 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 968 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 969 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 970 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 971 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 972 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 973 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 974 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 975 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 976 .reo_setup = ath11k_hw_ipq8074_reo_setup, 977 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 978 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 979 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 980 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 981 }; 982 983 const struct ath11k_hw_ops qca6390_ops = { 984 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 985 .wmi_init_config = ath11k_init_wmi_config_qca6390, 986 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 987 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 988 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 989 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 990 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 991 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 992 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 993 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 994 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 995 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 996 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 997 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 998 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 999 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 1000 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 1001 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 1002 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 1003 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 1004 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 1005 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 1006 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 1007 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 1008 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 1009 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 1010 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 1011 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 1012 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 1013 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 1014 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 1015 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 1016 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1017 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1018 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 1019 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 1020 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1021 }; 1022 1023 const struct ath11k_hw_ops qcn9074_ops = { 1024 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1025 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1026 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1027 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1028 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1029 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1030 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1031 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1032 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1033 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1034 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1035 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1036 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1037 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1038 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1039 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1040 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1041 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1042 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1043 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1044 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1045 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1046 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1047 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1048 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1049 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1050 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1051 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1052 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1053 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1054 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1055 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1056 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1057 .mpdu_info_get_peerid = ath11k_hw_qcn9074_mpdu_info_get_peerid, 1058 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1059 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1060 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1061 }; 1062 1063 const struct ath11k_hw_ops wcn6855_ops = { 1064 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1065 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1066 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1067 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1068 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 1069 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 1070 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 1071 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 1072 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 1073 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 1074 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 1075 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 1076 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 1077 .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support, 1078 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 1079 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 1080 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 1081 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 1082 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 1083 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 1084 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 1085 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 1086 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 1087 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 1088 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 1089 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 1090 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 1091 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1092 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1093 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1094 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1095 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 1096 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1097 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 1098 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 1099 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 1100 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1101 }; 1102 1103 const struct ath11k_hw_ops wcn6750_ops = { 1104 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1105 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1106 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1107 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1108 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1109 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1110 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1111 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1112 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1113 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1114 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1115 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1116 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1117 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1118 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1119 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1120 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1121 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1122 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1123 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1124 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1125 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1126 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1127 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1128 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1129 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1130 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1131 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1132 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1133 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1134 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1135 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1136 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1137 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1138 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1139 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1140 .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector, 1141 }; 1142 1143 /* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */ 1144 const struct ath11k_hw_ops ipq5018_ops = { 1145 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1146 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1147 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1148 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1149 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1150 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1151 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1152 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1153 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1154 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1155 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1156 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1157 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1158 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1159 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1160 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1161 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1162 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1163 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1164 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1165 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1166 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1167 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1168 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1169 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1170 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1171 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1172 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1173 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1174 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1175 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1176 .reo_setup = ath11k_hw_ipq5018_reo_setup, 1177 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1178 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1179 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1180 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1181 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1182 }; 1183 1184 #define ATH11K_TX_RING_MASK_0 BIT(0) 1185 #define ATH11K_TX_RING_MASK_1 BIT(1) 1186 #define ATH11K_TX_RING_MASK_2 BIT(2) 1187 #define ATH11K_TX_RING_MASK_3 BIT(3) 1188 #define ATH11K_TX_RING_MASK_4 BIT(4) 1189 1190 #define ATH11K_RX_RING_MASK_0 0x1 1191 #define ATH11K_RX_RING_MASK_1 0x2 1192 #define ATH11K_RX_RING_MASK_2 0x4 1193 #define ATH11K_RX_RING_MASK_3 0x8 1194 1195 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1196 1197 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1198 1199 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1200 1201 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1202 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1203 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1204 1205 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1206 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1207 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1208 1209 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1210 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1211 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1212 1213 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1214 .tx = { 1215 ATH11K_TX_RING_MASK_0, 1216 ATH11K_TX_RING_MASK_1, 1217 ATH11K_TX_RING_MASK_2, 1218 }, 1219 .rx_mon_status = { 1220 0, 0, 0, 0, 1221 ATH11K_RX_MON_STATUS_RING_MASK_0, 1222 ATH11K_RX_MON_STATUS_RING_MASK_1, 1223 ATH11K_RX_MON_STATUS_RING_MASK_2, 1224 }, 1225 .rx = { 1226 0, 0, 0, 0, 0, 0, 0, 1227 ATH11K_RX_RING_MASK_0, 1228 ATH11K_RX_RING_MASK_1, 1229 ATH11K_RX_RING_MASK_2, 1230 ATH11K_RX_RING_MASK_3, 1231 }, 1232 .rx_err = { 1233 ATH11K_RX_ERR_RING_MASK_0, 1234 }, 1235 .rx_wbm_rel = { 1236 ATH11K_RX_WBM_REL_RING_MASK_0, 1237 }, 1238 .reo_status = { 1239 0, 0, 0, 1240 ATH11K_REO_STATUS_RING_MASK_0, 1241 }, 1242 .rxdma2host = { 1243 ATH11K_RXDMA2HOST_RING_MASK_0, 1244 ATH11K_RXDMA2HOST_RING_MASK_1, 1245 ATH11K_RXDMA2HOST_RING_MASK_2, 1246 }, 1247 .host2rxdma = { 1248 ATH11K_HOST2RXDMA_RING_MASK_0, 1249 ATH11K_HOST2RXDMA_RING_MASK_1, 1250 ATH11K_HOST2RXDMA_RING_MASK_2, 1251 }, 1252 }; 1253 1254 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1255 .tx = { 1256 ATH11K_TX_RING_MASK_0, 1257 }, 1258 .rx_mon_status = { 1259 0, 0, 0, 0, 1260 ATH11K_RX_MON_STATUS_RING_MASK_0, 1261 ATH11K_RX_MON_STATUS_RING_MASK_1, 1262 ATH11K_RX_MON_STATUS_RING_MASK_2, 1263 }, 1264 .rx = { 1265 0, 0, 0, 0, 0, 0, 0, 1266 ATH11K_RX_RING_MASK_0, 1267 ATH11K_RX_RING_MASK_1, 1268 ATH11K_RX_RING_MASK_2, 1269 ATH11K_RX_RING_MASK_3, 1270 }, 1271 .rx_err = { 1272 ATH11K_RX_ERR_RING_MASK_0, 1273 }, 1274 .rx_wbm_rel = { 1275 ATH11K_RX_WBM_REL_RING_MASK_0, 1276 }, 1277 .reo_status = { 1278 ATH11K_REO_STATUS_RING_MASK_0, 1279 }, 1280 .rxdma2host = { 1281 ATH11K_RXDMA2HOST_RING_MASK_0, 1282 ATH11K_RXDMA2HOST_RING_MASK_1, 1283 ATH11K_RXDMA2HOST_RING_MASK_2, 1284 }, 1285 .host2rxdma = { 1286 }, 1287 }; 1288 1289 /* Target firmware's Copy Engine configuration. */ 1290 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1291 /* CE0: host->target HTC control and raw streams */ 1292 { 1293 .pipenum = __cpu_to_le32(0), 1294 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1295 .nentries = __cpu_to_le32(32), 1296 .nbytes_max = __cpu_to_le32(2048), 1297 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1298 .reserved = __cpu_to_le32(0), 1299 }, 1300 1301 /* CE1: target->host HTT + HTC control */ 1302 { 1303 .pipenum = __cpu_to_le32(1), 1304 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1305 .nentries = __cpu_to_le32(32), 1306 .nbytes_max = __cpu_to_le32(2048), 1307 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1308 .reserved = __cpu_to_le32(0), 1309 }, 1310 1311 /* CE2: target->host WMI */ 1312 { 1313 .pipenum = __cpu_to_le32(2), 1314 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1315 .nentries = __cpu_to_le32(32), 1316 .nbytes_max = __cpu_to_le32(2048), 1317 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1318 .reserved = __cpu_to_le32(0), 1319 }, 1320 1321 /* CE3: host->target WMI */ 1322 { 1323 .pipenum = __cpu_to_le32(3), 1324 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1325 .nentries = __cpu_to_le32(32), 1326 .nbytes_max = __cpu_to_le32(2048), 1327 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1328 .reserved = __cpu_to_le32(0), 1329 }, 1330 1331 /* CE4: host->target HTT */ 1332 { 1333 .pipenum = __cpu_to_le32(4), 1334 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1335 .nentries = __cpu_to_le32(256), 1336 .nbytes_max = __cpu_to_le32(256), 1337 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1338 .reserved = __cpu_to_le32(0), 1339 }, 1340 1341 /* CE5: target->host Pktlog */ 1342 { 1343 .pipenum = __cpu_to_le32(5), 1344 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1345 .nentries = __cpu_to_le32(32), 1346 .nbytes_max = __cpu_to_le32(2048), 1347 .flags = __cpu_to_le32(0), 1348 .reserved = __cpu_to_le32(0), 1349 }, 1350 1351 /* CE6: Reserved for target autonomous hif_memcpy */ 1352 { 1353 .pipenum = __cpu_to_le32(6), 1354 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1355 .nentries = __cpu_to_le32(32), 1356 .nbytes_max = __cpu_to_le32(65535), 1357 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1358 .reserved = __cpu_to_le32(0), 1359 }, 1360 1361 /* CE7 used only by Host */ 1362 { 1363 .pipenum = __cpu_to_le32(7), 1364 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1365 .nentries = __cpu_to_le32(32), 1366 .nbytes_max = __cpu_to_le32(2048), 1367 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1368 .reserved = __cpu_to_le32(0), 1369 }, 1370 1371 /* CE8 target->host used only by IPA */ 1372 { 1373 .pipenum = __cpu_to_le32(8), 1374 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1375 .nentries = __cpu_to_le32(32), 1376 .nbytes_max = __cpu_to_le32(65535), 1377 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1378 .reserved = __cpu_to_le32(0), 1379 }, 1380 1381 /* CE9 host->target HTT */ 1382 { 1383 .pipenum = __cpu_to_le32(9), 1384 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1385 .nentries = __cpu_to_le32(32), 1386 .nbytes_max = __cpu_to_le32(2048), 1387 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1388 .reserved = __cpu_to_le32(0), 1389 }, 1390 1391 /* CE10 target->host HTT */ 1392 { 1393 .pipenum = __cpu_to_le32(10), 1394 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1395 .nentries = __cpu_to_le32(0), 1396 .nbytes_max = __cpu_to_le32(0), 1397 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1398 .reserved = __cpu_to_le32(0), 1399 }, 1400 1401 /* CE11 Not used */ 1402 }; 1403 1404 /* Map from service/endpoint to Copy Engine. 1405 * This table is derived from the CE_PCI TABLE, above. 1406 * It is passed to the Target at startup for use by firmware. 1407 */ 1408 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1409 { 1410 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1411 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1412 .pipenum = __cpu_to_le32(3), 1413 }, 1414 { 1415 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1416 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1417 .pipenum = __cpu_to_le32(2), 1418 }, 1419 { 1420 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1421 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1422 .pipenum = __cpu_to_le32(3), 1423 }, 1424 { 1425 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1426 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1427 .pipenum = __cpu_to_le32(2), 1428 }, 1429 { 1430 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1431 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1432 .pipenum = __cpu_to_le32(3), 1433 }, 1434 { 1435 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1436 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1437 .pipenum = __cpu_to_le32(2), 1438 }, 1439 { 1440 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1441 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1442 .pipenum = __cpu_to_le32(3), 1443 }, 1444 { 1445 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1446 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1447 .pipenum = __cpu_to_le32(2), 1448 }, 1449 { 1450 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1451 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1452 .pipenum = __cpu_to_le32(3), 1453 }, 1454 { 1455 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1456 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1457 .pipenum = __cpu_to_le32(2), 1458 }, 1459 { 1460 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1461 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1462 .pipenum = __cpu_to_le32(7), 1463 }, 1464 { 1465 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1466 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1467 .pipenum = __cpu_to_le32(2), 1468 }, 1469 { 1470 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1471 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1472 .pipenum = __cpu_to_le32(9), 1473 }, 1474 { 1475 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1476 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1477 .pipenum = __cpu_to_le32(2), 1478 }, 1479 { 1480 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1481 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1482 .pipenum = __cpu_to_le32(0), 1483 }, 1484 { 1485 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1486 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1487 .pipenum = __cpu_to_le32(1), 1488 }, 1489 { /* not used */ 1490 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1491 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1492 .pipenum = __cpu_to_le32(0), 1493 }, 1494 { /* not used */ 1495 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1496 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1497 .pipenum = __cpu_to_le32(1), 1498 }, 1499 { 1500 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1501 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1502 .pipenum = __cpu_to_le32(4), 1503 }, 1504 { 1505 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1506 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1507 .pipenum = __cpu_to_le32(1), 1508 }, 1509 { 1510 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1511 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1512 .pipenum = __cpu_to_le32(5), 1513 }, 1514 1515 /* (Additions here) */ 1516 1517 { /* terminator entry */ } 1518 }; 1519 1520 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1521 { 1522 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1523 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1524 .pipenum = __cpu_to_le32(3), 1525 }, 1526 { 1527 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1528 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1529 .pipenum = __cpu_to_le32(2), 1530 }, 1531 { 1532 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1533 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1534 .pipenum = __cpu_to_le32(3), 1535 }, 1536 { 1537 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1538 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1539 .pipenum = __cpu_to_le32(2), 1540 }, 1541 { 1542 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1543 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1544 .pipenum = __cpu_to_le32(3), 1545 }, 1546 { 1547 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1548 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1549 .pipenum = __cpu_to_le32(2), 1550 }, 1551 { 1552 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1553 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1554 .pipenum = __cpu_to_le32(3), 1555 }, 1556 { 1557 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1558 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1559 .pipenum = __cpu_to_le32(2), 1560 }, 1561 { 1562 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1563 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1564 .pipenum = __cpu_to_le32(3), 1565 }, 1566 { 1567 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1568 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1569 .pipenum = __cpu_to_le32(2), 1570 }, 1571 { 1572 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1573 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1574 .pipenum = __cpu_to_le32(7), 1575 }, 1576 { 1577 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1578 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1579 .pipenum = __cpu_to_le32(2), 1580 }, 1581 { 1582 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1583 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1584 .pipenum = __cpu_to_le32(0), 1585 }, 1586 { 1587 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1588 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1589 .pipenum = __cpu_to_le32(1), 1590 }, 1591 { /* not used */ 1592 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1593 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1594 .pipenum = __cpu_to_le32(0), 1595 }, 1596 { /* not used */ 1597 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1598 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1599 .pipenum = __cpu_to_le32(1), 1600 }, 1601 { 1602 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1603 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1604 .pipenum = __cpu_to_le32(4), 1605 }, 1606 { 1607 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1608 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1609 .pipenum = __cpu_to_le32(1), 1610 }, 1611 { 1612 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1613 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1614 .pipenum = __cpu_to_le32(5), 1615 }, 1616 1617 /* (Additions here) */ 1618 1619 { /* terminator entry */ } 1620 }; 1621 1622 /* Target firmware's Copy Engine configuration. */ 1623 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1624 /* CE0: host->target HTC control and raw streams */ 1625 { 1626 .pipenum = __cpu_to_le32(0), 1627 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1628 .nentries = __cpu_to_le32(32), 1629 .nbytes_max = __cpu_to_le32(2048), 1630 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1631 .reserved = __cpu_to_le32(0), 1632 }, 1633 1634 /* CE1: target->host HTT + HTC control */ 1635 { 1636 .pipenum = __cpu_to_le32(1), 1637 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1638 .nentries = __cpu_to_le32(32), 1639 .nbytes_max = __cpu_to_le32(2048), 1640 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1641 .reserved = __cpu_to_le32(0), 1642 }, 1643 1644 /* CE2: target->host WMI */ 1645 { 1646 .pipenum = __cpu_to_le32(2), 1647 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1648 .nentries = __cpu_to_le32(32), 1649 .nbytes_max = __cpu_to_le32(2048), 1650 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1651 .reserved = __cpu_to_le32(0), 1652 }, 1653 1654 /* CE3: host->target WMI */ 1655 { 1656 .pipenum = __cpu_to_le32(3), 1657 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1658 .nentries = __cpu_to_le32(32), 1659 .nbytes_max = __cpu_to_le32(2048), 1660 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1661 .reserved = __cpu_to_le32(0), 1662 }, 1663 1664 /* CE4: host->target HTT */ 1665 { 1666 .pipenum = __cpu_to_le32(4), 1667 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1668 .nentries = __cpu_to_le32(256), 1669 .nbytes_max = __cpu_to_le32(256), 1670 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1671 .reserved = __cpu_to_le32(0), 1672 }, 1673 1674 /* CE5: target->host Pktlog */ 1675 { 1676 .pipenum = __cpu_to_le32(5), 1677 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1678 .nentries = __cpu_to_le32(32), 1679 .nbytes_max = __cpu_to_le32(2048), 1680 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1681 .reserved = __cpu_to_le32(0), 1682 }, 1683 1684 /* CE6: Reserved for target autonomous hif_memcpy */ 1685 { 1686 .pipenum = __cpu_to_le32(6), 1687 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1688 .nentries = __cpu_to_le32(32), 1689 .nbytes_max = __cpu_to_le32(16384), 1690 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1691 .reserved = __cpu_to_le32(0), 1692 }, 1693 1694 /* CE7 used only by Host */ 1695 { 1696 .pipenum = __cpu_to_le32(7), 1697 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1698 .nentries = __cpu_to_le32(0), 1699 .nbytes_max = __cpu_to_le32(0), 1700 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1701 .reserved = __cpu_to_le32(0), 1702 }, 1703 1704 /* CE8 target->host used only by IPA */ 1705 { 1706 .pipenum = __cpu_to_le32(8), 1707 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1708 .nentries = __cpu_to_le32(32), 1709 .nbytes_max = __cpu_to_le32(16384), 1710 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1711 .reserved = __cpu_to_le32(0), 1712 }, 1713 /* CE 9, 10, 11 are used by MHI driver */ 1714 }; 1715 1716 /* Map from service/endpoint to Copy Engine. 1717 * This table is derived from the CE_PCI TABLE, above. 1718 * It is passed to the Target at startup for use by firmware. 1719 */ 1720 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1721 { 1722 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1723 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1724 __cpu_to_le32(3), 1725 }, 1726 { 1727 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1728 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1729 __cpu_to_le32(2), 1730 }, 1731 { 1732 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1733 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1734 __cpu_to_le32(3), 1735 }, 1736 { 1737 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1738 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1739 __cpu_to_le32(2), 1740 }, 1741 { 1742 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1743 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1744 __cpu_to_le32(3), 1745 }, 1746 { 1747 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1748 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1749 __cpu_to_le32(2), 1750 }, 1751 { 1752 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1753 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1754 __cpu_to_le32(3), 1755 }, 1756 { 1757 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1758 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1759 __cpu_to_le32(2), 1760 }, 1761 { 1762 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1763 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1764 __cpu_to_le32(3), 1765 }, 1766 { 1767 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1768 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1769 __cpu_to_le32(2), 1770 }, 1771 { 1772 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1773 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1774 __cpu_to_le32(0), 1775 }, 1776 { 1777 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1778 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1779 __cpu_to_le32(2), 1780 }, 1781 { 1782 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1783 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1784 __cpu_to_le32(4), 1785 }, 1786 { 1787 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1788 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1789 __cpu_to_le32(1), 1790 }, 1791 1792 /* (Additions here) */ 1793 1794 { /* must be last */ 1795 __cpu_to_le32(0), 1796 __cpu_to_le32(0), 1797 __cpu_to_le32(0), 1798 }, 1799 }; 1800 1801 /* Target firmware's Copy Engine configuration. */ 1802 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1803 /* CE0: host->target HTC control and raw streams */ 1804 { 1805 .pipenum = __cpu_to_le32(0), 1806 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1807 .nentries = __cpu_to_le32(32), 1808 .nbytes_max = __cpu_to_le32(2048), 1809 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1810 .reserved = __cpu_to_le32(0), 1811 }, 1812 1813 /* CE1: target->host HTT + HTC control */ 1814 { 1815 .pipenum = __cpu_to_le32(1), 1816 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1817 .nentries = __cpu_to_le32(32), 1818 .nbytes_max = __cpu_to_le32(2048), 1819 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1820 .reserved = __cpu_to_le32(0), 1821 }, 1822 1823 /* CE2: target->host WMI */ 1824 { 1825 .pipenum = __cpu_to_le32(2), 1826 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1827 .nentries = __cpu_to_le32(32), 1828 .nbytes_max = __cpu_to_le32(2048), 1829 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1830 .reserved = __cpu_to_le32(0), 1831 }, 1832 1833 /* CE3: host->target WMI */ 1834 { 1835 .pipenum = __cpu_to_le32(3), 1836 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1837 .nentries = __cpu_to_le32(32), 1838 .nbytes_max = __cpu_to_le32(2048), 1839 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1840 .reserved = __cpu_to_le32(0), 1841 }, 1842 1843 /* CE4: host->target HTT */ 1844 { 1845 .pipenum = __cpu_to_le32(4), 1846 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1847 .nentries = __cpu_to_le32(256), 1848 .nbytes_max = __cpu_to_le32(256), 1849 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1850 .reserved = __cpu_to_le32(0), 1851 }, 1852 1853 /* CE5: target->host Pktlog */ 1854 { 1855 .pipenum = __cpu_to_le32(5), 1856 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1857 .nentries = __cpu_to_le32(32), 1858 .nbytes_max = __cpu_to_le32(2048), 1859 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1860 .reserved = __cpu_to_le32(0), 1861 }, 1862 1863 /* CE6: Reserved for target autonomous hif_memcpy */ 1864 { 1865 .pipenum = __cpu_to_le32(6), 1866 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1867 .nentries = __cpu_to_le32(32), 1868 .nbytes_max = __cpu_to_le32(16384), 1869 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1870 .reserved = __cpu_to_le32(0), 1871 }, 1872 1873 /* CE7 used only by Host */ 1874 { 1875 .pipenum = __cpu_to_le32(7), 1876 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1877 .nentries = __cpu_to_le32(0), 1878 .nbytes_max = __cpu_to_le32(0), 1879 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1880 .reserved = __cpu_to_le32(0), 1881 }, 1882 1883 /* CE8 target->host used only by IPA */ 1884 { 1885 .pipenum = __cpu_to_le32(8), 1886 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1887 .nentries = __cpu_to_le32(32), 1888 .nbytes_max = __cpu_to_le32(16384), 1889 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1890 .reserved = __cpu_to_le32(0), 1891 }, 1892 /* CE 9, 10, 11 are used by MHI driver */ 1893 }; 1894 1895 /* Map from service/endpoint to Copy Engine. 1896 * This table is derived from the CE_PCI TABLE, above. 1897 * It is passed to the Target at startup for use by firmware. 1898 */ 1899 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1900 { 1901 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1902 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1903 __cpu_to_le32(3), 1904 }, 1905 { 1906 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1907 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1908 __cpu_to_le32(2), 1909 }, 1910 { 1911 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1912 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1913 __cpu_to_le32(3), 1914 }, 1915 { 1916 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1917 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1918 __cpu_to_le32(2), 1919 }, 1920 { 1921 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1922 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1923 __cpu_to_le32(3), 1924 }, 1925 { 1926 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1927 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1928 __cpu_to_le32(2), 1929 }, 1930 { 1931 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1932 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1933 __cpu_to_le32(3), 1934 }, 1935 { 1936 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1937 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1938 __cpu_to_le32(2), 1939 }, 1940 { 1941 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1942 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1943 __cpu_to_le32(3), 1944 }, 1945 { 1946 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1947 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1948 __cpu_to_le32(2), 1949 }, 1950 { 1951 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1952 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1953 __cpu_to_le32(0), 1954 }, 1955 { 1956 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1957 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1958 __cpu_to_le32(1), 1959 }, 1960 { 1961 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1962 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1963 __cpu_to_le32(0), 1964 }, 1965 { 1966 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1967 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1968 __cpu_to_le32(1), 1969 }, 1970 { 1971 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1972 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1973 __cpu_to_le32(4), 1974 }, 1975 { 1976 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1977 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1978 __cpu_to_le32(1), 1979 }, 1980 { 1981 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1982 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1983 __cpu_to_le32(5), 1984 }, 1985 1986 /* (Additions here) */ 1987 1988 { /* must be last */ 1989 __cpu_to_le32(0), 1990 __cpu_to_le32(0), 1991 __cpu_to_le32(0), 1992 }, 1993 }; 1994 1995 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1996 .tx = { 1997 ATH11K_TX_RING_MASK_0, 1998 ATH11K_TX_RING_MASK_1, 1999 ATH11K_TX_RING_MASK_2, 2000 }, 2001 .rx_mon_status = { 2002 0, 0, 0, 2003 ATH11K_RX_MON_STATUS_RING_MASK_0, 2004 ATH11K_RX_MON_STATUS_RING_MASK_1, 2005 ATH11K_RX_MON_STATUS_RING_MASK_2, 2006 }, 2007 .rx = { 2008 0, 0, 0, 0, 2009 ATH11K_RX_RING_MASK_0, 2010 ATH11K_RX_RING_MASK_1, 2011 ATH11K_RX_RING_MASK_2, 2012 ATH11K_RX_RING_MASK_3, 2013 }, 2014 .rx_err = { 2015 0, 0, 0, 2016 ATH11K_RX_ERR_RING_MASK_0, 2017 }, 2018 .rx_wbm_rel = { 2019 0, 0, 0, 2020 ATH11K_RX_WBM_REL_RING_MASK_0, 2021 }, 2022 .reo_status = { 2023 0, 0, 0, 2024 ATH11K_REO_STATUS_RING_MASK_0, 2025 }, 2026 .rxdma2host = { 2027 0, 0, 0, 2028 ATH11K_RXDMA2HOST_RING_MASK_0, 2029 }, 2030 .host2rxdma = { 2031 0, 0, 0, 2032 ATH11K_HOST2RXDMA_RING_MASK_0, 2033 }, 2034 }; 2035 2036 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = { 2037 .tx = { 2038 ATH11K_TX_RING_MASK_0, 2039 0, 2040 ATH11K_TX_RING_MASK_2, 2041 0, 2042 ATH11K_TX_RING_MASK_4, 2043 }, 2044 .rx_mon_status = { 2045 0, 0, 0, 0, 0, 0, 2046 ATH11K_RX_MON_STATUS_RING_MASK_0, 2047 }, 2048 .rx = { 2049 0, 0, 0, 0, 0, 0, 0, 2050 ATH11K_RX_RING_MASK_0, 2051 ATH11K_RX_RING_MASK_1, 2052 ATH11K_RX_RING_MASK_2, 2053 ATH11K_RX_RING_MASK_3, 2054 }, 2055 .rx_err = { 2056 0, ATH11K_RX_ERR_RING_MASK_0, 2057 }, 2058 .rx_wbm_rel = { 2059 0, ATH11K_RX_WBM_REL_RING_MASK_0, 2060 }, 2061 .reo_status = { 2062 0, ATH11K_REO_STATUS_RING_MASK_0, 2063 }, 2064 .rxdma2host = { 2065 ATH11K_RXDMA2HOST_RING_MASK_0, 2066 ATH11K_RXDMA2HOST_RING_MASK_1, 2067 ATH11K_RXDMA2HOST_RING_MASK_2, 2068 }, 2069 .host2rxdma = { 2070 }, 2071 }; 2072 2073 /* Target firmware's Copy Engine configuration for IPQ5018 */ 2074 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = { 2075 /* CE0: host->target HTC control and raw streams */ 2076 { 2077 .pipenum = __cpu_to_le32(0), 2078 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2079 .nentries = __cpu_to_le32(32), 2080 .nbytes_max = __cpu_to_le32(2048), 2081 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2082 .reserved = __cpu_to_le32(0), 2083 }, 2084 2085 /* CE1: target->host HTT + HTC control */ 2086 { 2087 .pipenum = __cpu_to_le32(1), 2088 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2089 .nentries = __cpu_to_le32(32), 2090 .nbytes_max = __cpu_to_le32(2048), 2091 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2092 .reserved = __cpu_to_le32(0), 2093 }, 2094 2095 /* CE2: target->host WMI */ 2096 { 2097 .pipenum = __cpu_to_le32(2), 2098 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2099 .nentries = __cpu_to_le32(32), 2100 .nbytes_max = __cpu_to_le32(2048), 2101 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2102 .reserved = __cpu_to_le32(0), 2103 }, 2104 2105 /* CE3: host->target WMI */ 2106 { 2107 .pipenum = __cpu_to_le32(3), 2108 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2109 .nentries = __cpu_to_le32(32), 2110 .nbytes_max = __cpu_to_le32(2048), 2111 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2112 .reserved = __cpu_to_le32(0), 2113 }, 2114 2115 /* CE4: host->target HTT */ 2116 { 2117 .pipenum = __cpu_to_le32(4), 2118 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2119 .nentries = __cpu_to_le32(256), 2120 .nbytes_max = __cpu_to_le32(256), 2121 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 2122 .reserved = __cpu_to_le32(0), 2123 }, 2124 2125 /* CE5: target->host Pktlog */ 2126 { 2127 .pipenum = __cpu_to_le32(5), 2128 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2129 .nentries = __cpu_to_le32(32), 2130 .nbytes_max = __cpu_to_le32(2048), 2131 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2132 .reserved = __cpu_to_le32(0), 2133 }, 2134 2135 /* CE6: Reserved for target autonomous hif_memcpy */ 2136 { 2137 .pipenum = __cpu_to_le32(6), 2138 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2139 .nentries = __cpu_to_le32(32), 2140 .nbytes_max = __cpu_to_le32(16384), 2141 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2142 .reserved = __cpu_to_le32(0), 2143 }, 2144 2145 /* CE7 used only by Host */ 2146 { 2147 .pipenum = __cpu_to_le32(7), 2148 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2149 .nentries = __cpu_to_le32(32), 2150 .nbytes_max = __cpu_to_le32(2048), 2151 .flags = __cpu_to_le32(0x2000), 2152 .reserved = __cpu_to_le32(0), 2153 }, 2154 2155 /* CE8 target->host used only by IPA */ 2156 { 2157 .pipenum = __cpu_to_le32(8), 2158 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2159 .nentries = __cpu_to_le32(32), 2160 .nbytes_max = __cpu_to_le32(16384), 2161 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2162 .reserved = __cpu_to_le32(0), 2163 }, 2164 }; 2165 2166 /* Map from service/endpoint to Copy Engine for IPQ5018. 2167 * This table is derived from the CE TABLE, above. 2168 * It is passed to the Target at startup for use by firmware. 2169 */ 2170 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = { 2171 { 2172 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2173 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2174 .pipenum = __cpu_to_le32(3), 2175 }, 2176 { 2177 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2178 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2179 .pipenum = __cpu_to_le32(2), 2180 }, 2181 { 2182 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2183 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2184 .pipenum = __cpu_to_le32(3), 2185 }, 2186 { 2187 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2188 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2189 .pipenum = __cpu_to_le32(2), 2190 }, 2191 { 2192 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2193 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2194 .pipenum = __cpu_to_le32(3), 2195 }, 2196 { 2197 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2198 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2199 .pipenum = __cpu_to_le32(2), 2200 }, 2201 { 2202 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2203 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2204 .pipenum = __cpu_to_le32(3), 2205 }, 2206 { 2207 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2208 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2209 .pipenum = __cpu_to_le32(2), 2210 }, 2211 { 2212 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2213 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2214 .pipenum = __cpu_to_le32(3), 2215 }, 2216 { 2217 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2218 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2219 .pipenum = __cpu_to_le32(2), 2220 }, 2221 2222 { 2223 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2224 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2225 .pipenum = __cpu_to_le32(0), 2226 }, 2227 { 2228 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2229 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2230 .pipenum = __cpu_to_le32(1), 2231 }, 2232 2233 { 2234 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2235 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2236 .pipenum = __cpu_to_le32(0), 2237 }, 2238 { 2239 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2240 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2241 .pipenum = __cpu_to_le32(1), 2242 }, 2243 { 2244 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2245 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2246 .pipenum = __cpu_to_le32(4), 2247 }, 2248 { 2249 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2250 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2251 .pipenum = __cpu_to_le32(1), 2252 }, 2253 { 2254 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 2255 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2256 .pipenum = __cpu_to_le32(5), 2257 }, 2258 2259 /* (Additions here) */ 2260 2261 { /* terminator entry */ } 2262 }; 2263 2264 const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = { 2265 .ie1_reg_addr = CE_HOST_IE_ADDRESS, 2266 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, 2267 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, 2268 }; 2269 2270 const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = { 2271 .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2272 .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2273 .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2274 }; 2275 2276 const struct ce_remap ath11k_ce_remap_ipq5018 = { 2277 .base = HAL_IPQ5018_CE_WFSS_REG_BASE, 2278 .size = HAL_IPQ5018_CE_SIZE, 2279 }; 2280 2281 const struct ath11k_hw_regs ipq8074_regs = { 2282 /* SW2TCL(x) R0 ring configuration address */ 2283 .hal_tcl1_ring_base_lsb = 0x00000510, 2284 .hal_tcl1_ring_base_msb = 0x00000514, 2285 .hal_tcl1_ring_id = 0x00000518, 2286 .hal_tcl1_ring_misc = 0x00000520, 2287 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 2288 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 2289 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 2290 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 2291 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 2292 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 2293 .hal_tcl1_ring_msi1_data = 0x00000560, 2294 .hal_tcl2_ring_base_lsb = 0x00000568, 2295 .hal_tcl_ring_base_lsb = 0x00000618, 2296 2297 /* TCL STATUS ring address */ 2298 .hal_tcl_status_ring_base_lsb = 0x00000720, 2299 2300 /* REO2SW(x) R0 ring configuration address */ 2301 .hal_reo1_ring_base_lsb = 0x0000029c, 2302 .hal_reo1_ring_base_msb = 0x000002a0, 2303 .hal_reo1_ring_id = 0x000002a4, 2304 .hal_reo1_ring_misc = 0x000002ac, 2305 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2306 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2307 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2308 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2309 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2310 .hal_reo1_ring_msi1_data = 0x000002ec, 2311 .hal_reo2_ring_base_lsb = 0x000002f4, 2312 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2313 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2314 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2315 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2316 2317 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2318 .hal_reo1_ring_hp = 0x00003038, 2319 .hal_reo1_ring_tp = 0x0000303c, 2320 .hal_reo2_ring_hp = 0x00003040, 2321 2322 /* REO2TCL R0 ring configuration address */ 2323 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2324 .hal_reo_tcl_ring_hp = 0x00003058, 2325 2326 /* REO CMD ring address */ 2327 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2328 .hal_reo_cmd_ring_hp = 0x00003020, 2329 2330 /* REO status address */ 2331 .hal_reo_status_ring_base_lsb = 0x00000504, 2332 .hal_reo_status_hp = 0x00003070, 2333 2334 /* SW2REO ring address */ 2335 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2336 .hal_sw2reo_ring_hp = 0x00003028, 2337 2338 /* WCSS relative address */ 2339 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2340 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2341 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2342 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2343 2344 /* WBM Idle address */ 2345 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2346 .hal_wbm_idle_link_ring_misc = 0x00000870, 2347 2348 /* SW2WBM release address */ 2349 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2350 2351 /* WBM2SW release address */ 2352 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2353 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2354 2355 /* PCIe base address */ 2356 .pcie_qserdes_sysclk_en_sel = 0x0, 2357 .pcie_pcs_osc_dtct_config_base = 0x0, 2358 2359 /* Shadow register area */ 2360 .hal_shadow_base_addr = 0x0, 2361 2362 /* REO misc control register, not used in IPQ8074 */ 2363 .hal_reo1_misc_ctl = 0x0, 2364 }; 2365 2366 const struct ath11k_hw_regs qca6390_regs = { 2367 /* SW2TCL(x) R0 ring configuration address */ 2368 .hal_tcl1_ring_base_lsb = 0x00000684, 2369 .hal_tcl1_ring_base_msb = 0x00000688, 2370 .hal_tcl1_ring_id = 0x0000068c, 2371 .hal_tcl1_ring_misc = 0x00000694, 2372 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 2373 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 2374 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 2375 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 2376 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 2377 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 2378 .hal_tcl1_ring_msi1_data = 0x000006d4, 2379 .hal_tcl2_ring_base_lsb = 0x000006dc, 2380 .hal_tcl_ring_base_lsb = 0x0000078c, 2381 2382 /* TCL STATUS ring address */ 2383 .hal_tcl_status_ring_base_lsb = 0x00000894, 2384 2385 /* REO2SW(x) R0 ring configuration address */ 2386 .hal_reo1_ring_base_lsb = 0x00000244, 2387 .hal_reo1_ring_base_msb = 0x00000248, 2388 .hal_reo1_ring_id = 0x0000024c, 2389 .hal_reo1_ring_misc = 0x00000254, 2390 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2391 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2392 .hal_reo1_ring_producer_int_setup = 0x00000268, 2393 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2394 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2395 .hal_reo1_ring_msi1_data = 0x00000294, 2396 .hal_reo2_ring_base_lsb = 0x0000029c, 2397 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 2398 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 2399 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 2400 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 2401 2402 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2403 .hal_reo1_ring_hp = 0x00003030, 2404 .hal_reo1_ring_tp = 0x00003034, 2405 .hal_reo2_ring_hp = 0x00003038, 2406 2407 /* REO2TCL R0 ring configuration address */ 2408 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 2409 .hal_reo_tcl_ring_hp = 0x00003050, 2410 2411 /* REO CMD ring address */ 2412 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2413 .hal_reo_cmd_ring_hp = 0x00003020, 2414 2415 /* REO status address */ 2416 .hal_reo_status_ring_base_lsb = 0x000004ac, 2417 .hal_reo_status_hp = 0x00003068, 2418 2419 /* SW2REO ring address */ 2420 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2421 .hal_sw2reo_ring_hp = 0x00003028, 2422 2423 /* WCSS relative address */ 2424 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2425 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2426 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2427 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2428 2429 /* WBM Idle address */ 2430 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2431 .hal_wbm_idle_link_ring_misc = 0x00000870, 2432 2433 /* SW2WBM release address */ 2434 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2435 2436 /* WBM2SW release address */ 2437 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2438 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2439 2440 /* PCIe base address */ 2441 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2442 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2443 2444 /* Shadow register area */ 2445 .hal_shadow_base_addr = 0x000008fc, 2446 2447 /* REO misc control register, not used in QCA6390 */ 2448 .hal_reo1_misc_ctl = 0x0, 2449 }; 2450 2451 const struct ath11k_hw_regs qcn9074_regs = { 2452 /* SW2TCL(x) R0 ring configuration address */ 2453 .hal_tcl1_ring_base_lsb = 0x000004f0, 2454 .hal_tcl1_ring_base_msb = 0x000004f4, 2455 .hal_tcl1_ring_id = 0x000004f8, 2456 .hal_tcl1_ring_misc = 0x00000500, 2457 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 2458 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 2459 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 2460 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 2461 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 2462 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 2463 .hal_tcl1_ring_msi1_data = 0x00000540, 2464 .hal_tcl2_ring_base_lsb = 0x00000548, 2465 .hal_tcl_ring_base_lsb = 0x000005f8, 2466 2467 /* TCL STATUS ring address */ 2468 .hal_tcl_status_ring_base_lsb = 0x00000700, 2469 2470 /* REO2SW(x) R0 ring configuration address */ 2471 .hal_reo1_ring_base_lsb = 0x0000029c, 2472 .hal_reo1_ring_base_msb = 0x000002a0, 2473 .hal_reo1_ring_id = 0x000002a4, 2474 .hal_reo1_ring_misc = 0x000002ac, 2475 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2476 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2477 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2478 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2479 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2480 .hal_reo1_ring_msi1_data = 0x000002ec, 2481 .hal_reo2_ring_base_lsb = 0x000002f4, 2482 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2483 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2484 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2485 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2486 2487 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2488 .hal_reo1_ring_hp = 0x00003038, 2489 .hal_reo1_ring_tp = 0x0000303c, 2490 .hal_reo2_ring_hp = 0x00003040, 2491 2492 /* REO2TCL R0 ring configuration address */ 2493 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2494 .hal_reo_tcl_ring_hp = 0x00003058, 2495 2496 /* REO CMD ring address */ 2497 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2498 .hal_reo_cmd_ring_hp = 0x00003020, 2499 2500 /* REO status address */ 2501 .hal_reo_status_ring_base_lsb = 0x00000504, 2502 .hal_reo_status_hp = 0x00003070, 2503 2504 /* SW2REO ring address */ 2505 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2506 .hal_sw2reo_ring_hp = 0x00003028, 2507 2508 /* WCSS relative address */ 2509 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2510 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2511 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2512 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2513 2514 /* WBM Idle address */ 2515 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2516 .hal_wbm_idle_link_ring_misc = 0x00000884, 2517 2518 /* SW2WBM release address */ 2519 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2520 2521 /* WBM2SW release address */ 2522 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2523 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2524 2525 /* PCIe base address */ 2526 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2527 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2528 2529 /* Shadow register area */ 2530 .hal_shadow_base_addr = 0x0, 2531 2532 /* REO misc control register, not used in QCN9074 */ 2533 .hal_reo1_misc_ctl = 0x0, 2534 }; 2535 2536 const struct ath11k_hw_regs wcn6855_regs = { 2537 /* SW2TCL(x) R0 ring configuration address */ 2538 .hal_tcl1_ring_base_lsb = 0x00000690, 2539 .hal_tcl1_ring_base_msb = 0x00000694, 2540 .hal_tcl1_ring_id = 0x00000698, 2541 .hal_tcl1_ring_misc = 0x000006a0, 2542 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2543 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2544 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2545 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2546 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2547 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2548 .hal_tcl1_ring_msi1_data = 0x000006e0, 2549 .hal_tcl2_ring_base_lsb = 0x000006e8, 2550 .hal_tcl_ring_base_lsb = 0x00000798, 2551 2552 /* TCL STATUS ring address */ 2553 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2554 2555 /* REO2SW(x) R0 ring configuration address */ 2556 .hal_reo1_ring_base_lsb = 0x00000244, 2557 .hal_reo1_ring_base_msb = 0x00000248, 2558 .hal_reo1_ring_id = 0x0000024c, 2559 .hal_reo1_ring_misc = 0x00000254, 2560 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2561 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2562 .hal_reo1_ring_producer_int_setup = 0x00000268, 2563 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2564 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2565 .hal_reo1_ring_msi1_data = 0x00000294, 2566 .hal_reo2_ring_base_lsb = 0x0000029c, 2567 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2568 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2569 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2570 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2571 2572 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2573 .hal_reo1_ring_hp = 0x00003030, 2574 .hal_reo1_ring_tp = 0x00003034, 2575 .hal_reo2_ring_hp = 0x00003038, 2576 2577 /* REO2TCL R0 ring configuration address */ 2578 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2579 .hal_reo_tcl_ring_hp = 0x00003060, 2580 2581 /* REO CMD ring address */ 2582 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2583 .hal_reo_cmd_ring_hp = 0x00003020, 2584 2585 /* REO status address */ 2586 .hal_reo_status_ring_base_lsb = 0x0000055c, 2587 .hal_reo_status_hp = 0x00003078, 2588 2589 /* SW2REO ring address */ 2590 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2591 .hal_sw2reo_ring_hp = 0x00003028, 2592 2593 /* WCSS relative address */ 2594 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2595 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2596 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2597 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2598 2599 /* WBM Idle address */ 2600 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2601 .hal_wbm_idle_link_ring_misc = 0x00000880, 2602 2603 /* SW2WBM release address */ 2604 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2605 2606 /* WBM2SW release address */ 2607 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2608 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2609 2610 /* PCIe base address */ 2611 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2612 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2613 2614 /* Shadow register area */ 2615 .hal_shadow_base_addr = 0x000008fc, 2616 2617 /* REO misc control register, used for fragment 2618 * destination ring config in WCN6855. 2619 */ 2620 .hal_reo1_misc_ctl = 0x00000630, 2621 }; 2622 2623 const struct ath11k_hw_regs wcn6750_regs = { 2624 /* SW2TCL(x) R0 ring configuration address */ 2625 .hal_tcl1_ring_base_lsb = 0x00000694, 2626 .hal_tcl1_ring_base_msb = 0x00000698, 2627 .hal_tcl1_ring_id = 0x0000069c, 2628 .hal_tcl1_ring_misc = 0x000006a4, 2629 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2630 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2631 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2632 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2633 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2634 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2635 .hal_tcl1_ring_msi1_data = 0x000006e4, 2636 .hal_tcl2_ring_base_lsb = 0x000006ec, 2637 .hal_tcl_ring_base_lsb = 0x0000079c, 2638 2639 /* TCL STATUS ring address */ 2640 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2641 2642 /* REO2SW(x) R0 ring configuration address */ 2643 .hal_reo1_ring_base_lsb = 0x000001ec, 2644 .hal_reo1_ring_base_msb = 0x000001f0, 2645 .hal_reo1_ring_id = 0x000001f4, 2646 .hal_reo1_ring_misc = 0x000001fc, 2647 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2648 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2649 .hal_reo1_ring_producer_int_setup = 0x00000210, 2650 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2651 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2652 .hal_reo1_ring_msi1_data = 0x0000023c, 2653 .hal_reo2_ring_base_lsb = 0x00000244, 2654 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2655 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2656 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2657 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2658 2659 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2660 .hal_reo1_ring_hp = 0x00003028, 2661 .hal_reo1_ring_tp = 0x0000302c, 2662 .hal_reo2_ring_hp = 0x00003030, 2663 2664 /* REO2TCL R0 ring configuration address */ 2665 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2666 .hal_reo_tcl_ring_hp = 0x00003058, 2667 2668 /* REO CMD ring address */ 2669 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2670 .hal_reo_cmd_ring_hp = 0x00003010, 2671 2672 /* REO status address */ 2673 .hal_reo_status_ring_base_lsb = 0x00000504, 2674 .hal_reo_status_hp = 0x00003070, 2675 2676 /* SW2REO ring address */ 2677 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2678 .hal_sw2reo_ring_hp = 0x00003018, 2679 2680 /* WCSS relative address */ 2681 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2682 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2683 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2684 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2685 2686 /* WBM Idle address */ 2687 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2688 .hal_wbm_idle_link_ring_misc = 0x00000884, 2689 2690 /* SW2WBM release address */ 2691 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2692 2693 /* WBM2SW release address */ 2694 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2695 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2696 2697 /* PCIe base address */ 2698 .pcie_qserdes_sysclk_en_sel = 0x0, 2699 .pcie_pcs_osc_dtct_config_base = 0x0, 2700 2701 /* Shadow register area */ 2702 .hal_shadow_base_addr = 0x00000504, 2703 2704 /* REO misc control register, used for fragment 2705 * destination ring config in WCN6750. 2706 */ 2707 .hal_reo1_misc_ctl = 0x000005d8, 2708 }; 2709 2710 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = { 2711 { 2712 .tcl_ring_num = 0, 2713 .wbm_ring_num = 0, 2714 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2715 }, 2716 { 2717 .tcl_ring_num = 1, 2718 .wbm_ring_num = 1, 2719 .rbm_id = HAL_RX_BUF_RBM_SW1_BM, 2720 }, 2721 { 2722 .tcl_ring_num = 2, 2723 .wbm_ring_num = 2, 2724 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2725 }, 2726 }; 2727 2728 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = { 2729 { 2730 .tcl_ring_num = 0, 2731 .wbm_ring_num = 0, 2732 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2733 }, 2734 { 2735 .tcl_ring_num = 1, 2736 .wbm_ring_num = 4, 2737 .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 2738 }, 2739 { 2740 .tcl_ring_num = 2, 2741 .wbm_ring_num = 2, 2742 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2743 }, 2744 }; 2745 2746 const struct ath11k_hw_regs ipq5018_regs = { 2747 /* SW2TCL(x) R0 ring configuration address */ 2748 .hal_tcl1_ring_base_lsb = 0x00000694, 2749 .hal_tcl1_ring_base_msb = 0x00000698, 2750 .hal_tcl1_ring_id = 0x0000069c, 2751 .hal_tcl1_ring_misc = 0x000006a4, 2752 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2753 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2754 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2755 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2756 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2757 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2758 .hal_tcl1_ring_msi1_data = 0x000006e4, 2759 .hal_tcl2_ring_base_lsb = 0x000006ec, 2760 .hal_tcl_ring_base_lsb = 0x0000079c, 2761 2762 /* TCL STATUS ring address */ 2763 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2764 2765 /* REO2SW(x) R0 ring configuration address */ 2766 .hal_reo1_ring_base_lsb = 0x000001ec, 2767 .hal_reo1_ring_base_msb = 0x000001f0, 2768 .hal_reo1_ring_id = 0x000001f4, 2769 .hal_reo1_ring_misc = 0x000001fc, 2770 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2771 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2772 .hal_reo1_ring_producer_int_setup = 0x00000210, 2773 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2774 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2775 .hal_reo1_ring_msi1_data = 0x0000023c, 2776 .hal_reo2_ring_base_lsb = 0x00000244, 2777 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2778 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2779 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2780 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2781 2782 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2783 .hal_reo1_ring_hp = 0x00003028, 2784 .hal_reo1_ring_tp = 0x0000302c, 2785 .hal_reo2_ring_hp = 0x00003030, 2786 2787 /* REO2TCL R0 ring configuration address */ 2788 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2789 .hal_reo_tcl_ring_hp = 0x00003058, 2790 2791 /* SW2REO ring address */ 2792 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2793 .hal_sw2reo_ring_hp = 0x00003018, 2794 2795 /* REO CMD ring address */ 2796 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2797 .hal_reo_cmd_ring_hp = 0x00003010, 2798 2799 /* REO status address */ 2800 .hal_reo_status_ring_base_lsb = 0x00000504, 2801 .hal_reo_status_hp = 0x00003070, 2802 2803 /* WCSS relative address */ 2804 .hal_seq_wcss_umac_ce0_src_reg = 0x08400000 2805 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2806 .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000 2807 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2808 .hal_seq_wcss_umac_ce1_src_reg = 0x08402000 2809 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2810 .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000 2811 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2812 2813 /* WBM Idle address */ 2814 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2815 .hal_wbm_idle_link_ring_misc = 0x00000884, 2816 2817 /* SW2WBM release address */ 2818 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2819 2820 /* WBM2SW release address */ 2821 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2822 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2823 }; 2824 2825 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2826 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2827 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2828 }; 2829 2830 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2831 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2832 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2833 }; 2834 2835 const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = { 2836 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2837 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750, 2838 }; 2839 2840 static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = { 2841 {.start_freq = 2402, .end_freq = 2482 }, /* 2G ch1~ch13 */ 2842 {.start_freq = 5150, .end_freq = 5250 }, /* 5G UNII-1 ch32~ch48 */ 2843 {.start_freq = 5250, .end_freq = 5725 }, /* 5G UNII-2 ch50~ch144 */ 2844 {.start_freq = 5725, .end_freq = 5810 }, /* 5G UNII-3 ch149~ch161 */ 2845 {.start_freq = 5815, .end_freq = 5895 }, /* 5G UNII-4 ch163~ch177 */ 2846 {.start_freq = 5925, .end_freq = 6165 }, /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */ 2847 {.start_freq = 6165, .end_freq = 6425 }, /* 6G UNII-5 ch45~ch93 */ 2848 {.start_freq = 6425, .end_freq = 6525 }, /* 6G UNII-6 ch97~ch113 */ 2849 {.start_freq = 6525, .end_freq = 6705 }, /* 6G UNII-7 ch117~ch149 */ 2850 {.start_freq = 6705, .end_freq = 6875 }, /* 6G UNII-7 ch153~ch185 */ 2851 {.start_freq = 6875, .end_freq = 7125 }, /* 6G UNII-8 ch189~ch233 */ 2852 }; 2853 2854 const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = { 2855 .type = NL80211_SAR_TYPE_POWER, 2856 .num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)), 2857 .freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855, 2858 }; 2859