1*dd4f32aeSBjoern A. Zeeb // SPDX-License-Identifier: BSD-3-Clause-Clear 2*dd4f32aeSBjoern A. Zeeb /* 3*dd4f32aeSBjoern A. Zeeb * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4*dd4f32aeSBjoern A. Zeeb */ 5*dd4f32aeSBjoern A. Zeeb 6*dd4f32aeSBjoern A. Zeeb #include "hal_desc.h" 7*dd4f32aeSBjoern A. Zeeb #include "hal.h" 8*dd4f32aeSBjoern A. Zeeb #include "hal_tx.h" 9*dd4f32aeSBjoern A. Zeeb #include "hif.h" 10*dd4f32aeSBjoern A. Zeeb 11*dd4f32aeSBjoern A. Zeeb #define DSCP_TID_MAP_TBL_ENTRY_SIZE 64 12*dd4f32aeSBjoern A. Zeeb 13*dd4f32aeSBjoern A. Zeeb /* dscp_tid_map - Default DSCP-TID mapping 14*dd4f32aeSBjoern A. Zeeb * 15*dd4f32aeSBjoern A. Zeeb * DSCP TID 16*dd4f32aeSBjoern A. Zeeb * 000000 0 17*dd4f32aeSBjoern A. Zeeb * 001000 1 18*dd4f32aeSBjoern A. Zeeb * 010000 2 19*dd4f32aeSBjoern A. Zeeb * 011000 3 20*dd4f32aeSBjoern A. Zeeb * 100000 4 21*dd4f32aeSBjoern A. Zeeb * 101000 5 22*dd4f32aeSBjoern A. Zeeb * 110000 6 23*dd4f32aeSBjoern A. Zeeb * 111000 7 24*dd4f32aeSBjoern A. Zeeb */ 25*dd4f32aeSBjoern A. Zeeb static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = { 26*dd4f32aeSBjoern A. Zeeb 0, 0, 0, 0, 0, 0, 0, 0, 27*dd4f32aeSBjoern A. Zeeb 1, 1, 1, 1, 1, 1, 1, 1, 28*dd4f32aeSBjoern A. Zeeb 2, 2, 2, 2, 2, 2, 2, 2, 29*dd4f32aeSBjoern A. Zeeb 3, 3, 3, 3, 3, 3, 3, 3, 30*dd4f32aeSBjoern A. Zeeb 4, 4, 4, 4, 4, 4, 4, 4, 31*dd4f32aeSBjoern A. Zeeb 5, 5, 5, 5, 5, 5, 5, 5, 32*dd4f32aeSBjoern A. Zeeb 6, 6, 6, 6, 6, 6, 6, 6, 33*dd4f32aeSBjoern A. Zeeb 7, 7, 7, 7, 7, 7, 7, 7, 34*dd4f32aeSBjoern A. Zeeb }; 35*dd4f32aeSBjoern A. Zeeb 36*dd4f32aeSBjoern A. Zeeb void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd, 37*dd4f32aeSBjoern A. Zeeb struct hal_tx_info *ti) 38*dd4f32aeSBjoern A. Zeeb { 39*dd4f32aeSBjoern A. Zeeb struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd; 40*dd4f32aeSBjoern A. Zeeb 41*dd4f32aeSBjoern A. Zeeb tcl_cmd->buf_addr_info.info0 = 42*dd4f32aeSBjoern A. Zeeb FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); 43*dd4f32aeSBjoern A. Zeeb tcl_cmd->buf_addr_info.info1 = 44*dd4f32aeSBjoern A. Zeeb FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 45*dd4f32aeSBjoern A. Zeeb ((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT)); 46*dd4f32aeSBjoern A. Zeeb tcl_cmd->buf_addr_info.info1 |= 47*dd4f32aeSBjoern A. Zeeb FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, 48*dd4f32aeSBjoern A. Zeeb (ti->ring_id + HAL_RX_BUF_RBM_SW0_BM)) | 49*dd4f32aeSBjoern A. Zeeb FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); 50*dd4f32aeSBjoern A. Zeeb 51*dd4f32aeSBjoern A. Zeeb tcl_cmd->info0 = 52*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | 53*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | 54*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, 55*dd4f32aeSBjoern A. Zeeb ti->encrypt_type) | 56*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, 57*dd4f32aeSBjoern A. Zeeb ti->search_type) | 58*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, 59*dd4f32aeSBjoern A. Zeeb ti->addr_search_flags) | 60*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, 61*dd4f32aeSBjoern A. Zeeb ti->meta_data_flags); 62*dd4f32aeSBjoern A. Zeeb 63*dd4f32aeSBjoern A. Zeeb tcl_cmd->info1 = ti->flags0 | 64*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) | 65*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset); 66*dd4f32aeSBjoern A. Zeeb 67*dd4f32aeSBjoern A. Zeeb tcl_cmd->info2 = ti->flags1 | 68*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) | 69*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id); 70*dd4f32aeSBjoern A. Zeeb 71*dd4f32aeSBjoern A. Zeeb tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX, 72*dd4f32aeSBjoern A. Zeeb ti->dscp_tid_tbl_idx) | 73*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX, 74*dd4f32aeSBjoern A. Zeeb ti->bss_ast_idx) | 75*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM, 76*dd4f32aeSBjoern A. Zeeb ti->bss_ast_hash); 77*dd4f32aeSBjoern A. Zeeb tcl_cmd->info4 = 0; 78*dd4f32aeSBjoern A. Zeeb 79*dd4f32aeSBjoern A. Zeeb if (ti->enable_mesh) 80*dd4f32aeSBjoern A. Zeeb ab->hw_params.hw_ops->tx_mesh_enable(ab, tcl_cmd); 81*dd4f32aeSBjoern A. Zeeb } 82*dd4f32aeSBjoern A. Zeeb 83*dd4f32aeSBjoern A. Zeeb void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id) 84*dd4f32aeSBjoern A. Zeeb { 85*dd4f32aeSBjoern A. Zeeb u32 ctrl_reg_val; 86*dd4f32aeSBjoern A. Zeeb u32 addr; 87*dd4f32aeSBjoern A. Zeeb u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE]; 88*dd4f32aeSBjoern A. Zeeb int i; 89*dd4f32aeSBjoern A. Zeeb u32 value; 90*dd4f32aeSBjoern A. Zeeb int cnt = 0; 91*dd4f32aeSBjoern A. Zeeb 92*dd4f32aeSBjoern A. Zeeb ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 93*dd4f32aeSBjoern A. Zeeb HAL_TCL1_RING_CMN_CTRL_REG); 94*dd4f32aeSBjoern A. Zeeb /* Enable read/write access */ 95*dd4f32aeSBjoern A. Zeeb ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 96*dd4f32aeSBjoern A. Zeeb ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 97*dd4f32aeSBjoern A. Zeeb HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val); 98*dd4f32aeSBjoern A. Zeeb 99*dd4f32aeSBjoern A. Zeeb addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + 100*dd4f32aeSBjoern A. Zeeb (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4)); 101*dd4f32aeSBjoern A. Zeeb 102*dd4f32aeSBjoern A. Zeeb /* Configure each DSCP-TID mapping in three bits there by configure 103*dd4f32aeSBjoern A. Zeeb * three bytes in an iteration. 104*dd4f32aeSBjoern A. Zeeb */ 105*dd4f32aeSBjoern A. Zeeb for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) { 106*dd4f32aeSBjoern A. Zeeb value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0, 107*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i]) | 108*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1, 109*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 1]) | 110*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2, 111*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 2]) | 112*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3, 113*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 3]) | 114*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4, 115*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 4]) | 116*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5, 117*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 5]) | 118*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6, 119*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 6]) | 120*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7, 121*dd4f32aeSBjoern A. Zeeb dscp_tid_map[i + 7]); 122*dd4f32aeSBjoern A. Zeeb memcpy(&hw_map_val[cnt], (u8 *)&value, 3); 123*dd4f32aeSBjoern A. Zeeb cnt += 3; 124*dd4f32aeSBjoern A. Zeeb } 125*dd4f32aeSBjoern A. Zeeb 126*dd4f32aeSBjoern A. Zeeb for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) { 127*dd4f32aeSBjoern A. Zeeb ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]); 128*dd4f32aeSBjoern A. Zeeb addr += 4; 129*dd4f32aeSBjoern A. Zeeb } 130*dd4f32aeSBjoern A. Zeeb 131*dd4f32aeSBjoern A. Zeeb /* Disable read/write access */ 132*dd4f32aeSBjoern A. Zeeb ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 133*dd4f32aeSBjoern A. Zeeb HAL_TCL1_RING_CMN_CTRL_REG); 134*dd4f32aeSBjoern A. Zeeb ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 135*dd4f32aeSBjoern A. Zeeb ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 136*dd4f32aeSBjoern A. Zeeb HAL_TCL1_RING_CMN_CTRL_REG, 137*dd4f32aeSBjoern A. Zeeb ctrl_reg_val); 138*dd4f32aeSBjoern A. Zeeb } 139*dd4f32aeSBjoern A. Zeeb 140*dd4f32aeSBjoern A. Zeeb void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng) 141*dd4f32aeSBjoern A. Zeeb { 142*dd4f32aeSBjoern A. Zeeb struct hal_srng_params params; 143*dd4f32aeSBjoern A. Zeeb struct hal_tlv_hdr *tlv; 144*dd4f32aeSBjoern A. Zeeb int i, entry_size; 145*dd4f32aeSBjoern A. Zeeb u8 *desc; 146*dd4f32aeSBjoern A. Zeeb 147*dd4f32aeSBjoern A. Zeeb memset(¶ms, 0, sizeof(params)); 148*dd4f32aeSBjoern A. Zeeb 149*dd4f32aeSBjoern A. Zeeb entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_TCL_DATA); 150*dd4f32aeSBjoern A. Zeeb ath11k_hal_srng_get_params(ab, srng, ¶ms); 151*dd4f32aeSBjoern A. Zeeb desc = (u8 *)params.ring_base_vaddr; 152*dd4f32aeSBjoern A. Zeeb 153*dd4f32aeSBjoern A. Zeeb for (i = 0; i < params.num_entries; i++) { 154*dd4f32aeSBjoern A. Zeeb tlv = (struct hal_tlv_hdr *)desc; 155*dd4f32aeSBjoern A. Zeeb tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) | 156*dd4f32aeSBjoern A. Zeeb FIELD_PREP(HAL_TLV_HDR_LEN, 157*dd4f32aeSBjoern A. Zeeb sizeof(struct hal_tcl_data_cmd)); 158*dd4f32aeSBjoern A. Zeeb desc += entry_size; 159*dd4f32aeSBjoern A. Zeeb } 160*dd4f32aeSBjoern A. Zeeb } 161