1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "debug.h" 7 #include "hal.h" 8 #include "hal_tx.h" 9 #include "hal_rx.h" 10 #include "hal_desc.h" 11 #include "hif.h" 12 13 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 14 u8 owner, u8 buffer_type, u32 magic) 15 { 16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | 17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); 18 19 /* Magic pattern in reserved bits for debugging */ 20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); 21 } 22 23 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv, 24 struct ath11k_hal_reo_cmd *cmd) 25 { 26 struct hal_reo_get_queue_stats *desc; 27 28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | 29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 30 31 desc = (struct hal_reo_get_queue_stats *)tlv->value; 32 memset_startat(desc, 0, queue_addr_lo); 33 34 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 35 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 36 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 37 38 desc->queue_addr_lo = cmd->addr_lo; 39 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, 40 cmd->addr_hi); 41 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 42 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS; 43 44 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 45 } 46 47 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv, 48 struct ath11k_hal_reo_cmd *cmd) 49 { 50 struct hal_reo_flush_cache *desc; 51 u8 avail_slot = ffz(hal->avail_blk_resource); 52 53 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 54 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 55 return -ENOSPC; 56 57 hal->current_blk_index = avail_slot; 58 } 59 60 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | 61 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 62 63 desc = (struct hal_reo_flush_cache *)tlv->value; 64 memset_startat(desc, 0, cache_addr_lo); 65 66 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 67 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 68 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 69 70 desc->cache_addr_lo = cmd->addr_lo; 71 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, 72 cmd->addr_hi); 73 74 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 75 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS; 76 77 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 78 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE; 79 desc->info0 |= 80 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, 81 avail_slot); 82 } 83 84 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 85 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE; 86 87 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 88 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL; 89 90 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 91 } 92 93 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv, 94 struct ath11k_hal_reo_cmd *cmd) 95 { 96 struct hal_reo_update_rx_queue *desc; 97 98 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) | 99 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 100 101 desc = (struct hal_reo_update_rx_queue *)tlv->value; 102 memset_startat(desc, 0, queue_addr_lo); 103 104 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 105 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 106 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 107 108 desc->queue_addr_lo = cmd->addr_lo; 109 desc->info0 = 110 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI, 111 cmd->addr_hi) | 112 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM, 113 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) | 114 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD, 115 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) | 116 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT, 117 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) | 118 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION, 119 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) | 120 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN, 121 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) | 122 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC, 123 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) | 124 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR, 125 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) | 126 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY, 127 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) | 128 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE, 129 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) | 130 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE, 131 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) | 132 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE, 133 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) | 134 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK, 135 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) | 136 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN, 137 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) | 138 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN, 139 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) | 140 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE, 141 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) | 142 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE, 143 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) | 144 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG, 145 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) | 146 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD, 147 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) | 148 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN, 149 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) | 150 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR, 151 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) | 152 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID, 153 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) | 154 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN, 155 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN)); 156 157 desc->info1 = 158 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER, 159 cmd->rx_queue_num) | 160 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD, 161 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) | 162 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER, 163 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) | 164 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION, 165 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) | 166 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN, 167 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) | 168 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC, 169 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) | 170 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR, 171 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) | 172 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE, 173 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) | 174 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY, 175 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) | 176 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE, 177 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) | 178 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK, 179 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) | 180 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN, 181 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) | 182 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN, 183 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) | 184 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE, 185 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) | 186 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG, 187 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG)); 188 189 if (cmd->pn_size == 24) 190 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 191 else if (cmd->pn_size == 48) 192 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 193 else if (cmd->pn_size == 128) 194 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 195 196 if (cmd->ba_window_size < 1) 197 cmd->ba_window_size = 1; 198 199 if (cmd->ba_window_size == 1) 200 cmd->ba_window_size++; 201 202 desc->info2 = 203 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE, 204 cmd->ba_window_size - 1) | 205 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) | 206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD, 207 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) | 208 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN, 209 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) | 210 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR, 211 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) | 212 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR, 213 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR)); 214 215 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 216 } 217 218 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng, 219 enum hal_reo_cmd_type type, 220 struct ath11k_hal_reo_cmd *cmd) 221 { 222 struct hal_tlv_hdr *reo_desc; 223 int ret; 224 225 spin_lock_bh(&srng->lock); 226 227 ath11k_hal_srng_access_begin(ab, srng); 228 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng); 229 if (!reo_desc) { 230 ret = -ENOBUFS; 231 goto out; 232 } 233 234 switch (type) { 235 case HAL_REO_CMD_GET_QUEUE_STATS: 236 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd); 237 break; 238 case HAL_REO_CMD_FLUSH_CACHE: 239 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd); 240 break; 241 case HAL_REO_CMD_UPDATE_RX_QUEUE: 242 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd); 243 break; 244 case HAL_REO_CMD_FLUSH_QUEUE: 245 case HAL_REO_CMD_UNBLOCK_CACHE: 246 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 247 ath11k_warn(ab, "Unsupported reo command %d\n", type); 248 ret = -ENOTSUPP; 249 break; 250 default: 251 ath11k_warn(ab, "Unknown reo command %d\n", type); 252 ret = -EINVAL; 253 break; 254 } 255 256 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer); 257 258 out: 259 ath11k_hal_srng_access_end(ab, srng); 260 spin_unlock_bh(&srng->lock); 261 262 return ret; 263 } 264 265 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr, 266 u32 cookie, u8 manager) 267 { 268 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc; 269 u32 paddr_lo, paddr_hi; 270 271 paddr_lo = lower_32_bits(paddr); 272 paddr_hi = upper_32_bits(paddr); 273 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo); 274 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) | 275 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) | 276 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager); 277 } 278 279 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr, 280 u32 *cookie, u8 *rbm) 281 { 282 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc; 283 284 *paddr = 285 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) | 286 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0); 287 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1); 288 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1); 289 } 290 291 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus, 292 u32 *msdu_cookies, 293 enum hal_rx_buf_return_buf_manager *rbm) 294 { 295 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc; 296 struct hal_rx_msdu_details *msdu; 297 int i; 298 299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 300 301 msdu = &link->msdu_link[0]; 302 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 303 msdu->buf_addr_info.info1); 304 305 for (i = 0; i < *num_msdus; i++) { 306 msdu = &link->msdu_link[i]; 307 308 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 309 msdu->buf_addr_info.info0)) { 310 *num_msdus = i; 311 break; 312 } 313 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 314 msdu->buf_addr_info.info1); 315 msdu_cookies++; 316 } 317 } 318 319 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc, 320 dma_addr_t *paddr, u32 *desc_bank) 321 { 322 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc; 323 enum hal_reo_dest_ring_push_reason push_reason; 324 enum hal_reo_dest_ring_error_code err_code; 325 326 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 327 desc->info0); 328 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE, 329 desc->info0); 330 ab->soc_stats.reo_error[err_code]++; 331 332 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 333 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 334 ath11k_warn(ab, "expected error push reason code, received %d\n", 335 push_reason); 336 return -EINVAL; 337 } 338 339 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) != 340 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) { 341 ath11k_warn(ab, "expected buffer type link_desc"); 342 return -EINVAL; 343 } 344 345 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank); 346 347 return 0; 348 } 349 350 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc, 351 struct hal_rx_wbm_rel_info *rel_info) 352 { 353 struct hal_wbm_release_ring *wbm_desc = desc; 354 enum hal_wbm_rel_desc_type type; 355 enum hal_wbm_rel_src_module rel_src; 356 enum hal_rx_buf_return_buf_manager ret_buf_mgr; 357 358 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 359 wbm_desc->info0); 360 /* We expect only WBM_REL buffer type */ 361 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 362 WARN_ON(1); 363 return -EINVAL; 364 } 365 366 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 367 wbm_desc->info0); 368 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 369 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 370 return -EINVAL; 371 372 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 373 wbm_desc->buf_addr_info.info1); 374 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) { 375 ab->soc_stats.invalid_rbm++; 376 return -EINVAL; 377 } 378 379 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 380 wbm_desc->buf_addr_info.info1); 381 rel_info->err_rel_src = rel_src; 382 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 383 rel_info->push_reason = 384 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON, 385 wbm_desc->info0); 386 rel_info->err_code = 387 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE, 388 wbm_desc->info0); 389 } else { 390 rel_info->push_reason = 391 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON, 392 wbm_desc->info0); 393 rel_info->err_code = 394 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE, 395 wbm_desc->info0); 396 } 397 398 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU, 399 wbm_desc->info2); 400 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU, 401 wbm_desc->info2); 402 return 0; 403 } 404 405 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc, 406 dma_addr_t *paddr, u32 *desc_bank) 407 { 408 struct ath11k_buffer_addr *buff_addr = desc; 409 410 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) | 411 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0); 412 413 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1); 414 } 415 416 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc, 417 void *link_desc, 418 enum hal_wbm_rel_bm_act action) 419 { 420 struct hal_wbm_release_ring *dst_desc = desc; 421 struct hal_wbm_release_ring *src_desc = link_desc; 422 423 dst_desc->buf_addr_info = src_desc->buf_addr_info; 424 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 425 HAL_WBM_REL_SRC_MODULE_SW) | 426 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) | 427 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 428 HAL_WBM_REL_DESC_TYPE_MSDU_LINK); 429 } 430 431 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc, 432 struct hal_reo_status *status) 433 { 434 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 435 struct hal_reo_get_queue_stats_status *desc = 436 (struct hal_reo_get_queue_stats_status *)tlv->value; 437 438 status->uniform_hdr.cmd_num = 439 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 440 desc->hdr.info0); 441 status->uniform_hdr.cmd_status = 442 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 443 desc->hdr.info0); 444 445 ath11k_dbg(ab, ATH11k_DBG_HAL, "Queue stats status:\n"); 446 ath11k_dbg(ab, ATH11k_DBG_HAL, "header: cmd_num %d status %d\n", 447 status->uniform_hdr.cmd_num, 448 status->uniform_hdr.cmd_status); 449 ath11k_dbg(ab, ATH11k_DBG_HAL, "ssn %ld cur_idx %ld\n", 450 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN, 451 desc->info0), 452 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX, 453 desc->info0)); 454 ath11k_dbg(ab, ATH11k_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 455 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 456 ath11k_dbg(ab, ATH11k_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 457 desc->last_rx_enqueue_timestamp, 458 desc->last_rx_dequeue_timestamp); 459 ath11k_dbg(ab, ATH11k_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 460 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 461 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 462 desc->rx_bitmap[6], desc->rx_bitmap[7]); 463 ath11k_dbg(ab, ATH11k_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n", 464 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT, 465 desc->info1), 466 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT, 467 desc->info1)); 468 ath11k_dbg(ab, ATH11k_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n", 469 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT, 470 desc->info2), 471 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT, 472 desc->info2), 473 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT, 474 desc->info2)); 475 ath11k_dbg(ab, ATH11k_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n", 476 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT, 477 desc->info3), 478 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT, 479 desc->info3)); 480 ath11k_dbg(ab, ATH11k_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 481 desc->num_mpdu_frames, desc->num_msdu_frames, 482 desc->total_bytes); 483 ath11k_dbg(ab, ATH11k_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n", 484 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU, 485 desc->info4), 486 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K, 487 desc->info4), 488 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT, 489 desc->info4)); 490 ath11k_dbg(ab, ATH11k_DBG_HAL, "looping count %ld\n", 491 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT, 492 desc->info5)); 493 } 494 495 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status) 496 { 497 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 498 struct hal_reo_status_hdr *hdr; 499 500 hdr = (struct hal_reo_status_hdr *)tlv->value; 501 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0); 502 503 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0); 504 } 505 506 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc, 507 struct hal_reo_status *status) 508 { 509 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 510 struct hal_reo_flush_queue_status *desc = 511 (struct hal_reo_flush_queue_status *)tlv->value; 512 513 status->uniform_hdr.cmd_num = 514 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 515 desc->hdr.info0); 516 status->uniform_hdr.cmd_status = 517 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 518 desc->hdr.info0); 519 status->u.flush_queue.err_detected = 520 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED, 521 desc->info0); 522 } 523 524 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, 525 struct hal_reo_status *status) 526 { 527 struct ath11k_hal *hal = &ab->hal; 528 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 529 struct hal_reo_flush_cache_status *desc = 530 (struct hal_reo_flush_cache_status *)tlv->value; 531 532 status->uniform_hdr.cmd_num = 533 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 534 desc->hdr.info0); 535 status->uniform_hdr.cmd_status = 536 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 537 desc->hdr.info0); 538 539 status->u.flush_cache.err_detected = 540 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR, 541 desc->info0); 542 status->u.flush_cache.err_code = 543 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE, 544 desc->info0); 545 if (!status->u.flush_cache.err_code) 546 hal->avail_blk_resource |= BIT(hal->current_blk_index); 547 548 status->u.flush_cache.cache_controller_flush_status_hit = 549 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT, 550 desc->info0); 551 552 status->u.flush_cache.cache_controller_flush_status_desc_type = 553 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE, 554 desc->info0); 555 status->u.flush_cache.cache_controller_flush_status_client_id = 556 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID, 557 desc->info0); 558 status->u.flush_cache.cache_controller_flush_status_err = 559 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR, 560 desc->info0); 561 status->u.flush_cache.cache_controller_flush_status_cnt = 562 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT, 563 desc->info0); 564 } 565 566 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc, 567 struct hal_reo_status *status) 568 { 569 struct ath11k_hal *hal = &ab->hal; 570 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 571 struct hal_reo_unblock_cache_status *desc = 572 (struct hal_reo_unblock_cache_status *)tlv->value; 573 574 status->uniform_hdr.cmd_num = 575 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 576 desc->hdr.info0); 577 status->uniform_hdr.cmd_status = 578 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 579 desc->hdr.info0); 580 581 status->u.unblock_cache.err_detected = 582 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR, 583 desc->info0); 584 status->u.unblock_cache.unblock_type = 585 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE, 586 desc->info0); 587 588 if (!status->u.unblock_cache.err_detected && 589 status->u.unblock_cache.unblock_type == 590 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 591 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 592 } 593 594 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab, 595 u32 *reo_desc, 596 struct hal_reo_status *status) 597 { 598 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 599 struct hal_reo_flush_timeout_list_status *desc = 600 (struct hal_reo_flush_timeout_list_status *)tlv->value; 601 602 status->uniform_hdr.cmd_num = 603 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 604 desc->hdr.info0); 605 status->uniform_hdr.cmd_status = 606 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 607 desc->hdr.info0); 608 609 status->u.timeout_list.err_detected = 610 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR, 611 desc->info0); 612 status->u.timeout_list.list_empty = 613 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY, 614 desc->info0); 615 616 status->u.timeout_list.release_desc_cnt = 617 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT, 618 desc->info1); 619 status->u.timeout_list.fwd_buf_cnt = 620 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT, 621 desc->info1); 622 } 623 624 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab, 625 u32 *reo_desc, 626 struct hal_reo_status *status) 627 { 628 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 629 struct hal_reo_desc_thresh_reached_status *desc = 630 (struct hal_reo_desc_thresh_reached_status *)tlv->value; 631 632 status->uniform_hdr.cmd_num = 633 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 634 desc->hdr.info0); 635 status->uniform_hdr.cmd_status = 636 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 637 desc->hdr.info0); 638 639 status->u.desc_thresh_reached.threshold_idx = 640 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX, 641 desc->info0); 642 643 status->u.desc_thresh_reached.link_desc_counter0 = 644 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0, 645 desc->info1); 646 647 status->u.desc_thresh_reached.link_desc_counter1 = 648 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1, 649 desc->info2); 650 651 status->u.desc_thresh_reached.link_desc_counter2 = 652 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2, 653 desc->info3); 654 655 status->u.desc_thresh_reached.link_desc_counter_sum = 656 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM, 657 desc->info4); 658 } 659 660 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab, 661 u32 *reo_desc, 662 struct hal_reo_status *status) 663 { 664 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 665 struct hal_reo_status_hdr *desc = 666 (struct hal_reo_status_hdr *)tlv->value; 667 668 status->uniform_hdr.cmd_num = 669 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 670 desc->info0); 671 status->uniform_hdr.cmd_status = 672 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 673 desc->info0); 674 } 675 676 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 677 { 678 u32 num_ext_desc; 679 680 if (ba_window_size <= 1) { 681 if (tid != HAL_DESC_REO_NON_QOS_TID) 682 num_ext_desc = 1; 683 else 684 num_ext_desc = 0; 685 } else if (ba_window_size <= 105) { 686 num_ext_desc = 1; 687 } else if (ba_window_size <= 210) { 688 num_ext_desc = 2; 689 } else { 690 num_ext_desc = 3; 691 } 692 693 return sizeof(struct hal_rx_reo_queue) + 694 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)); 695 } 696 697 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 698 u32 start_seq, enum hal_pn_type type) 699 { 700 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr; 701 struct hal_rx_reo_queue_ext *ext_desc; 702 703 memset(qdesc, 0, sizeof(*qdesc)); 704 705 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 706 HAL_DESC_REO_QUEUE_DESC, 707 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 708 709 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid); 710 711 qdesc->info0 = 712 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) | 713 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) | 714 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid)); 715 716 if (ba_window_size < 1) 717 ba_window_size = 1; 718 719 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 720 ba_window_size++; 721 722 if (ba_window_size == 1) 723 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1); 724 725 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE, 726 ba_window_size - 1); 727 switch (type) { 728 case HAL_PN_TYPE_NONE: 729 case HAL_PN_TYPE_WAPI_EVEN: 730 case HAL_PN_TYPE_WAPI_UNEVEN: 731 break; 732 case HAL_PN_TYPE_WPA: 733 qdesc->info0 |= 734 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) | 735 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE, 736 HAL_RX_REO_QUEUE_PN_SIZE_48); 737 break; 738 } 739 740 /* TODO: Set Ignore ampdu flags based on BA window size and/or 741 * AMPDU capabilities 742 */ 743 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1); 744 745 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0); 746 747 if (start_seq <= 0xfff) 748 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN, 749 start_seq); 750 751 if (tid == HAL_DESC_REO_NON_QOS_TID) 752 return; 753 754 ext_desc = qdesc->ext_desc; 755 756 /* TODO: HW queue descriptors are currently allocated for max BA 757 * window size for all QOS TIDs so that same descriptor can be used 758 * later when ADDBA request is recevied. This should be changed to 759 * allocate HW queue descriptors based on BA window size being 760 * negotiated (0 for non BA cases), and reallocate when BA window 761 * size changes and also send WMI message to FW to change the REO 762 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 763 */ 764 memset(ext_desc, 0, sizeof(*ext_desc)); 765 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 766 HAL_DESC_REO_QUEUE_EXT_DESC, 767 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 768 ext_desc++; 769 memset(ext_desc, 0, sizeof(*ext_desc)); 770 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 771 HAL_DESC_REO_QUEUE_EXT_DESC, 772 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 773 ext_desc++; 774 memset(ext_desc, 0, sizeof(*ext_desc)); 775 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 776 HAL_DESC_REO_QUEUE_EXT_DESC, 777 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 778 } 779 780 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 781 struct hal_srng *srng) 782 { 783 struct hal_srng_params params; 784 struct hal_tlv_hdr *tlv; 785 struct hal_reo_get_queue_stats *desc; 786 int i, cmd_num = 1; 787 int entry_size; 788 u8 *entry; 789 790 memset(¶ms, 0, sizeof(params)); 791 792 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 793 ath11k_hal_srng_get_params(ab, srng, ¶ms); 794 entry = (u8 *)params.ring_base_vaddr; 795 796 for (i = 0; i < params.num_entries; i++) { 797 tlv = (struct hal_tlv_hdr *)entry; 798 desc = (struct hal_reo_get_queue_stats *)tlv->value; 799 desc->cmd.info0 = 800 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++); 801 entry += entry_size; 802 } 803 } 804 805 static enum hal_rx_mon_status 806 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, 807 struct hal_rx_mon_ppdu_info *ppdu_info, 808 u32 tlv_tag, u8 *tlv_data) 809 { 810 u32 info0, info1; 811 812 switch (tlv_tag) { 813 case HAL_RX_PPDU_START: { 814 struct hal_rx_ppdu_start *ppdu_start = 815 (struct hal_rx_ppdu_start *)tlv_data; 816 817 ppdu_info->ppdu_id = 818 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 819 __le32_to_cpu(ppdu_start->info0)); 820 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); 821 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); 822 break; 823 } 824 case HAL_RX_PPDU_END_USER_STATS: { 825 struct hal_rx_ppdu_end_user_stats *eu_stats = 826 (struct hal_rx_ppdu_end_user_stats *)tlv_data; 827 828 info0 = __le32_to_cpu(eu_stats->info0); 829 info1 = __le32_to_cpu(eu_stats->info1); 830 831 ppdu_info->tid = 832 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP, 833 __le32_to_cpu(eu_stats->info6))) - 1; 834 ppdu_info->tcp_msdu_count = 835 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT, 836 __le32_to_cpu(eu_stats->info4)); 837 ppdu_info->udp_msdu_count = 838 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT, 839 __le32_to_cpu(eu_stats->info4)); 840 ppdu_info->other_msdu_count = 841 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT, 842 __le32_to_cpu(eu_stats->info5)); 843 ppdu_info->tcp_ack_msdu_count = 844 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT, 845 __le32_to_cpu(eu_stats->info5)); 846 ppdu_info->preamble_type = 847 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1); 848 ppdu_info->num_mpdu_fcs_ok = 849 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK, 850 info1); 851 ppdu_info->num_mpdu_fcs_err = 852 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR, 853 info0); 854 break; 855 } 856 case HAL_PHYRX_HT_SIG: { 857 struct hal_rx_ht_sig_info *ht_sig = 858 (struct hal_rx_ht_sig_info *)tlv_data; 859 860 info0 = __le32_to_cpu(ht_sig->info0); 861 info1 = __le32_to_cpu(ht_sig->info1); 862 863 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0); 864 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0); 865 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC, 866 info1); 867 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1); 868 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI; 869 870 switch (ppdu_info->mcs) { 871 case 0 ... 7: 872 ppdu_info->nss = 1; 873 break; 874 case 8 ... 15: 875 ppdu_info->nss = 2; 876 break; 877 case 16 ... 23: 878 ppdu_info->nss = 3; 879 break; 880 case 24 ... 31: 881 ppdu_info->nss = 4; 882 break; 883 } 884 885 if (ppdu_info->nss > 1) 886 ppdu_info->mcs = ppdu_info->mcs % 8; 887 888 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 889 break; 890 } 891 case HAL_PHYRX_L_SIG_B: { 892 struct hal_rx_lsig_b_info *lsigb = 893 (struct hal_rx_lsig_b_info *)tlv_data; 894 895 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE, 896 __le32_to_cpu(lsigb->info0)); 897 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 898 break; 899 } 900 case HAL_PHYRX_L_SIG_A: { 901 struct hal_rx_lsig_a_info *lsiga = 902 (struct hal_rx_lsig_a_info *)tlv_data; 903 904 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE, 905 __le32_to_cpu(lsiga->info0)); 906 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 907 break; 908 } 909 case HAL_PHYRX_VHT_SIG_A: { 910 struct hal_rx_vht_sig_a_info *vht_sig = 911 (struct hal_rx_vht_sig_a_info *)tlv_data; 912 u32 nsts; 913 u32 group_id; 914 u8 gi_setting; 915 916 info0 = __le32_to_cpu(vht_sig->info0); 917 info1 = __le32_to_cpu(vht_sig->info1); 918 919 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, 920 info0); 921 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS, 922 info1); 923 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING, 924 info1); 925 switch (gi_setting) { 926 case HAL_RX_VHT_SIG_A_NORMAL_GI: 927 ppdu_info->gi = HAL_RX_GI_0_8_US; 928 break; 929 case HAL_RX_VHT_SIG_A_SHORT_GI: 930 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 931 ppdu_info->gi = HAL_RX_GI_0_4_US; 932 break; 933 } 934 935 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC; 936 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0); 937 if (ppdu_info->is_stbc && nsts > 0) 938 nsts = ((nsts + 1) >> 1) - 1; 939 940 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1; 941 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW, 942 info0); 943 ppdu_info->beamformed = info1 & 944 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED; 945 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID, 946 info0); 947 if (group_id == 0 || group_id == 63) 948 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 949 else 950 ppdu_info->reception_type = 951 HAL_RX_RECEPTION_TYPE_MU_MIMO; 952 break; 953 } 954 case HAL_PHYRX_HE_SIG_A_SU: { 955 struct hal_rx_he_sig_a_su_info *he_sig_a = 956 (struct hal_rx_he_sig_a_su_info *)tlv_data; 957 u32 nsts, cp_ltf, dcm; 958 959 info0 = __le32_to_cpu(he_sig_a->info0); 960 info1 = __le32_to_cpu(he_sig_a->info1); 961 962 ppdu_info->mcs = 963 FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, 964 info0); 965 ppdu_info->bw = 966 FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, 967 info0); 968 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info0); 969 ppdu_info->is_stbc = info1 & 970 HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC; 971 ppdu_info->beamformed = info1 & 972 HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF; 973 dcm = info0 & HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM; 974 cp_ltf = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, 975 info0); 976 nsts = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0); 977 978 switch (cp_ltf) { 979 case 0: 980 case 1: 981 ppdu_info->gi = HAL_RX_GI_0_8_US; 982 break; 983 case 2: 984 ppdu_info->gi = HAL_RX_GI_1_6_US; 985 break; 986 case 3: 987 if (dcm && ppdu_info->is_stbc) 988 ppdu_info->gi = HAL_RX_GI_0_8_US; 989 else 990 ppdu_info->gi = HAL_RX_GI_3_2_US; 991 break; 992 } 993 994 ppdu_info->nss = nsts + 1; 995 ppdu_info->dcm = dcm; 996 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 997 break; 998 } 999 case HAL_PHYRX_HE_SIG_A_MU_DL: { 1000 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl = 1001 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data; 1002 1003 u32 cp_ltf; 1004 1005 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 1006 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 1007 1008 ppdu_info->bw = 1009 FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, 1010 info0); 1011 cp_ltf = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, 1012 info0); 1013 1014 switch (cp_ltf) { 1015 case 0: 1016 case 1: 1017 ppdu_info->gi = HAL_RX_GI_0_8_US; 1018 break; 1019 case 2: 1020 ppdu_info->gi = HAL_RX_GI_1_6_US; 1021 break; 1022 case 3: 1023 ppdu_info->gi = HAL_RX_GI_3_2_US; 1024 break; 1025 } 1026 1027 ppdu_info->is_stbc = info1 & 1028 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC; 1029 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1030 break; 1031 } 1032 case HAL_PHYRX_HE_SIG_B1_MU: { 1033 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu = 1034 (struct hal_rx_he_sig_b1_mu_info *)tlv_data; 1035 u16 ru_tones; 1036 1037 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 1038 1039 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION, 1040 info0); 1041 ppdu_info->ru_alloc = 1042 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones); 1043 1044 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1045 break; 1046 } 1047 case HAL_PHYRX_HE_SIG_B2_MU: { 1048 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu = 1049 (struct hal_rx_he_sig_b2_mu_info *)tlv_data; 1050 1051 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 1052 1053 ppdu_info->mcs = 1054 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, 1055 info0); 1056 ppdu_info->nss = 1057 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, 1058 info0) + 1; 1059 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, 1060 info0); 1061 break; 1062 } 1063 case HAL_PHYRX_HE_SIG_B2_OFDMA: { 1064 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma = 1065 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data; 1066 1067 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0); 1068 1069 ppdu_info->mcs = 1070 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS, 1071 info0); 1072 ppdu_info->nss = 1073 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS, 1074 info0) + 1; 1075 ppdu_info->beamformed = 1076 info0 & 1077 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF; 1078 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, 1079 info0); 1080 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 1081 break; 1082 } 1083 case HAL_PHYRX_RSSI_LEGACY: { 1084 int i; 1085 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 1086 ab->wmi_ab.svc_map); 1087 struct hal_rx_phyrx_rssi_legacy_info *rssi = 1088 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; 1089 1090 /* TODO: Please note that the combined rssi will not be accurate 1091 * in MU case. Rssi in MU needs to be retrieved from 1092 * PHYRX_OTHER_RECEIVE_INFO TLV. 1093 */ 1094 ppdu_info->rssi_comb = 1095 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB, 1096 __le32_to_cpu(rssi->info0)); 1097 1098 if (db2dbm) { 1099 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) { 1100 ppdu_info->rssi_chain_pri20[i] = 1101 le32_get_bits(rssi->preamble[i].rssi_2040, 1102 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20); 1103 } 1104 } 1105 break; 1106 } 1107 case HAL_RX_MPDU_START: { 1108 u16 peer_id; 1109 1110 peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data); 1111 if (peer_id) 1112 ppdu_info->peer_id = peer_id; 1113 break; 1114 } 1115 case HAL_RXPCU_PPDU_END_INFO: { 1116 struct hal_rx_ppdu_end_duration *ppdu_rx_duration = 1117 (struct hal_rx_ppdu_end_duration *)tlv_data; 1118 ppdu_info->rx_duration = 1119 FIELD_GET(HAL_RX_PPDU_END_DURATION, 1120 __le32_to_cpu(ppdu_rx_duration->info0)); 1121 break; 1122 } 1123 case HAL_DUMMY: 1124 return HAL_RX_MON_STATUS_BUF_DONE; 1125 case HAL_RX_PPDU_END_STATUS_DONE: 1126 case 0: 1127 return HAL_RX_MON_STATUS_PPDU_DONE; 1128 default: 1129 break; 1130 } 1131 1132 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 1133 } 1134 1135 enum hal_rx_mon_status 1136 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab, 1137 struct hal_rx_mon_ppdu_info *ppdu_info, 1138 struct sk_buff *skb) 1139 { 1140 struct hal_tlv_hdr *tlv; 1141 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1142 u16 tlv_tag; 1143 u16 tlv_len; 1144 u8 *ptr = skb->data; 1145 1146 do { 1147 tlv = (struct hal_tlv_hdr *)ptr; 1148 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl); 1149 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 1150 ptr += sizeof(*tlv); 1151 1152 /* The actual length of PPDU_END is the combined length of many PHY 1153 * TLVs that follow. Skip the TLV header and 1154 * rx_rxpcu_classification_overview that follows the header to get to 1155 * next TLV. 1156 */ 1157 if (tlv_tag == HAL_RX_PPDU_END) 1158 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1159 1160 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info, 1161 tlv_tag, ptr); 1162 ptr += tlv_len; 1163 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1164 1165 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1166 break; 1167 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1168 1169 return hal_status; 1170 } 1171 1172 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 1173 u32 *sw_cookie, void **pp_buf_addr, 1174 u8 *rbm, u32 *msdu_cnt) 1175 { 1176 struct hal_reo_entrance_ring *reo_ent_ring = 1177 (struct hal_reo_entrance_ring *)rx_desc; 1178 struct ath11k_buffer_addr *buf_addr_info; 1179 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1180 1181 rx_mpdu_desc_info_details = 1182 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 1183 1184 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1185 rx_mpdu_desc_info_details->info0); 1186 1187 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info; 1188 1189 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1190 buf_addr_info->info1)) << 32) | 1191 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1192 buf_addr_info->info0); 1193 1194 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1195 buf_addr_info->info1); 1196 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 1197 buf_addr_info->info1); 1198 1199 *pp_buf_addr = (void *)buf_addr_info; 1200 } 1201 1202 void 1203 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc, 1204 struct hal_sw_mon_ring_entries *sw_mon_entries) 1205 { 1206 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc; 1207 struct ath11k_buffer_addr *buf_addr_info; 1208 struct ath11k_buffer_addr *status_buf_addr_info; 1209 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1210 1211 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info; 1212 1213 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1214 rx_mpdu_desc_info_details->info0); 1215 1216 buf_addr_info = &sw_mon_ring->buf_addr_info; 1217 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info; 1218 1219 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1220 buf_addr_info->info1)) << 32) | 1221 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1222 buf_addr_info->info0); 1223 1224 sw_mon_entries->mon_status_paddr = 1225 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1226 status_buf_addr_info->info1)) << 32) | 1227 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1228 status_buf_addr_info->info0); 1229 1230 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1231 buf_addr_info->info1); 1232 1233 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1234 status_buf_addr_info->info1); 1235 1236 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT, 1237 sw_mon_ring->info0); 1238 1239 sw_mon_entries->dst_buf_addr_info = buf_addr_info; 1240 sw_mon_entries->status_buf_addr_info = status_buf_addr_info; 1241 1242 sw_mon_entries->ppdu_id = 1243 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1); 1244 } 1245