1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 #if defined(__FreeBSD__) 6 #include <asm/io.h> 7 #endif 8 #include <linux/dma-mapping.h> 9 #include "hal_tx.h" 10 #include "debug.h" 11 #include "hal_desc.h" 12 #include "hif.h" 13 14 static const struct hal_srng_config hw_srng_config_template[] = { 15 /* TODO: max_rings can populated by querying HW capabilities */ 16 { /* REO_DST */ 17 .start_ring_id = HAL_SRNG_RING_ID_REO2SW1, 18 .max_rings = 4, 19 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 20 .lmac_ring = false, 21 .ring_dir = HAL_SRNG_DIR_DST, 22 .max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE, 23 }, 24 { /* REO_EXCEPTION */ 25 /* Designating REO2TCL ring as exception ring. This ring is 26 * similar to other REO2SW rings though it is named as REO2TCL. 27 * Any of theREO2SW rings can be used as exception ring. 28 */ 29 .start_ring_id = HAL_SRNG_RING_ID_REO2TCL, 30 .max_rings = 1, 31 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 32 .lmac_ring = false, 33 .ring_dir = HAL_SRNG_DIR_DST, 34 .max_size = HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE, 35 }, 36 { /* REO_REINJECT */ 37 .start_ring_id = HAL_SRNG_RING_ID_SW2REO, 38 .max_rings = 1, 39 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 40 .lmac_ring = false, 41 .ring_dir = HAL_SRNG_DIR_SRC, 42 .max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE, 43 }, 44 { /* REO_CMD */ 45 .start_ring_id = HAL_SRNG_RING_ID_REO_CMD, 46 .max_rings = 1, 47 .entry_size = (sizeof(struct hal_tlv_hdr) + 48 sizeof(struct hal_reo_get_queue_stats)) >> 2, 49 .lmac_ring = false, 50 .ring_dir = HAL_SRNG_DIR_SRC, 51 .max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE, 52 }, 53 { /* REO_STATUS */ 54 .start_ring_id = HAL_SRNG_RING_ID_REO_STATUS, 55 .max_rings = 1, 56 .entry_size = (sizeof(struct hal_tlv_hdr) + 57 sizeof(struct hal_reo_get_queue_stats_status)) >> 2, 58 .lmac_ring = false, 59 .ring_dir = HAL_SRNG_DIR_DST, 60 .max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE, 61 }, 62 { /* TCL_DATA */ 63 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1, 64 .max_rings = 3, 65 .entry_size = (sizeof(struct hal_tlv_hdr) + 66 sizeof(struct hal_tcl_data_cmd)) >> 2, 67 .lmac_ring = false, 68 .ring_dir = HAL_SRNG_DIR_SRC, 69 .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, 70 }, 71 { /* TCL_CMD */ 72 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD, 73 .max_rings = 1, 74 .entry_size = (sizeof(struct hal_tlv_hdr) + 75 sizeof(struct hal_tcl_gse_cmd)) >> 2, 76 .lmac_ring = false, 77 .ring_dir = HAL_SRNG_DIR_SRC, 78 .max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE, 79 }, 80 { /* TCL_STATUS */ 81 .start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS, 82 .max_rings = 1, 83 .entry_size = (sizeof(struct hal_tlv_hdr) + 84 sizeof(struct hal_tcl_status_ring)) >> 2, 85 .lmac_ring = false, 86 .ring_dir = HAL_SRNG_DIR_DST, 87 .max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE, 88 }, 89 { /* CE_SRC */ 90 .start_ring_id = HAL_SRNG_RING_ID_CE0_SRC, 91 .max_rings = 12, 92 .entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2, 93 .lmac_ring = false, 94 .ring_dir = HAL_SRNG_DIR_SRC, 95 .max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE, 96 }, 97 { /* CE_DST */ 98 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST, 99 .max_rings = 12, 100 .entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2, 101 .lmac_ring = false, 102 .ring_dir = HAL_SRNG_DIR_SRC, 103 .max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE, 104 }, 105 { /* CE_DST_STATUS */ 106 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS, 107 .max_rings = 12, 108 .entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2, 109 .lmac_ring = false, 110 .ring_dir = HAL_SRNG_DIR_DST, 111 .max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE, 112 }, 113 { /* WBM_IDLE_LINK */ 114 .start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK, 115 .max_rings = 1, 116 .entry_size = sizeof(struct hal_wbm_link_desc) >> 2, 117 .lmac_ring = false, 118 .ring_dir = HAL_SRNG_DIR_SRC, 119 .max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE, 120 }, 121 { /* SW2WBM_RELEASE */ 122 .start_ring_id = HAL_SRNG_RING_ID_WBM_SW_RELEASE, 123 .max_rings = 1, 124 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 125 .lmac_ring = false, 126 .ring_dir = HAL_SRNG_DIR_SRC, 127 .max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE, 128 }, 129 { /* WBM2SW_RELEASE */ 130 .start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 131 .max_rings = 4, 132 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 133 .lmac_ring = false, 134 .ring_dir = HAL_SRNG_DIR_DST, 135 .max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE, 136 }, 137 { /* RXDMA_BUF */ 138 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF, 139 .max_rings = 2, 140 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 141 .lmac_ring = true, 142 .ring_dir = HAL_SRNG_DIR_SRC, 143 .max_size = HAL_RXDMA_RING_MAX_SIZE, 144 }, 145 { /* RXDMA_DST */ 146 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 147 .max_rings = 1, 148 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 149 .lmac_ring = true, 150 .ring_dir = HAL_SRNG_DIR_DST, 151 .max_size = HAL_RXDMA_RING_MAX_SIZE, 152 }, 153 { /* RXDMA_MONITOR_BUF */ 154 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 155 .max_rings = 1, 156 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 157 .lmac_ring = true, 158 .ring_dir = HAL_SRNG_DIR_SRC, 159 .max_size = HAL_RXDMA_RING_MAX_SIZE, 160 }, 161 { /* RXDMA_MONITOR_STATUS */ 162 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 163 .max_rings = 1, 164 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 165 .lmac_ring = true, 166 .ring_dir = HAL_SRNG_DIR_SRC, 167 .max_size = HAL_RXDMA_RING_MAX_SIZE, 168 }, 169 { /* RXDMA_MONITOR_DST */ 170 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 171 .max_rings = 1, 172 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 173 .lmac_ring = true, 174 .ring_dir = HAL_SRNG_DIR_DST, 175 .max_size = HAL_RXDMA_RING_MAX_SIZE, 176 }, 177 { /* RXDMA_MONITOR_DESC */ 178 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 179 .max_rings = 1, 180 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 181 .lmac_ring = true, 182 .ring_dir = HAL_SRNG_DIR_SRC, 183 .max_size = HAL_RXDMA_RING_MAX_SIZE, 184 }, 185 { /* RXDMA DIR BUF */ 186 .start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 187 .max_rings = 1, 188 .entry_size = 8 >> 2, /* TODO: Define the struct */ 189 .lmac_ring = true, 190 .ring_dir = HAL_SRNG_DIR_SRC, 191 .max_size = HAL_RXDMA_RING_MAX_SIZE, 192 }, 193 }; 194 195 static int ath11k_hal_alloc_cont_rdp(struct ath11k_base *ab) 196 { 197 struct ath11k_hal *hal = &ab->hal; 198 size_t size; 199 200 size = sizeof(u32) * HAL_SRNG_RING_ID_MAX; 201 hal->rdp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->rdp.paddr, 202 GFP_KERNEL); 203 if (!hal->rdp.vaddr) 204 return -ENOMEM; 205 206 return 0; 207 } 208 209 static void ath11k_hal_free_cont_rdp(struct ath11k_base *ab) 210 { 211 struct ath11k_hal *hal = &ab->hal; 212 size_t size; 213 214 if (!hal->rdp.vaddr) 215 return; 216 217 size = sizeof(u32) * HAL_SRNG_RING_ID_MAX; 218 dma_free_coherent(ab->dev, size, 219 hal->rdp.vaddr, hal->rdp.paddr); 220 hal->rdp.vaddr = NULL; 221 } 222 223 static int ath11k_hal_alloc_cont_wrp(struct ath11k_base *ab) 224 { 225 struct ath11k_hal *hal = &ab->hal; 226 size_t size; 227 228 size = sizeof(u32) * HAL_SRNG_NUM_LMAC_RINGS; 229 hal->wrp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->wrp.paddr, 230 GFP_KERNEL); 231 if (!hal->wrp.vaddr) 232 return -ENOMEM; 233 234 return 0; 235 } 236 237 static void ath11k_hal_free_cont_wrp(struct ath11k_base *ab) 238 { 239 struct ath11k_hal *hal = &ab->hal; 240 size_t size; 241 242 if (!hal->wrp.vaddr) 243 return; 244 245 size = sizeof(u32) * HAL_SRNG_NUM_LMAC_RINGS; 246 dma_free_coherent(ab->dev, size, 247 hal->wrp.vaddr, hal->wrp.paddr); 248 hal->wrp.vaddr = NULL; 249 } 250 251 static void ath11k_hal_ce_dst_setup(struct ath11k_base *ab, 252 struct hal_srng *srng, int ring_num) 253 { 254 struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST]; 255 u32 addr; 256 u32 val; 257 258 addr = HAL_CE_DST_RING_CTRL + 259 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + 260 ring_num * srng_config->reg_size[HAL_SRNG_REG_GRP_R0]; 261 262 val = ath11k_hif_read32(ab, addr); 263 val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN; 264 val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN, 265 srng->u.dst_ring.max_buffer_length); 266 ath11k_hif_write32(ab, addr, val); 267 } 268 269 static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab, 270 struct hal_srng *srng) 271 { 272 struct ath11k_hal *hal = &ab->hal; 273 u32 val; 274 u64 hp_addr; 275 u32 reg_base; 276 277 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 278 279 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 280 ath11k_hif_write32(ab, reg_base + 281 HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab), 282 srng->msi_addr); 283 284 val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR, 285 ((u64)srng->msi_addr >> 286 HAL_ADDR_MSB_REG_SHIFT)) | 287 HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 288 ath11k_hif_write32(ab, reg_base + 289 HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab), val); 290 291 ath11k_hif_write32(ab, 292 reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab), 293 srng->msi_data); 294 } 295 296 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); 297 298 val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 299 ((u64)srng->ring_base_paddr >> 300 HAL_ADDR_MSB_REG_SHIFT)) | 301 FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_SIZE, 302 (srng->entry_size * srng->num_entries)); 303 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val); 304 305 val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) | 306 FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); 307 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val); 308 309 /* interrupt setup */ 310 val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD, 311 (srng->intr_timer_thres_us >> 3)); 312 313 val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD, 314 (srng->intr_batch_cntr_thres_entries * 315 srng->entry_size)); 316 317 ath11k_hif_write32(ab, 318 reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab), 319 val); 320 321 hp_addr = hal->rdp.paddr + 322 ((unsigned long)srng->u.dst_ring.hp_addr - 323 (unsigned long)hal->rdp.vaddr); 324 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab), 325 hp_addr & HAL_ADDR_LSB_REG_MASK); 326 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab), 327 hp_addr >> HAL_ADDR_MSB_REG_SHIFT); 328 329 /* Initialize head and tail pointers to indicate ring is empty */ 330 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 331 ath11k_hif_write32(ab, reg_base, 0); 332 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0); 333 *srng->u.dst_ring.hp_addr = 0; 334 335 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 336 val = 0; 337 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 338 val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP; 339 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 340 val |= HAL_REO1_RING_MISC_HOST_FW_SWAP; 341 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 342 val |= HAL_REO1_RING_MISC_MSI_SWAP; 343 val |= HAL_REO1_RING_MISC_SRNG_ENABLE; 344 345 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val); 346 } 347 348 static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab, 349 struct hal_srng *srng) 350 { 351 struct ath11k_hal *hal = &ab->hal; 352 u32 val; 353 u64 tp_addr; 354 u32 reg_base; 355 356 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 357 358 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 359 ath11k_hif_write32(ab, reg_base + 360 HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab), 361 srng->msi_addr); 362 363 val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR, 364 ((u64)srng->msi_addr >> 365 HAL_ADDR_MSB_REG_SHIFT)) | 366 HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 367 ath11k_hif_write32(ab, reg_base + 368 HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab), 369 val); 370 371 ath11k_hif_write32(ab, reg_base + 372 HAL_TCL1_RING_MSI1_DATA_OFFSET(ab), 373 srng->msi_data); 374 } 375 376 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); 377 378 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 379 ((u64)srng->ring_base_paddr >> 380 HAL_ADDR_MSB_REG_SHIFT)) | 381 FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE, 382 (srng->entry_size * srng->num_entries)); 383 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); 384 385 val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); 386 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val); 387 388 if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) { 389 ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr); 390 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 391 ((u64)srng->ring_base_paddr >> 392 HAL_ADDR_MSB_REG_SHIFT)) | 393 FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE, 394 (srng->entry_size * srng->num_entries)); 395 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); 396 } 397 398 /* interrupt setup */ 399 /* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the 400 * unit of 8 usecs instead of 1 usec (as required by v1). 401 */ 402 val = FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD, 403 srng->intr_timer_thres_us); 404 405 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD, 406 (srng->intr_batch_cntr_thres_entries * 407 srng->entry_size)); 408 409 ath11k_hif_write32(ab, 410 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab), 411 val); 412 413 val = 0; 414 if (srng->flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 415 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD, 416 srng->u.src_ring.low_threshold); 417 } 418 ath11k_hif_write32(ab, 419 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab), 420 val); 421 422 if (srng->ring_id != HAL_SRNG_RING_ID_WBM_IDLE_LINK) { 423 tp_addr = hal->rdp.paddr + 424 ((unsigned long)srng->u.src_ring.tp_addr - 425 (unsigned long)hal->rdp.vaddr); 426 ath11k_hif_write32(ab, 427 reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab), 428 tp_addr & HAL_ADDR_LSB_REG_MASK); 429 ath11k_hif_write32(ab, 430 reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab), 431 tp_addr >> HAL_ADDR_MSB_REG_SHIFT); 432 } 433 434 /* Initialize head and tail pointers to indicate ring is empty */ 435 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 436 ath11k_hif_write32(ab, reg_base, 0); 437 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); 438 *srng->u.src_ring.tp_addr = 0; 439 440 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 441 val = 0; 442 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 443 val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP; 444 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 445 val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP; 446 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 447 val |= HAL_TCL1_RING_MISC_MSI_SWAP; 448 449 /* Loop count is not used for SRC rings */ 450 val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE; 451 452 val |= HAL_TCL1_RING_MISC_SRNG_ENABLE; 453 454 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val); 455 } 456 457 static void ath11k_hal_srng_hw_init(struct ath11k_base *ab, 458 struct hal_srng *srng) 459 { 460 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 461 ath11k_hal_srng_src_hw_init(ab, srng); 462 else 463 ath11k_hal_srng_dst_hw_init(ab, srng); 464 } 465 466 static int ath11k_hal_srng_get_ring_id(struct ath11k_base *ab, 467 enum hal_ring_type type, 468 int ring_num, int mac_id) 469 { 470 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; 471 int ring_id; 472 473 if (ring_num >= srng_config->max_rings) { 474 ath11k_warn(ab, "invalid ring number :%d\n", ring_num); 475 return -EINVAL; 476 } 477 478 ring_id = srng_config->start_ring_id + ring_num; 479 if (srng_config->lmac_ring) 480 ring_id += mac_id * HAL_SRNG_RINGS_PER_LMAC; 481 482 if (WARN_ON(ring_id >= HAL_SRNG_RING_ID_MAX)) 483 return -EINVAL; 484 485 return ring_id; 486 } 487 488 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type) 489 { 490 struct hal_srng_config *srng_config; 491 492 if (WARN_ON(ring_type >= HAL_MAX_RING_TYPES)) 493 return -EINVAL; 494 495 srng_config = &ab->hal.srng_config[ring_type]; 496 497 return (srng_config->entry_size << 2); 498 } 499 500 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type) 501 { 502 struct hal_srng_config *srng_config; 503 504 if (WARN_ON(ring_type >= HAL_MAX_RING_TYPES)) 505 return -EINVAL; 506 507 srng_config = &ab->hal.srng_config[ring_type]; 508 509 return (srng_config->max_size / srng_config->entry_size); 510 } 511 512 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 513 struct hal_srng_params *params) 514 { 515 params->ring_base_paddr = srng->ring_base_paddr; 516 params->ring_base_vaddr = srng->ring_base_vaddr; 517 params->num_entries = srng->num_entries; 518 params->intr_timer_thres_us = srng->intr_timer_thres_us; 519 params->intr_batch_cntr_thres_entries = 520 srng->intr_batch_cntr_thres_entries; 521 params->low_threshold = srng->u.src_ring.low_threshold; 522 params->msi_addr = srng->msi_addr; 523 params->msi_data = srng->msi_data; 524 params->flags = srng->flags; 525 } 526 527 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 528 struct hal_srng *srng) 529 { 530 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) 531 return 0; 532 533 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 534 return ab->hal.wrp.paddr + 535 ((unsigned long)srng->u.src_ring.hp_addr - 536 (unsigned long)ab->hal.wrp.vaddr); 537 else 538 return ab->hal.rdp.paddr + 539 ((unsigned long)srng->u.dst_ring.hp_addr - 540 (unsigned long)ab->hal.rdp.vaddr); 541 } 542 543 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 544 struct hal_srng *srng) 545 { 546 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) 547 return 0; 548 549 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 550 return ab->hal.rdp.paddr + 551 ((unsigned long)srng->u.src_ring.tp_addr - 552 (unsigned long)ab->hal.rdp.vaddr); 553 else 554 return ab->hal.wrp.paddr + 555 ((unsigned long)srng->u.dst_ring.tp_addr - 556 (unsigned long)ab->hal.wrp.vaddr); 557 } 558 559 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type) 560 { 561 switch (type) { 562 case HAL_CE_DESC_SRC: 563 return sizeof(struct hal_ce_srng_src_desc); 564 case HAL_CE_DESC_DST: 565 return sizeof(struct hal_ce_srng_dest_desc); 566 case HAL_CE_DESC_DST_STATUS: 567 return sizeof(struct hal_ce_srng_dst_status_desc); 568 } 569 570 return 0; 571 } 572 573 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 574 u8 byte_swap_data) 575 { 576 struct hal_ce_srng_src_desc *desc = (struct hal_ce_srng_src_desc *)buf; 577 578 desc->buffer_addr_low = paddr & HAL_ADDR_LSB_REG_MASK; 579 desc->buffer_addr_info = 580 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI, 581 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 582 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP, 583 byte_swap_data) | 584 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_GATHER, 0) | 585 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_LEN, len); 586 desc->meta_info = FIELD_PREP(HAL_CE_SRC_DESC_META_INFO_DATA, id); 587 } 588 589 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr) 590 { 591 struct hal_ce_srng_dest_desc *desc = 592 (struct hal_ce_srng_dest_desc *)buf; 593 594 desc->buffer_addr_low = paddr & HAL_ADDR_LSB_REG_MASK; 595 desc->buffer_addr_info = 596 FIELD_PREP(HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI, 597 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)); 598 } 599 600 u32 ath11k_hal_ce_dst_status_get_length(void *buf) 601 { 602 struct hal_ce_srng_dst_status_desc *desc = 603 (struct hal_ce_srng_dst_status_desc *)buf; 604 u32 len; 605 606 len = FIELD_GET(HAL_CE_DST_STATUS_DESC_FLAGS_LEN, desc->flags); 607 desc->flags &= ~HAL_CE_DST_STATUS_DESC_FLAGS_LEN; 608 609 return len; 610 } 611 612 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 613 dma_addr_t paddr) 614 { 615 desc->buf_addr_info.info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 616 (paddr & HAL_ADDR_LSB_REG_MASK)); 617 desc->buf_addr_info.info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 618 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 619 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, 1) | 620 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie); 621 } 622 623 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng) 624 { 625 lockdep_assert_held(&srng->lock); 626 627 if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) 628 return (srng->ring_base_vaddr + srng->u.dst_ring.tp); 629 630 return NULL; 631 } 632 633 static void ath11k_hal_srng_prefetch_desc(struct ath11k_base *ab, 634 struct hal_srng *srng) 635 { 636 u32 *desc; 637 638 /* prefetch only if desc is available */ 639 desc = ath11k_hal_srng_dst_peek(ab, srng); 640 if (likely(desc)) { 641 dma_sync_single_for_cpu(ab->dev, virt_to_phys(desc), 642 (srng->entry_size * sizeof(u32)), 643 DMA_FROM_DEVICE); 644 prefetch(desc); 645 } 646 } 647 648 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 649 struct hal_srng *srng) 650 { 651 u32 *desc; 652 653 lockdep_assert_held(&srng->lock); 654 655 if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp) 656 return NULL; 657 658 desc = srng->ring_base_vaddr + srng->u.dst_ring.tp; 659 660 srng->u.dst_ring.tp += srng->entry_size; 661 662 /* wrap around to start of ring*/ 663 if (srng->u.dst_ring.tp == srng->ring_size) 664 srng->u.dst_ring.tp = 0; 665 666 /* Try to prefetch the next descriptor in the ring */ 667 if (srng->flags & HAL_SRNG_FLAGS_CACHED) 668 ath11k_hal_srng_prefetch_desc(ab, srng); 669 670 return desc; 671 } 672 673 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 674 bool sync_hw_ptr) 675 { 676 u32 tp, hp; 677 678 lockdep_assert_held(&srng->lock); 679 680 tp = srng->u.dst_ring.tp; 681 682 if (sync_hw_ptr) { 683 hp = *srng->u.dst_ring.hp_addr; 684 srng->u.dst_ring.cached_hp = hp; 685 } else { 686 hp = srng->u.dst_ring.cached_hp; 687 } 688 689 if (hp >= tp) 690 return (hp - tp) / srng->entry_size; 691 else 692 return (srng->ring_size - tp + hp) / srng->entry_size; 693 } 694 695 /* Returns number of available entries in src ring */ 696 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 697 bool sync_hw_ptr) 698 { 699 u32 tp, hp; 700 701 lockdep_assert_held(&srng->lock); 702 703 hp = srng->u.src_ring.hp; 704 705 if (sync_hw_ptr) { 706 tp = *srng->u.src_ring.tp_addr; 707 srng->u.src_ring.cached_tp = tp; 708 } else { 709 tp = srng->u.src_ring.cached_tp; 710 } 711 712 if (tp > hp) 713 return ((tp - hp) / srng->entry_size) - 1; 714 else 715 return ((srng->ring_size - hp + tp) / srng->entry_size) - 1; 716 } 717 718 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 719 struct hal_srng *srng) 720 { 721 u32 *desc; 722 u32 next_hp; 723 724 lockdep_assert_held(&srng->lock); 725 726 /* TODO: Using % is expensive, but we have to do this since size of some 727 * SRNG rings is not power of 2 (due to descriptor sizes). Need to see 728 * if separate function is defined for rings having power of 2 ring size 729 * (TCL2SW, REO2SW, SW2RXDMA and CE rings) so that we can avoid the 730 * overhead of % by using mask (with &). 731 */ 732 next_hp = (srng->u.src_ring.hp + srng->entry_size) % srng->ring_size; 733 734 if (next_hp == srng->u.src_ring.cached_tp) 735 return NULL; 736 737 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; 738 srng->u.src_ring.hp = next_hp; 739 740 /* TODO: Reap functionality is not used by all rings. If particular 741 * ring does not use reap functionality, we need not update reap_hp 742 * with next_hp pointer. Need to make sure a separate function is used 743 * before doing any optimization by removing below code updating 744 * reap_hp. 745 */ 746 srng->u.src_ring.reap_hp = next_hp; 747 748 return desc; 749 } 750 751 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 752 struct hal_srng *srng) 753 { 754 u32 *desc; 755 u32 next_reap_hp; 756 757 lockdep_assert_held(&srng->lock); 758 759 next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % 760 srng->ring_size; 761 762 if (next_reap_hp == srng->u.src_ring.cached_tp) 763 return NULL; 764 765 desc = srng->ring_base_vaddr + next_reap_hp; 766 srng->u.src_ring.reap_hp = next_reap_hp; 767 768 return desc; 769 } 770 771 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 772 struct hal_srng *srng) 773 { 774 u32 *desc; 775 776 lockdep_assert_held(&srng->lock); 777 778 if (srng->u.src_ring.hp == srng->u.src_ring.reap_hp) 779 return NULL; 780 781 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; 782 srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) % 783 srng->ring_size; 784 785 return desc; 786 } 787 788 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng) 789 { 790 lockdep_assert_held(&srng->lock); 791 792 if (((srng->u.src_ring.hp + srng->entry_size) % srng->ring_size) == 793 srng->u.src_ring.cached_tp) 794 return NULL; 795 796 return srng->ring_base_vaddr + srng->u.src_ring.hp; 797 } 798 799 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, struct hal_srng *srng) 800 { 801 lockdep_assert_held(&srng->lock); 802 803 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 804 srng->u.src_ring.cached_tp = 805 *(volatile u32 *)srng->u.src_ring.tp_addr; 806 } else { 807 srng->u.dst_ring.cached_hp = *srng->u.dst_ring.hp_addr; 808 809 /* Try to prefetch the next descriptor in the ring */ 810 if (srng->flags & HAL_SRNG_FLAGS_CACHED) 811 ath11k_hal_srng_prefetch_desc(ab, srng); 812 } 813 } 814 815 /* Update cached ring head/tail pointers to HW. ath11k_hal_srng_access_begin() 816 * should have been called before this. 817 */ 818 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng) 819 { 820 lockdep_assert_held(&srng->lock); 821 822 /* TODO: See if we need a write memory barrier here */ 823 if (srng->flags & HAL_SRNG_FLAGS_LMAC_RING) { 824 /* For LMAC rings, ring pointer updates are done through FW and 825 * hence written to a shared memory location that is read by FW 826 */ 827 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 828 srng->u.src_ring.last_tp = 829 *(volatile u32 *)srng->u.src_ring.tp_addr; 830 *srng->u.src_ring.hp_addr = srng->u.src_ring.hp; 831 } else { 832 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; 833 *srng->u.dst_ring.tp_addr = srng->u.dst_ring.tp; 834 } 835 } else { 836 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 837 srng->u.src_ring.last_tp = 838 *(volatile u32 *)srng->u.src_ring.tp_addr; 839 ath11k_hif_write32(ab, 840 (unsigned long)srng->u.src_ring.hp_addr - 841 (unsigned long)ab->mem, 842 srng->u.src_ring.hp); 843 } else { 844 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; 845 ath11k_hif_write32(ab, 846 (unsigned long)srng->u.dst_ring.tp_addr - 847 (unsigned long)ab->mem, 848 srng->u.dst_ring.tp); 849 } 850 } 851 852 srng->timestamp = jiffies; 853 } 854 855 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 856 struct hal_wbm_idle_scatter_list *sbuf, 857 u32 nsbufs, u32 tot_link_desc, 858 u32 end_offset) 859 { 860 struct ath11k_buffer_addr *link_addr; 861 int i; 862 u32 reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64; 863 864 #if defined(__linux__) 865 link_addr = (void *)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE; 866 #elif defined(__FreeBSD__) 867 link_addr = (void *)((uintptr_t)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE); 868 #endif 869 870 for (i = 1; i < nsbufs; i++) { 871 link_addr->info0 = sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK; 872 link_addr->info1 = FIELD_PREP( 873 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 874 (u64)sbuf[i].paddr >> HAL_ADDR_MSB_REG_SHIFT) | 875 FIELD_PREP( 876 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG, 877 BASE_ADDR_MATCH_TAG_VAL); 878 879 #if defined(__linux__) 880 link_addr = (void *)sbuf[i].vaddr + 881 HAL_WBM_IDLE_SCATTER_BUF_SIZE; 882 #elif defined(__FreeBSD__) 883 link_addr = (void *)((uintptr_t)sbuf[i].vaddr + 884 HAL_WBM_IDLE_SCATTER_BUF_SIZE); 885 #endif 886 } 887 888 ath11k_hif_write32(ab, 889 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR, 890 FIELD_PREP(HAL_WBM_SCATTER_BUFFER_SIZE, reg_scatter_buf_sz) | 891 FIELD_PREP(HAL_WBM_LINK_DESC_IDLE_LIST_MODE, 0x1)); 892 ath11k_hif_write32(ab, 893 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR, 894 FIELD_PREP(HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 895 reg_scatter_buf_sz * nsbufs)); 896 ath11k_hif_write32(ab, 897 HAL_SEQ_WCSS_UMAC_WBM_REG + 898 HAL_WBM_SCATTERED_RING_BASE_LSB, 899 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 900 sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK)); 901 ath11k_hif_write32(ab, 902 HAL_SEQ_WCSS_UMAC_WBM_REG + 903 HAL_WBM_SCATTERED_RING_BASE_MSB, 904 FIELD_PREP( 905 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 906 (u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT) | 907 FIELD_PREP( 908 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG, 909 BASE_ADDR_MATCH_TAG_VAL)); 910 911 /* Setup head and tail pointers for the idle list */ 912 ath11k_hif_write32(ab, 913 HAL_SEQ_WCSS_UMAC_WBM_REG + 914 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0, 915 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 916 sbuf[nsbufs - 1].paddr)); 917 ath11k_hif_write32(ab, 918 HAL_SEQ_WCSS_UMAC_WBM_REG + 919 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1, 920 FIELD_PREP( 921 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 922 ((u64)sbuf[nsbufs - 1].paddr >> 923 HAL_ADDR_MSB_REG_SHIFT)) | 924 FIELD_PREP(HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1, 925 (end_offset >> 2))); 926 ath11k_hif_write32(ab, 927 HAL_SEQ_WCSS_UMAC_WBM_REG + 928 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0, 929 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 930 sbuf[0].paddr)); 931 932 ath11k_hif_write32(ab, 933 HAL_SEQ_WCSS_UMAC_WBM_REG + 934 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0, 935 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 936 sbuf[0].paddr)); 937 ath11k_hif_write32(ab, 938 HAL_SEQ_WCSS_UMAC_WBM_REG + 939 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1, 940 FIELD_PREP( 941 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 942 ((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 943 FIELD_PREP(HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1, 944 0)); 945 ath11k_hif_write32(ab, 946 HAL_SEQ_WCSS_UMAC_WBM_REG + 947 HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR, 948 2 * tot_link_desc); 949 950 /* Enable the SRNG */ 951 ath11k_hif_write32(ab, 952 HAL_SEQ_WCSS_UMAC_WBM_REG + 953 HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab), 0x40); 954 } 955 956 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 957 int ring_num, int mac_id, 958 struct hal_srng_params *params) 959 { 960 struct ath11k_hal *hal = &ab->hal; 961 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; 962 struct hal_srng *srng; 963 int ring_id; 964 u32 lmac_idx; 965 int i; 966 u32 reg_base; 967 968 ring_id = ath11k_hal_srng_get_ring_id(ab, type, ring_num, mac_id); 969 if (ring_id < 0) 970 return ring_id; 971 972 srng = &hal->srng_list[ring_id]; 973 974 srng->ring_id = ring_id; 975 srng->ring_dir = srng_config->ring_dir; 976 srng->ring_base_paddr = params->ring_base_paddr; 977 srng->ring_base_vaddr = params->ring_base_vaddr; 978 srng->entry_size = srng_config->entry_size; 979 srng->num_entries = params->num_entries; 980 srng->ring_size = srng->entry_size * srng->num_entries; 981 srng->intr_batch_cntr_thres_entries = 982 params->intr_batch_cntr_thres_entries; 983 srng->intr_timer_thres_us = params->intr_timer_thres_us; 984 srng->flags = params->flags; 985 srng->msi_addr = params->msi_addr; 986 srng->msi_data = params->msi_data; 987 srng->initialized = 1; 988 spin_lock_init(&srng->lock); 989 lockdep_set_class(&srng->lock, hal->srng_key + ring_id); 990 991 for (i = 0; i < HAL_SRNG_NUM_REG_GRP; i++) { 992 srng->hwreg_base[i] = srng_config->reg_start[i] + 993 (ring_num * srng_config->reg_size[i]); 994 } 995 996 memset(srng->ring_base_vaddr, 0, 997 (srng->entry_size * srng->num_entries) << 2); 998 999 /* TODO: Add comments on these swap configurations */ 1000 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 1001 srng->flags |= HAL_SRNG_FLAGS_MSI_SWAP | HAL_SRNG_FLAGS_DATA_TLV_SWAP | 1002 HAL_SRNG_FLAGS_RING_PTR_SWAP; 1003 1004 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 1005 1006 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 1007 srng->u.src_ring.hp = 0; 1008 srng->u.src_ring.cached_tp = 0; 1009 srng->u.src_ring.reap_hp = srng->ring_size - srng->entry_size; 1010 srng->u.src_ring.tp_addr = (void *)(hal->rdp.vaddr + ring_id); 1011 srng->u.src_ring.low_threshold = params->low_threshold * 1012 srng->entry_size; 1013 if (srng_config->lmac_ring) { 1014 lmac_idx = ring_id - HAL_SRNG_RING_ID_LMAC1_ID_START; 1015 srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr + 1016 lmac_idx); 1017 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; 1018 } else { 1019 if (!ab->hw_params.supports_shadow_regs) 1020 srng->u.src_ring.hp_addr = 1021 (u32 *)((unsigned long)ab->mem + reg_base); 1022 else 1023 ath11k_dbg(ab, ATH11k_DBG_HAL, 1024 "hal type %d ring_num %d reg_base 0x%x shadow 0x%lx\n", 1025 type, ring_num, 1026 reg_base, 1027 (unsigned long)srng->u.src_ring.hp_addr - 1028 (unsigned long)ab->mem); 1029 } 1030 } else { 1031 /* During initialization loop count in all the descriptors 1032 * will be set to zero, and HW will set it to 1 on completing 1033 * descriptor update in first loop, and increments it by 1 on 1034 * subsequent loops (loop count wraps around after reaching 1035 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1036 * loop count in descriptors updated by HW (to be processed 1037 * by SW). 1038 */ 1039 srng->u.dst_ring.loop_cnt = 1; 1040 srng->u.dst_ring.tp = 0; 1041 srng->u.dst_ring.cached_hp = 0; 1042 srng->u.dst_ring.hp_addr = (void *)(hal->rdp.vaddr + ring_id); 1043 if (srng_config->lmac_ring) { 1044 /* For LMAC rings, tail pointer updates will be done 1045 * through FW by writing to a shared memory location 1046 */ 1047 lmac_idx = ring_id - HAL_SRNG_RING_ID_LMAC1_ID_START; 1048 srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr + 1049 lmac_idx); 1050 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; 1051 } else { 1052 if (!ab->hw_params.supports_shadow_regs) 1053 srng->u.dst_ring.tp_addr = 1054 (u32 *)((unsigned long)ab->mem + reg_base + 1055 (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))); 1056 else 1057 ath11k_dbg(ab, ATH11k_DBG_HAL, 1058 "type %d ring_num %d target_reg 0x%x shadow 0x%lx\n", 1059 type, ring_num, 1060 reg_base + (HAL_REO1_RING_TP(ab) - 1061 HAL_REO1_RING_HP(ab)), 1062 (unsigned long)srng->u.dst_ring.tp_addr - 1063 (unsigned long)ab->mem); 1064 } 1065 } 1066 1067 if (srng_config->lmac_ring) 1068 return ring_id; 1069 1070 ath11k_hal_srng_hw_init(ab, srng); 1071 1072 if (type == HAL_CE_DST) { 1073 srng->u.dst_ring.max_buffer_length = params->max_buffer_len; 1074 ath11k_hal_ce_dst_setup(ab, srng, ring_num); 1075 } 1076 1077 return ring_id; 1078 } 1079 1080 static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab, 1081 int shadow_cfg_idx, 1082 enum hal_ring_type ring_type, 1083 int ring_num) 1084 { 1085 struct hal_srng *srng; 1086 struct ath11k_hal *hal = &ab->hal; 1087 int ring_id; 1088 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1089 1090 ring_id = ath11k_hal_srng_get_ring_id(ab, ring_type, ring_num, 0); 1091 if (ring_id < 0) 1092 return; 1093 1094 srng = &hal->srng_list[ring_id]; 1095 1096 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 1097 srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + 1098 (unsigned long)ab->mem); 1099 else 1100 srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + 1101 (unsigned long)ab->mem); 1102 } 1103 1104 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 1105 enum hal_ring_type ring_type, 1106 int ring_num) 1107 { 1108 struct ath11k_hal *hal = &ab->hal; 1109 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1110 int shadow_cfg_idx = hal->num_shadow_reg_configured; 1111 u32 target_reg; 1112 1113 if (shadow_cfg_idx >= HAL_SHADOW_NUM_REGS) 1114 return -EINVAL; 1115 1116 hal->num_shadow_reg_configured++; 1117 1118 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; 1119 target_reg += srng_config->reg_size[HAL_HP_OFFSET_IN_REG_START] * 1120 ring_num; 1121 1122 /* For destination ring, shadow the TP */ 1123 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 1124 target_reg += HAL_OFFSET_FROM_HP_TO_TP; 1125 1126 hal->shadow_reg_addr[shadow_cfg_idx] = target_reg; 1127 1128 /* update hp/tp addr to hal structure*/ 1129 ath11k_hal_srng_update_hp_tp_addr(ab, shadow_cfg_idx, ring_type, 1130 ring_num); 1131 1132 ath11k_dbg(ab, ATH11k_DBG_HAL, 1133 "target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d", 1134 target_reg, 1135 HAL_SHADOW_REG(shadow_cfg_idx), 1136 shadow_cfg_idx, 1137 ring_type, ring_num); 1138 1139 return 0; 1140 } 1141 1142 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab) 1143 { 1144 struct ath11k_hal *hal = &ab->hal; 1145 int ring_type, ring_num; 1146 1147 /* update all the non-CE srngs. */ 1148 for (ring_type = 0; ring_type < HAL_MAX_RING_TYPES; ring_type++) { 1149 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1150 1151 if (ring_type == HAL_CE_SRC || 1152 ring_type == HAL_CE_DST || 1153 ring_type == HAL_CE_DST_STATUS) 1154 continue; 1155 1156 if (srng_config->lmac_ring) 1157 continue; 1158 1159 for (ring_num = 0; ring_num < srng_config->max_rings; ring_num++) 1160 ath11k_hal_srng_update_shadow_config(ab, ring_type, ring_num); 1161 } 1162 } 1163 1164 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 1165 u32 **cfg, u32 *len) 1166 { 1167 struct ath11k_hal *hal = &ab->hal; 1168 1169 *len = hal->num_shadow_reg_configured; 1170 *cfg = hal->shadow_reg_addr; 1171 } 1172 1173 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, 1174 struct hal_srng *srng) 1175 { 1176 lockdep_assert_held(&srng->lock); 1177 1178 /* check whether the ring is emptry. Update the shadow 1179 * HP only when then ring isn't' empty. 1180 */ 1181 if (srng->ring_dir == HAL_SRNG_DIR_SRC && 1182 *srng->u.src_ring.tp_addr != srng->u.src_ring.hp) 1183 ath11k_hal_srng_access_end(ab, srng); 1184 } 1185 1186 static int ath11k_hal_srng_create_config(struct ath11k_base *ab) 1187 { 1188 struct ath11k_hal *hal = &ab->hal; 1189 struct hal_srng_config *s; 1190 1191 hal->srng_config = kmemdup(hw_srng_config_template, 1192 sizeof(hw_srng_config_template), 1193 GFP_KERNEL); 1194 if (!hal->srng_config) 1195 return -ENOMEM; 1196 1197 s = &hal->srng_config[HAL_REO_DST]; 1198 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); 1199 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP(ab); 1200 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); 1201 s->reg_size[1] = HAL_REO2_RING_HP(ab) - HAL_REO1_RING_HP(ab); 1202 1203 s = &hal->srng_config[HAL_REO_EXCEPTION]; 1204 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB(ab); 1205 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab); 1206 1207 s = &hal->srng_config[HAL_REO_REINJECT]; 1208 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB; 1209 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; 1210 1211 s = &hal->srng_config[HAL_REO_CMD]; 1212 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB; 1213 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; 1214 1215 s = &hal->srng_config[HAL_REO_STATUS]; 1216 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); 1217 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP(ab); 1218 1219 s = &hal->srng_config[HAL_TCL_DATA]; 1220 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); 1221 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; 1222 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); 1223 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; 1224 1225 s = &hal->srng_config[HAL_TCL_CMD]; 1226 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); 1227 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; 1228 1229 s = &hal->srng_config[HAL_TCL_STATUS]; 1230 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); 1231 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; 1232 1233 s = &hal->srng_config[HAL_CE_SRC]; 1234 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; 1235 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; 1236 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - 1237 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); 1238 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - 1239 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); 1240 1241 s = &hal->srng_config[HAL_CE_DST]; 1242 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; 1243 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; 1244 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1245 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1246 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1247 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1248 1249 s = &hal->srng_config[HAL_CE_DST_STATUS]; 1250 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + 1251 HAL_CE_DST_STATUS_RING_BASE_LSB; 1252 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; 1253 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1254 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1255 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1256 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1257 1258 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; 1259 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); 1260 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; 1261 1262 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; 1263 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(ab); 1264 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP; 1265 1266 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; 1267 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); 1268 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; 1269 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) - 1270 HAL_WBM0_RELEASE_RING_BASE_LSB(ab); 1271 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; 1272 1273 return 0; 1274 } 1275 1276 static void ath11k_hal_register_srng_key(struct ath11k_base *ab) 1277 { 1278 #if defined(__linux__) 1279 struct ath11k_hal *hal = &ab->hal; 1280 u32 ring_id; 1281 1282 for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++) 1283 lockdep_register_key(hal->srng_key + ring_id); 1284 #endif 1285 } 1286 1287 static void ath11k_hal_unregister_srng_key(struct ath11k_base *ab) 1288 { 1289 #if defined(__linux__) 1290 struct ath11k_hal *hal = &ab->hal; 1291 u32 ring_id; 1292 1293 for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++) 1294 lockdep_unregister_key(hal->srng_key + ring_id); 1295 #endif 1296 } 1297 1298 int ath11k_hal_srng_init(struct ath11k_base *ab) 1299 { 1300 struct ath11k_hal *hal = &ab->hal; 1301 int ret; 1302 1303 memset(hal, 0, sizeof(*hal)); 1304 1305 ret = ath11k_hal_srng_create_config(ab); 1306 if (ret) 1307 goto err_hal; 1308 1309 ret = ath11k_hal_alloc_cont_rdp(ab); 1310 if (ret) 1311 goto err_hal; 1312 1313 ret = ath11k_hal_alloc_cont_wrp(ab); 1314 if (ret) 1315 goto err_free_cont_rdp; 1316 1317 ath11k_hal_register_srng_key(ab); 1318 1319 return 0; 1320 1321 err_free_cont_rdp: 1322 ath11k_hal_free_cont_rdp(ab); 1323 1324 err_hal: 1325 return ret; 1326 } 1327 EXPORT_SYMBOL(ath11k_hal_srng_init); 1328 1329 void ath11k_hal_srng_deinit(struct ath11k_base *ab) 1330 { 1331 struct ath11k_hal *hal = &ab->hal; 1332 1333 ath11k_hal_unregister_srng_key(ab); 1334 ath11k_hal_free_cont_rdp(ab); 1335 ath11k_hal_free_cont_wrp(ab); 1336 kfree(hal->srng_config); 1337 } 1338 EXPORT_SYMBOL(ath11k_hal_srng_deinit); 1339 1340 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab) 1341 { 1342 struct hal_srng *srng; 1343 struct ath11k_ext_irq_grp *irq_grp; 1344 struct ath11k_ce_pipe *ce_pipe; 1345 int i; 1346 1347 ath11k_err(ab, "Last interrupt received for each CE:\n"); 1348 for (i = 0; i < ab->hw_params.ce_count; i++) { 1349 ce_pipe = &ab->ce.ce_pipe[i]; 1350 1351 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1352 continue; 1353 1354 #if defined(__linux__) 1355 ath11k_err(ab, "CE_id %d pipe_num %d %ums before\n", 1356 i, ce_pipe->pipe_num, 1357 jiffies_to_msecs(jiffies - ce_pipe->timestamp)); 1358 #elif defined(__FreeBSD__) 1359 ath11k_err(ab, "CE_id %d pipe_num %d %jums before\n", 1360 i, ce_pipe->pipe_num, 1361 (uintmax_t)jiffies_to_msecs(jiffies - ce_pipe->timestamp)); 1362 #endif 1363 } 1364 1365 ath11k_err(ab, "\nLast interrupt received for each group:\n"); 1366 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 1367 irq_grp = &ab->ext_irq_grp[i]; 1368 #if defined(__linux__) 1369 ath11k_err(ab, "group_id %d %ums before\n", 1370 irq_grp->grp_id, 1371 jiffies_to_msecs(jiffies - irq_grp->timestamp)); 1372 #elif defined(__FreeBSD__) 1373 ath11k_err(ab, "group_id %d %jums before\n", 1374 irq_grp->grp_id, 1375 (uintmax_t)jiffies_to_msecs(jiffies - irq_grp->timestamp)); 1376 #endif 1377 } 1378 1379 for (i = 0; i < HAL_SRNG_RING_ID_MAX; i++) { 1380 srng = &ab->hal.srng_list[i]; 1381 1382 if (!srng->initialized) 1383 continue; 1384 1385 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 1386 ath11k_err(ab, 1387 #if defined(__linux__) 1388 "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %ums\n", 1389 #elif defined(__FreeBSD__) 1390 "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %jums\n", 1391 #endif 1392 srng->ring_id, srng->u.src_ring.hp, 1393 srng->u.src_ring.reap_hp, 1394 *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, 1395 srng->u.src_ring.last_tp, 1396 #if defined(__linux__) 1397 jiffies_to_msecs(jiffies - srng->timestamp)); 1398 #elif defined(__FreeBSD__) 1399 (uintmax_t)jiffies_to_msecs(jiffies - srng->timestamp)); 1400 #endif 1401 else if (srng->ring_dir == HAL_SRNG_DIR_DST) 1402 ath11k_err(ab, 1403 #if defined(__linux__) 1404 "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %ums\n", 1405 #elif defined(__FreeBSD__) 1406 "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %jums\n", 1407 #endif 1408 srng->ring_id, srng->u.dst_ring.tp, 1409 *srng->u.dst_ring.hp_addr, 1410 srng->u.dst_ring.cached_hp, 1411 srng->u.dst_ring.last_hp, 1412 #if defined(__linux__) 1413 jiffies_to_msecs(jiffies - srng->timestamp)); 1414 #elif defined(__FreeBSD__) 1415 (uintmax_t)jiffies_to_msecs(jiffies - srng->timestamp)); 1416 #endif 1417 } 1418 } 1419