1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef DEBUG_HTT_STATS_H 7 #define DEBUG_HTT_STATS_H 8 9 #define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 10 #define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 11 #define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 12 13 enum htt_tlv_tag_t { 14 HTT_STATS_TX_PDEV_CMN_TAG = 0, 15 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 16 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 17 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 18 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, 19 HTT_STATS_STRING_TAG = 5, 20 HTT_STATS_TX_HWQ_CMN_TAG = 6, 21 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, 22 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, 23 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, 24 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, 25 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 26 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 27 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 28 HTT_STATS_TX_TQM_CMN_TAG = 14, 29 HTT_STATS_TX_TQM_PDEV_TAG = 15, 30 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, 31 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 32 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 33 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 34 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 35 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 36 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 37 HTT_STATS_TX_DE_CMN_TAG = 23, 38 HTT_STATS_RING_IF_TAG = 24, 39 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 40 HTT_STATS_SFM_CMN_TAG = 26, 41 HTT_STATS_SRING_STATS_TAG = 27, 42 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 43 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, 44 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, 45 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, 46 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, 47 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, 48 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 49 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 50 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 51 HTT_STATS_TX_SCHED_CMN_TAG = 37, 52 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, 53 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 54 HTT_STATS_RING_IF_CMN_TAG = 40, 55 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 56 HTT_STATS_SFM_CLIENT_TAG = 42, 57 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 58 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 59 HTT_STATS_SRING_CMN_TAG = 45, 60 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 61 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 62 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 63 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 64 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 65 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, 66 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, 67 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, 68 HTT_STATS_HW_INTR_MISC_TAG = 54, 69 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, 70 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 71 HTT_STATS_COUNTER_NAME_TAG = 57, 72 HTT_STATS_TX_TID_DETAILS_TAG = 58, 73 HTT_STATS_RX_TID_DETAILS_TAG = 59, 74 HTT_STATS_PEER_STATS_CMN_TAG = 60, 75 HTT_STATS_PEER_DETAILS_TAG = 61, 76 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, 77 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, 78 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, 79 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 80 HTT_STATS_WHAL_TX_TAG = 66, 81 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 82 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, 83 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, 84 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 85 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 86 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 87 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 88 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 89 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, 90 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, 91 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, 92 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, 93 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, 94 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 95 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, 96 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, 97 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, 98 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, 99 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, 100 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 101 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 102 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 103 HTT_STATS_HW_WAR_TAG = 89, 104 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, 105 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, 106 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 107 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, 108 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, 109 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, 110 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, 111 HTT_STATS_PHY_COUNTERS_TAG = 121, 112 HTT_STATS_PHY_STATS_TAG = 122, 113 114 HTT_STATS_MAX_TAG, 115 }; 116 117 #define HTT_STATS_MAX_STRING_SZ32 4 118 #define HTT_STATS_MACID_INVALID 0xff 119 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 120 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 121 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 122 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 123 124 enum htt_tx_pdev_underrun_enum { 125 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 126 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 127 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 128 HTT_TX_PDEV_MAX_URRN_STATS = 3, 129 }; 130 131 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71 132 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 133 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 134 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 135 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 136 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 137 138 #define HTT_RX_STATS_REFILL_MAX_RING 4 139 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 140 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 141 142 /* Bytes stored in little endian order */ 143 /* Length should be multiple of DWORD */ 144 struct htt_stats_string_tlv { 145 u32 data[0]; /* Can be variable length */ 146 } __packed; 147 148 #define HTT_STATS_MAC_ID GENMASK(7, 0) 149 150 /* == TX PDEV STATS == */ 151 struct htt_tx_pdev_stats_cmn_tlv { 152 u32 mac_id__word; 153 u32 hw_queued; 154 u32 hw_reaped; 155 u32 underrun; 156 u32 hw_paused; 157 u32 hw_flush; 158 u32 hw_filt; 159 u32 tx_abort; 160 u32 mpdu_requeued; 161 u32 tx_xretry; 162 u32 data_rc; 163 u32 mpdu_dropped_xretry; 164 u32 illgl_rate_phy_err; 165 u32 cont_xretry; 166 u32 tx_timeout; 167 u32 pdev_resets; 168 u32 phy_underrun; 169 u32 txop_ovf; 170 u32 seq_posted; 171 u32 seq_failed_queueing; 172 u32 seq_completed; 173 u32 seq_restarted; 174 u32 mu_seq_posted; 175 u32 seq_switch_hw_paused; 176 u32 next_seq_posted_dsr; 177 u32 seq_posted_isr; 178 u32 seq_ctrl_cached; 179 u32 mpdu_count_tqm; 180 u32 msdu_count_tqm; 181 u32 mpdu_removed_tqm; 182 u32 msdu_removed_tqm; 183 u32 mpdus_sw_flush; 184 u32 mpdus_hw_filter; 185 u32 mpdus_truncated; 186 u32 mpdus_ack_failed; 187 u32 mpdus_expired; 188 u32 mpdus_seq_hw_retry; 189 u32 ack_tlv_proc; 190 u32 coex_abort_mpdu_cnt_valid; 191 u32 coex_abort_mpdu_cnt; 192 u32 num_total_ppdus_tried_ota; 193 u32 num_data_ppdus_tried_ota; 194 u32 local_ctrl_mgmt_enqued; 195 u32 local_ctrl_mgmt_freed; 196 u32 local_data_enqued; 197 u32 local_data_freed; 198 u32 mpdu_tried; 199 u32 isr_wait_seq_posted; 200 201 u32 tx_active_dur_us_low; 202 u32 tx_active_dur_us_high; 203 }; 204 205 /* NOTE: Variable length TLV, use length spec to infer array size */ 206 struct htt_tx_pdev_stats_urrn_tlv_v { 207 u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */ 208 }; 209 210 /* NOTE: Variable length TLV, use length spec to infer array size */ 211 struct htt_tx_pdev_stats_flush_tlv_v { 212 u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 213 }; 214 215 /* NOTE: Variable length TLV, use length spec to infer array size */ 216 struct htt_tx_pdev_stats_sifs_tlv_v { 217 u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 218 }; 219 220 /* NOTE: Variable length TLV, use length spec to infer array size */ 221 struct htt_tx_pdev_stats_phy_err_tlv_v { 222 u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 223 }; 224 225 /* NOTE: Variable length TLV, use length spec to infer array size */ 226 struct htt_tx_pdev_stats_sifs_hist_tlv_v { 227 u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 228 }; 229 230 struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { 231 u32 num_data_ppdus_legacy_su; 232 u32 num_data_ppdus_ac_su; 233 u32 num_data_ppdus_ax_su; 234 u32 num_data_ppdus_ac_su_txbf; 235 u32 num_data_ppdus_ax_su_txbf; 236 }; 237 238 /* NOTE: Variable length TLV, use length spec to infer array size . 239 * 240 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 241 * The tries here is the count of the MPDUS within a PPDU that the 242 * HW had attempted to transmit on air, for the HWSCH Schedule 243 * command submitted by FW.It is not the retry attempts. 244 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 245 * 10 bins in this histogram. They are defined in FW using the 246 * following macros 247 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 248 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 249 */ 250 struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v { 251 u32 hist_bin_size; 252 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 253 }; 254 255 /* == SOC ERROR STATS == */ 256 257 /* =============== PDEV ERROR STATS ============== */ 258 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 259 struct htt_hw_stats_intr_misc_tlv { 260 /* Stored as little endian */ 261 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 262 u32 mask; 263 u32 count; 264 }; 265 266 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 267 struct htt_hw_stats_wd_timeout_tlv { 268 /* Stored as little endian */ 269 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 270 u32 count; 271 }; 272 273 struct htt_hw_stats_pdev_errs_tlv { 274 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */ 275 u32 tx_abort; 276 u32 tx_abort_fail_count; 277 u32 rx_abort; 278 u32 rx_abort_fail_count; 279 u32 warm_reset; 280 u32 cold_reset; 281 u32 tx_flush; 282 u32 tx_glb_reset; 283 u32 tx_txq_reset; 284 u32 rx_timeout_reset; 285 }; 286 287 struct htt_hw_stats_whal_tx_tlv { 288 u32 mac_id__word; 289 u32 last_unpause_ppdu_id; 290 u32 hwsch_unpause_wait_tqm_write; 291 u32 hwsch_dummy_tlv_skipped; 292 u32 hwsch_misaligned_offset_received; 293 u32 hwsch_reset_count; 294 u32 hwsch_dev_reset_war; 295 u32 hwsch_delayed_pause; 296 u32 hwsch_long_delayed_pause; 297 u32 sch_rx_ppdu_no_response; 298 u32 sch_selfgen_response; 299 u32 sch_rx_sifs_resp_trigger; 300 }; 301 302 /* ============ PEER STATS ============ */ 303 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0) 304 #define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16) 305 #define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20) 306 307 struct htt_msdu_flow_stats_tlv { 308 u32 last_update_timestamp; 309 u32 last_add_timestamp; 310 u32 last_remove_timestamp; 311 u32 total_processed_msdu_count; 312 u32 cur_msdu_count_in_flowq; 313 u32 sw_peer_id; 314 u32 tx_flow_no__tid_num__drop_rule; 315 u32 last_cycle_enqueue_count; 316 u32 last_cycle_dequeue_count; 317 u32 last_cycle_drop_count; 318 u32 current_drop_th; 319 }; 320 321 #define MAX_HTT_TID_NAME 8 322 323 #define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 324 #define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16) 325 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0) 326 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8) 327 328 /* Tidq stats */ 329 struct htt_tx_tid_stats_tlv { 330 /* Stored as little endian */ 331 u8 tid_name[MAX_HTT_TID_NAME]; 332 u32 sw_peer_id__tid_num; 333 u32 num_sched_pending__num_ppdu_in_hwq; 334 u32 tid_flags; 335 u32 hw_queued; 336 u32 hw_reaped; 337 u32 mpdus_hw_filter; 338 339 u32 qdepth_bytes; 340 u32 qdepth_num_msdu; 341 u32 qdepth_num_mpdu; 342 u32 last_scheduled_tsmp; 343 u32 pause_module_id; 344 u32 block_module_id; 345 u32 tid_tx_airtime; 346 }; 347 348 #define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0) 349 #define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16) 350 #define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0) 351 #define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8) 352 353 /* Tidq stats */ 354 struct htt_tx_tid_stats_v1_tlv { 355 /* Stored as little endian */ 356 u8 tid_name[MAX_HTT_TID_NAME]; 357 u32 sw_peer_id__tid_num; 358 u32 num_sched_pending__num_ppdu_in_hwq; 359 u32 tid_flags; 360 u32 max_qdepth_bytes; 361 u32 max_qdepth_n_msdus; 362 u32 rsvd; 363 364 u32 qdepth_bytes; 365 u32 qdepth_num_msdu; 366 u32 qdepth_num_mpdu; 367 u32 last_scheduled_tsmp; 368 u32 pause_module_id; 369 u32 block_module_id; 370 u32 tid_tx_airtime; 371 u32 allow_n_flags; 372 u32 sendn_frms_allowed; 373 }; 374 375 #define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 376 #define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16) 377 378 struct htt_rx_tid_stats_tlv { 379 u32 sw_peer_id__tid_num; 380 u8 tid_name[MAX_HTT_TID_NAME]; 381 u32 dup_in_reorder; 382 u32 dup_past_outside_window; 383 u32 dup_past_within_window; 384 u32 rxdesc_err_decrypt; 385 u32 tid_rx_airtime; 386 }; 387 388 #define HTT_MAX_COUNTER_NAME 8 389 struct htt_counter_tlv { 390 u8 counter_name[HTT_MAX_COUNTER_NAME]; 391 u32 count; 392 }; 393 394 struct htt_peer_stats_cmn_tlv { 395 u32 ppdu_cnt; 396 u32 mpdu_cnt; 397 u32 msdu_cnt; 398 u32 pause_bitmap; 399 u32 block_bitmap; 400 u32 current_timestamp; 401 u32 peer_tx_airtime; 402 u32 peer_rx_airtime; 403 s32 rssi; 404 u32 peer_enqueued_count_low; 405 u32 peer_enqueued_count_high; 406 u32 peer_dequeued_count_low; 407 u32 peer_dequeued_count_high; 408 u32 peer_dropped_count_low; 409 u32 peer_dropped_count_high; 410 u32 ppdu_transmitted_bytes_low; 411 u32 ppdu_transmitted_bytes_high; 412 u32 peer_ttl_removed_count; 413 u32 inactive_time; 414 }; 415 416 #define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0) 417 #define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8) 418 #define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16) 419 420 struct htt_peer_details_tlv { 421 u32 peer_type; 422 u32 sw_peer_id; 423 u32 vdev_pdev_ast_idx; 424 struct htt_mac_addr mac_addr; 425 u32 peer_flags; 426 u32 qpeer_flags; 427 }; 428 429 enum htt_stats_param_type { 430 HTT_STATS_PREAM_OFDM, 431 HTT_STATS_PREAM_CCK, 432 HTT_STATS_PREAM_HT, 433 HTT_STATS_PREAM_VHT, 434 HTT_STATS_PREAM_HE, 435 HTT_STATS_PREAM_RSVD, 436 HTT_STATS_PREAM_RSVD1, 437 438 HTT_STATS_PREAM_COUNT, 439 }; 440 441 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 442 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 443 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 444 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 445 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 446 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 447 448 struct htt_tx_peer_rate_stats_tlv { 449 u32 tx_ldpc; 450 u32 rts_cnt; 451 u32 ack_rssi; 452 453 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 454 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 455 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 456 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 457 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 458 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 459 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 460 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 461 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 462 463 /* Counters to track number of tx packets in each GI 464 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 465 */ 466 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 467 468 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 469 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 470 471 }; 472 473 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 474 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 475 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 476 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 477 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 478 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 479 480 struct htt_rx_peer_rate_stats_tlv { 481 u32 nsts; 482 483 /* Number of rx ldpc packets */ 484 u32 rx_ldpc; 485 /* Number of rx rts packets */ 486 u32 rts_cnt; 487 488 u32 rssi_mgmt; /* units = dB above noise floor */ 489 u32 rssi_data; /* units = dB above noise floor */ 490 u32 rssi_comb; /* units = dB above noise floor */ 491 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 492 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 493 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 494 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 495 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 496 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 497 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 498 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 499 /* units = dB above noise floor */ 500 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] 501 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 502 503 /* Counters to track number of rx packets in each GI in each mcs (0-11) */ 504 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] 505 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 506 }; 507 508 enum htt_peer_stats_req_mode { 509 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 510 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 511 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 512 }; 513 514 enum htt_peer_stats_tlv_enum { 515 HTT_PEER_STATS_CMN_TLV = 0, 516 HTT_PEER_DETAILS_TLV = 1, 517 HTT_TX_PEER_RATE_STATS_TLV = 2, 518 HTT_RX_PEER_RATE_STATS_TLV = 3, 519 HTT_TX_TID_STATS_TLV = 4, 520 HTT_RX_TID_STATS_TLV = 5, 521 HTT_MSDU_FLOW_STATS_TLV = 6, 522 523 HTT_PEER_STATS_MAX_TLV = 31, 524 }; 525 526 /* =========== MUMIMO HWQ stats =========== */ 527 /* MU MIMO stats per hwQ */ 528 struct htt_tx_hwq_mu_mimo_sch_stats_tlv { 529 u32 mu_mimo_sch_posted; 530 u32 mu_mimo_sch_failed; 531 u32 mu_mimo_ppdu_posted; 532 }; 533 534 struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv { 535 u32 mu_mimo_mpdus_queued_usr; 536 u32 mu_mimo_mpdus_tried_usr; 537 u32 mu_mimo_mpdus_failed_usr; 538 u32 mu_mimo_mpdus_requeued_usr; 539 u32 mu_mimo_err_no_ba_usr; 540 u32 mu_mimo_mpdu_underrun_usr; 541 u32 mu_mimo_ampdu_underrun_usr; 542 }; 543 544 #define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0) 545 #define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8) 546 547 struct htt_tx_hwq_mu_mimo_cmn_stats_tlv { 548 u32 mac_id__hwq_id__word; 549 }; 550 551 /* == TX HWQ STATS == */ 552 struct htt_tx_hwq_stats_cmn_tlv { 553 u32 mac_id__hwq_id__word; 554 555 /* PPDU level stats */ 556 u32 xretry; 557 u32 underrun_cnt; 558 u32 flush_cnt; 559 u32 filt_cnt; 560 u32 null_mpdu_bmap; 561 u32 user_ack_failure; 562 u32 ack_tlv_proc; 563 u32 sched_id_proc; 564 u32 null_mpdu_tx_count; 565 u32 mpdu_bmap_not_recvd; 566 567 /* Selfgen stats per hwQ */ 568 u32 num_bar; 569 u32 rts; 570 u32 cts2self; 571 u32 qos_null; 572 573 /* MPDU level stats */ 574 u32 mpdu_tried_cnt; 575 u32 mpdu_queued_cnt; 576 u32 mpdu_ack_fail_cnt; 577 u32 mpdu_filt_cnt; 578 u32 false_mpdu_ack_count; 579 580 u32 txq_timeout; 581 }; 582 583 /* NOTE: Variable length TLV, use length spec to infer array size */ 584 struct htt_tx_hwq_difs_latency_stats_tlv_v { 585 u32 hist_intvl; 586 /* histogram of ppdu post to hwsch - > cmd status received */ 587 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ 588 }; 589 590 /* NOTE: Variable length TLV, use length spec to infer array size */ 591 struct htt_tx_hwq_cmd_result_stats_tlv_v { 592 /* Histogram of sched cmd result */ 593 u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ 594 }; 595 596 /* NOTE: Variable length TLV, use length spec to infer array size */ 597 struct htt_tx_hwq_cmd_stall_stats_tlv_v { 598 /* Histogram of various pause conitions */ 599 u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ 600 }; 601 602 /* NOTE: Variable length TLV, use length spec to infer array size */ 603 struct htt_tx_hwq_fes_result_stats_tlv_v { 604 /* Histogram of number of user fes result */ 605 u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ 606 }; 607 608 /* NOTE: Variable length TLV, use length spec to infer array size 609 * 610 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 611 * The tries here is the count of the MPDUS within a PPDU that the HW 612 * had attempted to transmit on air, for the HWSCH Schedule command 613 * submitted by FW in this HWQ .It is not the retry attempts. The 614 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 615 * in this histogram. 616 * they are defined in FW using the following macros 617 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 618 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 619 */ 620 struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v { 621 u32 hist_bin_size; 622 /* Histogram of number of mpdus on tried mpdu */ 623 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ 624 }; 625 626 /* NOTE: Variable length TLV, use length spec to infer array size 627 * 628 * The txop_used_cnt_hist is the histogram of txop per burst. After 629 * completing the burst, we identify the txop used in the burst and 630 * incr the corresponding bin. 631 * Each bin represents 1ms & we have 10 bins in this histogram. 632 * they are deined in FW using the following macros 633 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 634 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 635 */ 636 struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { 637 /* Histogram of txop used cnt */ 638 u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ 639 }; 640 641 /* == TX SELFGEN STATS == */ 642 struct htt_tx_selfgen_cmn_stats_tlv { 643 u32 mac_id__word; 644 u32 su_bar; 645 u32 rts; 646 u32 cts2self; 647 u32 qos_null; 648 u32 delayed_bar_1; /* MU user 1 */ 649 u32 delayed_bar_2; /* MU user 2 */ 650 u32 delayed_bar_3; /* MU user 3 */ 651 u32 delayed_bar_4; /* MU user 4 */ 652 u32 delayed_bar_5; /* MU user 5 */ 653 u32 delayed_bar_6; /* MU user 6 */ 654 u32 delayed_bar_7; /* MU user 7 */ 655 }; 656 657 struct htt_tx_selfgen_ac_stats_tlv { 658 /* 11AC */ 659 u32 ac_su_ndpa; 660 u32 ac_su_ndp; 661 u32 ac_mu_mimo_ndpa; 662 u32 ac_mu_mimo_ndp; 663 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */ 664 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */ 665 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */ 666 }; 667 668 struct htt_tx_selfgen_ax_stats_tlv { 669 /* 11AX */ 670 u32 ax_su_ndpa; 671 u32 ax_su_ndp; 672 u32 ax_mu_mimo_ndpa; 673 u32 ax_mu_mimo_ndp; 674 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */ 675 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */ 676 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */ 677 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */ 678 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */ 679 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */ 680 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */ 681 u32 ax_basic_trigger; 682 u32 ax_bsr_trigger; 683 u32 ax_mu_bar_trigger; 684 u32 ax_mu_rts_trigger; 685 }; 686 687 struct htt_tx_selfgen_ac_err_stats_tlv { 688 /* 11AC error stats */ 689 u32 ac_su_ndp_err; 690 u32 ac_su_ndpa_err; 691 u32 ac_mu_mimo_ndpa_err; 692 u32 ac_mu_mimo_ndp_err; 693 u32 ac_mu_mimo_brp1_err; 694 u32 ac_mu_mimo_brp2_err; 695 u32 ac_mu_mimo_brp3_err; 696 }; 697 698 struct htt_tx_selfgen_ax_err_stats_tlv { 699 /* 11AX error stats */ 700 u32 ax_su_ndp_err; 701 u32 ax_su_ndpa_err; 702 u32 ax_mu_mimo_ndpa_err; 703 u32 ax_mu_mimo_ndp_err; 704 u32 ax_mu_mimo_brp1_err; 705 u32 ax_mu_mimo_brp2_err; 706 u32 ax_mu_mimo_brp3_err; 707 u32 ax_mu_mimo_brp4_err; 708 u32 ax_mu_mimo_brp5_err; 709 u32 ax_mu_mimo_brp6_err; 710 u32 ax_mu_mimo_brp7_err; 711 u32 ax_basic_trigger_err; 712 u32 ax_bsr_trigger_err; 713 u32 ax_mu_bar_trigger_err; 714 u32 ax_mu_rts_trigger_err; 715 }; 716 717 /* == TX MU STATS == */ 718 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 719 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 720 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 721 722 struct htt_tx_pdev_mu_mimo_sch_stats_tlv { 723 /* mu-mimo sw sched cmd stats */ 724 u32 mu_mimo_sch_posted; 725 u32 mu_mimo_sch_failed; 726 /* MU PPDU stats per hwQ */ 727 u32 mu_mimo_ppdu_posted; 728 /* 729 * Counts the number of users in each transmission of 730 * the given TX mode. 731 * 732 * Index is the number of users - 1. 733 */ 734 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 735 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 736 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 737 }; 738 739 struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv { 740 u32 mu_mimo_mpdus_queued_usr; 741 u32 mu_mimo_mpdus_tried_usr; 742 u32 mu_mimo_mpdus_failed_usr; 743 u32 mu_mimo_mpdus_requeued_usr; 744 u32 mu_mimo_err_no_ba_usr; 745 u32 mu_mimo_mpdu_underrun_usr; 746 u32 mu_mimo_ampdu_underrun_usr; 747 748 u32 ax_mu_mimo_mpdus_queued_usr; 749 u32 ax_mu_mimo_mpdus_tried_usr; 750 u32 ax_mu_mimo_mpdus_failed_usr; 751 u32 ax_mu_mimo_mpdus_requeued_usr; 752 u32 ax_mu_mimo_err_no_ba_usr; 753 u32 ax_mu_mimo_mpdu_underrun_usr; 754 u32 ax_mu_mimo_ampdu_underrun_usr; 755 756 u32 ax_ofdma_mpdus_queued_usr; 757 u32 ax_ofdma_mpdus_tried_usr; 758 u32 ax_ofdma_mpdus_failed_usr; 759 u32 ax_ofdma_mpdus_requeued_usr; 760 u32 ax_ofdma_err_no_ba_usr; 761 u32 ax_ofdma_mpdu_underrun_usr; 762 u32 ax_ofdma_ampdu_underrun_usr; 763 }; 764 765 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 766 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 767 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 768 769 struct htt_tx_pdev_mpdu_stats_tlv { 770 /* mpdu level stats */ 771 u32 mpdus_queued_usr; 772 u32 mpdus_tried_usr; 773 u32 mpdus_failed_usr; 774 u32 mpdus_requeued_usr; 775 u32 err_no_ba_usr; 776 u32 mpdu_underrun_usr; 777 u32 ampdu_underrun_usr; 778 u32 user_index; 779 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ 780 }; 781 782 /* == TX SCHED STATS == */ 783 /* NOTE: Variable length TLV, use length spec to infer array size */ 784 struct htt_sched_txq_cmd_posted_tlv_v { 785 u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 786 }; 787 788 /* NOTE: Variable length TLV, use length spec to infer array size */ 789 struct htt_sched_txq_cmd_reaped_tlv_v { 790 u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 791 }; 792 793 /* NOTE: Variable length TLV, use length spec to infer array size */ 794 struct htt_sched_txq_sched_order_su_tlv_v { 795 u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ 796 }; 797 798 enum htt_sched_txq_sched_ineligibility_tlv_enum { 799 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, 800 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, 801 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, 802 HTT_SCHED_TID_SKIP_SCHED_DISABLED, 803 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, 804 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, 805 806 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, 807 HTT_SCHED_TID_SKIP_NO_ENQ, 808 HTT_SCHED_TID_SKIP_LOW_ENQ, 809 HTT_SCHED_TID_SKIP_PAUSED, 810 HTT_SCHED_TID_SKIP_UL, 811 HTT_SCHED_TID_REMOVE_PAUSED, 812 HTT_SCHED_TID_REMOVE_NO_ENQ, 813 HTT_SCHED_TID_REMOVE_UL, 814 HTT_SCHED_TID_QUERY, 815 HTT_SCHED_TID_SU_ONLY, 816 HTT_SCHED_TID_ELIGIBLE, 817 HTT_SCHED_INELIGIBILITY_MAX, 818 }; 819 820 /* NOTE: Variable length TLV, use length spec to infer array size */ 821 struct htt_sched_txq_sched_ineligibility_tlv_v { 822 /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ 823 u32 sched_ineligibility[0]; 824 }; 825 826 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 827 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 828 829 struct htt_tx_pdev_stats_sched_per_txq_tlv { 830 u32 mac_id__txq_id__word; 831 u32 sched_policy; 832 u32 last_sched_cmd_posted_timestamp; 833 u32 last_sched_cmd_compl_timestamp; 834 u32 sched_2_tac_lwm_count; 835 u32 sched_2_tac_ring_full; 836 u32 sched_cmd_post_failure; 837 u32 num_active_tids; 838 u32 num_ps_schedules; 839 u32 sched_cmds_pending; 840 u32 num_tid_register; 841 u32 num_tid_unregister; 842 u32 num_qstats_queried; 843 u32 qstats_update_pending; 844 u32 last_qstats_query_timestamp; 845 u32 num_tqm_cmdq_full; 846 u32 num_de_sched_algo_trigger; 847 u32 num_rt_sched_algo_trigger; 848 u32 num_tqm_sched_algo_trigger; 849 u32 notify_sched; 850 u32 dur_based_sendn_term; 851 }; 852 853 struct htt_stats_tx_sched_cmn_tlv { 854 /* BIT [ 7 : 0] :- mac_id 855 * BIT [31 : 8] :- reserved 856 */ 857 u32 mac_id__word; 858 /* Current timestamp */ 859 u32 current_timestamp; 860 }; 861 862 /* == TQM STATS == */ 863 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16 864 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 865 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 866 867 /* NOTE: Variable length TLV, use length spec to infer array size */ 868 struct htt_tx_tqm_gen_mpdu_stats_tlv_v { 869 u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 870 }; 871 872 /* NOTE: Variable length TLV, use length spec to infer array size */ 873 struct htt_tx_tqm_list_mpdu_stats_tlv_v { 874 u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 875 }; 876 877 /* NOTE: Variable length TLV, use length spec to infer array size */ 878 struct htt_tx_tqm_list_mpdu_cnt_tlv_v { 879 u32 list_mpdu_cnt_hist[0]; 880 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 881 }; 882 883 struct htt_tx_tqm_pdev_stats_tlv_v { 884 u32 msdu_count; 885 u32 mpdu_count; 886 u32 remove_msdu; 887 u32 remove_mpdu; 888 u32 remove_msdu_ttl; 889 u32 send_bar; 890 u32 bar_sync; 891 u32 notify_mpdu; 892 u32 sync_cmd; 893 u32 write_cmd; 894 u32 hwsch_trigger; 895 u32 ack_tlv_proc; 896 u32 gen_mpdu_cmd; 897 u32 gen_list_cmd; 898 u32 remove_mpdu_cmd; 899 u32 remove_mpdu_tried_cmd; 900 u32 mpdu_queue_stats_cmd; 901 u32 mpdu_head_info_cmd; 902 u32 msdu_flow_stats_cmd; 903 u32 remove_msdu_cmd; 904 u32 remove_msdu_ttl_cmd; 905 u32 flush_cache_cmd; 906 u32 update_mpduq_cmd; 907 u32 enqueue; 908 u32 enqueue_notify; 909 u32 notify_mpdu_at_head; 910 u32 notify_mpdu_state_valid; 911 /* 912 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 913 * the flow is non empty), if the number of MSDUs is greater than the threshold, 914 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 915 * for non-UDP MSDUs. 916 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 917 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 918 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 919 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 920 * 921 * Notify signifies that we trigger the scheduler. 922 */ 923 u32 sched_udp_notify1; 924 u32 sched_udp_notify2; 925 u32 sched_nonudp_notify1; 926 u32 sched_nonudp_notify2; 927 }; 928 929 struct htt_tx_tqm_cmn_stats_tlv { 930 u32 mac_id__word; 931 u32 max_cmdq_id; 932 u32 list_mpdu_cnt_hist_intvl; 933 934 /* Global stats */ 935 u32 add_msdu; 936 u32 q_empty; 937 u32 q_not_empty; 938 u32 drop_notification; 939 u32 desc_threshold; 940 }; 941 942 struct htt_tx_tqm_error_stats_tlv { 943 /* Error stats */ 944 u32 q_empty_failure; 945 u32 q_not_empty_failure; 946 u32 add_msdu_failure; 947 }; 948 949 /* == TQM CMDQ stats == */ 950 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0) 951 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8) 952 953 struct htt_tx_tqm_cmdq_status_tlv { 954 u32 mac_id__cmdq_id__word; 955 u32 sync_cmd; 956 u32 write_cmd; 957 u32 gen_mpdu_cmd; 958 u32 mpdu_queue_stats_cmd; 959 u32 mpdu_head_info_cmd; 960 u32 msdu_flow_stats_cmd; 961 u32 remove_mpdu_cmd; 962 u32 remove_msdu_cmd; 963 u32 flush_cache_cmd; 964 u32 update_mpduq_cmd; 965 u32 update_msduq_cmd; 966 }; 967 968 /* == TX-DE STATS == */ 969 /* Structures for tx de stats */ 970 struct htt_tx_de_eapol_packets_stats_tlv { 971 u32 m1_packets; 972 u32 m2_packets; 973 u32 m3_packets; 974 u32 m4_packets; 975 u32 g1_packets; 976 u32 g2_packets; 977 }; 978 979 struct htt_tx_de_classify_failed_stats_tlv { 980 u32 ap_bss_peer_not_found; 981 u32 ap_bcast_mcast_no_peer; 982 u32 sta_delete_in_progress; 983 u32 ibss_no_bss_peer; 984 u32 invalid_vdev_type; 985 u32 invalid_ast_peer_entry; 986 u32 peer_entry_invalid; 987 u32 ethertype_not_ip; 988 u32 eapol_lookup_failed; 989 u32 qpeer_not_allow_data; 990 u32 fse_tid_override; 991 u32 ipv6_jumbogram_zero_length; 992 u32 qos_to_non_qos_in_prog; 993 }; 994 995 struct htt_tx_de_classify_stats_tlv { 996 u32 arp_packets; 997 u32 igmp_packets; 998 u32 dhcp_packets; 999 u32 host_inspected; 1000 u32 htt_included; 1001 u32 htt_valid_mcs; 1002 u32 htt_valid_nss; 1003 u32 htt_valid_preamble_type; 1004 u32 htt_valid_chainmask; 1005 u32 htt_valid_guard_interval; 1006 u32 htt_valid_retries; 1007 u32 htt_valid_bw_info; 1008 u32 htt_valid_power; 1009 u32 htt_valid_key_flags; 1010 u32 htt_valid_no_encryption; 1011 u32 fse_entry_count; 1012 u32 fse_priority_be; 1013 u32 fse_priority_high; 1014 u32 fse_priority_low; 1015 u32 fse_traffic_ptrn_be; 1016 u32 fse_traffic_ptrn_over_sub; 1017 u32 fse_traffic_ptrn_bursty; 1018 u32 fse_traffic_ptrn_interactive; 1019 u32 fse_traffic_ptrn_periodic; 1020 u32 fse_hwqueue_alloc; 1021 u32 fse_hwqueue_created; 1022 u32 fse_hwqueue_send_to_host; 1023 u32 mcast_entry; 1024 u32 bcast_entry; 1025 u32 htt_update_peer_cache; 1026 u32 htt_learning_frame; 1027 u32 fse_invalid_peer; 1028 /* 1029 * mec_notify is HTT TX WBM multicast echo check notification 1030 * from firmware to host. FW sends SA addresses to host for all 1031 * multicast/broadcast packets received on STA side. 1032 */ 1033 u32 mec_notify; 1034 }; 1035 1036 struct htt_tx_de_classify_status_stats_tlv { 1037 u32 eok; 1038 u32 classify_done; 1039 u32 lookup_failed; 1040 u32 send_host_dhcp; 1041 u32 send_host_mcast; 1042 u32 send_host_unknown_dest; 1043 u32 send_host; 1044 u32 status_invalid; 1045 }; 1046 1047 struct htt_tx_de_enqueue_packets_stats_tlv { 1048 u32 enqueued_pkts; 1049 u32 to_tqm; 1050 u32 to_tqm_bypass; 1051 }; 1052 1053 struct htt_tx_de_enqueue_discard_stats_tlv { 1054 u32 discarded_pkts; 1055 u32 local_frames; 1056 u32 is_ext_msdu; 1057 }; 1058 1059 struct htt_tx_de_compl_stats_tlv { 1060 u32 tcl_dummy_frame; 1061 u32 tqm_dummy_frame; 1062 u32 tqm_notify_frame; 1063 u32 fw2wbm_enq; 1064 u32 tqm_bypass_frame; 1065 }; 1066 1067 /* 1068 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 1069 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 1070 * ring,which may fail, due to non availability of buffer. Hence we sleep for 1071 * 200us & again request for it. This is a histogram of time we wait, with 1072 * bin of 200ms & there are 10 bin (2 seconds max) 1073 * They are defined by the following macros in FW 1074 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 1075 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 1076 * ENTRIES_PER_BIN_COUNT) 1077 */ 1078 struct htt_tx_de_fw2wbm_ring_full_hist_tlv { 1079 u32 fw2wbm_ring_full_hist[0]; 1080 }; 1081 1082 struct htt_tx_de_cmn_stats_tlv { 1083 u32 mac_id__word; 1084 1085 /* Global Stats */ 1086 u32 tcl2fw_entry_count; 1087 u32 not_to_fw; 1088 u32 invalid_pdev_vdev_peer; 1089 u32 tcl_res_invalid_addrx; 1090 u32 wbm2fw_entry_count; 1091 u32 invalid_pdev; 1092 }; 1093 1094 /* == RING-IF STATS == */ 1095 #define HTT_STATS_LOW_WM_BINS 5 1096 #define HTT_STATS_HIGH_WM_BINS 5 1097 1098 #define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0) 1099 #define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16) 1100 #define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0) 1101 #define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16) 1102 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0) 1103 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16) 1104 #define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0) 1105 #define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16) 1106 1107 struct htt_ring_if_stats_tlv { 1108 u32 base_addr; /* DWORD aligned base memory address of the ring */ 1109 u32 elem_size; 1110 u32 num_elems__prefetch_tail_idx; 1111 u32 head_idx__tail_idx; 1112 u32 shadow_head_idx__shadow_tail_idx; 1113 u32 num_tail_incr; 1114 u32 lwm_thresh__hwm_thresh; 1115 u32 overrun_hit_count; 1116 u32 underrun_hit_count; 1117 u32 prod_blockwait_count; 1118 u32 cons_blockwait_count; 1119 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 1120 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 1121 }; 1122 1123 struct htt_ring_if_cmn_tlv { 1124 u32 mac_id__word; 1125 u32 num_records; 1126 }; 1127 1128 /* == SFM STATS == */ 1129 /* NOTE: Variable length TLV, use length spec to infer array size */ 1130 struct htt_sfm_client_user_tlv_v { 1131 /* Number of DWORDS used per user and per client */ 1132 u32 dwords_used_by_user_n[0]; 1133 }; 1134 1135 struct htt_sfm_client_tlv { 1136 /* Client ID */ 1137 u32 client_id; 1138 /* Minimum number of buffers */ 1139 u32 buf_min; 1140 /* Maximum number of buffers */ 1141 u32 buf_max; 1142 /* Number of Busy buffers */ 1143 u32 buf_busy; 1144 /* Number of Allocated buffers */ 1145 u32 buf_alloc; 1146 /* Number of Available/Usable buffers */ 1147 u32 buf_avail; 1148 /* Number of users */ 1149 u32 num_users; 1150 }; 1151 1152 struct htt_sfm_cmn_tlv { 1153 u32 mac_id__word; 1154 /* Indicates the total number of 128 byte buffers 1155 * in the CMEM that are available for buffer sharing 1156 */ 1157 u32 buf_total; 1158 /* Indicates for certain client or all the clients 1159 * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY 1160 */ 1161 u32 mem_empty; 1162 /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 1163 u32 deallocate_bufs; 1164 /* Number of Records */ 1165 u32 num_records; 1166 }; 1167 1168 /* == SRNG STATS == */ 1169 #define HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1170 #define HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1171 #define HTT_SRING_STATS_ARENA GENMASK(23, 16) 1172 #define HTT_SRING_STATS_EP BIT(24) 1173 #define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1174 #define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1175 #define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1176 #define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1177 #define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1178 #define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1179 #define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1180 #define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1181 1182 struct htt_sring_stats_tlv { 1183 u32 mac_id__ring_id__arena__ep; 1184 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ 1185 u32 base_addr_msb; 1186 u32 ring_size; 1187 u32 elem_size; 1188 1189 u32 num_avail_words__num_valid_words; 1190 u32 head_ptr__tail_ptr; 1191 u32 consumer_empty__producer_full; 1192 u32 prefetch_count__internal_tail_ptr; 1193 }; 1194 1195 struct htt_sring_cmn_tlv { 1196 u32 num_records; 1197 }; 1198 1199 /* == PDEV TX RATE CTRL STATS == */ 1200 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 1201 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 1202 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 1203 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1204 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1205 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1206 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1207 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1208 #define HTT_TX_PDEV_STATS_NUM_LTF 4 1209 1210 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1211 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1212 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 1213 1214 struct htt_tx_pdev_rate_stats_tlv { 1215 u32 mac_id__word; 1216 u32 tx_ldpc; 1217 u32 rts_cnt; 1218 /* RSSI value of last ack packet (units = dB above noise floor) */ 1219 u32 ack_rssi; 1220 1221 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1222 1223 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1224 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1225 1226 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1227 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1228 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1229 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1230 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1231 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1232 1233 /* Counters to track number of tx packets 1234 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) 1235 */ 1236 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1237 1238 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 1239 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 1240 /* Number of CTS-acknowledged RTS packets */ 1241 u32 rts_success; 1242 1243 /* 1244 * Counters for legacy 11a and 11b transmissions. 1245 * 1246 * The index corresponds to: 1247 * 1248 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 1249 * 1250 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 1251 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 1252 */ 1253 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1254 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1255 1256 u32 ac_mu_mimo_tx_ldpc; 1257 u32 ax_mu_mimo_tx_ldpc; 1258 u32 ofdma_tx_ldpc; 1259 1260 /* 1261 * Counters for 11ax HE LTF selection during TX. 1262 * 1263 * The index corresponds to: 1264 * 1265 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 1266 */ 1267 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 1268 1269 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1270 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1271 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1272 1273 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1274 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1275 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1276 1277 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1278 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1279 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1280 1281 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1282 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1283 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1284 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1285 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1286 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1287 }; 1288 1289 /* == PDEV RX RATE CTRL STATS == */ 1290 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1291 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1292 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 1293 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 1294 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 1295 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 1296 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1297 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1298 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 1299 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 1300 1301 struct htt_rx_pdev_rate_stats_tlv { 1302 u32 mac_id__word; 1303 u32 nsts; 1304 1305 u32 rx_ldpc; 1306 u32 rts_cnt; 1307 1308 u32 rssi_mgmt; /* units = dB above noise floor */ 1309 u32 rssi_data; /* units = dB above noise floor */ 1310 u32 rssi_comb; /* units = dB above noise floor */ 1311 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1312 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1313 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1314 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 1315 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1316 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1317 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1318 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1319 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1320 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1321 /* units = dB above noise floor */ 1322 1323 /* Counters to track number of rx packets 1324 * in each GI in each mcs (0-11) 1325 */ 1326 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1327 s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ 1328 1329 u32 rx_11ax_su_ext; 1330 u32 rx_11ac_mumimo; 1331 u32 rx_11ax_mumimo; 1332 u32 rx_11ax_ofdma; 1333 u32 txbf; 1334 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1335 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1336 u32 rx_active_dur_us_low; 1337 u32 rx_active_dur_us_high; 1338 1339 u32 rx_11ax_ul_ofdma; 1340 1341 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1342 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1343 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1344 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1345 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1346 u32 ul_ofdma_rx_stbc; 1347 u32 ul_ofdma_rx_ldpc; 1348 1349 /* record the stats for each user index */ 1350 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1351 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1352 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1353 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1354 1355 u32 nss_count; 1356 u32 pilot_count; 1357 /* RxEVM stats in dB */ 1358 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1359 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 1360 /* rx_pilot_evm_db_mean: 1361 * EVM mean across pilots, computed as 1362 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db) 1363 */ 1364 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1365 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1366 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ 1367 /* per_chain_rssi_pkt_type: 1368 * This field shows what type of rx frame the per-chain RSSI was computed 1369 * on, by recording the frame type and sub-type as bit-fields within this 1370 * field: 1371 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 1372 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 1373 * BIT [31 : 8] :- Reserved 1374 */ 1375 u32 per_chain_rssi_pkt_type; 1376 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1377 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1378 }; 1379 1380 /* == RX PDEV/SOC STATS == */ 1381 struct htt_rx_soc_fw_stats_tlv { 1382 u32 fw_reo_ring_data_msdu; 1383 u32 fw_to_host_data_msdu_bcmc; 1384 u32 fw_to_host_data_msdu_uc; 1385 u32 ofld_remote_data_buf_recycle_cnt; 1386 u32 ofld_remote_free_buf_indication_cnt; 1387 1388 u32 ofld_buf_to_host_data_msdu_uc; 1389 u32 reo_fw_ring_to_host_data_msdu_uc; 1390 1391 u32 wbm_sw_ring_reap; 1392 u32 wbm_forward_to_host_cnt; 1393 u32 wbm_target_recycle_cnt; 1394 1395 u32 target_refill_ring_recycle_cnt; 1396 }; 1397 1398 /* NOTE: Variable length TLV, use length spec to infer array size */ 1399 struct htt_rx_soc_fw_refill_ring_empty_tlv_v { 1400 u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ 1401 }; 1402 1403 /* NOTE: Variable length TLV, use length spec to infer array size */ 1404 struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 1405 u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ 1406 }; 1407 1408 /* RXDMA error code from WBM released packets */ 1409 enum htt_rx_rxdma_error_code_enum { 1410 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 1411 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 1412 HTT_RX_RXDMA_FCS_ERR = 2, 1413 HTT_RX_RXDMA_DECRYPT_ERR = 3, 1414 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 1415 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 1416 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 1417 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 1418 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 1419 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 1420 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 1421 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 1422 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 1423 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 1424 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 1425 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 1426 1427 /* This MAX_ERR_CODE should not be used in any host/target messages, 1428 * so that even though it is defined within a host/target interface 1429 * definition header file, it isn't actually part of the host/target 1430 * interface, and thus can be modified. 1431 */ 1432 HTT_RX_RXDMA_MAX_ERR_CODE 1433 }; 1434 1435 /* NOTE: Variable length TLV, use length spec to infer array size */ 1436 struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { 1437 u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ 1438 }; 1439 1440 /* REO error code from WBM released packets */ 1441 enum htt_rx_reo_error_code_enum { 1442 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 1443 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 1444 HTT_RX_AMPDU_IN_NON_BA = 2, 1445 HTT_RX_NON_BA_DUPLICATE = 3, 1446 HTT_RX_BA_DUPLICATE = 4, 1447 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 1448 HTT_RX_BAR_FRAME_2K_JUMP = 6, 1449 HTT_RX_REGULAR_FRAME_OOR = 7, 1450 HTT_RX_BAR_FRAME_OOR = 8, 1451 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 1452 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 1453 HTT_RX_PN_CHECK_FAILED = 11, 1454 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 1455 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 1456 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 1457 HTT_RX_REO_ERR_CODE_RVSD = 15, 1458 1459 /* This MAX_ERR_CODE should not be used in any host/target messages, 1460 * so that even though it is defined within a host/target interface 1461 * definition header file, it isn't actually part of the host/target 1462 * interface, and thus can be modified. 1463 */ 1464 HTT_RX_REO_MAX_ERR_CODE 1465 }; 1466 1467 /* NOTE: Variable length TLV, use length spec to infer array size */ 1468 struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { 1469 u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */ 1470 }; 1471 1472 /* == RX PDEV STATS == */ 1473 #define HTT_STATS_SUBTYPE_MAX 16 1474 1475 struct htt_rx_pdev_fw_stats_tlv { 1476 u32 mac_id__word; 1477 u32 ppdu_recvd; 1478 u32 mpdu_cnt_fcs_ok; 1479 u32 mpdu_cnt_fcs_err; 1480 u32 tcp_msdu_cnt; 1481 u32 tcp_ack_msdu_cnt; 1482 u32 udp_msdu_cnt; 1483 u32 other_msdu_cnt; 1484 u32 fw_ring_mpdu_ind; 1485 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1486 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 1487 u32 fw_ring_mcast_data_msdu; 1488 u32 fw_ring_bcast_data_msdu; 1489 u32 fw_ring_ucast_data_msdu; 1490 u32 fw_ring_null_data_msdu; 1491 u32 fw_ring_mpdu_drop; 1492 u32 ofld_local_data_ind_cnt; 1493 u32 ofld_local_data_buf_recycle_cnt; 1494 u32 drx_local_data_ind_cnt; 1495 u32 drx_local_data_buf_recycle_cnt; 1496 u32 local_nondata_ind_cnt; 1497 u32 local_nondata_buf_recycle_cnt; 1498 1499 u32 fw_status_buf_ring_refill_cnt; 1500 u32 fw_status_buf_ring_empty_cnt; 1501 u32 fw_pkt_buf_ring_refill_cnt; 1502 u32 fw_pkt_buf_ring_empty_cnt; 1503 u32 fw_link_buf_ring_refill_cnt; 1504 u32 fw_link_buf_ring_empty_cnt; 1505 1506 u32 host_pkt_buf_ring_refill_cnt; 1507 u32 host_pkt_buf_ring_empty_cnt; 1508 u32 mon_pkt_buf_ring_refill_cnt; 1509 u32 mon_pkt_buf_ring_empty_cnt; 1510 u32 mon_status_buf_ring_refill_cnt; 1511 u32 mon_status_buf_ring_empty_cnt; 1512 u32 mon_desc_buf_ring_refill_cnt; 1513 u32 mon_desc_buf_ring_empty_cnt; 1514 u32 mon_dest_ring_update_cnt; 1515 u32 mon_dest_ring_full_cnt; 1516 1517 u32 rx_suspend_cnt; 1518 u32 rx_suspend_fail_cnt; 1519 u32 rx_resume_cnt; 1520 u32 rx_resume_fail_cnt; 1521 u32 rx_ring_switch_cnt; 1522 u32 rx_ring_restore_cnt; 1523 u32 rx_flush_cnt; 1524 u32 rx_recovery_reset_cnt; 1525 }; 1526 1527 #define HTT_STATS_PHY_ERR_MAX 43 1528 1529 struct htt_rx_pdev_fw_stats_phy_err_tlv { 1530 u32 mac_id__word; 1531 u32 total_phy_err_cnt; 1532 /* Counts of different types of phy errs 1533 * The mapping of PHY error types to phy_err array elements is HW dependent. 1534 * The only currently-supported mapping is shown below: 1535 * 1536 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 1537 * 1 phyrx_err_synth_off 1538 * 2 phyrx_err_ofdma_timing 1539 * 3 phyrx_err_ofdma_signal_parity 1540 * 4 phyrx_err_ofdma_rate_illegal 1541 * 5 phyrx_err_ofdma_length_illegal 1542 * 6 phyrx_err_ofdma_restart 1543 * 7 phyrx_err_ofdma_service 1544 * 8 phyrx_err_ppdu_ofdma_power_drop 1545 * 9 phyrx_err_cck_blokker 1546 * 10 phyrx_err_cck_timing 1547 * 11 phyrx_err_cck_header_crc 1548 * 12 phyrx_err_cck_rate_illegal 1549 * 13 phyrx_err_cck_length_illegal 1550 * 14 phyrx_err_cck_restart 1551 * 15 phyrx_err_cck_service 1552 * 16 phyrx_err_cck_power_drop 1553 * 17 phyrx_err_ht_crc_err 1554 * 18 phyrx_err_ht_length_illegal 1555 * 19 phyrx_err_ht_rate_illegal 1556 * 20 phyrx_err_ht_zlf 1557 * 21 phyrx_err_false_radar_ext 1558 * 22 phyrx_err_green_field 1559 * 23 phyrx_err_bw_gt_dyn_bw 1560 * 24 phyrx_err_leg_ht_mismatch 1561 * 25 phyrx_err_vht_crc_error 1562 * 26 phyrx_err_vht_siga_unsupported 1563 * 27 phyrx_err_vht_lsig_len_invalid 1564 * 28 phyrx_err_vht_ndp_or_zlf 1565 * 29 phyrx_err_vht_nsym_lt_zero 1566 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 1567 * 31 phyrx_err_vht_rx_skip_group_id0 1568 * 32 phyrx_err_vht_rx_skip_group_id1to62 1569 * 33 phyrx_err_vht_rx_skip_group_id63 1570 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 1571 * 35 phyrx_err_defer_nap 1572 * 36 phyrx_err_fdomain_timeout 1573 * 37 phyrx_err_lsig_rel_check 1574 * 38 phyrx_err_bt_collision 1575 * 39 phyrx_err_unsupported_mu_feedback 1576 * 40 phyrx_err_ppdu_tx_interrupt_rx 1577 * 41 phyrx_err_unsupported_cbf 1578 * 42 phyrx_err_other 1579 */ 1580 u32 phy_err[HTT_STATS_PHY_ERR_MAX]; 1581 }; 1582 1583 /* NOTE: Variable length TLV, use length spec to infer array size */ 1584 struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 1585 /* Num error MPDU for each RxDMA error type */ 1586 u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ 1587 }; 1588 1589 /* NOTE: Variable length TLV, use length spec to infer array size */ 1590 struct htt_rx_pdev_fw_mpdu_drop_tlv_v { 1591 /* Num MPDU dropped */ 1592 u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 1593 }; 1594 1595 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 1596 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 1597 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 1598 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 1599 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 1600 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 1601 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 1602 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 1603 1604 struct htt_pdev_stats_cca_counters_tlv { 1605 /* Below values are obtained from the HW Cycles counter registers */ 1606 u32 tx_frame_usec; 1607 u32 rx_frame_usec; 1608 u32 rx_clear_usec; 1609 u32 my_rx_frame_usec; 1610 u32 usec_cnt; 1611 u32 med_rx_idle_usec; 1612 u32 med_tx_idle_global_usec; 1613 u32 cca_obss_usec; 1614 }; 1615 1616 struct htt_pdev_cca_stats_hist_v1_tlv { 1617 u32 chan_num; 1618 /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 1619 u32 num_records; 1620 u32 valid_cca_counters_bitmap; 1621 u32 collection_interval; 1622 1623 /* This will be followed by an array which contains the CCA stats 1624 * collected in the last N intervals, 1625 * if the indication is for last N intervals CCA stats. 1626 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 1627 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 1628 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 1629 */ 1630 }; 1631 1632 struct htt_pdev_stats_twt_session_tlv { 1633 u32 vdev_id; 1634 struct htt_mac_addr peer_mac; 1635 u32 flow_id_flags; 1636 1637 /* TWT_DIALOG_ID_UNAVAILABLE is used 1638 * when TWT session is not initiated by host 1639 */ 1640 u32 dialog_id; 1641 u32 wake_dura_us; 1642 u32 wake_intvl_us; 1643 u32 sp_offset_us; 1644 }; 1645 1646 struct htt_pdev_stats_twt_sessions_tlv { 1647 u32 pdev_id; 1648 u32 num_sessions; 1649 struct htt_pdev_stats_twt_session_tlv twt_session[]; 1650 }; 1651 1652 enum htt_rx_reo_resource_sample_id_enum { 1653 /* Global link descriptor queued in REO */ 1654 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 1655 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 1656 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 1657 /*Number of queue descriptors of this aging group */ 1658 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 1659 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 1660 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 1661 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 1662 /* Total number of MSDUs buffered in AC */ 1663 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 1664 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 1665 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 1666 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 1667 1668 HTT_RX_REO_RESOURCE_STATS_MAX = 16 1669 }; 1670 1671 struct htt_rx_reo_resource_stats_tlv_v { 1672 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 1673 u32 sample_id; 1674 u32 total_max; 1675 u32 total_avg; 1676 u32 total_sample; 1677 u32 non_zeros_avg; 1678 u32 non_zeros_sample; 1679 u32 last_non_zeros_max; 1680 u32 last_non_zeros_min; 1681 u32 last_non_zeros_avg; 1682 u32 last_non_zeros_sample; 1683 }; 1684 1685 /* == TX SOUNDING STATS == */ 1686 1687 enum htt_txbf_sound_steer_modes { 1688 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 1689 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 1690 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 1691 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 1692 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 1693 HTT_TXBF_MAX_NUM_OF_MODES = 5 1694 }; 1695 1696 enum htt_stats_sounding_tx_mode { 1697 HTT_TX_AC_SOUNDING_MODE = 0, 1698 HTT_TX_AX_SOUNDING_MODE = 1, 1699 }; 1700 1701 struct htt_tx_sounding_stats_tlv { 1702 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 1703 /* Counts number of soundings for all steering modes in each bw */ 1704 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 1705 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 1706 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 1707 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 1708 /* 1709 * The sounding array is a 2-D array stored as an 1-D array of 1710 * u32. The stats for a particular user/bw combination is 1711 * referenced with the following: 1712 * 1713 * sounding[(user* max_bw) + bw] 1714 * 1715 * ... where max_bw == 4 for 160mhz 1716 */ 1717 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1718 }; 1719 1720 struct htt_pdev_obss_pd_stats_tlv { 1721 u32 num_obss_tx_ppdu_success; 1722 u32 num_obss_tx_ppdu_failure; 1723 u32 num_sr_tx_transmissions; 1724 u32 num_spatial_reuse_opportunities; 1725 u32 num_non_srg_opportunities; 1726 u32 num_non_srg_ppdu_tried; 1727 u32 num_non_srg_ppdu_success; 1728 u32 num_srg_opportunities; 1729 u32 num_srg_ppdu_tried; 1730 u32 num_srg_ppdu_success; 1731 u32 num_psr_opportunities; 1732 u32 num_psr_ppdu_tried; 1733 u32 num_psr_ppdu_success; 1734 }; 1735 1736 struct htt_ring_backpressure_stats_tlv { 1737 u32 pdev_id; 1738 u32 current_head_idx; 1739 u32 current_tail_idx; 1740 u32 num_htt_msgs_sent; 1741 /* Time in milliseconds for which the ring has been in 1742 * its current backpressure condition 1743 */ 1744 u32 backpressure_time_ms; 1745 /* backpressure_hist - histogram showing how many times 1746 * different degrees of backpressure duration occurred: 1747 * Index 0 indicates the number of times ring was 1748 * continuously in backpressure state for 100 - 200ms. 1749 * Index 1 indicates the number of times ring was 1750 * continuously in backpressure state for 200 - 300ms. 1751 * Index 2 indicates the number of times ring was 1752 * continuously in backpressure state for 300 - 400ms. 1753 * Index 3 indicates the number of times ring was 1754 * continuously in backpressure state for 400 - 500ms. 1755 * Index 4 indicates the number of times ring was 1756 * continuously in backpressure state beyond 500ms. 1757 */ 1758 u32 backpressure_hist[5]; 1759 }; 1760 1761 #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 1762 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 1763 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1764 1765 struct htt_pdev_txrate_txbf_stats_tlv { 1766 /* SU TxBF TX MCS stats */ 1767 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1768 /* Implicit BF TX MCS stats */ 1769 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1770 /* Open loop TX MCS stats */ 1771 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1772 /* SU TxBF TX NSS stats */ 1773 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1774 /* Implicit BF TX NSS stats */ 1775 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1776 /* Open loop TX NSS stats */ 1777 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1778 /* SU TxBF TX BW stats */ 1779 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1780 /* Implicit BF TX BW stats */ 1781 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1782 /* Open loop TX BW stats */ 1783 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1784 }; 1785 1786 struct htt_txbf_ofdma_ndpa_stats_tlv { 1787 /* 11AX HE OFDMA NDPA frame queued to the HW */ 1788 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1789 /* 11AX HE OFDMA NDPA frame sent over the air */ 1790 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1791 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1792 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1793 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1794 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1795 }; 1796 1797 struct htt_txbf_ofdma_ndp_stats_tlv { 1798 /* 11AX HE OFDMA NDP frame queued to the HW */ 1799 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1800 /* 11AX HE OFDMA NDPA frame sent over the air */ 1801 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1802 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1803 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1804 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1805 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1806 }; 1807 1808 struct htt_txbf_ofdma_brp_stats_tlv { 1809 /* 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 1810 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1811 /* 11AX HE OFDMA MU BRPOLL frame sent over the air */ 1812 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1813 /* 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 1814 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1815 /* 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 1816 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1817 /* Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 1818 * completed with error(s). 1819 */ 1820 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1]; 1821 }; 1822 1823 struct htt_txbf_ofdma_steer_stats_tlv { 1824 /* 11AX HE OFDMA PPDUs that were sent over the air with steering (TXBF + OFDMA) */ 1825 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1826 /* 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 1827 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1828 /* 11AX HE OFDMA number of users for which CBF prefetch was 1829 * initiated to PHY HW during TX. 1830 */ 1831 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1832 /* 11AX HE OFDMA number of users for which sounding was initiated during TX */ 1833 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1834 /* 11AX HE OFDMA number of users for which sounding was forced during TX */ 1835 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1836 }; 1837 1838 #define HTT_MAX_RX_PKT_CNT 8 1839 #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1840 #define HTT_MAX_PER_BLK_ERR_CNT 20 1841 #define HTT_MAX_RX_OTA_ERR_CNT 14 1842 #define HTT_STATS_MAX_CHAINS 8 1843 #define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16 1844 1845 struct htt_phy_counters_tlv { 1846 /* number of RXTD OFDMA OTA error counts except power surge and drop */ 1847 u32 rx_ofdma_timing_err_cnt; 1848 /* rx_cck_fail_cnt: 1849 * number of cck error counts due to rx reception failure because of 1850 * timing error in cck 1851 */ 1852 u32 rx_cck_fail_cnt; 1853 /* number of times tx abort initiated by mac */ 1854 u32 mactx_abort_cnt; 1855 /* number of times rx abort initiated by mac */ 1856 u32 macrx_abort_cnt; 1857 /* number of times tx abort initiated by phy */ 1858 u32 phytx_abort_cnt; 1859 /* number of times rx abort initiated by phy */ 1860 u32 phyrx_abort_cnt; 1861 /* number of rx defered count initiated by phy */ 1862 u32 phyrx_defer_abort_cnt; 1863 /* number of sizing events generated at LSTF */ 1864 u32 rx_gain_adj_lstf_event_cnt; 1865 /* number of sizing events generated at non-legacy LTF */ 1866 u32 rx_gain_adj_non_legacy_cnt; 1867 /* rx_pkt_cnt - 1868 * Received EOP (end-of-packet) count per packet type; 1869 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1870 * [6-7]=RSVD 1871 */ 1872 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; 1873 /* rx_pkt_crc_pass_cnt - 1874 * Received EOP (end-of-packet) count per packet type; 1875 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1876 * [6-7]=RSVD 1877 */ 1878 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1879 /* per_blk_err_cnt - 1880 * Error count per error source; 1881 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; 1882 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; 1883 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF 1884 * [13-19]=RSVD 1885 */ 1886 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; 1887 /* rx_ota_err_cnt - 1888 * RXTD OTA (over-the-air) error count per error reason; 1889 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; 1890 * [3] = cck fail; [4] = power surge; [5] = power drop; 1891 * [6] = btcf timing timeout error; [7] = btcf packet detect error; 1892 * [8] = coarse timing timeout error 1893 * [9-13]=RSVD 1894 */ 1895 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; 1896 }; 1897 1898 struct htt_phy_stats_tlv { 1899 /* per chain hw noise floor values in dBm */ 1900 s32 nf_chain[HTT_STATS_MAX_CHAINS]; 1901 /* number of false radars detected */ 1902 u32 false_radar_cnt; 1903 /* number of channel switches happened due to radar detection */ 1904 u32 radar_cs_cnt; 1905 /* ani_level - 1906 * ANI level (noise interference) corresponds to the channel 1907 * the desense levels range from -5 to 15 in dB units, 1908 * higher values indicating more noise interference. 1909 */ 1910 s32 ani_level; 1911 /* running time in minutes since FW boot */ 1912 u32 fw_run_time; 1913 }; 1914 1915 struct htt_peer_ctrl_path_txrx_stats_tlv { 1916 /* peer mac address */ 1917 u8 peer_mac_addr[ETH_ALEN]; 1918 u8 rsvd[2]; 1919 /* Num of tx mgmt frames with subtype on peer level */ 1920 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 1921 /* Num of rx mgmt frames with subtype on peer level */ 1922 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 1923 }; 1924 1925 #ifdef CONFIG_ATH11K_DEBUGFS 1926 1927 void ath11k_debugfs_htt_stats_init(struct ath11k *ar); 1928 void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1929 struct sk_buff *skb); 1930 int ath11k_debugfs_htt_stats_req(struct ath11k *ar); 1931 1932 #else /* CONFIG_ATH11K_DEBUGFS */ 1933 1934 static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar) 1935 { 1936 } 1937 1938 static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1939 struct sk_buff *skb) 1940 { 1941 } 1942 1943 static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar) 1944 { 1945 return 0; 1946 } 1947 1948 #endif /* CONFIG_ATH11K_DEBUGFS */ 1949 1950 #endif 1951