1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/platform_device.h> 8 #include <linux/of_device.h> 9 #include <linux/of.h> 10 #include <linux/dma-mapping.h> 11 #include "ahb.h" 12 #include "debug.h" 13 #include "hif.h" 14 #include <linux/remoteproc.h> 15 16 static const struct of_device_id ath11k_ahb_of_match[] = { 17 /* TODO: Should we change the compatible string to something similar 18 * to one that ath10k uses? 19 */ 20 { .compatible = "qcom,ipq8074-wifi", 21 .data = (void *)ATH11K_HW_IPQ8074, 22 }, 23 { .compatible = "qcom,ipq6018-wifi", 24 .data = (void *)ATH11K_HW_IPQ6018_HW10, 25 }, 26 { } 27 }; 28 29 MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match); 30 31 static const struct ath11k_bus_params ath11k_ahb_bus_params = { 32 .mhi_support = false, 33 .m3_fw_support = false, 34 .fixed_bdf_addr = true, 35 .fixed_mem_region = true, 36 }; 37 38 #define ATH11K_IRQ_CE0_OFFSET 4 39 40 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 41 "misc-pulse1", 42 "misc-latch", 43 "sw-exception", 44 "watchdog", 45 "ce0", 46 "ce1", 47 "ce2", 48 "ce3", 49 "ce4", 50 "ce5", 51 "ce6", 52 "ce7", 53 "ce8", 54 "ce9", 55 "ce10", 56 "ce11", 57 "host2wbm-desc-feed", 58 "host2reo-re-injection", 59 "host2reo-command", 60 "host2rxdma-monitor-ring3", 61 "host2rxdma-monitor-ring2", 62 "host2rxdma-monitor-ring1", 63 "reo2ost-exception", 64 "wbm2host-rx-release", 65 "reo2host-status", 66 "reo2host-destination-ring4", 67 "reo2host-destination-ring3", 68 "reo2host-destination-ring2", 69 "reo2host-destination-ring1", 70 "rxdma2host-monitor-destination-mac3", 71 "rxdma2host-monitor-destination-mac2", 72 "rxdma2host-monitor-destination-mac1", 73 "ppdu-end-interrupts-mac3", 74 "ppdu-end-interrupts-mac2", 75 "ppdu-end-interrupts-mac1", 76 "rxdma2host-monitor-status-ring-mac3", 77 "rxdma2host-monitor-status-ring-mac2", 78 "rxdma2host-monitor-status-ring-mac1", 79 "host2rxdma-host-buf-ring-mac3", 80 "host2rxdma-host-buf-ring-mac2", 81 "host2rxdma-host-buf-ring-mac1", 82 "rxdma2host-destination-ring-mac3", 83 "rxdma2host-destination-ring-mac2", 84 "rxdma2host-destination-ring-mac1", 85 "host2tcl-input-ring4", 86 "host2tcl-input-ring3", 87 "host2tcl-input-ring2", 88 "host2tcl-input-ring1", 89 "wbm2host-tx-completions-ring3", 90 "wbm2host-tx-completions-ring2", 91 "wbm2host-tx-completions-ring1", 92 "tcl2host-status-ring", 93 }; 94 95 /* enum ext_irq_num - irq numbers that can be used by external modules 96 * like datapath 97 */ 98 enum ext_irq_num { 99 host2wbm_desc_feed = 16, 100 host2reo_re_injection, 101 host2reo_command, 102 host2rxdma_monitor_ring3, 103 host2rxdma_monitor_ring2, 104 host2rxdma_monitor_ring1, 105 reo2host_exception, 106 wbm2host_rx_release, 107 reo2host_status, 108 reo2host_destination_ring4, 109 reo2host_destination_ring3, 110 reo2host_destination_ring2, 111 reo2host_destination_ring1, 112 rxdma2host_monitor_destination_mac3, 113 rxdma2host_monitor_destination_mac2, 114 rxdma2host_monitor_destination_mac1, 115 ppdu_end_interrupts_mac3, 116 ppdu_end_interrupts_mac2, 117 ppdu_end_interrupts_mac1, 118 rxdma2host_monitor_status_ring_mac3, 119 rxdma2host_monitor_status_ring_mac2, 120 rxdma2host_monitor_status_ring_mac1, 121 host2rxdma_host_buf_ring_mac3, 122 host2rxdma_host_buf_ring_mac2, 123 host2rxdma_host_buf_ring_mac1, 124 rxdma2host_destination_ring_mac3, 125 rxdma2host_destination_ring_mac2, 126 rxdma2host_destination_ring_mac1, 127 host2tcl_input_ring4, 128 host2tcl_input_ring3, 129 host2tcl_input_ring2, 130 host2tcl_input_ring1, 131 wbm2host_tx_completions_ring3, 132 wbm2host_tx_completions_ring2, 133 wbm2host_tx_completions_ring1, 134 tcl2host_status_ring, 135 }; 136 137 static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset) 138 { 139 return ioread32(ab->mem + offset); 140 } 141 142 static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value) 143 { 144 iowrite32(value, ab->mem + offset); 145 } 146 147 static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab) 148 { 149 int i; 150 151 for (i = 0; i < ab->hw_params.ce_count; i++) { 152 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 153 154 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 155 continue; 156 157 tasklet_kill(&ce_pipe->intr_tq); 158 } 159 } 160 161 static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 162 { 163 int i; 164 165 for (i = 0; i < irq_grp->num_irq; i++) 166 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 167 } 168 169 static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) 170 { 171 int i; 172 173 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 174 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 175 176 ath11k_ahb_ext_grp_disable(irq_grp); 177 178 if (irq_grp->napi_enabled) { 179 napi_synchronize(&irq_grp->napi); 180 napi_disable(&irq_grp->napi); 181 irq_grp->napi_enabled = false; 182 } 183 } 184 } 185 186 static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 187 { 188 int i; 189 190 for (i = 0; i < irq_grp->num_irq; i++) 191 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 192 } 193 194 static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset) 195 { 196 u32 val; 197 198 val = ath11k_ahb_read32(ab, offset); 199 ath11k_ahb_write32(ab, offset, val | BIT(bit)); 200 } 201 202 static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset) 203 { 204 u32 val; 205 206 val = ath11k_ahb_read32(ab, offset); 207 ath11k_ahb_write32(ab, offset, val & ~BIT(bit)); 208 } 209 210 static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 211 { 212 const struct ce_attr *ce_attr; 213 214 ce_attr = &ab->hw_params.host_ce_config[ce_id]; 215 if (ce_attr->src_nentries) 216 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS); 217 218 if (ce_attr->dest_nentries) { 219 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); 220 ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, 221 CE_HOST_IE_3_ADDRESS); 222 } 223 } 224 225 static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 226 { 227 const struct ce_attr *ce_attr; 228 229 ce_attr = &ab->hw_params.host_ce_config[ce_id]; 230 if (ce_attr->src_nentries) 231 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS); 232 233 if (ce_attr->dest_nentries) { 234 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); 235 ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, 236 CE_HOST_IE_3_ADDRESS); 237 } 238 } 239 240 static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab) 241 { 242 int i; 243 int irq_idx; 244 245 for (i = 0; i < ab->hw_params.ce_count; i++) { 246 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 247 continue; 248 249 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 250 synchronize_irq(ab->irq_num[irq_idx]); 251 } 252 } 253 254 static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab) 255 { 256 int i, j; 257 int irq_idx; 258 259 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 260 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 261 262 for (j = 0; j < irq_grp->num_irq; j++) { 263 irq_idx = irq_grp->irqs[j]; 264 synchronize_irq(ab->irq_num[irq_idx]); 265 } 266 } 267 } 268 269 static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab) 270 { 271 int i; 272 273 for (i = 0; i < ab->hw_params.ce_count; i++) { 274 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 275 continue; 276 ath11k_ahb_ce_irq_enable(ab, i); 277 } 278 } 279 280 static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab) 281 { 282 int i; 283 284 for (i = 0; i < ab->hw_params.ce_count; i++) { 285 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 286 continue; 287 ath11k_ahb_ce_irq_disable(ab, i); 288 } 289 } 290 291 static int ath11k_ahb_start(struct ath11k_base *ab) 292 { 293 ath11k_ahb_ce_irqs_enable(ab); 294 ath11k_ce_rx_post_buf(ab); 295 296 return 0; 297 } 298 299 static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab) 300 { 301 int i; 302 303 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 304 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 305 306 if (!irq_grp->napi_enabled) { 307 napi_enable(&irq_grp->napi); 308 irq_grp->napi_enabled = true; 309 } 310 ath11k_ahb_ext_grp_enable(irq_grp); 311 } 312 } 313 314 static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) 315 { 316 __ath11k_ahb_ext_irq_disable(ab); 317 ath11k_ahb_sync_ext_irqs(ab); 318 } 319 320 static void ath11k_ahb_stop(struct ath11k_base *ab) 321 { 322 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 323 ath11k_ahb_ce_irqs_disable(ab); 324 ath11k_ahb_sync_ce_irqs(ab); 325 ath11k_ahb_kill_tasklets(ab); 326 del_timer_sync(&ab->rx_replenish_retry); 327 ath11k_ce_cleanup_pipes(ab); 328 } 329 330 static int ath11k_ahb_power_up(struct ath11k_base *ab) 331 { 332 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 333 int ret; 334 335 ret = rproc_boot(ab_ahb->tgt_rproc); 336 if (ret) 337 ath11k_err(ab, "failed to boot the remote processor Q6\n"); 338 339 return ret; 340 } 341 342 static void ath11k_ahb_power_down(struct ath11k_base *ab) 343 { 344 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 345 346 rproc_shutdown(ab_ahb->tgt_rproc); 347 } 348 349 static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab) 350 { 351 int timeout; 352 353 if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done || 354 ab->hw_params.cold_boot_calib == 0) 355 return 0; 356 357 ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n"); 358 timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, 359 (ab->qmi.cal_done == 1), 360 ATH11K_COLD_BOOT_FW_RESET_DELAY); 361 if (timeout <= 0) { 362 ath11k_cold_boot_cal = 0; 363 ath11k_warn(ab, "Coldboot Calibration failed timed out\n"); 364 } 365 366 /* reset the firmware */ 367 ath11k_ahb_power_down(ab); 368 ath11k_ahb_power_up(ab); 369 370 ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n"); 371 return 0; 372 } 373 374 static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab) 375 { 376 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 377 378 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 379 cfg->tgt_ce = ab->hw_params.target_ce_config; 380 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 381 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 382 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 383 } 384 385 static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab) 386 { 387 int i, j; 388 389 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 390 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 391 392 for (j = 0; j < irq_grp->num_irq; j++) 393 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 394 } 395 } 396 397 static void ath11k_ahb_free_irq(struct ath11k_base *ab) 398 { 399 int irq_idx; 400 int i; 401 402 for (i = 0; i < ab->hw_params.ce_count; i++) { 403 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 404 continue; 405 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 406 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 407 } 408 409 ath11k_ahb_free_ext_irq(ab); 410 } 411 412 static void ath11k_ahb_ce_tasklet(struct tasklet_struct *t) 413 { 414 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 415 416 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 417 418 ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 419 } 420 421 static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg) 422 { 423 struct ath11k_ce_pipe *ce_pipe = arg; 424 425 /* last interrupt received for this CE */ 426 ce_pipe->timestamp = jiffies; 427 428 ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 429 430 tasklet_schedule(&ce_pipe->intr_tq); 431 432 return IRQ_HANDLED; 433 } 434 435 static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget) 436 { 437 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 438 struct ath11k_ext_irq_grp, 439 napi); 440 struct ath11k_base *ab = irq_grp->ab; 441 int work_done; 442 443 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 444 if (work_done < budget) { 445 napi_complete_done(napi, work_done); 446 ath11k_ahb_ext_grp_enable(irq_grp); 447 } 448 449 if (work_done > budget) 450 work_done = budget; 451 452 return work_done; 453 } 454 455 static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg) 456 { 457 struct ath11k_ext_irq_grp *irq_grp = arg; 458 459 /* last interrupt received for this group */ 460 irq_grp->timestamp = jiffies; 461 462 ath11k_ahb_ext_grp_disable(irq_grp); 463 464 napi_schedule(&irq_grp->napi); 465 466 return IRQ_HANDLED; 467 } 468 469 static int ath11k_ahb_ext_irq_config(struct ath11k_base *ab) 470 { 471 struct ath11k_hw_params *hw = &ab->hw_params; 472 int i, j; 473 int irq; 474 int ret; 475 476 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 477 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 478 u32 num_irq = 0; 479 480 irq_grp->ab = ab; 481 irq_grp->grp_id = i; 482 init_dummy_netdev(&irq_grp->napi_ndev); 483 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 484 ath11k_ahb_ext_grp_napi_poll); 485 486 for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) { 487 if (ab->hw_params.ring_mask->tx[i] & BIT(j)) { 488 irq_grp->irqs[num_irq++] = 489 wbm2host_tx_completions_ring1 - j; 490 } 491 492 if (ab->hw_params.ring_mask->rx[i] & BIT(j)) { 493 irq_grp->irqs[num_irq++] = 494 reo2host_destination_ring1 - j; 495 } 496 497 if (ab->hw_params.ring_mask->rx_err[i] & BIT(j)) 498 irq_grp->irqs[num_irq++] = reo2host_exception; 499 500 if (ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j)) 501 irq_grp->irqs[num_irq++] = wbm2host_rx_release; 502 503 if (ab->hw_params.ring_mask->reo_status[i] & BIT(j)) 504 irq_grp->irqs[num_irq++] = reo2host_status; 505 506 if (j < ab->hw_params.max_radios) { 507 if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) { 508 irq_grp->irqs[num_irq++] = 509 rxdma2host_destination_ring_mac1 - 510 ath11k_hw_get_mac_from_pdev_id(hw, j); 511 } 512 513 if (ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) { 514 irq_grp->irqs[num_irq++] = 515 host2rxdma_host_buf_ring_mac1 - 516 ath11k_hw_get_mac_from_pdev_id(hw, j); 517 } 518 519 if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) { 520 irq_grp->irqs[num_irq++] = 521 ppdu_end_interrupts_mac1 - 522 ath11k_hw_get_mac_from_pdev_id(hw, j); 523 irq_grp->irqs[num_irq++] = 524 rxdma2host_monitor_status_ring_mac1 - 525 ath11k_hw_get_mac_from_pdev_id(hw, j); 526 } 527 } 528 } 529 irq_grp->num_irq = num_irq; 530 531 for (j = 0; j < irq_grp->num_irq; j++) { 532 int irq_idx = irq_grp->irqs[j]; 533 534 irq = platform_get_irq_byname(ab->pdev, 535 irq_name[irq_idx]); 536 ab->irq_num[irq_idx] = irq; 537 irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY); 538 ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler, 539 IRQF_TRIGGER_RISING, 540 irq_name[irq_idx], irq_grp); 541 if (ret) { 542 ath11k_err(ab, "failed request_irq for %d\n", 543 irq); 544 } 545 } 546 } 547 548 return 0; 549 } 550 551 static int ath11k_ahb_config_irq(struct ath11k_base *ab) 552 { 553 int irq, irq_idx, i; 554 int ret; 555 556 /* Configure CE irqs */ 557 for (i = 0; i < ab->hw_params.ce_count; i++) { 558 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 559 560 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 561 continue; 562 563 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 564 565 tasklet_setup(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet); 566 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]); 567 ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler, 568 IRQF_TRIGGER_RISING, irq_name[irq_idx], 569 ce_pipe); 570 if (ret) 571 return ret; 572 573 ab->irq_num[irq_idx] = irq; 574 } 575 576 /* Configure external interrupts */ 577 ret = ath11k_ahb_ext_irq_config(ab); 578 579 return ret; 580 } 581 582 static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 583 u8 *ul_pipe, u8 *dl_pipe) 584 { 585 const struct service_to_pipe *entry; 586 bool ul_set = false, dl_set = false; 587 int i; 588 589 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 590 entry = &ab->hw_params.svc_to_ce_map[i]; 591 592 if (__le32_to_cpu(entry->service_id) != service_id) 593 continue; 594 595 switch (__le32_to_cpu(entry->pipedir)) { 596 case PIPEDIR_NONE: 597 break; 598 case PIPEDIR_IN: 599 WARN_ON(dl_set); 600 *dl_pipe = __le32_to_cpu(entry->pipenum); 601 dl_set = true; 602 break; 603 case PIPEDIR_OUT: 604 WARN_ON(ul_set); 605 *ul_pipe = __le32_to_cpu(entry->pipenum); 606 ul_set = true; 607 break; 608 case PIPEDIR_INOUT: 609 WARN_ON(dl_set); 610 WARN_ON(ul_set); 611 *dl_pipe = __le32_to_cpu(entry->pipenum); 612 *ul_pipe = __le32_to_cpu(entry->pipenum); 613 dl_set = true; 614 ul_set = true; 615 break; 616 } 617 } 618 619 if (WARN_ON(!ul_set || !dl_set)) 620 return -ENOENT; 621 622 return 0; 623 } 624 625 static const struct ath11k_hif_ops ath11k_ahb_hif_ops = { 626 .start = ath11k_ahb_start, 627 .stop = ath11k_ahb_stop, 628 .read32 = ath11k_ahb_read32, 629 .write32 = ath11k_ahb_write32, 630 .irq_enable = ath11k_ahb_ext_irq_enable, 631 .irq_disable = ath11k_ahb_ext_irq_disable, 632 .map_service_to_pipe = ath11k_ahb_map_service_to_pipe, 633 .power_down = ath11k_ahb_power_down, 634 .power_up = ath11k_ahb_power_up, 635 }; 636 637 static int ath11k_core_get_rproc(struct ath11k_base *ab) 638 { 639 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 640 struct device *dev = ab->dev; 641 struct rproc *prproc; 642 phandle rproc_phandle; 643 644 if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) { 645 ath11k_err(ab, "failed to get q6_rproc handle\n"); 646 return -ENOENT; 647 } 648 649 prproc = rproc_get_by_phandle(rproc_phandle); 650 if (!prproc) { 651 ath11k_err(ab, "failed to get rproc\n"); 652 return -EINVAL; 653 } 654 ab_ahb->tgt_rproc = prproc; 655 656 return 0; 657 } 658 659 static int ath11k_ahb_probe(struct platform_device *pdev) 660 { 661 struct ath11k_base *ab; 662 const struct of_device_id *of_id; 663 struct resource *mem_res; 664 void __iomem *mem; 665 int ret; 666 667 of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev); 668 if (!of_id) { 669 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 670 return -EINVAL; 671 } 672 673 mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 674 if (IS_ERR(mem)) { 675 dev_err(&pdev->dev, "ioremap error\n"); 676 return PTR_ERR(mem); 677 } 678 679 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 680 if (ret) { 681 dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n"); 682 return ret; 683 } 684 685 ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb), 686 ATH11K_BUS_AHB, 687 &ath11k_ahb_bus_params); 688 if (!ab) { 689 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 690 return -ENOMEM; 691 } 692 693 ab->hif.ops = &ath11k_ahb_hif_ops; 694 ab->pdev = pdev; 695 ab->hw_rev = (enum ath11k_hw_rev)of_id->data; 696 ab->mem = mem; 697 ab->mem_len = resource_size(mem_res); 698 platform_set_drvdata(pdev, ab); 699 700 ret = ath11k_core_pre_init(ab); 701 if (ret) 702 goto err_core_free; 703 704 ret = ath11k_hal_srng_init(ab); 705 if (ret) 706 goto err_core_free; 707 708 ret = ath11k_ce_alloc_pipes(ab); 709 if (ret) { 710 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 711 goto err_hal_srng_deinit; 712 } 713 714 ath11k_ahb_init_qmi_ce_config(ab); 715 716 ret = ath11k_core_get_rproc(ab); 717 if (ret) { 718 ath11k_err(ab, "failed to get rproc: %d\n", ret); 719 goto err_ce_free; 720 } 721 722 ret = ath11k_core_init(ab); 723 if (ret) { 724 ath11k_err(ab, "failed to init core: %d\n", ret); 725 goto err_ce_free; 726 } 727 728 ret = ath11k_ahb_config_irq(ab); 729 if (ret) { 730 ath11k_err(ab, "failed to configure irq: %d\n", ret); 731 goto err_ce_free; 732 } 733 734 ath11k_ahb_fwreset_from_cold_boot(ab); 735 736 return 0; 737 738 err_ce_free: 739 ath11k_ce_free_pipes(ab); 740 741 err_hal_srng_deinit: 742 ath11k_hal_srng_deinit(ab); 743 744 err_core_free: 745 ath11k_core_free(ab); 746 platform_set_drvdata(pdev, NULL); 747 748 return ret; 749 } 750 751 static int ath11k_ahb_remove(struct platform_device *pdev) 752 { 753 struct ath11k_base *ab = platform_get_drvdata(pdev); 754 unsigned long left; 755 756 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 757 ath11k_ahb_power_down(ab); 758 ath11k_debugfs_soc_destroy(ab); 759 ath11k_qmi_deinit_service(ab); 760 goto qmi_fail; 761 } 762 763 reinit_completion(&ab->driver_recovery); 764 765 if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) { 766 left = wait_for_completion_timeout(&ab->driver_recovery, 767 ATH11K_AHB_RECOVERY_TIMEOUT); 768 if (!left) 769 ath11k_warn(ab, "failed to receive recovery response completion\n"); 770 } 771 772 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 773 cancel_work_sync(&ab->restart_work); 774 775 ath11k_core_deinit(ab); 776 qmi_fail: 777 ath11k_ahb_free_irq(ab); 778 ath11k_hal_srng_deinit(ab); 779 ath11k_ce_free_pipes(ab); 780 ath11k_core_free(ab); 781 platform_set_drvdata(pdev, NULL); 782 783 return 0; 784 } 785 786 static struct platform_driver ath11k_ahb_driver = { 787 .driver = { 788 .name = "ath11k", 789 .of_match_table = ath11k_ahb_of_match, 790 }, 791 .probe = ath11k_ahb_probe, 792 .remove = ath11k_ahb_remove, 793 }; 794 795 static int ath11k_ahb_init(void) 796 { 797 return platform_driver_register(&ath11k_ahb_driver); 798 } 799 module_init(ath11k_ahb_init); 800 801 static void ath11k_ahb_exit(void) 802 { 803 platform_driver_unregister(&ath11k_ahb_driver); 804 } 805 module_exit(ath11k_ahb_exit); 806 807 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices"); 808 MODULE_LICENSE("Dual BSD/GPL"); 809