1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7 #if defined(__FreeBSD__) 8 #define LINUXKPI_PARAM_PREFIX ath10k_pci_ 9 #endif 10 11 #include <linux/pci.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/spinlock.h> 15 #include <linux/bitops.h> 16 #if defined(__FreeBSD__) 17 #include <linux/delay.h> 18 #endif 19 20 #include "core.h" 21 #include "debug.h" 22 #include "coredump.h" 23 24 #include "targaddrs.h" 25 #include "bmi.h" 26 27 #include "hif.h" 28 #include "htc.h" 29 30 #include "ce.h" 31 #include "pci.h" 32 33 enum ath10k_pci_reset_mode { 34 ATH10K_PCI_RESET_AUTO = 0, 35 ATH10K_PCI_RESET_WARM_ONLY = 1, 36 }; 37 38 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 39 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 40 41 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 42 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 43 44 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 45 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 46 47 /* how long wait to wait for target to initialise, in ms */ 48 #define ATH10K_PCI_TARGET_WAIT 3000 49 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 50 51 /* Maximum number of bytes that can be handled atomically by 52 * diag read and write. 53 */ 54 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 55 56 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 57 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c 58 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 59 60 static const struct pci_device_id ath10k_pci_id_table[] = { 61 /* PCI-E QCA988X V2 (Ubiquiti branded) */ 62 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, 63 64 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 65 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 66 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 67 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 68 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 69 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 70 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 71 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 72 {0} 73 }; 74 75 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 76 /* QCA988X pre 2.0 chips are not supported because they need some nasty 77 * hacks. ath10k doesn't have them and these devices crash horribly 78 * because of that. 79 */ 80 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, 81 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 82 83 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 84 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 85 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 86 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 88 89 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 90 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 91 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 94 95 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 96 97 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 98 99 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 100 101 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 102 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 103 104 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 105 }; 106 107 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 108 static int ath10k_pci_cold_reset(struct ath10k *ar); 109 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 110 static int ath10k_pci_init_irq(struct ath10k *ar); 111 static int ath10k_pci_deinit_irq(struct ath10k *ar); 112 static int ath10k_pci_request_irq(struct ath10k *ar); 113 static void ath10k_pci_free_irq(struct ath10k *ar); 114 static int ath10k_pci_bmi_wait(struct ath10k *ar, 115 struct ath10k_ce_pipe *tx_pipe, 116 struct ath10k_ce_pipe *rx_pipe, 117 struct bmi_xfer *xfer); 118 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 119 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 120 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 121 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 122 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 123 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 124 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 125 126 static const struct ce_attr pci_host_ce_config_wlan[] = { 127 /* CE0: host->target HTC control and raw streams */ 128 { 129 .flags = CE_ATTR_FLAGS, 130 .src_nentries = 16, 131 .src_sz_max = 256, 132 .dest_nentries = 0, 133 .send_cb = ath10k_pci_htc_tx_cb, 134 }, 135 136 /* CE1: target->host HTT + HTC control */ 137 { 138 .flags = CE_ATTR_FLAGS, 139 .src_nentries = 0, 140 .src_sz_max = 2048, 141 .dest_nentries = 512, 142 .recv_cb = ath10k_pci_htt_htc_rx_cb, 143 }, 144 145 /* CE2: target->host WMI */ 146 { 147 .flags = CE_ATTR_FLAGS, 148 .src_nentries = 0, 149 .src_sz_max = 2048, 150 .dest_nentries = 128, 151 .recv_cb = ath10k_pci_htc_rx_cb, 152 }, 153 154 /* CE3: host->target WMI */ 155 { 156 .flags = CE_ATTR_FLAGS, 157 .src_nentries = 32, 158 .src_sz_max = 2048, 159 .dest_nentries = 0, 160 .send_cb = ath10k_pci_htc_tx_cb, 161 }, 162 163 /* CE4: host->target HTT */ 164 { 165 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 166 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 167 .src_sz_max = 256, 168 .dest_nentries = 0, 169 .send_cb = ath10k_pci_htt_tx_cb, 170 }, 171 172 /* CE5: target->host HTT (HIF->HTT) */ 173 { 174 .flags = CE_ATTR_FLAGS, 175 .src_nentries = 0, 176 .src_sz_max = 512, 177 .dest_nentries = 512, 178 .recv_cb = ath10k_pci_htt_rx_cb, 179 }, 180 181 /* CE6: target autonomous hif_memcpy */ 182 { 183 .flags = CE_ATTR_FLAGS, 184 .src_nentries = 0, 185 .src_sz_max = 0, 186 .dest_nentries = 0, 187 }, 188 189 /* CE7: ce_diag, the Diagnostic Window */ 190 { 191 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, 192 .src_nentries = 2, 193 .src_sz_max = DIAG_TRANSFER_LIMIT, 194 .dest_nentries = 2, 195 }, 196 197 /* CE8: target->host pktlog */ 198 { 199 .flags = CE_ATTR_FLAGS, 200 .src_nentries = 0, 201 .src_sz_max = 2048, 202 .dest_nentries = 128, 203 .recv_cb = ath10k_pci_pktlog_rx_cb, 204 }, 205 206 /* CE9 target autonomous qcache memcpy */ 207 { 208 .flags = CE_ATTR_FLAGS, 209 .src_nentries = 0, 210 .src_sz_max = 0, 211 .dest_nentries = 0, 212 }, 213 214 /* CE10: target autonomous hif memcpy */ 215 { 216 .flags = CE_ATTR_FLAGS, 217 .src_nentries = 0, 218 .src_sz_max = 0, 219 .dest_nentries = 0, 220 }, 221 222 /* CE11: target autonomous hif memcpy */ 223 { 224 .flags = CE_ATTR_FLAGS, 225 .src_nentries = 0, 226 .src_sz_max = 0, 227 .dest_nentries = 0, 228 }, 229 }; 230 231 /* Target firmware's Copy Engine configuration. */ 232 static const struct ce_pipe_config pci_target_ce_config_wlan[] = { 233 /* CE0: host->target HTC control and raw streams */ 234 { 235 .pipenum = __cpu_to_le32(0), 236 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 237 .nentries = __cpu_to_le32(32), 238 .nbytes_max = __cpu_to_le32(256), 239 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 240 .reserved = __cpu_to_le32(0), 241 }, 242 243 /* CE1: target->host HTT + HTC control */ 244 { 245 .pipenum = __cpu_to_le32(1), 246 .pipedir = __cpu_to_le32(PIPEDIR_IN), 247 .nentries = __cpu_to_le32(32), 248 .nbytes_max = __cpu_to_le32(2048), 249 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 250 .reserved = __cpu_to_le32(0), 251 }, 252 253 /* CE2: target->host WMI */ 254 { 255 .pipenum = __cpu_to_le32(2), 256 .pipedir = __cpu_to_le32(PIPEDIR_IN), 257 .nentries = __cpu_to_le32(64), 258 .nbytes_max = __cpu_to_le32(2048), 259 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 260 .reserved = __cpu_to_le32(0), 261 }, 262 263 /* CE3: host->target WMI */ 264 { 265 .pipenum = __cpu_to_le32(3), 266 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 267 .nentries = __cpu_to_le32(32), 268 .nbytes_max = __cpu_to_le32(2048), 269 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 270 .reserved = __cpu_to_le32(0), 271 }, 272 273 /* CE4: host->target HTT */ 274 { 275 .pipenum = __cpu_to_le32(4), 276 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 277 .nentries = __cpu_to_le32(256), 278 .nbytes_max = __cpu_to_le32(256), 279 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 280 .reserved = __cpu_to_le32(0), 281 }, 282 283 /* NB: 50% of src nentries, since tx has 2 frags */ 284 285 /* CE5: target->host HTT (HIF->HTT) */ 286 { 287 .pipenum = __cpu_to_le32(5), 288 .pipedir = __cpu_to_le32(PIPEDIR_IN), 289 .nentries = __cpu_to_le32(32), 290 .nbytes_max = __cpu_to_le32(512), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE6: Reserved for target autonomous hif_memcpy */ 296 { 297 .pipenum = __cpu_to_le32(6), 298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 299 .nentries = __cpu_to_le32(32), 300 .nbytes_max = __cpu_to_le32(4096), 301 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE7 used only by Host */ 306 { 307 .pipenum = __cpu_to_le32(7), 308 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 309 .nentries = __cpu_to_le32(0), 310 .nbytes_max = __cpu_to_le32(0), 311 .flags = __cpu_to_le32(0), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE8 target->host packtlog */ 316 { 317 .pipenum = __cpu_to_le32(8), 318 .pipedir = __cpu_to_le32(PIPEDIR_IN), 319 .nentries = __cpu_to_le32(64), 320 .nbytes_max = __cpu_to_le32(2048), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* CE9 target autonomous qcache memcpy */ 326 { 327 .pipenum = __cpu_to_le32(9), 328 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 329 .nentries = __cpu_to_le32(32), 330 .nbytes_max = __cpu_to_le32(2048), 331 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 332 .reserved = __cpu_to_le32(0), 333 }, 334 335 /* It not necessary to send target wlan configuration for CE10 & CE11 336 * as these CEs are not actively used in target. 337 */ 338 }; 339 340 /* 341 * Map from service/endpoint to Copy Engine. 342 * This table is derived from the CE_PCI TABLE, above. 343 * It is passed to the Target at startup for use by firmware. 344 */ 345 static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = { 346 { 347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 349 __cpu_to_le32(3), 350 }, 351 { 352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 354 __cpu_to_le32(2), 355 }, 356 { 357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 359 __cpu_to_le32(3), 360 }, 361 { 362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 364 __cpu_to_le32(2), 365 }, 366 { 367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 369 __cpu_to_le32(3), 370 }, 371 { 372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 374 __cpu_to_le32(2), 375 }, 376 { 377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 379 __cpu_to_le32(3), 380 }, 381 { 382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 384 __cpu_to_le32(2), 385 }, 386 { 387 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 389 __cpu_to_le32(3), 390 }, 391 { 392 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 394 __cpu_to_le32(2), 395 }, 396 { 397 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 399 __cpu_to_le32(0), 400 }, 401 { 402 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 404 __cpu_to_le32(1), 405 }, 406 { /* not used */ 407 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 409 __cpu_to_le32(0), 410 }, 411 { /* not used */ 412 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 414 __cpu_to_le32(1), 415 }, 416 { 417 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 418 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 419 __cpu_to_le32(4), 420 }, 421 { 422 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 423 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 424 __cpu_to_le32(5), 425 }, 426 427 /* (Additions here) */ 428 429 { /* must be last */ 430 __cpu_to_le32(0), 431 __cpu_to_le32(0), 432 __cpu_to_le32(0), 433 }, 434 }; 435 436 static bool ath10k_pci_is_awake(struct ath10k *ar) 437 { 438 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 439 #if defined(__linux__) 440 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 441 RTC_STATE_ADDRESS); 442 #elif defined(__FreeBSD__) 443 u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + 444 RTC_STATE_ADDRESS); 445 #endif 446 447 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 448 } 449 450 static void __ath10k_pci_wake(struct ath10k *ar) 451 { 452 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 453 454 lockdep_assert_held(&ar_pci->ps_lock); 455 456 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 457 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 458 459 #if defined(__linux__) 460 iowrite32(PCIE_SOC_WAKE_V_MASK, 461 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 462 PCIE_SOC_WAKE_ADDRESS); 463 #elif defined(__FreeBSD__) 464 bus_write_4((struct resource *)ar_pci->mem, 465 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 466 PCIE_SOC_WAKE_V_MASK); 467 #endif 468 } 469 470 static void __ath10k_pci_sleep(struct ath10k *ar) 471 { 472 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 473 474 lockdep_assert_held(&ar_pci->ps_lock); 475 476 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 477 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 478 479 #if defined(__linux__) 480 iowrite32(PCIE_SOC_WAKE_RESET, 481 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 482 PCIE_SOC_WAKE_ADDRESS); 483 #elif defined(__FreeBSD__) 484 bus_write_4((struct resource *)ar_pci->mem, 485 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 486 PCIE_SOC_WAKE_RESET); 487 #endif 488 ar_pci->ps_awake = false; 489 } 490 491 static int ath10k_pci_wake_wait(struct ath10k *ar) 492 { 493 int tot_delay = 0; 494 int curr_delay = 5; 495 496 while (tot_delay < PCIE_WAKE_TIMEOUT) { 497 if (ath10k_pci_is_awake(ar)) { 498 if (tot_delay > PCIE_WAKE_LATE_US) 499 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 500 tot_delay / 1000); 501 return 0; 502 } 503 504 udelay(curr_delay); 505 tot_delay += curr_delay; 506 507 if (curr_delay < 50) 508 curr_delay += 5; 509 } 510 511 return -ETIMEDOUT; 512 } 513 514 static int ath10k_pci_force_wake(struct ath10k *ar) 515 { 516 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 517 unsigned long flags; 518 int ret = 0; 519 520 if (ar_pci->pci_ps) 521 return ret; 522 523 spin_lock_irqsave(&ar_pci->ps_lock, flags); 524 525 if (!ar_pci->ps_awake) { 526 #if defined(__linux__) 527 iowrite32(PCIE_SOC_WAKE_V_MASK, 528 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 529 PCIE_SOC_WAKE_ADDRESS); 530 #elif defined(__FreeBSD__) 531 bus_write_4((struct resource *)ar_pci->mem, 532 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 533 PCIE_SOC_WAKE_V_MASK); 534 #endif 535 536 ret = ath10k_pci_wake_wait(ar); 537 if (ret == 0) 538 ar_pci->ps_awake = true; 539 } 540 541 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 542 543 return ret; 544 } 545 546 static void ath10k_pci_force_sleep(struct ath10k *ar) 547 { 548 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 549 unsigned long flags; 550 551 spin_lock_irqsave(&ar_pci->ps_lock, flags); 552 553 #if defined(__linux__) 554 iowrite32(PCIE_SOC_WAKE_RESET, 555 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 556 PCIE_SOC_WAKE_ADDRESS); 557 #elif defined(__FreeBSD__) 558 bus_write_4((struct resource *)ar_pci->mem, 559 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 560 PCIE_SOC_WAKE_RESET); 561 #endif 562 ar_pci->ps_awake = false; 563 564 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 565 } 566 567 static int ath10k_pci_wake(struct ath10k *ar) 568 { 569 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 570 unsigned long flags; 571 int ret = 0; 572 573 if (ar_pci->pci_ps == 0) 574 return ret; 575 576 spin_lock_irqsave(&ar_pci->ps_lock, flags); 577 578 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 579 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 580 581 /* This function can be called very frequently. To avoid excessive 582 * CPU stalls for MMIO reads use a cache var to hold the device state. 583 */ 584 if (!ar_pci->ps_awake) { 585 __ath10k_pci_wake(ar); 586 587 ret = ath10k_pci_wake_wait(ar); 588 if (ret == 0) 589 ar_pci->ps_awake = true; 590 } 591 592 if (ret == 0) { 593 ar_pci->ps_wake_refcount++; 594 WARN_ON(ar_pci->ps_wake_refcount == 0); 595 } 596 597 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 598 599 return ret; 600 } 601 602 static void ath10k_pci_sleep(struct ath10k *ar) 603 { 604 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 605 unsigned long flags; 606 607 if (ar_pci->pci_ps == 0) 608 return; 609 610 spin_lock_irqsave(&ar_pci->ps_lock, flags); 611 612 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 613 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 614 615 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 616 goto skip; 617 618 ar_pci->ps_wake_refcount--; 619 620 mod_timer(&ar_pci->ps_timer, jiffies + 621 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 622 623 skip: 624 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 625 } 626 627 static void ath10k_pci_ps_timer(struct timer_list *t) 628 { 629 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); 630 struct ath10k *ar = ar_pci->ar; 631 unsigned long flags; 632 633 spin_lock_irqsave(&ar_pci->ps_lock, flags); 634 635 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 636 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 637 638 if (ar_pci->ps_wake_refcount > 0) 639 goto skip; 640 641 __ath10k_pci_sleep(ar); 642 643 skip: 644 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 645 } 646 647 static void ath10k_pci_sleep_sync(struct ath10k *ar) 648 { 649 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 650 unsigned long flags; 651 652 if (ar_pci->pci_ps == 0) { 653 ath10k_pci_force_sleep(ar); 654 return; 655 } 656 657 del_timer_sync(&ar_pci->ps_timer); 658 659 spin_lock_irqsave(&ar_pci->ps_lock, flags); 660 WARN_ON(ar_pci->ps_wake_refcount > 0); 661 __ath10k_pci_sleep(ar); 662 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 663 } 664 665 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 666 { 667 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 668 int ret; 669 670 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 671 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 672 offset, offset + sizeof(value), ar_pci->mem_len); 673 return; 674 } 675 676 ret = ath10k_pci_wake(ar); 677 if (ret) { 678 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 679 value, offset, ret); 680 return; 681 } 682 683 #if defined(__linux__) 684 iowrite32(value, ar_pci->mem + offset); 685 #elif defined(__FreeBSD__) 686 bus_write_4((struct resource *)ar_pci->mem, offset, value); 687 #endif 688 ath10k_pci_sleep(ar); 689 } 690 691 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 692 { 693 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 694 u32 val; 695 int ret; 696 697 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 698 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 699 offset, offset + sizeof(val), ar_pci->mem_len); 700 return 0; 701 } 702 703 ret = ath10k_pci_wake(ar); 704 if (ret) { 705 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 706 offset, ret); 707 return 0xffffffff; 708 } 709 710 #if defined(__linux__) 711 val = ioread32(ar_pci->mem + offset); 712 #elif defined(__FreeBSD__) 713 val = bus_read_4((struct resource *)ar_pci->mem, offset); 714 #endif 715 ath10k_pci_sleep(ar); 716 717 return val; 718 } 719 720 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 721 { 722 struct ath10k_ce *ce = ath10k_ce_priv(ar); 723 724 ce->bus_ops->write32(ar, offset, value); 725 } 726 727 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 728 { 729 struct ath10k_ce *ce = ath10k_ce_priv(ar); 730 731 return ce->bus_ops->read32(ar, offset); 732 } 733 734 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 735 { 736 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 737 } 738 739 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 740 { 741 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 742 } 743 744 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 745 { 746 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 747 } 748 749 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 750 { 751 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 752 } 753 754 bool ath10k_pci_irq_pending(struct ath10k *ar) 755 { 756 u32 cause; 757 758 /* Check if the shared legacy irq is for us */ 759 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 760 PCIE_INTR_CAUSE_ADDRESS); 761 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 762 return true; 763 764 return false; 765 } 766 767 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 768 { 769 /* IMPORTANT: INTR_CLR register has to be set after 770 * INTR_ENABLE is set to 0, otherwise interrupt can not be 771 * really cleared. 772 */ 773 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 774 0); 775 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 776 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 777 778 /* IMPORTANT: this extra read transaction is required to 779 * flush the posted write buffer. 780 */ 781 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 782 PCIE_INTR_ENABLE_ADDRESS); 783 } 784 785 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 786 { 787 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 788 PCIE_INTR_ENABLE_ADDRESS, 789 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 790 791 /* IMPORTANT: this extra read transaction is required to 792 * flush the posted write buffer. 793 */ 794 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 795 PCIE_INTR_ENABLE_ADDRESS); 796 } 797 798 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 799 { 800 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 801 802 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 803 return "msi"; 804 805 return "legacy"; 806 } 807 808 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 809 { 810 struct ath10k *ar = pipe->hif_ce_state; 811 struct ath10k_ce *ce = ath10k_ce_priv(ar); 812 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 813 struct sk_buff *skb; 814 dma_addr_t paddr; 815 int ret; 816 817 skb = dev_alloc_skb(pipe->buf_sz); 818 if (!skb) 819 return -ENOMEM; 820 821 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 822 823 paddr = dma_map_single(ar->dev, skb->data, 824 skb->len + skb_tailroom(skb), 825 DMA_FROM_DEVICE); 826 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 827 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 828 dev_kfree_skb_any(skb); 829 return -EIO; 830 } 831 832 ATH10K_SKB_RXCB(skb)->paddr = paddr; 833 834 spin_lock_bh(&ce->ce_lock); 835 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 836 spin_unlock_bh(&ce->ce_lock); 837 if (ret) { 838 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 839 DMA_FROM_DEVICE); 840 dev_kfree_skb_any(skb); 841 return ret; 842 } 843 844 return 0; 845 } 846 847 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 848 { 849 struct ath10k *ar = pipe->hif_ce_state; 850 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 851 struct ath10k_ce *ce = ath10k_ce_priv(ar); 852 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 853 int ret, num; 854 855 if (pipe->buf_sz == 0) 856 return; 857 858 if (!ce_pipe->dest_ring) 859 return; 860 861 spin_lock_bh(&ce->ce_lock); 862 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 863 spin_unlock_bh(&ce->ce_lock); 864 865 while (num >= 0) { 866 ret = __ath10k_pci_rx_post_buf(pipe); 867 if (ret) { 868 if (ret == -ENOSPC) 869 break; 870 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 871 mod_timer(&ar_pci->rx_post_retry, jiffies + 872 ATH10K_PCI_RX_POST_RETRY_MS); 873 break; 874 } 875 num--; 876 } 877 } 878 879 void ath10k_pci_rx_post(struct ath10k *ar) 880 { 881 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 882 int i; 883 884 for (i = 0; i < CE_COUNT; i++) 885 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 886 } 887 888 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 889 { 890 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); 891 struct ath10k *ar = ar_pci->ar; 892 893 ath10k_pci_rx_post(ar); 894 } 895 896 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 897 { 898 u32 val = 0, region = addr & 0xfffff; 899 900 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 901 & 0x7ff) << 21; 902 val |= 0x100000 | region; 903 return val; 904 } 905 906 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. 907 * Support to access target space below 1M for qca6174 and qca9377. 908 * If target space is below 1M, the bit[20] of converted CE addr is 0. 909 * Otherwise bit[20] of converted CE addr is 1. 910 */ 911 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 912 { 913 u32 val = 0, region = addr & 0xfffff; 914 915 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 916 & 0x7ff) << 21; 917 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; 918 return val; 919 } 920 921 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 922 { 923 u32 val = 0, region = addr & 0xfffff; 924 925 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 926 val |= 0x100000 | region; 927 return val; 928 } 929 930 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 931 { 932 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 933 934 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 935 return -ENOTSUPP; 936 937 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 938 } 939 940 /* 941 * Diagnostic read/write access is provided for startup/config/debug usage. 942 * Caller must guarantee proper alignment, when applicable, and single user 943 * at any moment. 944 */ 945 #if defined(__linux__) 946 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 947 #elif defined(__FreeBSD__) 948 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data, 949 #endif 950 int nbytes) 951 { 952 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 953 int ret = 0; 954 u32 *buf; 955 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 956 struct ath10k_ce_pipe *ce_diag; 957 /* Host buffer address in CE space */ 958 u32 ce_data; 959 dma_addr_t ce_data_base = 0; 960 void *data_buf; 961 int i; 962 963 mutex_lock(&ar_pci->ce_diag_mutex); 964 ce_diag = ar_pci->ce_diag; 965 966 /* 967 * Allocate a temporary bounce buffer to hold caller's data 968 * to be DMA'ed from Target. This guarantees 969 * 1) 4-byte alignment 970 * 2) Buffer in DMA-able space 971 */ 972 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 973 974 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 975 GFP_ATOMIC); 976 if (!data_buf) { 977 ret = -ENOMEM; 978 goto done; 979 } 980 981 /* The address supplied by the caller is in the 982 * Target CPU virtual address space. 983 * 984 * In order to use this address with the diagnostic CE, 985 * convert it from Target CPU virtual address space 986 * to CE address space 987 */ 988 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 989 990 remaining_bytes = nbytes; 991 ce_data = ce_data_base; 992 while (remaining_bytes) { 993 nbytes = min_t(unsigned int, remaining_bytes, 994 DIAG_TRANSFER_LIMIT); 995 996 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 997 if (ret != 0) 998 goto done; 999 1000 /* Request CE to send from Target(!) address to Host buffer */ 1001 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0); 1002 if (ret) 1003 goto done; 1004 1005 i = 0; 1006 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1007 udelay(DIAG_ACCESS_CE_WAIT_US); 1008 i += DIAG_ACCESS_CE_WAIT_US; 1009 1010 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1011 ret = -EBUSY; 1012 goto done; 1013 } 1014 } 1015 1016 i = 0; 1017 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1018 &completed_nbytes) != 0) { 1019 udelay(DIAG_ACCESS_CE_WAIT_US); 1020 i += DIAG_ACCESS_CE_WAIT_US; 1021 1022 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1023 ret = -EBUSY; 1024 goto done; 1025 } 1026 } 1027 1028 if (nbytes != completed_nbytes) { 1029 ret = -EIO; 1030 goto done; 1031 } 1032 1033 if (*buf != ce_data) { 1034 ret = -EIO; 1035 goto done; 1036 } 1037 1038 remaining_bytes -= nbytes; 1039 memcpy(data, data_buf, nbytes); 1040 1041 address += nbytes; 1042 data += nbytes; 1043 } 1044 1045 done: 1046 1047 if (data_buf) 1048 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1049 ce_data_base); 1050 1051 mutex_unlock(&ar_pci->ce_diag_mutex); 1052 1053 return ret; 1054 } 1055 1056 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 1057 { 1058 __le32 val = 0; 1059 int ret; 1060 1061 #if defined(__linux__) 1062 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1063 #elif defined(__FreeBSD__) 1064 ret = ath10k_pci_diag_read_mem(ar, address, (u8 *)&val, sizeof(val)); 1065 #endif 1066 *value = __le32_to_cpu(val); 1067 1068 return ret; 1069 } 1070 1071 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1072 u32 src, u32 len) 1073 { 1074 u32 host_addr, addr; 1075 int ret; 1076 1077 host_addr = host_interest_item_address(src); 1078 1079 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1080 if (ret != 0) { 1081 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1082 src, ret); 1083 return ret; 1084 } 1085 1086 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1087 if (ret != 0) { 1088 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1089 addr, len, ret); 1090 return ret; 1091 } 1092 1093 return 0; 1094 } 1095 1096 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1097 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1098 1099 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1100 #if defined(__linux__) 1101 const void *data, int nbytes) 1102 #elif defined(__FreeBSD__) 1103 const void *_d, int nbytes) 1104 #endif 1105 { 1106 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1107 int ret = 0; 1108 u32 *buf; 1109 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 1110 struct ath10k_ce_pipe *ce_diag; 1111 void *data_buf; 1112 dma_addr_t ce_data_base = 0; 1113 int i; 1114 #if defined(__FreeBSD__) 1115 const u8 *data = _d; 1116 #endif 1117 1118 mutex_lock(&ar_pci->ce_diag_mutex); 1119 ce_diag = ar_pci->ce_diag; 1120 1121 /* 1122 * Allocate a temporary bounce buffer to hold caller's data 1123 * to be DMA'ed to Target. This guarantees 1124 * 1) 4-byte alignment 1125 * 2) Buffer in DMA-able space 1126 */ 1127 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 1128 1129 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 1130 GFP_ATOMIC); 1131 if (!data_buf) { 1132 ret = -ENOMEM; 1133 goto done; 1134 } 1135 1136 /* 1137 * The address supplied by the caller is in the 1138 * Target CPU virtual address space. 1139 * 1140 * In order to use this address with the diagnostic CE, 1141 * convert it from 1142 * Target CPU virtual address space 1143 * to 1144 * CE address space 1145 */ 1146 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1147 1148 remaining_bytes = nbytes; 1149 while (remaining_bytes) { 1150 /* FIXME: check cast */ 1151 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1152 1153 /* Copy caller's data to allocated DMA buf */ 1154 memcpy(data_buf, data, nbytes); 1155 1156 /* Set up to receive directly into Target(!) address */ 1157 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address); 1158 if (ret != 0) 1159 goto done; 1160 1161 /* 1162 * Request CE to send caller-supplied data that 1163 * was copied to bounce buffer to Target(!) address. 1164 */ 1165 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0); 1166 if (ret != 0) 1167 goto done; 1168 1169 i = 0; 1170 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1171 udelay(DIAG_ACCESS_CE_WAIT_US); 1172 i += DIAG_ACCESS_CE_WAIT_US; 1173 1174 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1175 ret = -EBUSY; 1176 goto done; 1177 } 1178 } 1179 1180 i = 0; 1181 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1182 &completed_nbytes) != 0) { 1183 udelay(DIAG_ACCESS_CE_WAIT_US); 1184 i += DIAG_ACCESS_CE_WAIT_US; 1185 1186 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1187 ret = -EBUSY; 1188 goto done; 1189 } 1190 } 1191 1192 if (nbytes != completed_nbytes) { 1193 ret = -EIO; 1194 goto done; 1195 } 1196 1197 if (*buf != address) { 1198 ret = -EIO; 1199 goto done; 1200 } 1201 1202 remaining_bytes -= nbytes; 1203 address += nbytes; 1204 data += nbytes; 1205 } 1206 1207 done: 1208 if (data_buf) { 1209 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1210 ce_data_base); 1211 } 1212 1213 if (ret != 0) 1214 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1215 address, ret); 1216 1217 mutex_unlock(&ar_pci->ce_diag_mutex); 1218 1219 return ret; 1220 } 1221 1222 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1223 { 1224 __le32 val = __cpu_to_le32(value); 1225 1226 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1227 } 1228 1229 /* Called by lower (CE) layer when a send to Target completes. */ 1230 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1231 { 1232 struct ath10k *ar = ce_state->ar; 1233 struct sk_buff_head list; 1234 struct sk_buff *skb; 1235 1236 __skb_queue_head_init(&list); 1237 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1238 /* no need to call tx completion for NULL pointers */ 1239 if (skb == NULL) 1240 continue; 1241 1242 __skb_queue_tail(&list, skb); 1243 } 1244 1245 while ((skb = __skb_dequeue(&list))) 1246 ath10k_htc_tx_completion_handler(ar, skb); 1247 } 1248 1249 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1250 void (*callback)(struct ath10k *ar, 1251 struct sk_buff *skb)) 1252 { 1253 struct ath10k *ar = ce_state->ar; 1254 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1255 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1256 struct sk_buff *skb; 1257 struct sk_buff_head list; 1258 void *transfer_context; 1259 unsigned int nbytes, max_nbytes; 1260 1261 __skb_queue_head_init(&list); 1262 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1263 &nbytes) == 0) { 1264 skb = transfer_context; 1265 max_nbytes = skb->len + skb_tailroom(skb); 1266 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1267 max_nbytes, DMA_FROM_DEVICE); 1268 1269 if (unlikely(max_nbytes < nbytes)) { 1270 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1271 nbytes, max_nbytes); 1272 dev_kfree_skb_any(skb); 1273 continue; 1274 } 1275 1276 skb_put(skb, nbytes); 1277 __skb_queue_tail(&list, skb); 1278 } 1279 1280 while ((skb = __skb_dequeue(&list))) { 1281 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1282 ce_state->id, skb->len); 1283 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1284 skb->data, skb->len); 1285 1286 callback(ar, skb); 1287 } 1288 1289 ath10k_pci_rx_post_pipe(pipe_info); 1290 } 1291 1292 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1293 void (*callback)(struct ath10k *ar, 1294 struct sk_buff *skb)) 1295 { 1296 struct ath10k *ar = ce_state->ar; 1297 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1298 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1299 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1300 struct sk_buff *skb; 1301 struct sk_buff_head list; 1302 void *transfer_context; 1303 unsigned int nbytes, max_nbytes, nentries; 1304 int orig_len; 1305 1306 /* No need to acquire ce_lock for CE5, since this is the only place CE5 1307 * is processed other than init and deinit. Before releasing CE5 1308 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1309 */ 1310 __skb_queue_head_init(&list); 1311 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1312 &nbytes) == 0) { 1313 skb = transfer_context; 1314 max_nbytes = skb->len + skb_tailroom(skb); 1315 1316 if (unlikely(max_nbytes < nbytes)) { 1317 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1318 nbytes, max_nbytes); 1319 continue; 1320 } 1321 1322 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1323 max_nbytes, DMA_FROM_DEVICE); 1324 skb_put(skb, nbytes); 1325 __skb_queue_tail(&list, skb); 1326 } 1327 1328 nentries = skb_queue_len(&list); 1329 while ((skb = __skb_dequeue(&list))) { 1330 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1331 ce_state->id, skb->len); 1332 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1333 skb->data, skb->len); 1334 1335 orig_len = skb->len; 1336 callback(ar, skb); 1337 skb_push(skb, orig_len - skb->len); 1338 skb_reset_tail_pointer(skb); 1339 skb_trim(skb, 0); 1340 1341 /*let device gain the buffer again*/ 1342 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1343 skb->len + skb_tailroom(skb), 1344 DMA_FROM_DEVICE); 1345 } 1346 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1347 } 1348 1349 /* Called by lower (CE) layer when data is received from the Target. */ 1350 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1351 { 1352 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1353 } 1354 1355 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1356 { 1357 /* CE4 polling needs to be done whenever CE pipe which transports 1358 * HTT Rx (target->host) is processed. 1359 */ 1360 ath10k_ce_per_engine_service(ce_state->ar, 4); 1361 1362 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1363 } 1364 1365 /* Called by lower (CE) layer when data is received from the Target. 1366 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1367 */ 1368 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1369 { 1370 ath10k_pci_process_rx_cb(ce_state, 1371 ath10k_htt_rx_pktlog_completion_handler); 1372 } 1373 1374 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1375 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1376 { 1377 struct ath10k *ar = ce_state->ar; 1378 struct sk_buff *skb; 1379 1380 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1381 /* no need to call tx completion for NULL pointers */ 1382 if (!skb) 1383 continue; 1384 1385 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1386 skb->len, DMA_TO_DEVICE); 1387 ath10k_htt_hif_tx_complete(ar, skb); 1388 } 1389 } 1390 1391 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1392 { 1393 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1394 ath10k_htt_t2h_msg_handler(ar, skb); 1395 } 1396 1397 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1398 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1399 { 1400 /* CE4 polling needs to be done whenever CE pipe which transports 1401 * HTT Rx (target->host) is processed. 1402 */ 1403 ath10k_ce_per_engine_service(ce_state->ar, 4); 1404 1405 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1406 } 1407 1408 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1409 struct ath10k_hif_sg_item *items, int n_items) 1410 { 1411 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1412 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1413 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1414 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1415 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1416 unsigned int nentries_mask; 1417 unsigned int sw_index; 1418 unsigned int write_index; 1419 int err, i = 0; 1420 1421 spin_lock_bh(&ce->ce_lock); 1422 1423 nentries_mask = src_ring->nentries_mask; 1424 sw_index = src_ring->sw_index; 1425 write_index = src_ring->write_index; 1426 1427 if (unlikely(CE_RING_DELTA(nentries_mask, 1428 write_index, sw_index - 1) < n_items)) { 1429 err = -ENOBUFS; 1430 goto err; 1431 } 1432 1433 for (i = 0; i < n_items - 1; i++) { 1434 ath10k_dbg(ar, ATH10K_DBG_PCI, 1435 "pci tx item %d paddr %pad len %d n_items %d\n", 1436 i, &items[i].paddr, items[i].len, n_items); 1437 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1438 items[i].vaddr, items[i].len); 1439 1440 err = ath10k_ce_send_nolock(ce_pipe, 1441 items[i].transfer_context, 1442 items[i].paddr, 1443 items[i].len, 1444 items[i].transfer_id, 1445 CE_SEND_FLAG_GATHER); 1446 if (err) 1447 goto err; 1448 } 1449 1450 /* `i` is equal to `n_items -1` after for() */ 1451 1452 ath10k_dbg(ar, ATH10K_DBG_PCI, 1453 #if defined(__linux__) 1454 "pci tx item %d paddr %pad len %d n_items %d\n", 1455 i, &items[i].paddr, items[i].len, n_items); 1456 #elif defined(__FreeBSD__) 1457 "pci tx item %d paddr %pad len %d n_items %d pipe_id %u\n", 1458 i, &items[i].paddr, items[i].len, n_items, pipe_id); 1459 /* 1460 * XXX-BZ specific debug; the DELAY makes things work for one chipset. 1461 * There's likely a race somewhere (here or LinuxKPI). 1462 */ 1463 if (n_items == 1 && items[i].len == 140) { 1464 ath10k_dbg_dump(ar, ATH10K_DBG_PCI, NULL, "pci tx data: ", 1465 items[i].vaddr, items[i].len); 1466 dump_stack(); 1467 DELAY(500); 1468 } 1469 #endif 1470 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1471 items[i].vaddr, items[i].len); 1472 1473 err = ath10k_ce_send_nolock(ce_pipe, 1474 items[i].transfer_context, 1475 items[i].paddr, 1476 items[i].len, 1477 items[i].transfer_id, 1478 0); 1479 if (err) 1480 goto err; 1481 1482 spin_unlock_bh(&ce->ce_lock); 1483 return 0; 1484 1485 err: 1486 for (; i > 0; i--) 1487 __ath10k_ce_send_revert(ce_pipe); 1488 1489 spin_unlock_bh(&ce->ce_lock); 1490 return err; 1491 } 1492 1493 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1494 size_t buf_len) 1495 { 1496 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1497 } 1498 1499 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1500 { 1501 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1502 1503 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1504 1505 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1506 } 1507 1508 static void ath10k_pci_dump_registers(struct ath10k *ar, 1509 struct ath10k_fw_crash_data *crash_data) 1510 { 1511 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1512 int i, ret; 1513 1514 lockdep_assert_held(&ar->dump_mutex); 1515 1516 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1517 hi_failure_state, 1518 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1519 if (ret) { 1520 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1521 return; 1522 } 1523 1524 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1525 1526 ath10k_err(ar, "firmware register dump:\n"); 1527 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1528 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1529 i, 1530 __le32_to_cpu(reg_dump_values[i]), 1531 __le32_to_cpu(reg_dump_values[i + 1]), 1532 __le32_to_cpu(reg_dump_values[i + 2]), 1533 __le32_to_cpu(reg_dump_values[i + 3])); 1534 1535 if (!crash_data) 1536 return; 1537 1538 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1539 crash_data->registers[i] = reg_dump_values[i]; 1540 } 1541 1542 static int ath10k_pci_dump_memory_section(struct ath10k *ar, 1543 const struct ath10k_mem_region *mem_region, 1544 u8 *buf, size_t buf_len) 1545 { 1546 const struct ath10k_mem_section *cur_section, *next_section; 1547 unsigned int count, section_size, skip_size; 1548 int ret, i, j; 1549 1550 if (!mem_region || !buf) 1551 return 0; 1552 1553 cur_section = &mem_region->section_table.sections[0]; 1554 1555 if (mem_region->start > cur_section->start) { 1556 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", 1557 mem_region->start, cur_section->start); 1558 return 0; 1559 } 1560 1561 skip_size = cur_section->start - mem_region->start; 1562 1563 /* fill the gap between the first register section and register 1564 * start address 1565 */ 1566 for (i = 0; i < skip_size; i++) { 1567 *buf = ATH10K_MAGIC_NOT_COPIED; 1568 buf++; 1569 } 1570 1571 count = 0; 1572 1573 for (i = 0; cur_section != NULL; i++) { 1574 section_size = cur_section->end - cur_section->start; 1575 1576 if (section_size <= 0) { 1577 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", 1578 cur_section->start, 1579 cur_section->end); 1580 break; 1581 } 1582 1583 if ((i + 1) == mem_region->section_table.size) { 1584 /* last section */ 1585 next_section = NULL; 1586 skip_size = 0; 1587 } else { 1588 next_section = cur_section + 1; 1589 1590 if (cur_section->end > next_section->start) { 1591 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", 1592 next_section->start, 1593 cur_section->end); 1594 break; 1595 } 1596 1597 skip_size = next_section->start - cur_section->end; 1598 } 1599 1600 if (buf_len < (skip_size + section_size)) { 1601 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); 1602 break; 1603 } 1604 1605 buf_len -= skip_size + section_size; 1606 1607 /* read section to dest memory */ 1608 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, 1609 buf, section_size); 1610 if (ret) { 1611 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", 1612 cur_section->start, ret); 1613 break; 1614 } 1615 1616 buf += section_size; 1617 count += section_size; 1618 1619 /* fill in the gap between this section and the next */ 1620 for (j = 0; j < skip_size; j++) { 1621 *buf = ATH10K_MAGIC_NOT_COPIED; 1622 buf++; 1623 } 1624 1625 count += skip_size; 1626 1627 if (!next_section) 1628 /* this was the last section */ 1629 break; 1630 1631 cur_section = next_section; 1632 } 1633 1634 return count; 1635 } 1636 1637 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) 1638 { 1639 u32 val; 1640 1641 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1642 FW_RAM_CONFIG_ADDRESS, config); 1643 1644 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1645 FW_RAM_CONFIG_ADDRESS); 1646 if (val != config) { 1647 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", 1648 val, config); 1649 return -EIO; 1650 } 1651 1652 return 0; 1653 } 1654 1655 /* Always returns the length */ 1656 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, 1657 const struct ath10k_mem_region *region, 1658 u8 *buf) 1659 { 1660 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1661 u32 base_addr, i; 1662 1663 #if defined(__linux__) 1664 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); 1665 #elif defined(__FreeBSD__) 1666 base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG); 1667 #endif 1668 base_addr += region->start; 1669 1670 for (i = 0; i < region->len; i += 4) { 1671 #if defined(__linux__) 1672 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); 1673 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); 1674 #elif defined(__FreeBSD__) 1675 bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i); 1676 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG); 1677 #endif 1678 } 1679 1680 return region->len; 1681 } 1682 1683 /* if an error happened returns < 0, otherwise the length */ 1684 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, 1685 const struct ath10k_mem_region *region, 1686 u8 *buf) 1687 { 1688 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1689 u32 i; 1690 int ret; 1691 1692 mutex_lock(&ar->conf_mutex); 1693 if (ar->state != ATH10K_STATE_ON) { 1694 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n"); 1695 ret = -EIO; 1696 goto done; 1697 } 1698 1699 for (i = 0; i < region->len; i += 4) 1700 #if defined(__linux__) 1701 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); 1702 #elif defined(__FreeBSD__) 1703 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i); 1704 #endif 1705 1706 ret = region->len; 1707 done: 1708 mutex_unlock(&ar->conf_mutex); 1709 return ret; 1710 } 1711 1712 /* if an error happened returns < 0, otherwise the length */ 1713 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, 1714 const struct ath10k_mem_region *current_region, 1715 u8 *buf) 1716 { 1717 int ret; 1718 1719 if (current_region->section_table.size > 0) 1720 /* Copy each section individually. */ 1721 return ath10k_pci_dump_memory_section(ar, 1722 current_region, 1723 buf, 1724 current_region->len); 1725 1726 /* No individiual memory sections defined so we can 1727 * copy the entire memory region. 1728 */ 1729 ret = ath10k_pci_diag_read_mem(ar, 1730 current_region->start, 1731 buf, 1732 current_region->len); 1733 if (ret) { 1734 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", 1735 current_region->name, ret); 1736 return ret; 1737 } 1738 1739 return current_region->len; 1740 } 1741 1742 static void ath10k_pci_dump_memory(struct ath10k *ar, 1743 struct ath10k_fw_crash_data *crash_data) 1744 { 1745 const struct ath10k_hw_mem_layout *mem_layout; 1746 const struct ath10k_mem_region *current_region; 1747 struct ath10k_dump_ram_data_hdr *hdr; 1748 u32 count, shift; 1749 size_t buf_len; 1750 int ret, i; 1751 u8 *buf; 1752 1753 lockdep_assert_held(&ar->dump_mutex); 1754 1755 if (!crash_data) 1756 return; 1757 1758 mem_layout = ath10k_coredump_get_mem_layout(ar); 1759 if (!mem_layout) 1760 return; 1761 1762 current_region = &mem_layout->region_table.regions[0]; 1763 1764 buf = crash_data->ramdump_buf; 1765 buf_len = crash_data->ramdump_buf_len; 1766 1767 memset(buf, 0, buf_len); 1768 1769 for (i = 0; i < mem_layout->region_table.size; i++) { 1770 count = 0; 1771 1772 if (current_region->len > buf_len) { 1773 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", 1774 current_region->name, 1775 current_region->len, 1776 buf_len); 1777 break; 1778 } 1779 1780 /* To get IRAM dump, the host driver needs to switch target 1781 * ram config from DRAM to IRAM. 1782 */ 1783 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || 1784 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { 1785 shift = current_region->start >> 20; 1786 1787 ret = ath10k_pci_set_ram_config(ar, shift); 1788 if (ret) { 1789 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", 1790 current_region->name, ret); 1791 break; 1792 } 1793 } 1794 1795 /* Reserve space for the header. */ 1796 hdr = (void *)buf; 1797 buf += sizeof(*hdr); 1798 buf_len -= sizeof(*hdr); 1799 1800 switch (current_region->type) { 1801 case ATH10K_MEM_REGION_TYPE_IOSRAM: 1802 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); 1803 break; 1804 case ATH10K_MEM_REGION_TYPE_IOREG: 1805 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf); 1806 if (ret < 0) 1807 break; 1808 1809 count = ret; 1810 break; 1811 default: 1812 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); 1813 if (ret < 0) 1814 break; 1815 1816 count = ret; 1817 break; 1818 } 1819 1820 hdr->region_type = cpu_to_le32(current_region->type); 1821 hdr->start = cpu_to_le32(current_region->start); 1822 hdr->length = cpu_to_le32(count); 1823 1824 if (count == 0) 1825 /* Note: the header remains, just with zero length. */ 1826 break; 1827 1828 buf += count; 1829 buf_len -= count; 1830 1831 current_region++; 1832 } 1833 } 1834 1835 static void ath10k_pci_fw_dump_work(struct work_struct *work) 1836 { 1837 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci, 1838 dump_work); 1839 struct ath10k_fw_crash_data *crash_data; 1840 struct ath10k *ar = ar_pci->ar; 1841 char guid[UUID_STRING_LEN + 1]; 1842 1843 mutex_lock(&ar->dump_mutex); 1844 1845 spin_lock_bh(&ar->data_lock); 1846 ar->stats.fw_crash_counter++; 1847 spin_unlock_bh(&ar->data_lock); 1848 1849 crash_data = ath10k_coredump_new(ar); 1850 1851 if (crash_data) 1852 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1853 else 1854 scnprintf(guid, sizeof(guid), "n/a"); 1855 1856 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1857 ath10k_print_driver_info(ar); 1858 ath10k_pci_dump_registers(ar, crash_data); 1859 ath10k_ce_dump_registers(ar, crash_data); 1860 ath10k_pci_dump_memory(ar, crash_data); 1861 1862 mutex_unlock(&ar->dump_mutex); 1863 1864 ath10k_core_start_recovery(ar); 1865 } 1866 1867 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1868 { 1869 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1870 1871 queue_work(ar->workqueue, &ar_pci->dump_work); 1872 } 1873 1874 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1875 int force) 1876 { 1877 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1878 1879 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1880 1881 if (!force) { 1882 int resources; 1883 /* 1884 * Decide whether to actually poll for completions, or just 1885 * wait for a later chance. 1886 * If there seem to be plenty of resources left, then just wait 1887 * since checking involves reading a CE register, which is a 1888 * relatively expensive operation. 1889 */ 1890 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1891 1892 /* 1893 * If at least 50% of the total resources are still available, 1894 * don't bother checking again yet. 1895 */ 1896 if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) 1897 return; 1898 } 1899 ath10k_ce_per_engine_service(ar, pipe); 1900 } 1901 1902 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1903 { 1904 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1905 1906 del_timer_sync(&ar_pci->rx_post_retry); 1907 } 1908 1909 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1910 u8 *ul_pipe, u8 *dl_pipe) 1911 { 1912 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1913 const struct ce_service_to_pipe *entry; 1914 bool ul_set = false, dl_set = false; 1915 int i; 1916 1917 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1918 1919 for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) { 1920 entry = &ar_pci->serv_to_pipe[i]; 1921 1922 if (__le32_to_cpu(entry->service_id) != service_id) 1923 continue; 1924 1925 switch (__le32_to_cpu(entry->pipedir)) { 1926 case PIPEDIR_NONE: 1927 break; 1928 case PIPEDIR_IN: 1929 WARN_ON(dl_set); 1930 *dl_pipe = __le32_to_cpu(entry->pipenum); 1931 dl_set = true; 1932 break; 1933 case PIPEDIR_OUT: 1934 WARN_ON(ul_set); 1935 *ul_pipe = __le32_to_cpu(entry->pipenum); 1936 ul_set = true; 1937 break; 1938 case PIPEDIR_INOUT: 1939 WARN_ON(dl_set); 1940 WARN_ON(ul_set); 1941 *dl_pipe = __le32_to_cpu(entry->pipenum); 1942 *ul_pipe = __le32_to_cpu(entry->pipenum); 1943 dl_set = true; 1944 ul_set = true; 1945 break; 1946 } 1947 } 1948 1949 if (!ul_set || !dl_set) 1950 return -ENOENT; 1951 1952 return 0; 1953 } 1954 1955 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1956 u8 *ul_pipe, u8 *dl_pipe) 1957 { 1958 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1959 1960 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1961 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1962 ul_pipe, dl_pipe); 1963 } 1964 1965 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1966 { 1967 u32 val; 1968 1969 switch (ar->hw_rev) { 1970 case ATH10K_HW_QCA988X: 1971 case ATH10K_HW_QCA9887: 1972 case ATH10K_HW_QCA6174: 1973 case ATH10K_HW_QCA9377: 1974 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1975 CORE_CTRL_ADDRESS); 1976 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1977 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1978 CORE_CTRL_ADDRESS, val); 1979 break; 1980 case ATH10K_HW_QCA99X0: 1981 case ATH10K_HW_QCA9984: 1982 case ATH10K_HW_QCA9888: 1983 case ATH10K_HW_QCA4019: 1984 /* TODO: Find appropriate register configuration for QCA99X0 1985 * to mask irq/MSI. 1986 */ 1987 break; 1988 case ATH10K_HW_WCN3990: 1989 break; 1990 } 1991 } 1992 1993 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1994 { 1995 u32 val; 1996 1997 switch (ar->hw_rev) { 1998 case ATH10K_HW_QCA988X: 1999 case ATH10K_HW_QCA9887: 2000 case ATH10K_HW_QCA6174: 2001 case ATH10K_HW_QCA9377: 2002 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 2003 CORE_CTRL_ADDRESS); 2004 val |= CORE_CTRL_PCIE_REG_31_MASK; 2005 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 2006 CORE_CTRL_ADDRESS, val); 2007 break; 2008 case ATH10K_HW_QCA99X0: 2009 case ATH10K_HW_QCA9984: 2010 case ATH10K_HW_QCA9888: 2011 case ATH10K_HW_QCA4019: 2012 /* TODO: Find appropriate register configuration for QCA99X0 2013 * to unmask irq/MSI. 2014 */ 2015 break; 2016 case ATH10K_HW_WCN3990: 2017 break; 2018 } 2019 } 2020 2021 static void ath10k_pci_irq_disable(struct ath10k *ar) 2022 { 2023 ath10k_ce_disable_interrupts(ar); 2024 ath10k_pci_disable_and_clear_legacy_irq(ar); 2025 ath10k_pci_irq_msi_fw_mask(ar); 2026 } 2027 2028 static void ath10k_pci_irq_sync(struct ath10k *ar) 2029 { 2030 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2031 2032 synchronize_irq(ar_pci->pdev->irq); 2033 } 2034 2035 static void ath10k_pci_irq_enable(struct ath10k *ar) 2036 { 2037 ath10k_ce_enable_interrupts(ar); 2038 ath10k_pci_enable_legacy_irq(ar); 2039 ath10k_pci_irq_msi_fw_unmask(ar); 2040 } 2041 2042 static int ath10k_pci_hif_start(struct ath10k *ar) 2043 { 2044 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2045 2046 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 2047 2048 ath10k_core_napi_enable(ar); 2049 2050 ath10k_pci_irq_enable(ar); 2051 ath10k_pci_rx_post(ar); 2052 2053 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2054 ar_pci->link_ctl); 2055 2056 return 0; 2057 } 2058 2059 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2060 { 2061 struct ath10k *ar; 2062 struct ath10k_ce_pipe *ce_pipe; 2063 struct ath10k_ce_ring *ce_ring; 2064 struct sk_buff *skb; 2065 int i; 2066 2067 ar = pci_pipe->hif_ce_state; 2068 ce_pipe = pci_pipe->ce_hdl; 2069 ce_ring = ce_pipe->dest_ring; 2070 2071 if (!ce_ring) 2072 return; 2073 2074 if (!pci_pipe->buf_sz) 2075 return; 2076 2077 for (i = 0; i < ce_ring->nentries; i++) { 2078 skb = ce_ring->per_transfer_context[i]; 2079 if (!skb) 2080 continue; 2081 2082 ce_ring->per_transfer_context[i] = NULL; 2083 2084 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 2085 skb->len + skb_tailroom(skb), 2086 DMA_FROM_DEVICE); 2087 dev_kfree_skb_any(skb); 2088 } 2089 } 2090 2091 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2092 { 2093 struct ath10k *ar; 2094 struct ath10k_ce_pipe *ce_pipe; 2095 struct ath10k_ce_ring *ce_ring; 2096 struct sk_buff *skb; 2097 int i; 2098 2099 ar = pci_pipe->hif_ce_state; 2100 ce_pipe = pci_pipe->ce_hdl; 2101 ce_ring = ce_pipe->src_ring; 2102 2103 if (!ce_ring) 2104 return; 2105 2106 if (!pci_pipe->buf_sz) 2107 return; 2108 2109 for (i = 0; i < ce_ring->nentries; i++) { 2110 skb = ce_ring->per_transfer_context[i]; 2111 if (!skb) 2112 continue; 2113 2114 ce_ring->per_transfer_context[i] = NULL; 2115 2116 ath10k_htc_tx_completion_handler(ar, skb); 2117 } 2118 } 2119 2120 /* 2121 * Cleanup residual buffers for device shutdown: 2122 * buffers that were enqueued for receive 2123 * buffers that were to be sent 2124 * Note: Buffers that had completed but which were 2125 * not yet processed are on a completion queue. They 2126 * are handled when the completion thread shuts down. 2127 */ 2128 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 2129 { 2130 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2131 int pipe_num; 2132 2133 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 2134 struct ath10k_pci_pipe *pipe_info; 2135 2136 pipe_info = &ar_pci->pipe_info[pipe_num]; 2137 ath10k_pci_rx_pipe_cleanup(pipe_info); 2138 ath10k_pci_tx_pipe_cleanup(pipe_info); 2139 } 2140 } 2141 2142 void ath10k_pci_ce_deinit(struct ath10k *ar) 2143 { 2144 int i; 2145 2146 for (i = 0; i < CE_COUNT; i++) 2147 ath10k_ce_deinit_pipe(ar, i); 2148 } 2149 2150 void ath10k_pci_flush(struct ath10k *ar) 2151 { 2152 ath10k_pci_rx_retry_sync(ar); 2153 ath10k_pci_buffer_cleanup(ar); 2154 } 2155 2156 static void ath10k_pci_hif_stop(struct ath10k *ar) 2157 { 2158 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2159 unsigned long flags; 2160 2161 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 2162 2163 ath10k_pci_irq_disable(ar); 2164 ath10k_pci_irq_sync(ar); 2165 2166 ath10k_core_napi_sync_disable(ar); 2167 2168 cancel_work_sync(&ar_pci->dump_work); 2169 2170 /* Most likely the device has HTT Rx ring configured. The only way to 2171 * prevent the device from accessing (and possible corrupting) host 2172 * memory is to reset the chip now. 2173 * 2174 * There's also no known way of masking MSI interrupts on the device. 2175 * For ranged MSI the CE-related interrupts can be masked. However 2176 * regardless how many MSI interrupts are assigned the first one 2177 * is always used for firmware indications (crashes) and cannot be 2178 * masked. To prevent the device from asserting the interrupt reset it 2179 * before proceeding with cleanup. 2180 */ 2181 ath10k_pci_safe_chip_reset(ar); 2182 2183 ath10k_pci_flush(ar); 2184 2185 spin_lock_irqsave(&ar_pci->ps_lock, flags); 2186 WARN_ON(ar_pci->ps_wake_refcount > 0); 2187 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 2188 } 2189 2190 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 2191 void *req, u32 req_len, 2192 void *resp, u32 *resp_len) 2193 { 2194 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2195 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 2196 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 2197 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 2198 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 2199 dma_addr_t req_paddr = 0; 2200 dma_addr_t resp_paddr = 0; 2201 struct bmi_xfer xfer = {}; 2202 void *treq, *tresp = NULL; 2203 int ret = 0; 2204 2205 might_sleep(); 2206 2207 if (resp && !resp_len) 2208 return -EINVAL; 2209 2210 if (resp && resp_len && *resp_len == 0) 2211 return -EINVAL; 2212 2213 treq = kmemdup(req, req_len, GFP_KERNEL); 2214 if (!treq) 2215 return -ENOMEM; 2216 2217 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 2218 ret = dma_mapping_error(ar->dev, req_paddr); 2219 if (ret) { 2220 ret = -EIO; 2221 goto err_dma; 2222 } 2223 2224 if (resp && resp_len) { 2225 tresp = kzalloc(*resp_len, GFP_KERNEL); 2226 if (!tresp) { 2227 ret = -ENOMEM; 2228 goto err_req; 2229 } 2230 2231 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 2232 DMA_FROM_DEVICE); 2233 ret = dma_mapping_error(ar->dev, resp_paddr); 2234 if (ret) { 2235 ret = -EIO; 2236 goto err_req; 2237 } 2238 2239 xfer.wait_for_resp = true; 2240 xfer.resp_len = 0; 2241 2242 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 2243 } 2244 2245 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 2246 if (ret) 2247 goto err_resp; 2248 2249 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 2250 if (ret) { 2251 dma_addr_t unused_buffer; 2252 unsigned int unused_nbytes; 2253 unsigned int unused_id; 2254 2255 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 2256 &unused_nbytes, &unused_id); 2257 } else { 2258 /* non-zero means we did not time out */ 2259 ret = 0; 2260 } 2261 2262 err_resp: 2263 if (resp) { 2264 dma_addr_t unused_buffer; 2265 2266 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 2267 dma_unmap_single(ar->dev, resp_paddr, 2268 *resp_len, DMA_FROM_DEVICE); 2269 } 2270 err_req: 2271 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 2272 2273 if (ret == 0 && resp_len) { 2274 *resp_len = min(*resp_len, xfer.resp_len); 2275 memcpy(resp, tresp, *resp_len); 2276 } 2277 err_dma: 2278 kfree(treq); 2279 kfree(tresp); 2280 2281 return ret; 2282 } 2283 2284 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 2285 { 2286 struct bmi_xfer *xfer; 2287 2288 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 2289 return; 2290 2291 xfer->tx_done = true; 2292 } 2293 2294 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 2295 { 2296 struct ath10k *ar = ce_state->ar; 2297 struct bmi_xfer *xfer; 2298 unsigned int nbytes; 2299 2300 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 2301 &nbytes)) 2302 return; 2303 2304 if (WARN_ON_ONCE(!xfer)) 2305 return; 2306 2307 if (!xfer->wait_for_resp) { 2308 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 2309 return; 2310 } 2311 2312 xfer->resp_len = nbytes; 2313 xfer->rx_done = true; 2314 } 2315 2316 static int ath10k_pci_bmi_wait(struct ath10k *ar, 2317 struct ath10k_ce_pipe *tx_pipe, 2318 struct ath10k_ce_pipe *rx_pipe, 2319 struct bmi_xfer *xfer) 2320 { 2321 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 2322 unsigned long started = jiffies; 2323 unsigned long dur; 2324 int ret; 2325 2326 while (time_before_eq(jiffies, timeout)) { 2327 ath10k_pci_bmi_send_done(tx_pipe); 2328 ath10k_pci_bmi_recv_data(rx_pipe); 2329 2330 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 2331 ret = 0; 2332 goto out; 2333 } 2334 2335 #if defined(__linux__) 2336 schedule(); 2337 #elif defined(__FreeBSD__) 2338 /* Using LinuxKPI we'll hang for-ever as there's no wake_up */ 2339 kern_yield(PRI_USER); 2340 #endif 2341 } 2342 2343 ret = -ETIMEDOUT; 2344 2345 out: 2346 dur = jiffies - started; 2347 if (dur > HZ) 2348 ath10k_dbg(ar, ATH10K_DBG_BMI, 2349 "bmi cmd took %lu jiffies hz %d ret %d\n", 2350 dur, HZ, ret); 2351 return ret; 2352 } 2353 2354 /* 2355 * Send an interrupt to the device to wake up the Target CPU 2356 * so it has an opportunity to notice any changed state. 2357 */ 2358 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 2359 { 2360 u32 addr, val; 2361 2362 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 2363 val = ath10k_pci_read32(ar, addr); 2364 val |= CORE_CTRL_CPU_INTR_MASK; 2365 ath10k_pci_write32(ar, addr, val); 2366 2367 return 0; 2368 } 2369 2370 static int ath10k_pci_get_num_banks(struct ath10k *ar) 2371 { 2372 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2373 2374 switch (ar_pci->pdev->device) { 2375 case QCA988X_2_0_DEVICE_ID_UBNT: 2376 case QCA988X_2_0_DEVICE_ID: 2377 case QCA99X0_2_0_DEVICE_ID: 2378 case QCA9888_2_0_DEVICE_ID: 2379 case QCA9984_1_0_DEVICE_ID: 2380 case QCA9887_1_0_DEVICE_ID: 2381 return 1; 2382 case QCA6164_2_1_DEVICE_ID: 2383 case QCA6174_2_1_DEVICE_ID: 2384 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { 2385 case QCA6174_HW_1_0_CHIP_ID_REV: 2386 case QCA6174_HW_1_1_CHIP_ID_REV: 2387 case QCA6174_HW_2_1_CHIP_ID_REV: 2388 case QCA6174_HW_2_2_CHIP_ID_REV: 2389 return 3; 2390 case QCA6174_HW_1_3_CHIP_ID_REV: 2391 return 2; 2392 case QCA6174_HW_3_0_CHIP_ID_REV: 2393 case QCA6174_HW_3_1_CHIP_ID_REV: 2394 case QCA6174_HW_3_2_CHIP_ID_REV: 2395 return 9; 2396 } 2397 break; 2398 case QCA9377_1_0_DEVICE_ID: 2399 return 9; 2400 } 2401 2402 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2403 return 1; 2404 } 2405 2406 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2407 { 2408 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2409 2410 return ce->bus_ops->get_num_banks(ar); 2411 } 2412 2413 int ath10k_pci_init_config(struct ath10k *ar) 2414 { 2415 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2416 u32 interconnect_targ_addr; 2417 u32 pcie_state_targ_addr = 0; 2418 u32 pipe_cfg_targ_addr = 0; 2419 u32 svc_to_pipe_map = 0; 2420 u32 pcie_config_flags = 0; 2421 u32 ealloc_value; 2422 u32 ealloc_targ_addr; 2423 u32 flag2_value; 2424 u32 flag2_targ_addr; 2425 int ret = 0; 2426 2427 /* Download to Target the CE Config and the service-to-CE map */ 2428 interconnect_targ_addr = 2429 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2430 2431 /* Supply Target-side CE configuration */ 2432 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2433 &pcie_state_targ_addr); 2434 if (ret != 0) { 2435 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2436 return ret; 2437 } 2438 2439 if (pcie_state_targ_addr == 0) { 2440 ret = -EIO; 2441 ath10k_err(ar, "Invalid pcie state addr\n"); 2442 return ret; 2443 } 2444 2445 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2446 offsetof(struct pcie_state, 2447 pipe_cfg_addr)), 2448 &pipe_cfg_targ_addr); 2449 if (ret != 0) { 2450 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2451 return ret; 2452 } 2453 2454 if (pipe_cfg_targ_addr == 0) { 2455 ret = -EIO; 2456 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2457 return ret; 2458 } 2459 2460 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2461 ar_pci->pipe_config, 2462 sizeof(struct ce_pipe_config) * 2463 NUM_TARGET_CE_CONFIG_WLAN); 2464 2465 if (ret != 0) { 2466 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2467 return ret; 2468 } 2469 2470 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2471 offsetof(struct pcie_state, 2472 svc_to_pipe_map)), 2473 &svc_to_pipe_map); 2474 if (ret != 0) { 2475 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2476 return ret; 2477 } 2478 2479 if (svc_to_pipe_map == 0) { 2480 ret = -EIO; 2481 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2482 return ret; 2483 } 2484 2485 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2486 ar_pci->serv_to_pipe, 2487 sizeof(pci_target_service_to_ce_map_wlan)); 2488 if (ret != 0) { 2489 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2490 return ret; 2491 } 2492 2493 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2494 offsetof(struct pcie_state, 2495 config_flags)), 2496 &pcie_config_flags); 2497 if (ret != 0) { 2498 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2499 return ret; 2500 } 2501 2502 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2503 2504 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2505 offsetof(struct pcie_state, 2506 config_flags)), 2507 pcie_config_flags); 2508 if (ret != 0) { 2509 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2510 return ret; 2511 } 2512 2513 /* configure early allocation */ 2514 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2515 2516 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2517 if (ret != 0) { 2518 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2519 return ret; 2520 } 2521 2522 /* first bank is switched to IRAM */ 2523 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2524 HI_EARLY_ALLOC_MAGIC_MASK); 2525 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2526 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2527 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2528 2529 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2530 if (ret != 0) { 2531 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2532 return ret; 2533 } 2534 2535 /* Tell Target to proceed with initialization */ 2536 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2537 2538 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2539 if (ret != 0) { 2540 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2541 return ret; 2542 } 2543 2544 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2545 2546 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2547 if (ret != 0) { 2548 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2549 return ret; 2550 } 2551 2552 return 0; 2553 } 2554 2555 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2556 { 2557 struct ce_attr *attr; 2558 struct ce_pipe_config *config; 2559 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2560 2561 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2562 * since it is currently used for other feature. 2563 */ 2564 2565 /* Override Host's Copy Engine 5 configuration */ 2566 attr = &ar_pci->attr[5]; 2567 attr->src_sz_max = 0; 2568 attr->dest_nentries = 0; 2569 2570 /* Override Target firmware's Copy Engine configuration */ 2571 config = &ar_pci->pipe_config[5]; 2572 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2573 config->nbytes_max = __cpu_to_le32(2048); 2574 2575 /* Map from service/endpoint to Copy Engine */ 2576 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); 2577 } 2578 2579 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2580 { 2581 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2582 struct ath10k_pci_pipe *pipe; 2583 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2584 int i, ret; 2585 2586 for (i = 0; i < CE_COUNT; i++) { 2587 pipe = &ar_pci->pipe_info[i]; 2588 pipe->ce_hdl = &ce->ce_states[i]; 2589 pipe->pipe_num = i; 2590 pipe->hif_ce_state = ar; 2591 2592 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); 2593 if (ret) { 2594 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2595 i, ret); 2596 return ret; 2597 } 2598 2599 /* Last CE is Diagnostic Window */ 2600 if (i == CE_DIAG_PIPE) { 2601 ar_pci->ce_diag = pipe->ce_hdl; 2602 continue; 2603 } 2604 2605 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); 2606 } 2607 2608 return 0; 2609 } 2610 2611 void ath10k_pci_free_pipes(struct ath10k *ar) 2612 { 2613 int i; 2614 2615 for (i = 0; i < CE_COUNT; i++) 2616 ath10k_ce_free_pipe(ar, i); 2617 } 2618 2619 int ath10k_pci_init_pipes(struct ath10k *ar) 2620 { 2621 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2622 int i, ret; 2623 2624 for (i = 0; i < CE_COUNT; i++) { 2625 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); 2626 if (ret) { 2627 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2628 i, ret); 2629 return ret; 2630 } 2631 } 2632 2633 return 0; 2634 } 2635 2636 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2637 { 2638 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2639 FW_IND_EVENT_PENDING; 2640 } 2641 2642 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2643 { 2644 u32 val; 2645 2646 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2647 val &= ~FW_IND_EVENT_PENDING; 2648 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2649 } 2650 2651 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2652 { 2653 u32 val; 2654 2655 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2656 return (val == 0xffffffff); 2657 } 2658 2659 /* this function effectively clears target memory controller assert line */ 2660 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2661 { 2662 u32 val; 2663 2664 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2665 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2666 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2667 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2668 2669 msleep(10); 2670 2671 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2672 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2673 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2674 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2675 2676 msleep(10); 2677 } 2678 2679 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2680 { 2681 u32 val; 2682 2683 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2684 2685 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2686 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2687 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2688 } 2689 2690 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2691 { 2692 u32 val; 2693 2694 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2695 2696 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2697 val | SOC_RESET_CONTROL_CE_RST_MASK); 2698 msleep(10); 2699 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2700 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2701 } 2702 2703 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2704 { 2705 u32 val; 2706 2707 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS); 2708 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS, 2709 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2710 } 2711 2712 static int ath10k_pci_warm_reset(struct ath10k *ar) 2713 { 2714 int ret; 2715 2716 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2717 2718 spin_lock_bh(&ar->data_lock); 2719 ar->stats.fw_warm_reset_counter++; 2720 spin_unlock_bh(&ar->data_lock); 2721 2722 ath10k_pci_irq_disable(ar); 2723 2724 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2725 * were to access copy engine while host performs copy engine reset 2726 * then it is possible for the device to confuse pci-e controller to 2727 * the point of bringing host system to a complete stop (i.e. hang). 2728 */ 2729 ath10k_pci_warm_reset_si0(ar); 2730 ath10k_pci_warm_reset_cpu(ar); 2731 ath10k_pci_init_pipes(ar); 2732 ath10k_pci_wait_for_target_init(ar); 2733 2734 ath10k_pci_warm_reset_clear_lf(ar); 2735 ath10k_pci_warm_reset_ce(ar); 2736 ath10k_pci_warm_reset_cpu(ar); 2737 ath10k_pci_init_pipes(ar); 2738 2739 ret = ath10k_pci_wait_for_target_init(ar); 2740 if (ret) { 2741 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2742 return ret; 2743 } 2744 2745 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2746 2747 return 0; 2748 } 2749 2750 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2751 { 2752 ath10k_pci_irq_disable(ar); 2753 return ath10k_pci_qca99x0_chip_reset(ar); 2754 } 2755 2756 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2757 { 2758 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2759 2760 if (!ar_pci->pci_soft_reset) 2761 return -ENOTSUPP; 2762 2763 return ar_pci->pci_soft_reset(ar); 2764 } 2765 2766 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2767 { 2768 int i, ret; 2769 u32 val; 2770 2771 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2772 2773 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2774 * It is thus preferred to use warm reset which is safer but may not be 2775 * able to recover the device from all possible fail scenarios. 2776 * 2777 * Warm reset doesn't always work on first try so attempt it a few 2778 * times before giving up. 2779 */ 2780 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2781 ret = ath10k_pci_warm_reset(ar); 2782 if (ret) { 2783 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2784 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2785 ret); 2786 continue; 2787 } 2788 2789 /* FIXME: Sometimes copy engine doesn't recover after warm 2790 * reset. In most cases this needs cold reset. In some of these 2791 * cases the device is in such a state that a cold reset may 2792 * lock up the host. 2793 * 2794 * Reading any host interest register via copy engine is 2795 * sufficient to verify if device is capable of booting 2796 * firmware blob. 2797 */ 2798 ret = ath10k_pci_init_pipes(ar); 2799 if (ret) { 2800 ath10k_warn(ar, "failed to init copy engine: %d\n", 2801 ret); 2802 continue; 2803 } 2804 2805 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2806 &val); 2807 if (ret) { 2808 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2809 ret); 2810 continue; 2811 } 2812 2813 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2814 return 0; 2815 } 2816 2817 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2818 ath10k_warn(ar, "refusing cold reset as requested\n"); 2819 return -EPERM; 2820 } 2821 2822 ret = ath10k_pci_cold_reset(ar); 2823 if (ret) { 2824 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2825 return ret; 2826 } 2827 2828 ret = ath10k_pci_wait_for_target_init(ar); 2829 if (ret) { 2830 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2831 ret); 2832 return ret; 2833 } 2834 2835 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2836 2837 return 0; 2838 } 2839 2840 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2841 { 2842 int ret; 2843 2844 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2845 2846 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2847 2848 ret = ath10k_pci_cold_reset(ar); 2849 if (ret) { 2850 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2851 return ret; 2852 } 2853 2854 ret = ath10k_pci_wait_for_target_init(ar); 2855 if (ret) { 2856 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2857 ret); 2858 return ret; 2859 } 2860 2861 ret = ath10k_pci_warm_reset(ar); 2862 if (ret) { 2863 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2864 return ret; 2865 } 2866 2867 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2868 2869 return 0; 2870 } 2871 2872 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2873 { 2874 int ret; 2875 2876 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2877 2878 ret = ath10k_pci_cold_reset(ar); 2879 if (ret) { 2880 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2881 return ret; 2882 } 2883 2884 ret = ath10k_pci_wait_for_target_init(ar); 2885 if (ret) { 2886 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2887 ret); 2888 return ret; 2889 } 2890 2891 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2892 2893 return 0; 2894 } 2895 2896 static int ath10k_pci_chip_reset(struct ath10k *ar) 2897 { 2898 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2899 2900 if (WARN_ON(!ar_pci->pci_hard_reset)) 2901 return -ENOTSUPP; 2902 2903 return ar_pci->pci_hard_reset(ar); 2904 } 2905 2906 static int ath10k_pci_hif_power_up(struct ath10k *ar, 2907 enum ath10k_firmware_mode fw_mode) 2908 { 2909 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2910 int ret; 2911 2912 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2913 2914 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2915 &ar_pci->link_ctl); 2916 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2917 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2918 2919 /* 2920 * Bring the target up cleanly. 2921 * 2922 * The target may be in an undefined state with an AUX-powered Target 2923 * and a Host in WoW mode. If the Host crashes, loses power, or is 2924 * restarted (without unloading the driver) then the Target is left 2925 * (aux) powered and running. On a subsequent driver load, the Target 2926 * is in an unexpected state. We try to catch that here in order to 2927 * reset the Target and retry the probe. 2928 */ 2929 ret = ath10k_pci_chip_reset(ar); 2930 if (ret) { 2931 if (ath10k_pci_has_fw_crashed(ar)) { 2932 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2933 ath10k_pci_fw_crashed_clear(ar); 2934 ath10k_pci_fw_crashed_dump(ar); 2935 } 2936 2937 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2938 goto err_sleep; 2939 } 2940 2941 ret = ath10k_pci_init_pipes(ar); 2942 if (ret) { 2943 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2944 goto err_sleep; 2945 } 2946 2947 ret = ath10k_pci_init_config(ar); 2948 if (ret) { 2949 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2950 goto err_ce; 2951 } 2952 2953 ret = ath10k_pci_wake_target_cpu(ar); 2954 if (ret) { 2955 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2956 goto err_ce; 2957 } 2958 2959 return 0; 2960 2961 err_ce: 2962 ath10k_pci_ce_deinit(ar); 2963 2964 err_sleep: 2965 return ret; 2966 } 2967 2968 void ath10k_pci_hif_power_down(struct ath10k *ar) 2969 { 2970 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2971 2972 /* Currently hif_power_up performs effectively a reset and hif_stop 2973 * resets the chip as well so there's no point in resetting here. 2974 */ 2975 } 2976 2977 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2978 { 2979 /* Nothing to do; the important stuff is in the driver suspend. */ 2980 return 0; 2981 } 2982 2983 #ifdef CONFIG_PM 2984 static int ath10k_pci_suspend(struct ath10k *ar) 2985 { 2986 /* The grace timer can still be counting down and ar->ps_awake be true. 2987 * It is known that the device may be asleep after resuming regardless 2988 * of the SoC powersave state before suspending. Hence make sure the 2989 * device is asleep before proceeding. 2990 */ 2991 ath10k_pci_sleep_sync(ar); 2992 2993 return 0; 2994 } 2995 #endif 2996 2997 static int ath10k_pci_hif_resume(struct ath10k *ar) 2998 { 2999 /* Nothing to do; the important stuff is in the driver resume. */ 3000 return 0; 3001 } 3002 3003 #ifdef CONFIG_PM 3004 static int ath10k_pci_resume(struct ath10k *ar) 3005 { 3006 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3007 struct pci_dev *pdev = ar_pci->pdev; 3008 u32 val; 3009 int ret = 0; 3010 3011 ret = ath10k_pci_force_wake(ar); 3012 if (ret) { 3013 ath10k_err(ar, "failed to wake up target: %d\n", ret); 3014 return ret; 3015 } 3016 3017 /* Suspend/Resume resets the PCI configuration space, so we have to 3018 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 3019 * from interfering with C3 CPU state. pci_restore_state won't help 3020 * here since it only restores the first 64 bytes pci config header. 3021 */ 3022 pci_read_config_dword(pdev, 0x40, &val); 3023 if ((val & 0x0000ff00) != 0) 3024 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 3025 3026 return ret; 3027 } 3028 #endif 3029 3030 static bool ath10k_pci_validate_cal(void *data, size_t size) 3031 { 3032 __le16 *cal_words = data; 3033 u16 checksum = 0; 3034 size_t i; 3035 3036 if (size % 2 != 0) 3037 return false; 3038 3039 for (i = 0; i < size / 2; i++) 3040 checksum ^= le16_to_cpu(cal_words[i]); 3041 3042 return checksum == 0xffff; 3043 } 3044 3045 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 3046 { 3047 /* Enable SI clock */ 3048 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 3049 3050 /* Configure GPIOs for I2C operation */ 3051 ath10k_pci_write32(ar, 3052 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 3053 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 3054 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 3055 GPIO_PIN0_CONFIG) | 3056 SM(1, GPIO_PIN0_PAD_PULL)); 3057 3058 ath10k_pci_write32(ar, 3059 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 3060 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 3061 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 3062 SM(1, GPIO_PIN0_PAD_PULL)); 3063 3064 ath10k_pci_write32(ar, 3065 GPIO_BASE_ADDRESS + 3066 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 3067 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 3068 3069 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 3070 ath10k_pci_write32(ar, 3071 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 3072 SM(1, SI_CONFIG_ERR_INT) | 3073 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 3074 SM(1, SI_CONFIG_I2C) | 3075 SM(1, SI_CONFIG_POS_SAMPLE) | 3076 SM(1, SI_CONFIG_INACTIVE_DATA) | 3077 SM(1, SI_CONFIG_INACTIVE_CLK) | 3078 SM(8, SI_CONFIG_DIVIDER)); 3079 } 3080 3081 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 3082 { 3083 u32 reg; 3084 int wait_limit; 3085 3086 /* set device select byte and for the read operation */ 3087 reg = QCA9887_EEPROM_SELECT_READ | 3088 SM(addr, QCA9887_EEPROM_ADDR_LO) | 3089 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 3090 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 3091 3092 /* write transmit data, transfer length, and START bit */ 3093 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 3094 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 3095 SM(4, SI_CS_TX_CNT)); 3096 3097 /* wait max 1 sec */ 3098 wait_limit = 100000; 3099 3100 /* wait for SI_CS_DONE_INT */ 3101 do { 3102 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 3103 if (MS(reg, SI_CS_DONE_INT)) 3104 break; 3105 3106 wait_limit--; 3107 udelay(10); 3108 } while (wait_limit > 0); 3109 3110 if (!MS(reg, SI_CS_DONE_INT)) { 3111 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 3112 addr); 3113 return -ETIMEDOUT; 3114 } 3115 3116 /* clear SI_CS_DONE_INT */ 3117 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 3118 3119 if (MS(reg, SI_CS_DONE_ERR)) { 3120 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 3121 return -EIO; 3122 } 3123 3124 /* extract receive data */ 3125 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 3126 *out = reg; 3127 3128 return 0; 3129 } 3130 3131 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 3132 size_t *data_len) 3133 { 3134 u8 *caldata = NULL; 3135 size_t calsize, i; 3136 int ret; 3137 3138 if (!QCA_REV_9887(ar)) 3139 return -EOPNOTSUPP; 3140 3141 calsize = ar->hw_params.cal_data_len; 3142 caldata = kmalloc(calsize, GFP_KERNEL); 3143 if (!caldata) 3144 return -ENOMEM; 3145 3146 ath10k_pci_enable_eeprom(ar); 3147 3148 for (i = 0; i < calsize; i++) { 3149 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 3150 if (ret) 3151 goto err_free; 3152 } 3153 3154 if (!ath10k_pci_validate_cal(caldata, calsize)) 3155 goto err_free; 3156 3157 *data = caldata; 3158 *data_len = calsize; 3159 3160 return 0; 3161 3162 err_free: 3163 kfree(caldata); 3164 3165 return -EINVAL; 3166 } 3167 3168 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 3169 .tx_sg = ath10k_pci_hif_tx_sg, 3170 .diag_read = ath10k_pci_hif_diag_read, 3171 .diag_write = ath10k_pci_diag_write_mem, 3172 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 3173 .start = ath10k_pci_hif_start, 3174 .stop = ath10k_pci_hif_stop, 3175 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 3176 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 3177 .send_complete_check = ath10k_pci_hif_send_complete_check, 3178 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 3179 .power_up = ath10k_pci_hif_power_up, 3180 .power_down = ath10k_pci_hif_power_down, 3181 .read32 = ath10k_pci_read32, 3182 .write32 = ath10k_pci_write32, 3183 .suspend = ath10k_pci_hif_suspend, 3184 .resume = ath10k_pci_hif_resume, 3185 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 3186 }; 3187 3188 /* 3189 * Top-level interrupt handler for all PCI interrupts from a Target. 3190 * When a block of MSI interrupts is allocated, this top-level handler 3191 * is not used; instead, we directly call the correct sub-handler. 3192 */ 3193 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 3194 { 3195 struct ath10k *ar = arg; 3196 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3197 int ret; 3198 3199 if (ath10k_pci_has_device_gone(ar)) 3200 return IRQ_NONE; 3201 3202 ret = ath10k_pci_force_wake(ar); 3203 if (ret) { 3204 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 3205 return IRQ_NONE; 3206 } 3207 3208 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 3209 !ath10k_pci_irq_pending(ar)) 3210 return IRQ_NONE; 3211 3212 ath10k_pci_disable_and_clear_legacy_irq(ar); 3213 ath10k_pci_irq_msi_fw_mask(ar); 3214 napi_schedule(&ar->napi); 3215 3216 return IRQ_HANDLED; 3217 } 3218 3219 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 3220 { 3221 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 3222 int done = 0; 3223 3224 if (ath10k_pci_has_fw_crashed(ar)) { 3225 ath10k_pci_fw_crashed_clear(ar); 3226 ath10k_pci_fw_crashed_dump(ar); 3227 napi_complete(ctx); 3228 return done; 3229 } 3230 3231 ath10k_ce_per_engine_service_any(ar); 3232 3233 done = ath10k_htt_txrx_compl_task(ar, budget); 3234 3235 if (done < budget) { 3236 napi_complete_done(ctx, done); 3237 /* In case of MSI, it is possible that interrupts are received 3238 * while NAPI poll is inprogress. So pending interrupts that are 3239 * received after processing all copy engine pipes by NAPI poll 3240 * will not be handled again. This is causing failure to 3241 * complete boot sequence in x86 platform. So before enabling 3242 * interrupts safer to check for pending interrupts for 3243 * immediate servicing. 3244 */ 3245 if (ath10k_ce_interrupt_summary(ar)) { 3246 napi_reschedule(ctx); 3247 goto out; 3248 } 3249 ath10k_pci_enable_legacy_irq(ar); 3250 ath10k_pci_irq_msi_fw_unmask(ar); 3251 } 3252 3253 out: 3254 return done; 3255 } 3256 3257 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 3258 { 3259 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3260 int ret; 3261 3262 ret = request_irq(ar_pci->pdev->irq, 3263 ath10k_pci_interrupt_handler, 3264 IRQF_SHARED, "ath10k_pci", ar); 3265 if (ret) { 3266 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 3267 ar_pci->pdev->irq, ret); 3268 return ret; 3269 } 3270 3271 return 0; 3272 } 3273 3274 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 3275 { 3276 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3277 int ret; 3278 3279 ret = request_irq(ar_pci->pdev->irq, 3280 ath10k_pci_interrupt_handler, 3281 IRQF_SHARED, "ath10k_pci", ar); 3282 if (ret) { 3283 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 3284 ar_pci->pdev->irq, ret); 3285 return ret; 3286 } 3287 3288 return 0; 3289 } 3290 3291 static int ath10k_pci_request_irq(struct ath10k *ar) 3292 { 3293 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3294 3295 switch (ar_pci->oper_irq_mode) { 3296 case ATH10K_PCI_IRQ_LEGACY: 3297 return ath10k_pci_request_irq_legacy(ar); 3298 case ATH10K_PCI_IRQ_MSI: 3299 return ath10k_pci_request_irq_msi(ar); 3300 default: 3301 return -EINVAL; 3302 } 3303 } 3304 3305 static void ath10k_pci_free_irq(struct ath10k *ar) 3306 { 3307 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3308 3309 free_irq(ar_pci->pdev->irq, ar); 3310 } 3311 3312 void ath10k_pci_init_napi(struct ath10k *ar) 3313 { 3314 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); 3315 } 3316 3317 static int ath10k_pci_init_irq(struct ath10k *ar) 3318 { 3319 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3320 int ret; 3321 3322 ath10k_pci_init_napi(ar); 3323 3324 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 3325 ath10k_info(ar, "limiting irq mode to: %d\n", 3326 ath10k_pci_irq_mode); 3327 3328 /* Try MSI */ 3329 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 3330 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 3331 ret = pci_enable_msi(ar_pci->pdev); 3332 if (ret == 0) 3333 return 0; 3334 3335 /* MHI failed, try legacy irq next */ 3336 } 3337 3338 /* Try legacy irq 3339 * 3340 * A potential race occurs here: The CORE_BASE write 3341 * depends on target correctly decoding AXI address but 3342 * host won't know when target writes BAR to CORE_CTRL. 3343 * This write might get lost if target has NOT written BAR. 3344 * For now, fix the race by repeating the write in below 3345 * synchronization checking. 3346 */ 3347 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 3348 3349 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3350 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3351 3352 return 0; 3353 } 3354 3355 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 3356 { 3357 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3358 0); 3359 } 3360 3361 static int ath10k_pci_deinit_irq(struct ath10k *ar) 3362 { 3363 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3364 3365 switch (ar_pci->oper_irq_mode) { 3366 case ATH10K_PCI_IRQ_LEGACY: 3367 ath10k_pci_deinit_irq_legacy(ar); 3368 break; 3369 default: 3370 pci_disable_msi(ar_pci->pdev); 3371 break; 3372 } 3373 3374 return 0; 3375 } 3376 3377 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 3378 { 3379 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3380 unsigned long timeout; 3381 u32 val; 3382 3383 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 3384 3385 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 3386 3387 do { 3388 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 3389 3390 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 3391 val); 3392 3393 /* target should never return this */ 3394 if (val == 0xffffffff) 3395 continue; 3396 3397 /* the device has crashed so don't bother trying anymore */ 3398 if (val & FW_IND_EVENT_PENDING) 3399 break; 3400 3401 if (val & FW_IND_INITIALIZED) 3402 break; 3403 3404 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 3405 /* Fix potential race by repeating CORE_BASE writes */ 3406 ath10k_pci_enable_legacy_irq(ar); 3407 3408 mdelay(10); 3409 } while (time_before(jiffies, timeout)); 3410 3411 ath10k_pci_disable_and_clear_legacy_irq(ar); 3412 ath10k_pci_irq_msi_fw_mask(ar); 3413 3414 if (val == 0xffffffff) { 3415 ath10k_err(ar, "failed to read device register, device is gone\n"); 3416 return -EIO; 3417 } 3418 3419 if (val & FW_IND_EVENT_PENDING) { 3420 ath10k_warn(ar, "device has crashed during init\n"); 3421 return -ECOMM; 3422 } 3423 3424 if (!(val & FW_IND_INITIALIZED)) { 3425 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3426 val); 3427 return -ETIMEDOUT; 3428 } 3429 3430 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3431 return 0; 3432 } 3433 3434 static int ath10k_pci_cold_reset(struct ath10k *ar) 3435 { 3436 u32 val; 3437 3438 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3439 3440 spin_lock_bh(&ar->data_lock); 3441 3442 ar->stats.fw_cold_reset_counter++; 3443 3444 spin_unlock_bh(&ar->data_lock); 3445 3446 /* Put Target, including PCIe, into RESET. */ 3447 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3448 val |= 1; 3449 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3450 3451 /* After writing into SOC_GLOBAL_RESET to put device into 3452 * reset and pulling out of reset pcie may not be stable 3453 * for any immediate pcie register access and cause bus error, 3454 * add delay before any pcie access request to fix this issue. 3455 */ 3456 msleep(20); 3457 3458 /* Pull Target, including PCIe, out of RESET. */ 3459 val &= ~1; 3460 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3461 3462 msleep(20); 3463 3464 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3465 3466 return 0; 3467 } 3468 3469 static int ath10k_pci_claim(struct ath10k *ar) 3470 { 3471 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3472 struct pci_dev *pdev = ar_pci->pdev; 3473 int ret; 3474 3475 pci_set_drvdata(pdev, ar); 3476 3477 ret = pci_enable_device(pdev); 3478 if (ret) { 3479 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3480 return ret; 3481 } 3482 3483 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3484 if (ret) { 3485 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3486 ret); 3487 goto err_device; 3488 } 3489 3490 /* Target expects 32 bit DMA. Enforce it. */ 3491 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3492 if (ret) { 3493 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3494 goto err_region; 3495 } 3496 3497 pci_set_master(pdev); 3498 3499 #if defined(__FreeBSD__) 3500 linuxkpi_pcim_want_to_use_bus_functions(pdev); 3501 #endif 3502 3503 /* Arrange for access to Target SoC registers. */ 3504 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3505 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3506 if (!ar_pci->mem) { 3507 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3508 ret = -EIO; 3509 goto err_region; 3510 } 3511 3512 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3513 return 0; 3514 3515 err_region: 3516 pci_release_region(pdev, BAR_NUM); 3517 3518 err_device: 3519 pci_disable_device(pdev); 3520 3521 return ret; 3522 } 3523 3524 static void ath10k_pci_release(struct ath10k *ar) 3525 { 3526 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3527 struct pci_dev *pdev = ar_pci->pdev; 3528 3529 pci_iounmap(pdev, ar_pci->mem); 3530 pci_release_region(pdev, BAR_NUM); 3531 pci_disable_device(pdev); 3532 } 3533 3534 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3535 { 3536 const struct ath10k_pci_supp_chip *supp_chip; 3537 int i; 3538 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3539 3540 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3541 supp_chip = &ath10k_pci_supp_chips[i]; 3542 3543 if (supp_chip->dev_id == dev_id && 3544 supp_chip->rev_id == rev_id) 3545 return true; 3546 } 3547 3548 return false; 3549 } 3550 3551 int ath10k_pci_setup_resource(struct ath10k *ar) 3552 { 3553 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3554 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3555 int ret; 3556 3557 spin_lock_init(&ce->ce_lock); 3558 spin_lock_init(&ar_pci->ps_lock); 3559 mutex_init(&ar_pci->ce_diag_mutex); 3560 3561 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); 3562 3563 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3564 3565 ar_pci->attr = kmemdup(pci_host_ce_config_wlan, 3566 sizeof(pci_host_ce_config_wlan), 3567 GFP_KERNEL); 3568 if (!ar_pci->attr) 3569 return -ENOMEM; 3570 3571 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, 3572 sizeof(pci_target_ce_config_wlan), 3573 GFP_KERNEL); 3574 if (!ar_pci->pipe_config) { 3575 ret = -ENOMEM; 3576 goto err_free_attr; 3577 } 3578 3579 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, 3580 sizeof(pci_target_service_to_ce_map_wlan), 3581 GFP_KERNEL); 3582 if (!ar_pci->serv_to_pipe) { 3583 ret = -ENOMEM; 3584 goto err_free_pipe_config; 3585 } 3586 3587 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3588 ath10k_pci_override_ce_config(ar); 3589 3590 ret = ath10k_pci_alloc_pipes(ar); 3591 if (ret) { 3592 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3593 ret); 3594 goto err_free_serv_to_pipe; 3595 } 3596 3597 return 0; 3598 3599 err_free_serv_to_pipe: 3600 kfree(ar_pci->serv_to_pipe); 3601 err_free_pipe_config: 3602 kfree(ar_pci->pipe_config); 3603 err_free_attr: 3604 kfree(ar_pci->attr); 3605 return ret; 3606 } 3607 3608 void ath10k_pci_release_resource(struct ath10k *ar) 3609 { 3610 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3611 3612 ath10k_pci_rx_retry_sync(ar); 3613 netif_napi_del(&ar->napi); 3614 ath10k_pci_ce_deinit(ar); 3615 ath10k_pci_free_pipes(ar); 3616 kfree(ar_pci->attr); 3617 kfree(ar_pci->pipe_config); 3618 kfree(ar_pci->serv_to_pipe); 3619 } 3620 3621 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3622 .read32 = ath10k_bus_pci_read32, 3623 .write32 = ath10k_bus_pci_write32, 3624 .get_num_banks = ath10k_pci_get_num_banks, 3625 }; 3626 3627 static int ath10k_pci_probe(struct pci_dev *pdev, 3628 const struct pci_device_id *pci_dev) 3629 { 3630 int ret = 0; 3631 struct ath10k *ar; 3632 struct ath10k_pci *ar_pci; 3633 enum ath10k_hw_rev hw_rev; 3634 struct ath10k_bus_params bus_params = {}; 3635 bool pci_ps, is_qca988x = false; 3636 int (*pci_soft_reset)(struct ath10k *ar); 3637 int (*pci_hard_reset)(struct ath10k *ar); 3638 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3639 3640 switch (pci_dev->device) { 3641 case QCA988X_2_0_DEVICE_ID_UBNT: 3642 case QCA988X_2_0_DEVICE_ID: 3643 hw_rev = ATH10K_HW_QCA988X; 3644 pci_ps = false; 3645 is_qca988x = true; 3646 pci_soft_reset = ath10k_pci_warm_reset; 3647 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3648 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3649 break; 3650 case QCA9887_1_0_DEVICE_ID: 3651 hw_rev = ATH10K_HW_QCA9887; 3652 pci_ps = false; 3653 pci_soft_reset = ath10k_pci_warm_reset; 3654 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3655 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3656 break; 3657 case QCA6164_2_1_DEVICE_ID: 3658 case QCA6174_2_1_DEVICE_ID: 3659 hw_rev = ATH10K_HW_QCA6174; 3660 pci_ps = true; 3661 pci_soft_reset = ath10k_pci_warm_reset; 3662 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3663 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3664 break; 3665 case QCA99X0_2_0_DEVICE_ID: 3666 hw_rev = ATH10K_HW_QCA99X0; 3667 pci_ps = false; 3668 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3669 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3670 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3671 break; 3672 case QCA9984_1_0_DEVICE_ID: 3673 hw_rev = ATH10K_HW_QCA9984; 3674 pci_ps = false; 3675 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3676 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3677 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3678 break; 3679 case QCA9888_2_0_DEVICE_ID: 3680 hw_rev = ATH10K_HW_QCA9888; 3681 pci_ps = false; 3682 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3683 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3684 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3685 break; 3686 case QCA9377_1_0_DEVICE_ID: 3687 hw_rev = ATH10K_HW_QCA9377; 3688 pci_ps = true; 3689 pci_soft_reset = ath10k_pci_warm_reset; 3690 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3691 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3692 break; 3693 default: 3694 WARN_ON(1); 3695 return -ENOTSUPP; 3696 } 3697 3698 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3699 hw_rev, &ath10k_pci_hif_ops); 3700 if (!ar) { 3701 dev_err(&pdev->dev, "failed to allocate core\n"); 3702 return -ENOMEM; 3703 } 3704 3705 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3706 pdev->vendor, pdev->device, 3707 pdev->subsystem_vendor, pdev->subsystem_device); 3708 3709 ar_pci = ath10k_pci_priv(ar); 3710 ar_pci->pdev = pdev; 3711 ar_pci->dev = &pdev->dev; 3712 ar_pci->ar = ar; 3713 ar->dev_id = pci_dev->device; 3714 ar_pci->pci_ps = pci_ps; 3715 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3716 ar_pci->pci_soft_reset = pci_soft_reset; 3717 ar_pci->pci_hard_reset = pci_hard_reset; 3718 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3719 ar->ce_priv = &ar_pci->ce; 3720 3721 ar->id.vendor = pdev->vendor; 3722 ar->id.device = pdev->device; 3723 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3724 ar->id.subsystem_device = pdev->subsystem_device; 3725 3726 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3727 3728 ret = ath10k_pci_setup_resource(ar); 3729 if (ret) { 3730 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3731 goto err_core_destroy; 3732 } 3733 3734 ret = ath10k_pci_claim(ar); 3735 if (ret) { 3736 ath10k_err(ar, "failed to claim device: %d\n", ret); 3737 goto err_free_pipes; 3738 } 3739 3740 ret = ath10k_pci_force_wake(ar); 3741 if (ret) { 3742 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3743 goto err_sleep; 3744 } 3745 3746 ath10k_pci_ce_deinit(ar); 3747 ath10k_pci_irq_disable(ar); 3748 3749 ret = ath10k_pci_init_irq(ar); 3750 if (ret) { 3751 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3752 goto err_sleep; 3753 } 3754 3755 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3756 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3757 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3758 3759 ret = ath10k_pci_request_irq(ar); 3760 if (ret) { 3761 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3762 goto err_deinit_irq; 3763 } 3764 3765 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 3766 bus_params.link_can_suspend = true; 3767 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that 3768 * fall off the bus during chip_reset. These chips have the same pci 3769 * device id as the QCA9880 BR4A or 2R4E. So that's why the check. 3770 */ 3771 if (is_qca988x) { 3772 bus_params.chip_id = 3773 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3774 if (bus_params.chip_id != 0xffffffff) { 3775 if (!ath10k_pci_chip_is_supported(pdev->device, 3776 bus_params.chip_id)) { 3777 ret = -ENODEV; 3778 goto err_unsupported; 3779 } 3780 } 3781 } 3782 3783 ret = ath10k_pci_chip_reset(ar); 3784 if (ret) { 3785 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3786 goto err_free_irq; 3787 } 3788 3789 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3790 if (bus_params.chip_id == 0xffffffff) { 3791 ret = -ENODEV; 3792 goto err_unsupported; 3793 } 3794 3795 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { 3796 ret = -ENODEV; 3797 goto err_unsupported; 3798 } 3799 3800 ret = ath10k_core_register(ar, &bus_params); 3801 if (ret) { 3802 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3803 goto err_free_irq; 3804 } 3805 3806 return 0; 3807 3808 err_unsupported: 3809 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3810 pdev->device, bus_params.chip_id); 3811 3812 err_free_irq: 3813 ath10k_pci_free_irq(ar); 3814 3815 err_deinit_irq: 3816 ath10k_pci_release_resource(ar); 3817 3818 err_sleep: 3819 ath10k_pci_sleep_sync(ar); 3820 ath10k_pci_release(ar); 3821 3822 err_free_pipes: 3823 ath10k_pci_free_pipes(ar); 3824 3825 err_core_destroy: 3826 ath10k_core_destroy(ar); 3827 3828 return ret; 3829 } 3830 3831 static void ath10k_pci_remove(struct pci_dev *pdev) 3832 { 3833 struct ath10k *ar = pci_get_drvdata(pdev); 3834 3835 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3836 3837 if (!ar) 3838 return; 3839 3840 ath10k_core_unregister(ar); 3841 ath10k_pci_free_irq(ar); 3842 ath10k_pci_deinit_irq(ar); 3843 ath10k_pci_release_resource(ar); 3844 ath10k_pci_sleep_sync(ar); 3845 ath10k_pci_release(ar); 3846 ath10k_core_destroy(ar); 3847 } 3848 3849 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3850 3851 #ifdef CONFIG_PM 3852 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3853 { 3854 struct ath10k *ar = dev_get_drvdata(dev); 3855 int ret; 3856 3857 ret = ath10k_pci_suspend(ar); 3858 if (ret) 3859 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3860 3861 return ret; 3862 } 3863 3864 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3865 { 3866 struct ath10k *ar = dev_get_drvdata(dev); 3867 int ret; 3868 3869 ret = ath10k_pci_resume(ar); 3870 if (ret) 3871 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3872 3873 return ret; 3874 } 3875 3876 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3877 ath10k_pci_pm_suspend, 3878 ath10k_pci_pm_resume); 3879 #endif 3880 3881 static struct pci_driver ath10k_pci_driver = { 3882 .name = "ath10k_pci", 3883 .id_table = ath10k_pci_id_table, 3884 .probe = ath10k_pci_probe, 3885 .remove = ath10k_pci_remove, 3886 #ifdef CONFIG_PM 3887 .driver.pm = &ath10k_pci_pm_ops, 3888 #endif 3889 #if defined(__FreeBSD__) 3890 .bsddriver.name = KBUILD_MODNAME, 3891 /* Allow a possible native driver to attach. */ 3892 .bsd_probe_return = (BUS_PROBE_DEFAULT - 1), 3893 #endif 3894 }; 3895 3896 static int __init ath10k_pci_init(void) 3897 { 3898 int ret1, ret2; 3899 3900 ret1 = pci_register_driver(&ath10k_pci_driver); 3901 if (ret1) 3902 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3903 ret1); 3904 3905 ret2 = ath10k_ahb_init(); 3906 if (ret2) 3907 printk(KERN_ERR "ahb init failed: %d\n", ret2); 3908 3909 if (ret1 && ret2) 3910 return ret1; 3911 3912 /* registered to at least one bus */ 3913 return 0; 3914 } 3915 module_init(ath10k_pci_init); 3916 3917 static void __exit ath10k_pci_exit(void) 3918 { 3919 pci_unregister_driver(&ath10k_pci_driver); 3920 ath10k_ahb_exit(); 3921 } 3922 3923 module_exit(ath10k_pci_exit); 3924 3925 MODULE_AUTHOR("Qualcomm Atheros"); 3926 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3927 MODULE_LICENSE("Dual BSD/GPL"); 3928 #if defined(__FreeBSD__) 3929 MODULE_VERSION(ath10k_pci, 1); 3930 MODULE_DEPEND(ath10k_pci, linuxkpi, 1, 1, 1); 3931 MODULE_DEPEND(ath10k_pci, linuxkpi_wlan, 1, 1, 1); 3932 MODULE_DEPEND(ath10k_pci, athk_common, 1, 1, 1); 3933 #ifdef CONFIG_ATH10K_DEBUGFS 3934 MODULE_DEPEND(ath10k_pci, debugfs, 1, 1, 1); 3935 #endif 3936 #endif 3937 3938 /* QCA988x 2.0 firmware files */ 3939 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3940 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3941 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3942 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3943 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3944 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3945 3946 /* QCA9887 1.0 firmware files */ 3947 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3948 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3949 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3950 3951 /* QCA6174 2.1 firmware files */ 3952 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3953 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3954 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3955 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3956 3957 /* QCA6174 3.1 firmware files */ 3958 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3959 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3960 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3961 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3962 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3963 3964 /* QCA9377 1.0 firmware files */ 3965 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3966 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3967 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3968