1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7 #if defined(__FreeBSD__) 8 #define LINUXKPI_PARAM_PREFIX ath10k_pci_ 9 #endif 10 11 #include <linux/pci.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/spinlock.h> 15 #include <linux/bitops.h> 16 #if defined(__FreeBSD__) 17 #include <linux/delay.h> 18 #endif 19 20 #include "core.h" 21 #include "debug.h" 22 #include "coredump.h" 23 24 #include "targaddrs.h" 25 #include "bmi.h" 26 27 #include "hif.h" 28 #include "htc.h" 29 30 #include "ce.h" 31 #include "pci.h" 32 33 enum ath10k_pci_reset_mode { 34 ATH10K_PCI_RESET_AUTO = 0, 35 ATH10K_PCI_RESET_WARM_ONLY = 1, 36 }; 37 38 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 39 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 40 41 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 42 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 43 44 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 45 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 46 47 /* how long wait to wait for target to initialise, in ms */ 48 #define ATH10K_PCI_TARGET_WAIT 3000 49 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 50 51 /* Maximum number of bytes that can be handled atomically by 52 * diag read and write. 53 */ 54 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 55 56 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 57 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c 58 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 59 60 static const struct pci_device_id ath10k_pci_id_table[] = { 61 /* PCI-E QCA988X V2 (Ubiquiti branded) */ 62 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, 63 64 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 65 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 66 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 67 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 68 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 69 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 70 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 71 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 72 {0} 73 }; 74 75 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 76 /* QCA988X pre 2.0 chips are not supported because they need some nasty 77 * hacks. ath10k doesn't have them and these devices crash horribly 78 * because of that. 79 */ 80 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, 81 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 82 83 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 84 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 85 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 86 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 88 89 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 90 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 91 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 94 95 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 96 97 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 98 99 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 100 101 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 102 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 103 104 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 105 }; 106 107 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 108 static int ath10k_pci_cold_reset(struct ath10k *ar); 109 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 110 static int ath10k_pci_init_irq(struct ath10k *ar); 111 static int ath10k_pci_deinit_irq(struct ath10k *ar); 112 static int ath10k_pci_request_irq(struct ath10k *ar); 113 static void ath10k_pci_free_irq(struct ath10k *ar); 114 static int ath10k_pci_bmi_wait(struct ath10k *ar, 115 struct ath10k_ce_pipe *tx_pipe, 116 struct ath10k_ce_pipe *rx_pipe, 117 struct bmi_xfer *xfer); 118 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 119 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 120 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 121 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 122 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 123 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 124 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 125 126 static const struct ce_attr pci_host_ce_config_wlan[] = { 127 /* CE0: host->target HTC control and raw streams */ 128 { 129 .flags = CE_ATTR_FLAGS, 130 .src_nentries = 16, 131 .src_sz_max = 256, 132 .dest_nentries = 0, 133 .send_cb = ath10k_pci_htc_tx_cb, 134 }, 135 136 /* CE1: target->host HTT + HTC control */ 137 { 138 .flags = CE_ATTR_FLAGS, 139 .src_nentries = 0, 140 .src_sz_max = 2048, 141 .dest_nentries = 512, 142 .recv_cb = ath10k_pci_htt_htc_rx_cb, 143 }, 144 145 /* CE2: target->host WMI */ 146 { 147 .flags = CE_ATTR_FLAGS, 148 .src_nentries = 0, 149 .src_sz_max = 2048, 150 .dest_nentries = 128, 151 .recv_cb = ath10k_pci_htc_rx_cb, 152 }, 153 154 /* CE3: host->target WMI */ 155 { 156 .flags = CE_ATTR_FLAGS, 157 .src_nentries = 32, 158 .src_sz_max = 2048, 159 .dest_nentries = 0, 160 .send_cb = ath10k_pci_htc_tx_cb, 161 }, 162 163 /* CE4: host->target HTT */ 164 { 165 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 166 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 167 .src_sz_max = 256, 168 .dest_nentries = 0, 169 .send_cb = ath10k_pci_htt_tx_cb, 170 }, 171 172 /* CE5: target->host HTT (HIF->HTT) */ 173 { 174 .flags = CE_ATTR_FLAGS, 175 .src_nentries = 0, 176 .src_sz_max = 512, 177 .dest_nentries = 512, 178 .recv_cb = ath10k_pci_htt_rx_cb, 179 }, 180 181 /* CE6: target autonomous hif_memcpy */ 182 { 183 .flags = CE_ATTR_FLAGS, 184 .src_nentries = 0, 185 .src_sz_max = 0, 186 .dest_nentries = 0, 187 }, 188 189 /* CE7: ce_diag, the Diagnostic Window */ 190 { 191 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, 192 .src_nentries = 2, 193 .src_sz_max = DIAG_TRANSFER_LIMIT, 194 .dest_nentries = 2, 195 }, 196 197 /* CE8: target->host pktlog */ 198 { 199 .flags = CE_ATTR_FLAGS, 200 .src_nentries = 0, 201 .src_sz_max = 2048, 202 .dest_nentries = 128, 203 .recv_cb = ath10k_pci_pktlog_rx_cb, 204 }, 205 206 /* CE9 target autonomous qcache memcpy */ 207 { 208 .flags = CE_ATTR_FLAGS, 209 .src_nentries = 0, 210 .src_sz_max = 0, 211 .dest_nentries = 0, 212 }, 213 214 /* CE10: target autonomous hif memcpy */ 215 { 216 .flags = CE_ATTR_FLAGS, 217 .src_nentries = 0, 218 .src_sz_max = 0, 219 .dest_nentries = 0, 220 }, 221 222 /* CE11: target autonomous hif memcpy */ 223 { 224 .flags = CE_ATTR_FLAGS, 225 .src_nentries = 0, 226 .src_sz_max = 0, 227 .dest_nentries = 0, 228 }, 229 }; 230 231 /* Target firmware's Copy Engine configuration. */ 232 static const struct ce_pipe_config pci_target_ce_config_wlan[] = { 233 /* CE0: host->target HTC control and raw streams */ 234 { 235 .pipenum = __cpu_to_le32(0), 236 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 237 .nentries = __cpu_to_le32(32), 238 .nbytes_max = __cpu_to_le32(256), 239 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 240 .reserved = __cpu_to_le32(0), 241 }, 242 243 /* CE1: target->host HTT + HTC control */ 244 { 245 .pipenum = __cpu_to_le32(1), 246 .pipedir = __cpu_to_le32(PIPEDIR_IN), 247 .nentries = __cpu_to_le32(32), 248 .nbytes_max = __cpu_to_le32(2048), 249 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 250 .reserved = __cpu_to_le32(0), 251 }, 252 253 /* CE2: target->host WMI */ 254 { 255 .pipenum = __cpu_to_le32(2), 256 .pipedir = __cpu_to_le32(PIPEDIR_IN), 257 .nentries = __cpu_to_le32(64), 258 .nbytes_max = __cpu_to_le32(2048), 259 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 260 .reserved = __cpu_to_le32(0), 261 }, 262 263 /* CE3: host->target WMI */ 264 { 265 .pipenum = __cpu_to_le32(3), 266 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 267 .nentries = __cpu_to_le32(32), 268 .nbytes_max = __cpu_to_le32(2048), 269 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 270 .reserved = __cpu_to_le32(0), 271 }, 272 273 /* CE4: host->target HTT */ 274 { 275 .pipenum = __cpu_to_le32(4), 276 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 277 .nentries = __cpu_to_le32(256), 278 .nbytes_max = __cpu_to_le32(256), 279 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 280 .reserved = __cpu_to_le32(0), 281 }, 282 283 /* NB: 50% of src nentries, since tx has 2 frags */ 284 285 /* CE5: target->host HTT (HIF->HTT) */ 286 { 287 .pipenum = __cpu_to_le32(5), 288 .pipedir = __cpu_to_le32(PIPEDIR_IN), 289 .nentries = __cpu_to_le32(32), 290 .nbytes_max = __cpu_to_le32(512), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE6: Reserved for target autonomous hif_memcpy */ 296 { 297 .pipenum = __cpu_to_le32(6), 298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 299 .nentries = __cpu_to_le32(32), 300 .nbytes_max = __cpu_to_le32(4096), 301 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE7 used only by Host */ 306 { 307 .pipenum = __cpu_to_le32(7), 308 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 309 .nentries = __cpu_to_le32(0), 310 .nbytes_max = __cpu_to_le32(0), 311 .flags = __cpu_to_le32(0), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE8 target->host packtlog */ 316 { 317 .pipenum = __cpu_to_le32(8), 318 .pipedir = __cpu_to_le32(PIPEDIR_IN), 319 .nentries = __cpu_to_le32(64), 320 .nbytes_max = __cpu_to_le32(2048), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* CE9 target autonomous qcache memcpy */ 326 { 327 .pipenum = __cpu_to_le32(9), 328 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 329 .nentries = __cpu_to_le32(32), 330 .nbytes_max = __cpu_to_le32(2048), 331 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 332 .reserved = __cpu_to_le32(0), 333 }, 334 335 /* It not necessary to send target wlan configuration for CE10 & CE11 336 * as these CEs are not actively used in target. 337 */ 338 }; 339 340 /* 341 * Map from service/endpoint to Copy Engine. 342 * This table is derived from the CE_PCI TABLE, above. 343 * It is passed to the Target at startup for use by firmware. 344 */ 345 static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = { 346 { 347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 349 __cpu_to_le32(3), 350 }, 351 { 352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 354 __cpu_to_le32(2), 355 }, 356 { 357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 359 __cpu_to_le32(3), 360 }, 361 { 362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 364 __cpu_to_le32(2), 365 }, 366 { 367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 369 __cpu_to_le32(3), 370 }, 371 { 372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 374 __cpu_to_le32(2), 375 }, 376 { 377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 379 __cpu_to_le32(3), 380 }, 381 { 382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 384 __cpu_to_le32(2), 385 }, 386 { 387 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 389 __cpu_to_le32(3), 390 }, 391 { 392 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 394 __cpu_to_le32(2), 395 }, 396 { 397 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 399 __cpu_to_le32(0), 400 }, 401 { 402 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 404 __cpu_to_le32(1), 405 }, 406 { /* not used */ 407 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 409 __cpu_to_le32(0), 410 }, 411 { /* not used */ 412 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 414 __cpu_to_le32(1), 415 }, 416 { 417 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 418 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 419 __cpu_to_le32(4), 420 }, 421 { 422 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 423 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 424 __cpu_to_le32(5), 425 }, 426 427 /* (Additions here) */ 428 429 { /* must be last */ 430 __cpu_to_le32(0), 431 __cpu_to_le32(0), 432 __cpu_to_le32(0), 433 }, 434 }; 435 436 static bool ath10k_pci_is_awake(struct ath10k *ar) 437 { 438 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 439 #if defined(__linux__) 440 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 441 RTC_STATE_ADDRESS); 442 #elif defined(__FreeBSD__) 443 u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + 444 RTC_STATE_ADDRESS); 445 #endif 446 447 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 448 } 449 450 static void __ath10k_pci_wake(struct ath10k *ar) 451 { 452 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 453 454 lockdep_assert_held(&ar_pci->ps_lock); 455 456 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 457 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 458 459 #if defined(__linux__) 460 iowrite32(PCIE_SOC_WAKE_V_MASK, 461 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 462 PCIE_SOC_WAKE_ADDRESS); 463 #elif defined(__FreeBSD__) 464 bus_write_4((struct resource *)ar_pci->mem, 465 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 466 PCIE_SOC_WAKE_V_MASK); 467 #endif 468 } 469 470 static void __ath10k_pci_sleep(struct ath10k *ar) 471 { 472 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 473 474 lockdep_assert_held(&ar_pci->ps_lock); 475 476 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 477 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 478 479 #if defined(__linux__) 480 iowrite32(PCIE_SOC_WAKE_RESET, 481 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 482 PCIE_SOC_WAKE_ADDRESS); 483 #elif defined(__FreeBSD__) 484 bus_write_4((struct resource *)ar_pci->mem, 485 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 486 PCIE_SOC_WAKE_RESET); 487 #endif 488 ar_pci->ps_awake = false; 489 } 490 491 static int ath10k_pci_wake_wait(struct ath10k *ar) 492 { 493 int tot_delay = 0; 494 int curr_delay = 5; 495 496 while (tot_delay < PCIE_WAKE_TIMEOUT) { 497 if (ath10k_pci_is_awake(ar)) { 498 if (tot_delay > PCIE_WAKE_LATE_US) 499 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 500 tot_delay / 1000); 501 return 0; 502 } 503 504 udelay(curr_delay); 505 tot_delay += curr_delay; 506 507 if (curr_delay < 50) 508 curr_delay += 5; 509 } 510 511 return -ETIMEDOUT; 512 } 513 514 static int ath10k_pci_force_wake(struct ath10k *ar) 515 { 516 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 517 unsigned long flags; 518 int ret = 0; 519 520 if (ar_pci->pci_ps) 521 return ret; 522 523 spin_lock_irqsave(&ar_pci->ps_lock, flags); 524 525 if (!ar_pci->ps_awake) { 526 #if defined(__linux__) 527 iowrite32(PCIE_SOC_WAKE_V_MASK, 528 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 529 PCIE_SOC_WAKE_ADDRESS); 530 #elif defined(__FreeBSD__) 531 bus_write_4((struct resource *)ar_pci->mem, 532 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 533 PCIE_SOC_WAKE_V_MASK); 534 #endif 535 536 ret = ath10k_pci_wake_wait(ar); 537 if (ret == 0) 538 ar_pci->ps_awake = true; 539 } 540 541 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 542 543 return ret; 544 } 545 546 static void ath10k_pci_force_sleep(struct ath10k *ar) 547 { 548 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 549 unsigned long flags; 550 551 spin_lock_irqsave(&ar_pci->ps_lock, flags); 552 553 #if defined(__linux__) 554 iowrite32(PCIE_SOC_WAKE_RESET, 555 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 556 PCIE_SOC_WAKE_ADDRESS); 557 #elif defined(__FreeBSD__) 558 bus_write_4((struct resource *)ar_pci->mem, 559 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, 560 PCIE_SOC_WAKE_RESET); 561 #endif 562 ar_pci->ps_awake = false; 563 564 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 565 } 566 567 static int ath10k_pci_wake(struct ath10k *ar) 568 { 569 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 570 unsigned long flags; 571 int ret = 0; 572 573 if (ar_pci->pci_ps == 0) 574 return ret; 575 576 spin_lock_irqsave(&ar_pci->ps_lock, flags); 577 578 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 579 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 580 581 /* This function can be called very frequently. To avoid excessive 582 * CPU stalls for MMIO reads use a cache var to hold the device state. 583 */ 584 if (!ar_pci->ps_awake) { 585 __ath10k_pci_wake(ar); 586 587 ret = ath10k_pci_wake_wait(ar); 588 if (ret == 0) 589 ar_pci->ps_awake = true; 590 } 591 592 if (ret == 0) { 593 ar_pci->ps_wake_refcount++; 594 WARN_ON(ar_pci->ps_wake_refcount == 0); 595 } 596 597 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 598 599 return ret; 600 } 601 602 static void ath10k_pci_sleep(struct ath10k *ar) 603 { 604 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 605 unsigned long flags; 606 607 if (ar_pci->pci_ps == 0) 608 return; 609 610 spin_lock_irqsave(&ar_pci->ps_lock, flags); 611 612 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 613 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 614 615 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 616 goto skip; 617 618 ar_pci->ps_wake_refcount--; 619 620 mod_timer(&ar_pci->ps_timer, jiffies + 621 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 622 623 skip: 624 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 625 } 626 627 static void ath10k_pci_ps_timer(struct timer_list *t) 628 { 629 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); 630 struct ath10k *ar = ar_pci->ar; 631 unsigned long flags; 632 633 spin_lock_irqsave(&ar_pci->ps_lock, flags); 634 635 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 636 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 637 638 if (ar_pci->ps_wake_refcount > 0) 639 goto skip; 640 641 __ath10k_pci_sleep(ar); 642 643 skip: 644 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 645 } 646 647 static void ath10k_pci_sleep_sync(struct ath10k *ar) 648 { 649 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 650 unsigned long flags; 651 652 if (ar_pci->pci_ps == 0) { 653 ath10k_pci_force_sleep(ar); 654 return; 655 } 656 657 del_timer_sync(&ar_pci->ps_timer); 658 659 spin_lock_irqsave(&ar_pci->ps_lock, flags); 660 WARN_ON(ar_pci->ps_wake_refcount > 0); 661 __ath10k_pci_sleep(ar); 662 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 663 } 664 665 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 666 { 667 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 668 int ret; 669 670 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 671 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 672 offset, offset + sizeof(value), ar_pci->mem_len); 673 return; 674 } 675 676 ret = ath10k_pci_wake(ar); 677 if (ret) { 678 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 679 value, offset, ret); 680 return; 681 } 682 683 #if defined(__linux__) 684 iowrite32(value, ar_pci->mem + offset); 685 #elif defined(__FreeBSD__) 686 bus_write_4((struct resource *)ar_pci->mem, offset, value); 687 #endif 688 ath10k_pci_sleep(ar); 689 } 690 691 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 692 { 693 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 694 u32 val; 695 int ret; 696 697 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 698 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 699 offset, offset + sizeof(val), ar_pci->mem_len); 700 return 0; 701 } 702 703 ret = ath10k_pci_wake(ar); 704 if (ret) { 705 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 706 offset, ret); 707 return 0xffffffff; 708 } 709 710 #if defined(__linux__) 711 val = ioread32(ar_pci->mem + offset); 712 #elif defined(__FreeBSD__) 713 val = bus_read_4((struct resource *)ar_pci->mem, offset); 714 #endif 715 ath10k_pci_sleep(ar); 716 717 return val; 718 } 719 720 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 721 { 722 struct ath10k_ce *ce = ath10k_ce_priv(ar); 723 724 ce->bus_ops->write32(ar, offset, value); 725 } 726 727 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 728 { 729 struct ath10k_ce *ce = ath10k_ce_priv(ar); 730 731 return ce->bus_ops->read32(ar, offset); 732 } 733 734 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 735 { 736 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 737 } 738 739 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 740 { 741 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 742 } 743 744 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 745 { 746 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 747 } 748 749 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 750 { 751 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 752 } 753 754 bool ath10k_pci_irq_pending(struct ath10k *ar) 755 { 756 u32 cause; 757 758 /* Check if the shared legacy irq is for us */ 759 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 760 PCIE_INTR_CAUSE_ADDRESS); 761 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 762 return true; 763 764 return false; 765 } 766 767 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 768 { 769 /* IMPORTANT: INTR_CLR register has to be set after 770 * INTR_ENABLE is set to 0, otherwise interrupt can not be 771 * really cleared. 772 */ 773 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 774 0); 775 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 776 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 777 778 /* IMPORTANT: this extra read transaction is required to 779 * flush the posted write buffer. 780 */ 781 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 782 PCIE_INTR_ENABLE_ADDRESS); 783 } 784 785 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 786 { 787 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 788 PCIE_INTR_ENABLE_ADDRESS, 789 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 790 791 /* IMPORTANT: this extra read transaction is required to 792 * flush the posted write buffer. 793 */ 794 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 795 PCIE_INTR_ENABLE_ADDRESS); 796 } 797 798 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 799 { 800 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 801 802 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 803 return "msi"; 804 805 return "legacy"; 806 } 807 808 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 809 { 810 struct ath10k *ar = pipe->hif_ce_state; 811 struct ath10k_ce *ce = ath10k_ce_priv(ar); 812 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 813 struct sk_buff *skb; 814 dma_addr_t paddr; 815 int ret; 816 817 skb = dev_alloc_skb(pipe->buf_sz); 818 if (!skb) 819 return -ENOMEM; 820 821 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 822 823 paddr = dma_map_single(ar->dev, skb->data, 824 skb->len + skb_tailroom(skb), 825 DMA_FROM_DEVICE); 826 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 827 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 828 dev_kfree_skb_any(skb); 829 return -EIO; 830 } 831 832 ATH10K_SKB_RXCB(skb)->paddr = paddr; 833 834 spin_lock_bh(&ce->ce_lock); 835 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 836 spin_unlock_bh(&ce->ce_lock); 837 if (ret) { 838 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 839 DMA_FROM_DEVICE); 840 dev_kfree_skb_any(skb); 841 return ret; 842 } 843 844 return 0; 845 } 846 847 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 848 { 849 struct ath10k *ar = pipe->hif_ce_state; 850 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 851 struct ath10k_ce *ce = ath10k_ce_priv(ar); 852 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 853 int ret, num; 854 855 if (pipe->buf_sz == 0) 856 return; 857 858 if (!ce_pipe->dest_ring) 859 return; 860 861 spin_lock_bh(&ce->ce_lock); 862 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 863 spin_unlock_bh(&ce->ce_lock); 864 865 while (num >= 0) { 866 ret = __ath10k_pci_rx_post_buf(pipe); 867 if (ret) { 868 if (ret == -ENOSPC) 869 break; 870 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 871 mod_timer(&ar_pci->rx_post_retry, jiffies + 872 ATH10K_PCI_RX_POST_RETRY_MS); 873 break; 874 } 875 num--; 876 } 877 } 878 879 void ath10k_pci_rx_post(struct ath10k *ar) 880 { 881 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 882 int i; 883 884 for (i = 0; i < CE_COUNT; i++) 885 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 886 } 887 888 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 889 { 890 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); 891 struct ath10k *ar = ar_pci->ar; 892 893 ath10k_pci_rx_post(ar); 894 } 895 896 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 897 { 898 u32 val = 0, region = addr & 0xfffff; 899 900 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 901 & 0x7ff) << 21; 902 val |= 0x100000 | region; 903 return val; 904 } 905 906 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. 907 * Support to access target space below 1M for qca6174 and qca9377. 908 * If target space is below 1M, the bit[20] of converted CE addr is 0. 909 * Otherwise bit[20] of converted CE addr is 1. 910 */ 911 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 912 { 913 u32 val = 0, region = addr & 0xfffff; 914 915 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 916 & 0x7ff) << 21; 917 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; 918 return val; 919 } 920 921 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 922 { 923 u32 val = 0, region = addr & 0xfffff; 924 925 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 926 val |= 0x100000 | region; 927 return val; 928 } 929 930 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 931 { 932 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 933 934 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 935 return -ENOTSUPP; 936 937 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 938 } 939 940 /* 941 * Diagnostic read/write access is provided for startup/config/debug usage. 942 * Caller must guarantee proper alignment, when applicable, and single user 943 * at any moment. 944 */ 945 #if defined(__linux__) 946 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 947 #elif defined(__FreeBSD__) 948 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data, 949 #endif 950 int nbytes) 951 { 952 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 953 int ret = 0; 954 u32 *buf; 955 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 956 struct ath10k_ce_pipe *ce_diag; 957 /* Host buffer address in CE space */ 958 u32 ce_data; 959 dma_addr_t ce_data_base = 0; 960 void *data_buf; 961 int i; 962 963 mutex_lock(&ar_pci->ce_diag_mutex); 964 ce_diag = ar_pci->ce_diag; 965 966 /* 967 * Allocate a temporary bounce buffer to hold caller's data 968 * to be DMA'ed from Target. This guarantees 969 * 1) 4-byte alignment 970 * 2) Buffer in DMA-able space 971 */ 972 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 973 974 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 975 GFP_ATOMIC); 976 if (!data_buf) { 977 ret = -ENOMEM; 978 goto done; 979 } 980 981 /* The address supplied by the caller is in the 982 * Target CPU virtual address space. 983 * 984 * In order to use this address with the diagnostic CE, 985 * convert it from Target CPU virtual address space 986 * to CE address space 987 */ 988 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 989 990 remaining_bytes = nbytes; 991 ce_data = ce_data_base; 992 while (remaining_bytes) { 993 nbytes = min_t(unsigned int, remaining_bytes, 994 DIAG_TRANSFER_LIMIT); 995 996 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 997 if (ret != 0) 998 goto done; 999 1000 /* Request CE to send from Target(!) address to Host buffer */ 1001 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0); 1002 if (ret) 1003 goto done; 1004 1005 i = 0; 1006 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1007 udelay(DIAG_ACCESS_CE_WAIT_US); 1008 i += DIAG_ACCESS_CE_WAIT_US; 1009 1010 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1011 ret = -EBUSY; 1012 goto done; 1013 } 1014 } 1015 1016 i = 0; 1017 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1018 &completed_nbytes) != 0) { 1019 udelay(DIAG_ACCESS_CE_WAIT_US); 1020 i += DIAG_ACCESS_CE_WAIT_US; 1021 1022 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1023 ret = -EBUSY; 1024 goto done; 1025 } 1026 } 1027 1028 if (nbytes != completed_nbytes) { 1029 ret = -EIO; 1030 goto done; 1031 } 1032 1033 if (*buf != ce_data) { 1034 ret = -EIO; 1035 goto done; 1036 } 1037 1038 remaining_bytes -= nbytes; 1039 memcpy(data, data_buf, nbytes); 1040 1041 address += nbytes; 1042 data += nbytes; 1043 } 1044 1045 done: 1046 1047 if (data_buf) 1048 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1049 ce_data_base); 1050 1051 mutex_unlock(&ar_pci->ce_diag_mutex); 1052 1053 return ret; 1054 } 1055 1056 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 1057 { 1058 __le32 val = 0; 1059 int ret; 1060 1061 #if defined(__linux__) 1062 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1063 #elif defined(__FreeBSD__) 1064 ret = ath10k_pci_diag_read_mem(ar, address, (u8 *)&val, sizeof(val)); 1065 #endif 1066 *value = __le32_to_cpu(val); 1067 1068 return ret; 1069 } 1070 1071 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1072 u32 src, u32 len) 1073 { 1074 u32 host_addr, addr; 1075 int ret; 1076 1077 host_addr = host_interest_item_address(src); 1078 1079 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1080 if (ret != 0) { 1081 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1082 src, ret); 1083 return ret; 1084 } 1085 1086 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1087 if (ret != 0) { 1088 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1089 addr, len, ret); 1090 return ret; 1091 } 1092 1093 return 0; 1094 } 1095 1096 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1097 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1098 1099 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1100 #if defined(__linux__) 1101 const void *data, int nbytes) 1102 #elif defined(__FreeBSD__) 1103 const void *_d, int nbytes) 1104 #endif 1105 { 1106 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1107 int ret = 0; 1108 u32 *buf; 1109 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 1110 struct ath10k_ce_pipe *ce_diag; 1111 void *data_buf; 1112 dma_addr_t ce_data_base = 0; 1113 int i; 1114 #if defined(__FreeBSD__) 1115 const u8 *data = _d; 1116 #endif 1117 1118 mutex_lock(&ar_pci->ce_diag_mutex); 1119 ce_diag = ar_pci->ce_diag; 1120 1121 /* 1122 * Allocate a temporary bounce buffer to hold caller's data 1123 * to be DMA'ed to Target. This guarantees 1124 * 1) 4-byte alignment 1125 * 2) Buffer in DMA-able space 1126 */ 1127 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 1128 1129 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 1130 GFP_ATOMIC); 1131 if (!data_buf) { 1132 ret = -ENOMEM; 1133 goto done; 1134 } 1135 1136 /* 1137 * The address supplied by the caller is in the 1138 * Target CPU virtual address space. 1139 * 1140 * In order to use this address with the diagnostic CE, 1141 * convert it from 1142 * Target CPU virtual address space 1143 * to 1144 * CE address space 1145 */ 1146 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1147 1148 remaining_bytes = nbytes; 1149 while (remaining_bytes) { 1150 /* FIXME: check cast */ 1151 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1152 1153 /* Copy caller's data to allocated DMA buf */ 1154 memcpy(data_buf, data, nbytes); 1155 1156 /* Set up to receive directly into Target(!) address */ 1157 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address); 1158 if (ret != 0) 1159 goto done; 1160 1161 /* 1162 * Request CE to send caller-supplied data that 1163 * was copied to bounce buffer to Target(!) address. 1164 */ 1165 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0); 1166 if (ret != 0) 1167 goto done; 1168 1169 i = 0; 1170 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1171 udelay(DIAG_ACCESS_CE_WAIT_US); 1172 i += DIAG_ACCESS_CE_WAIT_US; 1173 1174 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1175 ret = -EBUSY; 1176 goto done; 1177 } 1178 } 1179 1180 i = 0; 1181 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1182 &completed_nbytes) != 0) { 1183 udelay(DIAG_ACCESS_CE_WAIT_US); 1184 i += DIAG_ACCESS_CE_WAIT_US; 1185 1186 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1187 ret = -EBUSY; 1188 goto done; 1189 } 1190 } 1191 1192 if (nbytes != completed_nbytes) { 1193 ret = -EIO; 1194 goto done; 1195 } 1196 1197 if (*buf != address) { 1198 ret = -EIO; 1199 goto done; 1200 } 1201 1202 remaining_bytes -= nbytes; 1203 address += nbytes; 1204 data += nbytes; 1205 } 1206 1207 done: 1208 if (data_buf) { 1209 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1210 ce_data_base); 1211 } 1212 1213 if (ret != 0) 1214 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1215 address, ret); 1216 1217 mutex_unlock(&ar_pci->ce_diag_mutex); 1218 1219 return ret; 1220 } 1221 1222 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1223 { 1224 __le32 val = __cpu_to_le32(value); 1225 1226 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1227 } 1228 1229 /* Called by lower (CE) layer when a send to Target completes. */ 1230 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1231 { 1232 struct ath10k *ar = ce_state->ar; 1233 struct sk_buff_head list; 1234 struct sk_buff *skb; 1235 1236 __skb_queue_head_init(&list); 1237 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1238 /* no need to call tx completion for NULL pointers */ 1239 if (skb == NULL) 1240 continue; 1241 1242 __skb_queue_tail(&list, skb); 1243 } 1244 1245 while ((skb = __skb_dequeue(&list))) 1246 ath10k_htc_tx_completion_handler(ar, skb); 1247 } 1248 1249 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1250 void (*callback)(struct ath10k *ar, 1251 struct sk_buff *skb)) 1252 { 1253 struct ath10k *ar = ce_state->ar; 1254 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1255 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1256 struct sk_buff *skb; 1257 struct sk_buff_head list; 1258 void *transfer_context; 1259 unsigned int nbytes, max_nbytes; 1260 1261 __skb_queue_head_init(&list); 1262 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1263 &nbytes) == 0) { 1264 skb = transfer_context; 1265 max_nbytes = skb->len + skb_tailroom(skb); 1266 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1267 max_nbytes, DMA_FROM_DEVICE); 1268 1269 if (unlikely(max_nbytes < nbytes)) { 1270 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1271 nbytes, max_nbytes); 1272 dev_kfree_skb_any(skb); 1273 continue; 1274 } 1275 1276 skb_put(skb, nbytes); 1277 __skb_queue_tail(&list, skb); 1278 } 1279 1280 while ((skb = __skb_dequeue(&list))) { 1281 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1282 ce_state->id, skb->len); 1283 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1284 skb->data, skb->len); 1285 1286 callback(ar, skb); 1287 } 1288 1289 ath10k_pci_rx_post_pipe(pipe_info); 1290 } 1291 1292 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1293 void (*callback)(struct ath10k *ar, 1294 struct sk_buff *skb)) 1295 { 1296 struct ath10k *ar = ce_state->ar; 1297 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1298 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1299 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1300 struct sk_buff *skb; 1301 struct sk_buff_head list; 1302 void *transfer_context; 1303 unsigned int nbytes, max_nbytes, nentries; 1304 int orig_len; 1305 1306 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1307 * is processed other than init and deinit. Before releasing CE5 1308 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1309 */ 1310 __skb_queue_head_init(&list); 1311 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1312 &nbytes) == 0) { 1313 skb = transfer_context; 1314 max_nbytes = skb->len + skb_tailroom(skb); 1315 1316 if (unlikely(max_nbytes < nbytes)) { 1317 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1318 nbytes, max_nbytes); 1319 continue; 1320 } 1321 1322 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1323 max_nbytes, DMA_FROM_DEVICE); 1324 skb_put(skb, nbytes); 1325 __skb_queue_tail(&list, skb); 1326 } 1327 1328 nentries = skb_queue_len(&list); 1329 while ((skb = __skb_dequeue(&list))) { 1330 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1331 ce_state->id, skb->len); 1332 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1333 skb->data, skb->len); 1334 1335 orig_len = skb->len; 1336 callback(ar, skb); 1337 skb_push(skb, orig_len - skb->len); 1338 skb_reset_tail_pointer(skb); 1339 skb_trim(skb, 0); 1340 1341 /*let device gain the buffer again*/ 1342 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1343 skb->len + skb_tailroom(skb), 1344 DMA_FROM_DEVICE); 1345 } 1346 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1347 } 1348 1349 /* Called by lower (CE) layer when data is received from the Target. */ 1350 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1351 { 1352 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1353 } 1354 1355 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1356 { 1357 /* CE4 polling needs to be done whenever CE pipe which transports 1358 * HTT Rx (target->host) is processed. 1359 */ 1360 ath10k_ce_per_engine_service(ce_state->ar, 4); 1361 1362 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1363 } 1364 1365 /* Called by lower (CE) layer when data is received from the Target. 1366 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1367 */ 1368 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1369 { 1370 ath10k_pci_process_rx_cb(ce_state, 1371 ath10k_htt_rx_pktlog_completion_handler); 1372 } 1373 1374 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1375 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1376 { 1377 struct ath10k *ar = ce_state->ar; 1378 struct sk_buff *skb; 1379 1380 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1381 /* no need to call tx completion for NULL pointers */ 1382 if (!skb) 1383 continue; 1384 1385 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1386 skb->len, DMA_TO_DEVICE); 1387 ath10k_htt_hif_tx_complete(ar, skb); 1388 } 1389 } 1390 1391 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1392 { 1393 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1394 ath10k_htt_t2h_msg_handler(ar, skb); 1395 } 1396 1397 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1398 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1399 { 1400 /* CE4 polling needs to be done whenever CE pipe which transports 1401 * HTT Rx (target->host) is processed. 1402 */ 1403 ath10k_ce_per_engine_service(ce_state->ar, 4); 1404 1405 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1406 } 1407 1408 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1409 struct ath10k_hif_sg_item *items, int n_items) 1410 { 1411 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1412 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1413 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1414 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1415 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1416 unsigned int nentries_mask; 1417 unsigned int sw_index; 1418 unsigned int write_index; 1419 int err, i = 0; 1420 1421 spin_lock_bh(&ce->ce_lock); 1422 1423 nentries_mask = src_ring->nentries_mask; 1424 sw_index = src_ring->sw_index; 1425 write_index = src_ring->write_index; 1426 1427 if (unlikely(CE_RING_DELTA(nentries_mask, 1428 write_index, sw_index - 1) < n_items)) { 1429 err = -ENOBUFS; 1430 goto err; 1431 } 1432 1433 for (i = 0; i < n_items - 1; i++) { 1434 ath10k_dbg(ar, ATH10K_DBG_PCI, 1435 "pci tx item %d paddr %pad len %d n_items %d\n", 1436 i, &items[i].paddr, items[i].len, n_items); 1437 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1438 items[i].vaddr, items[i].len); 1439 1440 err = ath10k_ce_send_nolock(ce_pipe, 1441 items[i].transfer_context, 1442 items[i].paddr, 1443 items[i].len, 1444 items[i].transfer_id, 1445 CE_SEND_FLAG_GATHER); 1446 if (err) 1447 goto err; 1448 } 1449 1450 /* `i` is equal to `n_items -1` after for() */ 1451 1452 ath10k_dbg(ar, ATH10K_DBG_PCI, 1453 "pci tx item %d paddr %pad len %d n_items %d pipe_id %u\n", 1454 i, &items[i].paddr, items[i].len, n_items, pipe_id); 1455 if (n_items == 1 && items[i].len == 140) { 1456 ath10k_dbg_dump(ar, ATH10K_DBG_PCI, NULL, "pci tx data: ", 1457 items[i].vaddr, items[i].len); 1458 dump_stack(); 1459 DELAY(500); 1460 } 1461 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1462 items[i].vaddr, items[i].len); 1463 1464 err = ath10k_ce_send_nolock(ce_pipe, 1465 items[i].transfer_context, 1466 items[i].paddr, 1467 items[i].len, 1468 items[i].transfer_id, 1469 0); 1470 if (err) 1471 goto err; 1472 1473 spin_unlock_bh(&ce->ce_lock); 1474 return 0; 1475 1476 err: 1477 for (; i > 0; i--) 1478 __ath10k_ce_send_revert(ce_pipe); 1479 1480 spin_unlock_bh(&ce->ce_lock); 1481 return err; 1482 } 1483 1484 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1485 size_t buf_len) 1486 { 1487 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1488 } 1489 1490 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1491 { 1492 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1493 1494 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1495 1496 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1497 } 1498 1499 static void ath10k_pci_dump_registers(struct ath10k *ar, 1500 struct ath10k_fw_crash_data *crash_data) 1501 { 1502 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1503 int i, ret; 1504 1505 lockdep_assert_held(&ar->dump_mutex); 1506 1507 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1508 hi_failure_state, 1509 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1510 if (ret) { 1511 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1512 return; 1513 } 1514 1515 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1516 1517 ath10k_err(ar, "firmware register dump:\n"); 1518 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1519 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1520 i, 1521 __le32_to_cpu(reg_dump_values[i]), 1522 __le32_to_cpu(reg_dump_values[i + 1]), 1523 __le32_to_cpu(reg_dump_values[i + 2]), 1524 __le32_to_cpu(reg_dump_values[i + 3])); 1525 1526 if (!crash_data) 1527 return; 1528 1529 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1530 crash_data->registers[i] = reg_dump_values[i]; 1531 } 1532 1533 static int ath10k_pci_dump_memory_section(struct ath10k *ar, 1534 const struct ath10k_mem_region *mem_region, 1535 u8 *buf, size_t buf_len) 1536 { 1537 const struct ath10k_mem_section *cur_section, *next_section; 1538 unsigned int count, section_size, skip_size; 1539 int ret, i, j; 1540 1541 if (!mem_region || !buf) 1542 return 0; 1543 1544 cur_section = &mem_region->section_table.sections[0]; 1545 1546 if (mem_region->start > cur_section->start) { 1547 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", 1548 mem_region->start, cur_section->start); 1549 return 0; 1550 } 1551 1552 skip_size = cur_section->start - mem_region->start; 1553 1554 /* fill the gap between the first register section and register 1555 * start address 1556 */ 1557 for (i = 0; i < skip_size; i++) { 1558 *buf = ATH10K_MAGIC_NOT_COPIED; 1559 buf++; 1560 } 1561 1562 count = 0; 1563 1564 for (i = 0; cur_section != NULL; i++) { 1565 section_size = cur_section->end - cur_section->start; 1566 1567 if (section_size <= 0) { 1568 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", 1569 cur_section->start, 1570 cur_section->end); 1571 break; 1572 } 1573 1574 if ((i + 1) == mem_region->section_table.size) { 1575 /* last section */ 1576 next_section = NULL; 1577 skip_size = 0; 1578 } else { 1579 next_section = cur_section + 1; 1580 1581 if (cur_section->end > next_section->start) { 1582 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", 1583 next_section->start, 1584 cur_section->end); 1585 break; 1586 } 1587 1588 skip_size = next_section->start - cur_section->end; 1589 } 1590 1591 if (buf_len < (skip_size + section_size)) { 1592 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); 1593 break; 1594 } 1595 1596 buf_len -= skip_size + section_size; 1597 1598 /* read section to dest memory */ 1599 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, 1600 buf, section_size); 1601 if (ret) { 1602 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", 1603 cur_section->start, ret); 1604 break; 1605 } 1606 1607 buf += section_size; 1608 count += section_size; 1609 1610 /* fill in the gap between this section and the next */ 1611 for (j = 0; j < skip_size; j++) { 1612 *buf = ATH10K_MAGIC_NOT_COPIED; 1613 buf++; 1614 } 1615 1616 count += skip_size; 1617 1618 if (!next_section) 1619 /* this was the last section */ 1620 break; 1621 1622 cur_section = next_section; 1623 } 1624 1625 return count; 1626 } 1627 1628 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) 1629 { 1630 u32 val; 1631 1632 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1633 FW_RAM_CONFIG_ADDRESS, config); 1634 1635 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1636 FW_RAM_CONFIG_ADDRESS); 1637 if (val != config) { 1638 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", 1639 val, config); 1640 return -EIO; 1641 } 1642 1643 return 0; 1644 } 1645 1646 /* Always returns the length */ 1647 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, 1648 const struct ath10k_mem_region *region, 1649 u8 *buf) 1650 { 1651 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1652 u32 base_addr, i; 1653 1654 #if defined(__linux__) 1655 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); 1656 #elif defined(__FreeBSD__) 1657 base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG); 1658 #endif 1659 base_addr += region->start; 1660 1661 for (i = 0; i < region->len; i += 4) { 1662 #if defined(__linux__) 1663 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); 1664 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); 1665 #elif defined(__FreeBSD__) 1666 bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i); 1667 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG); 1668 #endif 1669 } 1670 1671 return region->len; 1672 } 1673 1674 /* if an error happened returns < 0, otherwise the length */ 1675 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, 1676 const struct ath10k_mem_region *region, 1677 u8 *buf) 1678 { 1679 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1680 u32 i; 1681 int ret; 1682 1683 mutex_lock(&ar->conf_mutex); 1684 if (ar->state != ATH10K_STATE_ON) { 1685 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n"); 1686 ret = -EIO; 1687 goto done; 1688 } 1689 1690 for (i = 0; i < region->len; i += 4) 1691 #if defined(__linux__) 1692 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); 1693 #elif defined(__FreeBSD__) 1694 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i); 1695 #endif 1696 1697 ret = region->len; 1698 done: 1699 mutex_unlock(&ar->conf_mutex); 1700 return ret; 1701 } 1702 1703 /* if an error happened returns < 0, otherwise the length */ 1704 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, 1705 const struct ath10k_mem_region *current_region, 1706 u8 *buf) 1707 { 1708 int ret; 1709 1710 if (current_region->section_table.size > 0) 1711 /* Copy each section individually. */ 1712 return ath10k_pci_dump_memory_section(ar, 1713 current_region, 1714 buf, 1715 current_region->len); 1716 1717 /* No individiual memory sections defined so we can 1718 * copy the entire memory region. 1719 */ 1720 ret = ath10k_pci_diag_read_mem(ar, 1721 current_region->start, 1722 buf, 1723 current_region->len); 1724 if (ret) { 1725 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", 1726 current_region->name, ret); 1727 return ret; 1728 } 1729 1730 return current_region->len; 1731 } 1732 1733 static void ath10k_pci_dump_memory(struct ath10k *ar, 1734 struct ath10k_fw_crash_data *crash_data) 1735 { 1736 const struct ath10k_hw_mem_layout *mem_layout; 1737 const struct ath10k_mem_region *current_region; 1738 struct ath10k_dump_ram_data_hdr *hdr; 1739 u32 count, shift; 1740 size_t buf_len; 1741 int ret, i; 1742 u8 *buf; 1743 1744 lockdep_assert_held(&ar->dump_mutex); 1745 1746 if (!crash_data) 1747 return; 1748 1749 mem_layout = ath10k_coredump_get_mem_layout(ar); 1750 if (!mem_layout) 1751 return; 1752 1753 current_region = &mem_layout->region_table.regions[0]; 1754 1755 buf = crash_data->ramdump_buf; 1756 buf_len = crash_data->ramdump_buf_len; 1757 1758 memset(buf, 0, buf_len); 1759 1760 for (i = 0; i < mem_layout->region_table.size; i++) { 1761 count = 0; 1762 1763 if (current_region->len > buf_len) { 1764 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", 1765 current_region->name, 1766 current_region->len, 1767 buf_len); 1768 break; 1769 } 1770 1771 /* To get IRAM dump, the host driver needs to switch target 1772 * ram config from DRAM to IRAM. 1773 */ 1774 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || 1775 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { 1776 shift = current_region->start >> 20; 1777 1778 ret = ath10k_pci_set_ram_config(ar, shift); 1779 if (ret) { 1780 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", 1781 current_region->name, ret); 1782 break; 1783 } 1784 } 1785 1786 /* Reserve space for the header. */ 1787 hdr = (void *)buf; 1788 buf += sizeof(*hdr); 1789 buf_len -= sizeof(*hdr); 1790 1791 switch (current_region->type) { 1792 case ATH10K_MEM_REGION_TYPE_IOSRAM: 1793 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); 1794 break; 1795 case ATH10K_MEM_REGION_TYPE_IOREG: 1796 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf); 1797 if (ret < 0) 1798 break; 1799 1800 count = ret; 1801 break; 1802 default: 1803 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); 1804 if (ret < 0) 1805 break; 1806 1807 count = ret; 1808 break; 1809 } 1810 1811 hdr->region_type = cpu_to_le32(current_region->type); 1812 hdr->start = cpu_to_le32(current_region->start); 1813 hdr->length = cpu_to_le32(count); 1814 1815 if (count == 0) 1816 /* Note: the header remains, just with zero length. */ 1817 break; 1818 1819 buf += count; 1820 buf_len -= count; 1821 1822 current_region++; 1823 } 1824 } 1825 1826 static void ath10k_pci_fw_dump_work(struct work_struct *work) 1827 { 1828 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci, 1829 dump_work); 1830 struct ath10k_fw_crash_data *crash_data; 1831 struct ath10k *ar = ar_pci->ar; 1832 char guid[UUID_STRING_LEN + 1]; 1833 1834 mutex_lock(&ar->dump_mutex); 1835 1836 spin_lock_bh(&ar->data_lock); 1837 ar->stats.fw_crash_counter++; 1838 spin_unlock_bh(&ar->data_lock); 1839 1840 crash_data = ath10k_coredump_new(ar); 1841 1842 if (crash_data) 1843 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1844 else 1845 scnprintf(guid, sizeof(guid), "n/a"); 1846 1847 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1848 ath10k_print_driver_info(ar); 1849 ath10k_pci_dump_registers(ar, crash_data); 1850 ath10k_ce_dump_registers(ar, crash_data); 1851 ath10k_pci_dump_memory(ar, crash_data); 1852 1853 mutex_unlock(&ar->dump_mutex); 1854 1855 ath10k_core_start_recovery(ar); 1856 } 1857 1858 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1859 { 1860 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1861 1862 queue_work(ar->workqueue, &ar_pci->dump_work); 1863 } 1864 1865 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1866 int force) 1867 { 1868 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1869 1870 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1871 1872 if (!force) { 1873 int resources; 1874 /* 1875 * Decide whether to actually poll for completions, or just 1876 * wait for a later chance. 1877 * If there seem to be plenty of resources left, then just wait 1878 * since checking involves reading a CE register, which is a 1879 * relatively expensive operation. 1880 */ 1881 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1882 1883 /* 1884 * If at least 50% of the total resources are still available, 1885 * don't bother checking again yet. 1886 */ 1887 if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) 1888 return; 1889 } 1890 ath10k_ce_per_engine_service(ar, pipe); 1891 } 1892 1893 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1894 { 1895 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1896 1897 del_timer_sync(&ar_pci->rx_post_retry); 1898 } 1899 1900 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1901 u8 *ul_pipe, u8 *dl_pipe) 1902 { 1903 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1904 const struct ce_service_to_pipe *entry; 1905 bool ul_set = false, dl_set = false; 1906 int i; 1907 1908 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1909 1910 for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) { 1911 entry = &ar_pci->serv_to_pipe[i]; 1912 1913 if (__le32_to_cpu(entry->service_id) != service_id) 1914 continue; 1915 1916 switch (__le32_to_cpu(entry->pipedir)) { 1917 case PIPEDIR_NONE: 1918 break; 1919 case PIPEDIR_IN: 1920 WARN_ON(dl_set); 1921 *dl_pipe = __le32_to_cpu(entry->pipenum); 1922 dl_set = true; 1923 break; 1924 case PIPEDIR_OUT: 1925 WARN_ON(ul_set); 1926 *ul_pipe = __le32_to_cpu(entry->pipenum); 1927 ul_set = true; 1928 break; 1929 case PIPEDIR_INOUT: 1930 WARN_ON(dl_set); 1931 WARN_ON(ul_set); 1932 *dl_pipe = __le32_to_cpu(entry->pipenum); 1933 *ul_pipe = __le32_to_cpu(entry->pipenum); 1934 dl_set = true; 1935 ul_set = true; 1936 break; 1937 } 1938 } 1939 1940 if (!ul_set || !dl_set) 1941 return -ENOENT; 1942 1943 return 0; 1944 } 1945 1946 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1947 u8 *ul_pipe, u8 *dl_pipe) 1948 { 1949 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1950 1951 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1952 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1953 ul_pipe, dl_pipe); 1954 } 1955 1956 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1957 { 1958 u32 val; 1959 1960 switch (ar->hw_rev) { 1961 case ATH10K_HW_QCA988X: 1962 case ATH10K_HW_QCA9887: 1963 case ATH10K_HW_QCA6174: 1964 case ATH10K_HW_QCA9377: 1965 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1966 CORE_CTRL_ADDRESS); 1967 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1968 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1969 CORE_CTRL_ADDRESS, val); 1970 break; 1971 case ATH10K_HW_QCA99X0: 1972 case ATH10K_HW_QCA9984: 1973 case ATH10K_HW_QCA9888: 1974 case ATH10K_HW_QCA4019: 1975 /* TODO: Find appropriate register configuration for QCA99X0 1976 * to mask irq/MSI. 1977 */ 1978 break; 1979 case ATH10K_HW_WCN3990: 1980 break; 1981 } 1982 } 1983 1984 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1985 { 1986 u32 val; 1987 1988 switch (ar->hw_rev) { 1989 case ATH10K_HW_QCA988X: 1990 case ATH10K_HW_QCA9887: 1991 case ATH10K_HW_QCA6174: 1992 case ATH10K_HW_QCA9377: 1993 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1994 CORE_CTRL_ADDRESS); 1995 val |= CORE_CTRL_PCIE_REG_31_MASK; 1996 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1997 CORE_CTRL_ADDRESS, val); 1998 break; 1999 case ATH10K_HW_QCA99X0: 2000 case ATH10K_HW_QCA9984: 2001 case ATH10K_HW_QCA9888: 2002 case ATH10K_HW_QCA4019: 2003 /* TODO: Find appropriate register configuration for QCA99X0 2004 * to unmask irq/MSI. 2005 */ 2006 break; 2007 case ATH10K_HW_WCN3990: 2008 break; 2009 } 2010 } 2011 2012 static void ath10k_pci_irq_disable(struct ath10k *ar) 2013 { 2014 ath10k_ce_disable_interrupts(ar); 2015 ath10k_pci_disable_and_clear_legacy_irq(ar); 2016 ath10k_pci_irq_msi_fw_mask(ar); 2017 } 2018 2019 static void ath10k_pci_irq_sync(struct ath10k *ar) 2020 { 2021 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2022 2023 synchronize_irq(ar_pci->pdev->irq); 2024 } 2025 2026 static void ath10k_pci_irq_enable(struct ath10k *ar) 2027 { 2028 ath10k_ce_enable_interrupts(ar); 2029 ath10k_pci_enable_legacy_irq(ar); 2030 ath10k_pci_irq_msi_fw_unmask(ar); 2031 } 2032 2033 static int ath10k_pci_hif_start(struct ath10k *ar) 2034 { 2035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2036 2037 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 2038 2039 ath10k_core_napi_enable(ar); 2040 2041 ath10k_pci_irq_enable(ar); 2042 ath10k_pci_rx_post(ar); 2043 2044 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2045 ar_pci->link_ctl); 2046 2047 return 0; 2048 } 2049 2050 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2051 { 2052 struct ath10k *ar; 2053 struct ath10k_ce_pipe *ce_pipe; 2054 struct ath10k_ce_ring *ce_ring; 2055 struct sk_buff *skb; 2056 int i; 2057 2058 ar = pci_pipe->hif_ce_state; 2059 ce_pipe = pci_pipe->ce_hdl; 2060 ce_ring = ce_pipe->dest_ring; 2061 2062 if (!ce_ring) 2063 return; 2064 2065 if (!pci_pipe->buf_sz) 2066 return; 2067 2068 for (i = 0; i < ce_ring->nentries; i++) { 2069 skb = ce_ring->per_transfer_context[i]; 2070 if (!skb) 2071 continue; 2072 2073 ce_ring->per_transfer_context[i] = NULL; 2074 2075 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 2076 skb->len + skb_tailroom(skb), 2077 DMA_FROM_DEVICE); 2078 dev_kfree_skb_any(skb); 2079 } 2080 } 2081 2082 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2083 { 2084 struct ath10k *ar; 2085 struct ath10k_ce_pipe *ce_pipe; 2086 struct ath10k_ce_ring *ce_ring; 2087 struct sk_buff *skb; 2088 int i; 2089 2090 ar = pci_pipe->hif_ce_state; 2091 ce_pipe = pci_pipe->ce_hdl; 2092 ce_ring = ce_pipe->src_ring; 2093 2094 if (!ce_ring) 2095 return; 2096 2097 if (!pci_pipe->buf_sz) 2098 return; 2099 2100 for (i = 0; i < ce_ring->nentries; i++) { 2101 skb = ce_ring->per_transfer_context[i]; 2102 if (!skb) 2103 continue; 2104 2105 ce_ring->per_transfer_context[i] = NULL; 2106 2107 ath10k_htc_tx_completion_handler(ar, skb); 2108 } 2109 } 2110 2111 /* 2112 * Cleanup residual buffers for device shutdown: 2113 * buffers that were enqueued for receive 2114 * buffers that were to be sent 2115 * Note: Buffers that had completed but which were 2116 * not yet processed are on a completion queue. They 2117 * are handled when the completion thread shuts down. 2118 */ 2119 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 2120 { 2121 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2122 int pipe_num; 2123 2124 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 2125 struct ath10k_pci_pipe *pipe_info; 2126 2127 pipe_info = &ar_pci->pipe_info[pipe_num]; 2128 ath10k_pci_rx_pipe_cleanup(pipe_info); 2129 ath10k_pci_tx_pipe_cleanup(pipe_info); 2130 } 2131 } 2132 2133 void ath10k_pci_ce_deinit(struct ath10k *ar) 2134 { 2135 int i; 2136 2137 for (i = 0; i < CE_COUNT; i++) 2138 ath10k_ce_deinit_pipe(ar, i); 2139 } 2140 2141 void ath10k_pci_flush(struct ath10k *ar) 2142 { 2143 ath10k_pci_rx_retry_sync(ar); 2144 ath10k_pci_buffer_cleanup(ar); 2145 } 2146 2147 static void ath10k_pci_hif_stop(struct ath10k *ar) 2148 { 2149 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2150 unsigned long flags; 2151 2152 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 2153 2154 ath10k_pci_irq_disable(ar); 2155 ath10k_pci_irq_sync(ar); 2156 2157 ath10k_core_napi_sync_disable(ar); 2158 2159 cancel_work_sync(&ar_pci->dump_work); 2160 2161 /* Most likely the device has HTT Rx ring configured. The only way to 2162 * prevent the device from accessing (and possible corrupting) host 2163 * memory is to reset the chip now. 2164 * 2165 * There's also no known way of masking MSI interrupts on the device. 2166 * For ranged MSI the CE-related interrupts can be masked. However 2167 * regardless how many MSI interrupts are assigned the first one 2168 * is always used for firmware indications (crashes) and cannot be 2169 * masked. To prevent the device from asserting the interrupt reset it 2170 * before proceeding with cleanup. 2171 */ 2172 ath10k_pci_safe_chip_reset(ar); 2173 2174 ath10k_pci_flush(ar); 2175 2176 spin_lock_irqsave(&ar_pci->ps_lock, flags); 2177 WARN_ON(ar_pci->ps_wake_refcount > 0); 2178 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 2179 } 2180 2181 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 2182 void *req, u32 req_len, 2183 void *resp, u32 *resp_len) 2184 { 2185 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2186 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 2187 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 2188 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 2189 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 2190 dma_addr_t req_paddr = 0; 2191 dma_addr_t resp_paddr = 0; 2192 struct bmi_xfer xfer = {}; 2193 void *treq, *tresp = NULL; 2194 int ret = 0; 2195 2196 might_sleep(); 2197 2198 if (resp && !resp_len) 2199 return -EINVAL; 2200 2201 if (resp && resp_len && *resp_len == 0) 2202 return -EINVAL; 2203 2204 treq = kmemdup(req, req_len, GFP_KERNEL); 2205 if (!treq) 2206 return -ENOMEM; 2207 2208 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 2209 ret = dma_mapping_error(ar->dev, req_paddr); 2210 if (ret) { 2211 ret = -EIO; 2212 goto err_dma; 2213 } 2214 2215 if (resp && resp_len) { 2216 tresp = kzalloc(*resp_len, GFP_KERNEL); 2217 if (!tresp) { 2218 ret = -ENOMEM; 2219 goto err_req; 2220 } 2221 2222 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 2223 DMA_FROM_DEVICE); 2224 ret = dma_mapping_error(ar->dev, resp_paddr); 2225 if (ret) { 2226 ret = -EIO; 2227 goto err_req; 2228 } 2229 2230 xfer.wait_for_resp = true; 2231 xfer.resp_len = 0; 2232 2233 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 2234 } 2235 2236 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 2237 if (ret) 2238 goto err_resp; 2239 2240 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 2241 if (ret) { 2242 dma_addr_t unused_buffer; 2243 unsigned int unused_nbytes; 2244 unsigned int unused_id; 2245 2246 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 2247 &unused_nbytes, &unused_id); 2248 } else { 2249 /* non-zero means we did not time out */ 2250 ret = 0; 2251 } 2252 2253 err_resp: 2254 if (resp) { 2255 dma_addr_t unused_buffer; 2256 2257 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 2258 dma_unmap_single(ar->dev, resp_paddr, 2259 *resp_len, DMA_FROM_DEVICE); 2260 } 2261 err_req: 2262 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 2263 2264 if (ret == 0 && resp_len) { 2265 *resp_len = min(*resp_len, xfer.resp_len); 2266 memcpy(resp, tresp, *resp_len); 2267 } 2268 err_dma: 2269 kfree(treq); 2270 kfree(tresp); 2271 2272 return ret; 2273 } 2274 2275 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 2276 { 2277 struct bmi_xfer *xfer; 2278 2279 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 2280 return; 2281 2282 xfer->tx_done = true; 2283 } 2284 2285 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 2286 { 2287 struct ath10k *ar = ce_state->ar; 2288 struct bmi_xfer *xfer; 2289 unsigned int nbytes; 2290 2291 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 2292 &nbytes)) 2293 return; 2294 2295 if (WARN_ON_ONCE(!xfer)) 2296 return; 2297 2298 if (!xfer->wait_for_resp) { 2299 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 2300 return; 2301 } 2302 2303 xfer->resp_len = nbytes; 2304 xfer->rx_done = true; 2305 } 2306 2307 static int ath10k_pci_bmi_wait(struct ath10k *ar, 2308 struct ath10k_ce_pipe *tx_pipe, 2309 struct ath10k_ce_pipe *rx_pipe, 2310 struct bmi_xfer *xfer) 2311 { 2312 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 2313 unsigned long started = jiffies; 2314 unsigned long dur; 2315 int ret; 2316 2317 while (time_before_eq(jiffies, timeout)) { 2318 ath10k_pci_bmi_send_done(tx_pipe); 2319 ath10k_pci_bmi_recv_data(rx_pipe); 2320 2321 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 2322 ret = 0; 2323 goto out; 2324 } 2325 2326 #if defined(__linux__) 2327 schedule(); 2328 #elif defined(__FreeBSD__) 2329 /* Using LinuxKPI we'll hang for-ever as there's no wake_up */ 2330 kern_yield(PRI_USER); 2331 #endif 2332 } 2333 2334 ret = -ETIMEDOUT; 2335 2336 out: 2337 dur = jiffies - started; 2338 if (dur > HZ) 2339 ath10k_dbg(ar, ATH10K_DBG_BMI, 2340 "bmi cmd took %lu jiffies hz %d ret %d\n", 2341 dur, HZ, ret); 2342 return ret; 2343 } 2344 2345 /* 2346 * Send an interrupt to the device to wake up the Target CPU 2347 * so it has an opportunity to notice any changed state. 2348 */ 2349 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 2350 { 2351 u32 addr, val; 2352 2353 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 2354 val = ath10k_pci_read32(ar, addr); 2355 val |= CORE_CTRL_CPU_INTR_MASK; 2356 ath10k_pci_write32(ar, addr, val); 2357 2358 return 0; 2359 } 2360 2361 static int ath10k_pci_get_num_banks(struct ath10k *ar) 2362 { 2363 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2364 2365 switch (ar_pci->pdev->device) { 2366 case QCA988X_2_0_DEVICE_ID_UBNT: 2367 case QCA988X_2_0_DEVICE_ID: 2368 case QCA99X0_2_0_DEVICE_ID: 2369 case QCA9888_2_0_DEVICE_ID: 2370 case QCA9984_1_0_DEVICE_ID: 2371 case QCA9887_1_0_DEVICE_ID: 2372 return 1; 2373 case QCA6164_2_1_DEVICE_ID: 2374 case QCA6174_2_1_DEVICE_ID: 2375 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { 2376 case QCA6174_HW_1_0_CHIP_ID_REV: 2377 case QCA6174_HW_1_1_CHIP_ID_REV: 2378 case QCA6174_HW_2_1_CHIP_ID_REV: 2379 case QCA6174_HW_2_2_CHIP_ID_REV: 2380 return 3; 2381 case QCA6174_HW_1_3_CHIP_ID_REV: 2382 return 2; 2383 case QCA6174_HW_3_0_CHIP_ID_REV: 2384 case QCA6174_HW_3_1_CHIP_ID_REV: 2385 case QCA6174_HW_3_2_CHIP_ID_REV: 2386 return 9; 2387 } 2388 break; 2389 case QCA9377_1_0_DEVICE_ID: 2390 return 9; 2391 } 2392 2393 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2394 return 1; 2395 } 2396 2397 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2398 { 2399 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2400 2401 return ce->bus_ops->get_num_banks(ar); 2402 } 2403 2404 int ath10k_pci_init_config(struct ath10k *ar) 2405 { 2406 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2407 u32 interconnect_targ_addr; 2408 u32 pcie_state_targ_addr = 0; 2409 u32 pipe_cfg_targ_addr = 0; 2410 u32 svc_to_pipe_map = 0; 2411 u32 pcie_config_flags = 0; 2412 u32 ealloc_value; 2413 u32 ealloc_targ_addr; 2414 u32 flag2_value; 2415 u32 flag2_targ_addr; 2416 int ret = 0; 2417 2418 /* Download to Target the CE Config and the service-to-CE map */ 2419 interconnect_targ_addr = 2420 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2421 2422 /* Supply Target-side CE configuration */ 2423 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2424 &pcie_state_targ_addr); 2425 if (ret != 0) { 2426 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2427 return ret; 2428 } 2429 2430 if (pcie_state_targ_addr == 0) { 2431 ret = -EIO; 2432 ath10k_err(ar, "Invalid pcie state addr\n"); 2433 return ret; 2434 } 2435 2436 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2437 offsetof(struct pcie_state, 2438 pipe_cfg_addr)), 2439 &pipe_cfg_targ_addr); 2440 if (ret != 0) { 2441 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2442 return ret; 2443 } 2444 2445 if (pipe_cfg_targ_addr == 0) { 2446 ret = -EIO; 2447 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2448 return ret; 2449 } 2450 2451 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2452 ar_pci->pipe_config, 2453 sizeof(struct ce_pipe_config) * 2454 NUM_TARGET_CE_CONFIG_WLAN); 2455 2456 if (ret != 0) { 2457 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2458 return ret; 2459 } 2460 2461 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2462 offsetof(struct pcie_state, 2463 svc_to_pipe_map)), 2464 &svc_to_pipe_map); 2465 if (ret != 0) { 2466 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2467 return ret; 2468 } 2469 2470 if (svc_to_pipe_map == 0) { 2471 ret = -EIO; 2472 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2473 return ret; 2474 } 2475 2476 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2477 ar_pci->serv_to_pipe, 2478 sizeof(pci_target_service_to_ce_map_wlan)); 2479 if (ret != 0) { 2480 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2481 return ret; 2482 } 2483 2484 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2485 offsetof(struct pcie_state, 2486 config_flags)), 2487 &pcie_config_flags); 2488 if (ret != 0) { 2489 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2490 return ret; 2491 } 2492 2493 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2494 2495 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2496 offsetof(struct pcie_state, 2497 config_flags)), 2498 pcie_config_flags); 2499 if (ret != 0) { 2500 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2501 return ret; 2502 } 2503 2504 /* configure early allocation */ 2505 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2506 2507 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2508 if (ret != 0) { 2509 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2510 return ret; 2511 } 2512 2513 /* first bank is switched to IRAM */ 2514 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2515 HI_EARLY_ALLOC_MAGIC_MASK); 2516 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2517 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2518 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2519 2520 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2521 if (ret != 0) { 2522 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2523 return ret; 2524 } 2525 2526 /* Tell Target to proceed with initialization */ 2527 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2528 2529 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2530 if (ret != 0) { 2531 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2532 return ret; 2533 } 2534 2535 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2536 2537 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2538 if (ret != 0) { 2539 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2540 return ret; 2541 } 2542 2543 return 0; 2544 } 2545 2546 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2547 { 2548 struct ce_attr *attr; 2549 struct ce_pipe_config *config; 2550 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2551 2552 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2553 * since it is currently used for other feature. 2554 */ 2555 2556 /* Override Host's Copy Engine 5 configuration */ 2557 attr = &ar_pci->attr[5]; 2558 attr->src_sz_max = 0; 2559 attr->dest_nentries = 0; 2560 2561 /* Override Target firmware's Copy Engine configuration */ 2562 config = &ar_pci->pipe_config[5]; 2563 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2564 config->nbytes_max = __cpu_to_le32(2048); 2565 2566 /* Map from service/endpoint to Copy Engine */ 2567 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); 2568 } 2569 2570 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2571 { 2572 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2573 struct ath10k_pci_pipe *pipe; 2574 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2575 int i, ret; 2576 2577 for (i = 0; i < CE_COUNT; i++) { 2578 pipe = &ar_pci->pipe_info[i]; 2579 pipe->ce_hdl = &ce->ce_states[i]; 2580 pipe->pipe_num = i; 2581 pipe->hif_ce_state = ar; 2582 2583 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); 2584 if (ret) { 2585 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2586 i, ret); 2587 return ret; 2588 } 2589 2590 /* Last CE is Diagnostic Window */ 2591 if (i == CE_DIAG_PIPE) { 2592 ar_pci->ce_diag = pipe->ce_hdl; 2593 continue; 2594 } 2595 2596 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); 2597 } 2598 2599 return 0; 2600 } 2601 2602 void ath10k_pci_free_pipes(struct ath10k *ar) 2603 { 2604 int i; 2605 2606 for (i = 0; i < CE_COUNT; i++) 2607 ath10k_ce_free_pipe(ar, i); 2608 } 2609 2610 int ath10k_pci_init_pipes(struct ath10k *ar) 2611 { 2612 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2613 int i, ret; 2614 2615 for (i = 0; i < CE_COUNT; i++) { 2616 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); 2617 if (ret) { 2618 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2619 i, ret); 2620 return ret; 2621 } 2622 } 2623 2624 return 0; 2625 } 2626 2627 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2628 { 2629 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2630 FW_IND_EVENT_PENDING; 2631 } 2632 2633 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2634 { 2635 u32 val; 2636 2637 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2638 val &= ~FW_IND_EVENT_PENDING; 2639 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2640 } 2641 2642 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2643 { 2644 u32 val; 2645 2646 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2647 return (val == 0xffffffff); 2648 } 2649 2650 /* this function effectively clears target memory controller assert line */ 2651 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2652 { 2653 u32 val; 2654 2655 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2656 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2657 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2658 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2659 2660 msleep(10); 2661 2662 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2663 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2664 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2665 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2666 2667 msleep(10); 2668 } 2669 2670 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2671 { 2672 u32 val; 2673 2674 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2675 2676 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2677 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2678 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2679 } 2680 2681 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2682 { 2683 u32 val; 2684 2685 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2686 2687 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2688 val | SOC_RESET_CONTROL_CE_RST_MASK); 2689 msleep(10); 2690 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2691 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2692 } 2693 2694 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2695 { 2696 u32 val; 2697 2698 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS); 2699 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS, 2700 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2701 } 2702 2703 static int ath10k_pci_warm_reset(struct ath10k *ar) 2704 { 2705 int ret; 2706 2707 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2708 2709 spin_lock_bh(&ar->data_lock); 2710 ar->stats.fw_warm_reset_counter++; 2711 spin_unlock_bh(&ar->data_lock); 2712 2713 ath10k_pci_irq_disable(ar); 2714 2715 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2716 * were to access copy engine while host performs copy engine reset 2717 * then it is possible for the device to confuse pci-e controller to 2718 * the point of bringing host system to a complete stop (i.e. hang). 2719 */ 2720 ath10k_pci_warm_reset_si0(ar); 2721 ath10k_pci_warm_reset_cpu(ar); 2722 ath10k_pci_init_pipes(ar); 2723 ath10k_pci_wait_for_target_init(ar); 2724 2725 ath10k_pci_warm_reset_clear_lf(ar); 2726 ath10k_pci_warm_reset_ce(ar); 2727 ath10k_pci_warm_reset_cpu(ar); 2728 ath10k_pci_init_pipes(ar); 2729 2730 ret = ath10k_pci_wait_for_target_init(ar); 2731 if (ret) { 2732 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2733 return ret; 2734 } 2735 2736 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2737 2738 return 0; 2739 } 2740 2741 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2742 { 2743 ath10k_pci_irq_disable(ar); 2744 return ath10k_pci_qca99x0_chip_reset(ar); 2745 } 2746 2747 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2748 { 2749 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2750 2751 if (!ar_pci->pci_soft_reset) 2752 return -ENOTSUPP; 2753 2754 return ar_pci->pci_soft_reset(ar); 2755 } 2756 2757 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2758 { 2759 int i, ret; 2760 u32 val; 2761 2762 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2763 2764 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2765 * It is thus preferred to use warm reset which is safer but may not be 2766 * able to recover the device from all possible fail scenarios. 2767 * 2768 * Warm reset doesn't always work on first try so attempt it a few 2769 * times before giving up. 2770 */ 2771 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2772 ret = ath10k_pci_warm_reset(ar); 2773 if (ret) { 2774 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2775 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2776 ret); 2777 continue; 2778 } 2779 2780 /* FIXME: Sometimes copy engine doesn't recover after warm 2781 * reset. In most cases this needs cold reset. In some of these 2782 * cases the device is in such a state that a cold reset may 2783 * lock up the host. 2784 * 2785 * Reading any host interest register via copy engine is 2786 * sufficient to verify if device is capable of booting 2787 * firmware blob. 2788 */ 2789 ret = ath10k_pci_init_pipes(ar); 2790 if (ret) { 2791 ath10k_warn(ar, "failed to init copy engine: %d\n", 2792 ret); 2793 continue; 2794 } 2795 2796 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2797 &val); 2798 if (ret) { 2799 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2800 ret); 2801 continue; 2802 } 2803 2804 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2805 return 0; 2806 } 2807 2808 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2809 ath10k_warn(ar, "refusing cold reset as requested\n"); 2810 return -EPERM; 2811 } 2812 2813 ret = ath10k_pci_cold_reset(ar); 2814 if (ret) { 2815 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2816 return ret; 2817 } 2818 2819 ret = ath10k_pci_wait_for_target_init(ar); 2820 if (ret) { 2821 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2822 ret); 2823 return ret; 2824 } 2825 2826 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2827 2828 return 0; 2829 } 2830 2831 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2832 { 2833 int ret; 2834 2835 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2836 2837 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2838 2839 ret = ath10k_pci_cold_reset(ar); 2840 if (ret) { 2841 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2842 return ret; 2843 } 2844 2845 ret = ath10k_pci_wait_for_target_init(ar); 2846 if (ret) { 2847 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2848 ret); 2849 return ret; 2850 } 2851 2852 ret = ath10k_pci_warm_reset(ar); 2853 if (ret) { 2854 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2855 return ret; 2856 } 2857 2858 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2859 2860 return 0; 2861 } 2862 2863 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2864 { 2865 int ret; 2866 2867 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2868 2869 ret = ath10k_pci_cold_reset(ar); 2870 if (ret) { 2871 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2872 return ret; 2873 } 2874 2875 ret = ath10k_pci_wait_for_target_init(ar); 2876 if (ret) { 2877 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2878 ret); 2879 return ret; 2880 } 2881 2882 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2883 2884 return 0; 2885 } 2886 2887 static int ath10k_pci_chip_reset(struct ath10k *ar) 2888 { 2889 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2890 2891 if (WARN_ON(!ar_pci->pci_hard_reset)) 2892 return -ENOTSUPP; 2893 2894 return ar_pci->pci_hard_reset(ar); 2895 } 2896 2897 static int ath10k_pci_hif_power_up(struct ath10k *ar, 2898 enum ath10k_firmware_mode fw_mode) 2899 { 2900 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2901 int ret; 2902 2903 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2904 2905 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2906 &ar_pci->link_ctl); 2907 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2908 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2909 2910 /* 2911 * Bring the target up cleanly. 2912 * 2913 * The target may be in an undefined state with an AUX-powered Target 2914 * and a Host in WoW mode. If the Host crashes, loses power, or is 2915 * restarted (without unloading the driver) then the Target is left 2916 * (aux) powered and running. On a subsequent driver load, the Target 2917 * is in an unexpected state. We try to catch that here in order to 2918 * reset the Target and retry the probe. 2919 */ 2920 ret = ath10k_pci_chip_reset(ar); 2921 if (ret) { 2922 if (ath10k_pci_has_fw_crashed(ar)) { 2923 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2924 ath10k_pci_fw_crashed_clear(ar); 2925 ath10k_pci_fw_crashed_dump(ar); 2926 } 2927 2928 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2929 goto err_sleep; 2930 } 2931 2932 ret = ath10k_pci_init_pipes(ar); 2933 if (ret) { 2934 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2935 goto err_sleep; 2936 } 2937 2938 ret = ath10k_pci_init_config(ar); 2939 if (ret) { 2940 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2941 goto err_ce; 2942 } 2943 2944 ret = ath10k_pci_wake_target_cpu(ar); 2945 if (ret) { 2946 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2947 goto err_ce; 2948 } 2949 2950 return 0; 2951 2952 err_ce: 2953 ath10k_pci_ce_deinit(ar); 2954 2955 err_sleep: 2956 return ret; 2957 } 2958 2959 void ath10k_pci_hif_power_down(struct ath10k *ar) 2960 { 2961 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2962 2963 /* Currently hif_power_up performs effectively a reset and hif_stop 2964 * resets the chip as well so there's no point in resetting here. 2965 */ 2966 } 2967 2968 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2969 { 2970 /* Nothing to do; the important stuff is in the driver suspend. */ 2971 return 0; 2972 } 2973 2974 #ifdef CONFIG_PM 2975 static int ath10k_pci_suspend(struct ath10k *ar) 2976 { 2977 /* The grace timer can still be counting down and ar->ps_awake be true. 2978 * It is known that the device may be asleep after resuming regardless 2979 * of the SoC powersave state before suspending. Hence make sure the 2980 * device is asleep before proceeding. 2981 */ 2982 ath10k_pci_sleep_sync(ar); 2983 2984 return 0; 2985 } 2986 #endif 2987 2988 static int ath10k_pci_hif_resume(struct ath10k *ar) 2989 { 2990 /* Nothing to do; the important stuff is in the driver resume. */ 2991 return 0; 2992 } 2993 2994 #ifdef CONFIG_PM 2995 static int ath10k_pci_resume(struct ath10k *ar) 2996 { 2997 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2998 struct pci_dev *pdev = ar_pci->pdev; 2999 u32 val; 3000 int ret = 0; 3001 3002 ret = ath10k_pci_force_wake(ar); 3003 if (ret) { 3004 ath10k_err(ar, "failed to wake up target: %d\n", ret); 3005 return ret; 3006 } 3007 3008 /* Suspend/Resume resets the PCI configuration space, so we have to 3009 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 3010 * from interfering with C3 CPU state. pci_restore_state won't help 3011 * here since it only restores the first 64 bytes pci config header. 3012 */ 3013 pci_read_config_dword(pdev, 0x40, &val); 3014 if ((val & 0x0000ff00) != 0) 3015 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 3016 3017 return ret; 3018 } 3019 #endif 3020 3021 static bool ath10k_pci_validate_cal(void *data, size_t size) 3022 { 3023 __le16 *cal_words = data; 3024 u16 checksum = 0; 3025 size_t i; 3026 3027 if (size % 2 != 0) 3028 return false; 3029 3030 for (i = 0; i < size / 2; i++) 3031 checksum ^= le16_to_cpu(cal_words[i]); 3032 3033 return checksum == 0xffff; 3034 } 3035 3036 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 3037 { 3038 /* Enable SI clock */ 3039 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 3040 3041 /* Configure GPIOs for I2C operation */ 3042 ath10k_pci_write32(ar, 3043 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 3044 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 3045 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 3046 GPIO_PIN0_CONFIG) | 3047 SM(1, GPIO_PIN0_PAD_PULL)); 3048 3049 ath10k_pci_write32(ar, 3050 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 3051 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 3052 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 3053 SM(1, GPIO_PIN0_PAD_PULL)); 3054 3055 ath10k_pci_write32(ar, 3056 GPIO_BASE_ADDRESS + 3057 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 3058 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 3059 3060 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 3061 ath10k_pci_write32(ar, 3062 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 3063 SM(1, SI_CONFIG_ERR_INT) | 3064 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 3065 SM(1, SI_CONFIG_I2C) | 3066 SM(1, SI_CONFIG_POS_SAMPLE) | 3067 SM(1, SI_CONFIG_INACTIVE_DATA) | 3068 SM(1, SI_CONFIG_INACTIVE_CLK) | 3069 SM(8, SI_CONFIG_DIVIDER)); 3070 } 3071 3072 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 3073 { 3074 u32 reg; 3075 int wait_limit; 3076 3077 /* set device select byte and for the read operation */ 3078 reg = QCA9887_EEPROM_SELECT_READ | 3079 SM(addr, QCA9887_EEPROM_ADDR_LO) | 3080 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 3081 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 3082 3083 /* write transmit data, transfer length, and START bit */ 3084 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 3085 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 3086 SM(4, SI_CS_TX_CNT)); 3087 3088 /* wait max 1 sec */ 3089 wait_limit = 100000; 3090 3091 /* wait for SI_CS_DONE_INT */ 3092 do { 3093 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 3094 if (MS(reg, SI_CS_DONE_INT)) 3095 break; 3096 3097 wait_limit--; 3098 udelay(10); 3099 } while (wait_limit > 0); 3100 3101 if (!MS(reg, SI_CS_DONE_INT)) { 3102 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 3103 addr); 3104 return -ETIMEDOUT; 3105 } 3106 3107 /* clear SI_CS_DONE_INT */ 3108 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 3109 3110 if (MS(reg, SI_CS_DONE_ERR)) { 3111 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 3112 return -EIO; 3113 } 3114 3115 /* extract receive data */ 3116 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 3117 *out = reg; 3118 3119 return 0; 3120 } 3121 3122 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 3123 size_t *data_len) 3124 { 3125 u8 *caldata = NULL; 3126 size_t calsize, i; 3127 int ret; 3128 3129 if (!QCA_REV_9887(ar)) 3130 return -EOPNOTSUPP; 3131 3132 calsize = ar->hw_params.cal_data_len; 3133 caldata = kmalloc(calsize, GFP_KERNEL); 3134 if (!caldata) 3135 return -ENOMEM; 3136 3137 ath10k_pci_enable_eeprom(ar); 3138 3139 for (i = 0; i < calsize; i++) { 3140 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 3141 if (ret) 3142 goto err_free; 3143 } 3144 3145 if (!ath10k_pci_validate_cal(caldata, calsize)) 3146 goto err_free; 3147 3148 *data = caldata; 3149 *data_len = calsize; 3150 3151 return 0; 3152 3153 err_free: 3154 kfree(caldata); 3155 3156 return -EINVAL; 3157 } 3158 3159 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 3160 .tx_sg = ath10k_pci_hif_tx_sg, 3161 .diag_read = ath10k_pci_hif_diag_read, 3162 .diag_write = ath10k_pci_diag_write_mem, 3163 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 3164 .start = ath10k_pci_hif_start, 3165 .stop = ath10k_pci_hif_stop, 3166 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 3167 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 3168 .send_complete_check = ath10k_pci_hif_send_complete_check, 3169 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 3170 .power_up = ath10k_pci_hif_power_up, 3171 .power_down = ath10k_pci_hif_power_down, 3172 .read32 = ath10k_pci_read32, 3173 .write32 = ath10k_pci_write32, 3174 .suspend = ath10k_pci_hif_suspend, 3175 .resume = ath10k_pci_hif_resume, 3176 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 3177 }; 3178 3179 /* 3180 * Top-level interrupt handler for all PCI interrupts from a Target. 3181 * When a block of MSI interrupts is allocated, this top-level handler 3182 * is not used; instead, we directly call the correct sub-handler. 3183 */ 3184 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 3185 { 3186 struct ath10k *ar = arg; 3187 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3188 int ret; 3189 3190 if (ath10k_pci_has_device_gone(ar)) 3191 return IRQ_NONE; 3192 3193 ret = ath10k_pci_force_wake(ar); 3194 if (ret) { 3195 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 3196 return IRQ_NONE; 3197 } 3198 3199 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 3200 !ath10k_pci_irq_pending(ar)) 3201 return IRQ_NONE; 3202 3203 ath10k_pci_disable_and_clear_legacy_irq(ar); 3204 ath10k_pci_irq_msi_fw_mask(ar); 3205 napi_schedule(&ar->napi); 3206 3207 return IRQ_HANDLED; 3208 } 3209 3210 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 3211 { 3212 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 3213 int done = 0; 3214 3215 if (ath10k_pci_has_fw_crashed(ar)) { 3216 ath10k_pci_fw_crashed_clear(ar); 3217 ath10k_pci_fw_crashed_dump(ar); 3218 napi_complete(ctx); 3219 return done; 3220 } 3221 3222 ath10k_ce_per_engine_service_any(ar); 3223 3224 done = ath10k_htt_txrx_compl_task(ar, budget); 3225 3226 if (done < budget) { 3227 napi_complete_done(ctx, done); 3228 /* In case of MSI, it is possible that interrupts are received 3229 * while NAPI poll is inprogress. So pending interrupts that are 3230 * received after processing all copy engine pipes by NAPI poll 3231 * will not be handled again. This is causing failure to 3232 * complete boot sequence in x86 platform. So before enabling 3233 * interrupts safer to check for pending interrupts for 3234 * immediate servicing. 3235 */ 3236 if (ath10k_ce_interrupt_summary(ar)) { 3237 napi_reschedule(ctx); 3238 goto out; 3239 } 3240 ath10k_pci_enable_legacy_irq(ar); 3241 ath10k_pci_irq_msi_fw_unmask(ar); 3242 } 3243 3244 out: 3245 return done; 3246 } 3247 3248 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 3249 { 3250 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3251 int ret; 3252 3253 ret = request_irq(ar_pci->pdev->irq, 3254 ath10k_pci_interrupt_handler, 3255 IRQF_SHARED, "ath10k_pci", ar); 3256 if (ret) { 3257 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 3258 ar_pci->pdev->irq, ret); 3259 return ret; 3260 } 3261 3262 return 0; 3263 } 3264 3265 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 3266 { 3267 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3268 int ret; 3269 3270 ret = request_irq(ar_pci->pdev->irq, 3271 ath10k_pci_interrupt_handler, 3272 IRQF_SHARED, "ath10k_pci", ar); 3273 if (ret) { 3274 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 3275 ar_pci->pdev->irq, ret); 3276 return ret; 3277 } 3278 3279 return 0; 3280 } 3281 3282 static int ath10k_pci_request_irq(struct ath10k *ar) 3283 { 3284 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3285 3286 switch (ar_pci->oper_irq_mode) { 3287 case ATH10K_PCI_IRQ_LEGACY: 3288 return ath10k_pci_request_irq_legacy(ar); 3289 case ATH10K_PCI_IRQ_MSI: 3290 return ath10k_pci_request_irq_msi(ar); 3291 default: 3292 return -EINVAL; 3293 } 3294 } 3295 3296 static void ath10k_pci_free_irq(struct ath10k *ar) 3297 { 3298 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3299 3300 free_irq(ar_pci->pdev->irq, ar); 3301 } 3302 3303 void ath10k_pci_init_napi(struct ath10k *ar) 3304 { 3305 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); 3306 } 3307 3308 static int ath10k_pci_init_irq(struct ath10k *ar) 3309 { 3310 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3311 int ret; 3312 3313 ath10k_pci_init_napi(ar); 3314 3315 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 3316 ath10k_info(ar, "limiting irq mode to: %d\n", 3317 ath10k_pci_irq_mode); 3318 3319 /* Try MSI */ 3320 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 3321 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 3322 ret = pci_enable_msi(ar_pci->pdev); 3323 if (ret == 0) 3324 return 0; 3325 3326 /* MHI failed, try legacy irq next */ 3327 } 3328 3329 /* Try legacy irq 3330 * 3331 * A potential race occurs here: The CORE_BASE write 3332 * depends on target correctly decoding AXI address but 3333 * host won't know when target writes BAR to CORE_CTRL. 3334 * This write might get lost if target has NOT written BAR. 3335 * For now, fix the race by repeating the write in below 3336 * synchronization checking. 3337 */ 3338 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 3339 3340 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3341 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3342 3343 return 0; 3344 } 3345 3346 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 3347 { 3348 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3349 0); 3350 } 3351 3352 static int ath10k_pci_deinit_irq(struct ath10k *ar) 3353 { 3354 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3355 3356 switch (ar_pci->oper_irq_mode) { 3357 case ATH10K_PCI_IRQ_LEGACY: 3358 ath10k_pci_deinit_irq_legacy(ar); 3359 break; 3360 default: 3361 pci_disable_msi(ar_pci->pdev); 3362 break; 3363 } 3364 3365 return 0; 3366 } 3367 3368 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 3369 { 3370 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3371 unsigned long timeout; 3372 u32 val; 3373 3374 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 3375 3376 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 3377 3378 do { 3379 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 3380 3381 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 3382 val); 3383 3384 /* target should never return this */ 3385 if (val == 0xffffffff) 3386 continue; 3387 3388 /* the device has crashed so don't bother trying anymore */ 3389 if (val & FW_IND_EVENT_PENDING) 3390 break; 3391 3392 if (val & FW_IND_INITIALIZED) 3393 break; 3394 3395 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 3396 /* Fix potential race by repeating CORE_BASE writes */ 3397 ath10k_pci_enable_legacy_irq(ar); 3398 3399 mdelay(10); 3400 } while (time_before(jiffies, timeout)); 3401 3402 ath10k_pci_disable_and_clear_legacy_irq(ar); 3403 ath10k_pci_irq_msi_fw_mask(ar); 3404 3405 if (val == 0xffffffff) { 3406 ath10k_err(ar, "failed to read device register, device is gone\n"); 3407 return -EIO; 3408 } 3409 3410 if (val & FW_IND_EVENT_PENDING) { 3411 ath10k_warn(ar, "device has crashed during init\n"); 3412 return -ECOMM; 3413 } 3414 3415 if (!(val & FW_IND_INITIALIZED)) { 3416 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3417 val); 3418 return -ETIMEDOUT; 3419 } 3420 3421 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3422 return 0; 3423 } 3424 3425 static int ath10k_pci_cold_reset(struct ath10k *ar) 3426 { 3427 u32 val; 3428 3429 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3430 3431 spin_lock_bh(&ar->data_lock); 3432 3433 ar->stats.fw_cold_reset_counter++; 3434 3435 spin_unlock_bh(&ar->data_lock); 3436 3437 /* Put Target, including PCIe, into RESET. */ 3438 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3439 val |= 1; 3440 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3441 3442 /* After writing into SOC_GLOBAL_RESET to put device into 3443 * reset and pulling out of reset pcie may not be stable 3444 * for any immediate pcie register access and cause bus error, 3445 * add delay before any pcie access request to fix this issue. 3446 */ 3447 msleep(20); 3448 3449 /* Pull Target, including PCIe, out of RESET. */ 3450 val &= ~1; 3451 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3452 3453 msleep(20); 3454 3455 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3456 3457 return 0; 3458 } 3459 3460 static int ath10k_pci_claim(struct ath10k *ar) 3461 { 3462 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3463 struct pci_dev *pdev = ar_pci->pdev; 3464 int ret; 3465 3466 pci_set_drvdata(pdev, ar); 3467 3468 ret = pci_enable_device(pdev); 3469 if (ret) { 3470 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3471 return ret; 3472 } 3473 3474 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3475 if (ret) { 3476 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3477 ret); 3478 goto err_device; 3479 } 3480 3481 /* Target expects 32 bit DMA. Enforce it. */ 3482 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3483 if (ret) { 3484 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3485 goto err_region; 3486 } 3487 3488 pci_set_master(pdev); 3489 3490 #if defined(__FreeBSD__) 3491 linuxkpi_pcim_want_to_use_bus_functions(pdev); 3492 #endif 3493 3494 /* Arrange for access to Target SoC registers. */ 3495 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3496 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3497 if (!ar_pci->mem) { 3498 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3499 ret = -EIO; 3500 goto err_master; 3501 } 3502 3503 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3504 return 0; 3505 3506 err_master: 3507 pci_clear_master(pdev); 3508 3509 err_region: 3510 pci_release_region(pdev, BAR_NUM); 3511 3512 err_device: 3513 pci_disable_device(pdev); 3514 3515 return ret; 3516 } 3517 3518 static void ath10k_pci_release(struct ath10k *ar) 3519 { 3520 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3521 struct pci_dev *pdev = ar_pci->pdev; 3522 3523 pci_iounmap(pdev, ar_pci->mem); 3524 pci_release_region(pdev, BAR_NUM); 3525 pci_clear_master(pdev); 3526 pci_disable_device(pdev); 3527 } 3528 3529 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3530 { 3531 const struct ath10k_pci_supp_chip *supp_chip; 3532 int i; 3533 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3534 3535 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3536 supp_chip = &ath10k_pci_supp_chips[i]; 3537 3538 if (supp_chip->dev_id == dev_id && 3539 supp_chip->rev_id == rev_id) 3540 return true; 3541 } 3542 3543 return false; 3544 } 3545 3546 int ath10k_pci_setup_resource(struct ath10k *ar) 3547 { 3548 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3549 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3550 int ret; 3551 3552 spin_lock_init(&ce->ce_lock); 3553 spin_lock_init(&ar_pci->ps_lock); 3554 mutex_init(&ar_pci->ce_diag_mutex); 3555 3556 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); 3557 3558 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3559 3560 ar_pci->attr = kmemdup(pci_host_ce_config_wlan, 3561 sizeof(pci_host_ce_config_wlan), 3562 GFP_KERNEL); 3563 if (!ar_pci->attr) 3564 return -ENOMEM; 3565 3566 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, 3567 sizeof(pci_target_ce_config_wlan), 3568 GFP_KERNEL); 3569 if (!ar_pci->pipe_config) { 3570 ret = -ENOMEM; 3571 goto err_free_attr; 3572 } 3573 3574 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, 3575 sizeof(pci_target_service_to_ce_map_wlan), 3576 GFP_KERNEL); 3577 if (!ar_pci->serv_to_pipe) { 3578 ret = -ENOMEM; 3579 goto err_free_pipe_config; 3580 } 3581 3582 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3583 ath10k_pci_override_ce_config(ar); 3584 3585 ret = ath10k_pci_alloc_pipes(ar); 3586 if (ret) { 3587 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3588 ret); 3589 goto err_free_serv_to_pipe; 3590 } 3591 3592 return 0; 3593 3594 err_free_serv_to_pipe: 3595 kfree(ar_pci->serv_to_pipe); 3596 err_free_pipe_config: 3597 kfree(ar_pci->pipe_config); 3598 err_free_attr: 3599 kfree(ar_pci->attr); 3600 return ret; 3601 } 3602 3603 void ath10k_pci_release_resource(struct ath10k *ar) 3604 { 3605 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3606 3607 ath10k_pci_rx_retry_sync(ar); 3608 netif_napi_del(&ar->napi); 3609 ath10k_pci_ce_deinit(ar); 3610 ath10k_pci_free_pipes(ar); 3611 kfree(ar_pci->attr); 3612 kfree(ar_pci->pipe_config); 3613 kfree(ar_pci->serv_to_pipe); 3614 } 3615 3616 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3617 .read32 = ath10k_bus_pci_read32, 3618 .write32 = ath10k_bus_pci_write32, 3619 .get_num_banks = ath10k_pci_get_num_banks, 3620 }; 3621 3622 static int ath10k_pci_probe(struct pci_dev *pdev, 3623 const struct pci_device_id *pci_dev) 3624 { 3625 int ret = 0; 3626 struct ath10k *ar; 3627 struct ath10k_pci *ar_pci; 3628 enum ath10k_hw_rev hw_rev; 3629 struct ath10k_bus_params bus_params = {}; 3630 bool pci_ps, is_qca988x = false; 3631 int (*pci_soft_reset)(struct ath10k *ar); 3632 int (*pci_hard_reset)(struct ath10k *ar); 3633 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3634 3635 switch (pci_dev->device) { 3636 case QCA988X_2_0_DEVICE_ID_UBNT: 3637 case QCA988X_2_0_DEVICE_ID: 3638 hw_rev = ATH10K_HW_QCA988X; 3639 pci_ps = false; 3640 is_qca988x = true; 3641 pci_soft_reset = ath10k_pci_warm_reset; 3642 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3643 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3644 break; 3645 case QCA9887_1_0_DEVICE_ID: 3646 hw_rev = ATH10K_HW_QCA9887; 3647 pci_ps = false; 3648 pci_soft_reset = ath10k_pci_warm_reset; 3649 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3650 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3651 break; 3652 case QCA6164_2_1_DEVICE_ID: 3653 case QCA6174_2_1_DEVICE_ID: 3654 hw_rev = ATH10K_HW_QCA6174; 3655 pci_ps = true; 3656 pci_soft_reset = ath10k_pci_warm_reset; 3657 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3658 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3659 break; 3660 case QCA99X0_2_0_DEVICE_ID: 3661 hw_rev = ATH10K_HW_QCA99X0; 3662 pci_ps = false; 3663 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3664 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3665 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3666 break; 3667 case QCA9984_1_0_DEVICE_ID: 3668 hw_rev = ATH10K_HW_QCA9984; 3669 pci_ps = false; 3670 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3671 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3672 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3673 break; 3674 case QCA9888_2_0_DEVICE_ID: 3675 hw_rev = ATH10K_HW_QCA9888; 3676 pci_ps = false; 3677 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3678 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3679 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3680 break; 3681 case QCA9377_1_0_DEVICE_ID: 3682 hw_rev = ATH10K_HW_QCA9377; 3683 pci_ps = true; 3684 pci_soft_reset = ath10k_pci_warm_reset; 3685 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3686 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3687 break; 3688 default: 3689 WARN_ON(1); 3690 return -ENOTSUPP; 3691 } 3692 3693 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3694 hw_rev, &ath10k_pci_hif_ops); 3695 if (!ar) { 3696 dev_err(&pdev->dev, "failed to allocate core\n"); 3697 return -ENOMEM; 3698 } 3699 3700 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3701 pdev->vendor, pdev->device, 3702 pdev->subsystem_vendor, pdev->subsystem_device); 3703 3704 ar_pci = ath10k_pci_priv(ar); 3705 ar_pci->pdev = pdev; 3706 ar_pci->dev = &pdev->dev; 3707 ar_pci->ar = ar; 3708 ar->dev_id = pci_dev->device; 3709 ar_pci->pci_ps = pci_ps; 3710 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3711 ar_pci->pci_soft_reset = pci_soft_reset; 3712 ar_pci->pci_hard_reset = pci_hard_reset; 3713 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3714 ar->ce_priv = &ar_pci->ce; 3715 3716 ar->id.vendor = pdev->vendor; 3717 ar->id.device = pdev->device; 3718 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3719 ar->id.subsystem_device = pdev->subsystem_device; 3720 3721 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3722 3723 ret = ath10k_pci_setup_resource(ar); 3724 if (ret) { 3725 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3726 goto err_core_destroy; 3727 } 3728 3729 ret = ath10k_pci_claim(ar); 3730 if (ret) { 3731 ath10k_err(ar, "failed to claim device: %d\n", ret); 3732 goto err_free_pipes; 3733 } 3734 3735 ret = ath10k_pci_force_wake(ar); 3736 if (ret) { 3737 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3738 goto err_sleep; 3739 } 3740 3741 ath10k_pci_ce_deinit(ar); 3742 ath10k_pci_irq_disable(ar); 3743 3744 ret = ath10k_pci_init_irq(ar); 3745 if (ret) { 3746 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3747 goto err_sleep; 3748 } 3749 3750 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3751 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3752 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3753 3754 ret = ath10k_pci_request_irq(ar); 3755 if (ret) { 3756 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3757 goto err_deinit_irq; 3758 } 3759 3760 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 3761 bus_params.link_can_suspend = true; 3762 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that 3763 * fall off the bus during chip_reset. These chips have the same pci 3764 * device id as the QCA9880 BR4A or 2R4E. So that's why the check. 3765 */ 3766 if (is_qca988x) { 3767 bus_params.chip_id = 3768 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3769 if (bus_params.chip_id != 0xffffffff) { 3770 if (!ath10k_pci_chip_is_supported(pdev->device, 3771 bus_params.chip_id)) { 3772 ret = -ENODEV; 3773 goto err_unsupported; 3774 } 3775 } 3776 } 3777 3778 ret = ath10k_pci_chip_reset(ar); 3779 if (ret) { 3780 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3781 goto err_free_irq; 3782 } 3783 3784 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3785 if (bus_params.chip_id == 0xffffffff) { 3786 ret = -ENODEV; 3787 goto err_unsupported; 3788 } 3789 3790 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { 3791 ret = -ENODEV; 3792 goto err_unsupported; 3793 } 3794 3795 ret = ath10k_core_register(ar, &bus_params); 3796 if (ret) { 3797 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3798 goto err_free_irq; 3799 } 3800 3801 return 0; 3802 3803 err_unsupported: 3804 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3805 pdev->device, bus_params.chip_id); 3806 3807 err_free_irq: 3808 ath10k_pci_free_irq(ar); 3809 3810 err_deinit_irq: 3811 ath10k_pci_release_resource(ar); 3812 3813 err_sleep: 3814 ath10k_pci_sleep_sync(ar); 3815 ath10k_pci_release(ar); 3816 3817 err_free_pipes: 3818 ath10k_pci_free_pipes(ar); 3819 3820 err_core_destroy: 3821 ath10k_core_destroy(ar); 3822 3823 return ret; 3824 } 3825 3826 static void ath10k_pci_remove(struct pci_dev *pdev) 3827 { 3828 struct ath10k *ar = pci_get_drvdata(pdev); 3829 3830 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3831 3832 if (!ar) 3833 return; 3834 3835 ath10k_core_unregister(ar); 3836 ath10k_pci_free_irq(ar); 3837 ath10k_pci_deinit_irq(ar); 3838 ath10k_pci_release_resource(ar); 3839 ath10k_pci_sleep_sync(ar); 3840 ath10k_pci_release(ar); 3841 ath10k_core_destroy(ar); 3842 } 3843 3844 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3845 3846 #ifdef CONFIG_PM 3847 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3848 { 3849 struct ath10k *ar = dev_get_drvdata(dev); 3850 int ret; 3851 3852 ret = ath10k_pci_suspend(ar); 3853 if (ret) 3854 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3855 3856 return ret; 3857 } 3858 3859 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3860 { 3861 struct ath10k *ar = dev_get_drvdata(dev); 3862 int ret; 3863 3864 ret = ath10k_pci_resume(ar); 3865 if (ret) 3866 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3867 3868 return ret; 3869 } 3870 3871 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3872 ath10k_pci_pm_suspend, 3873 ath10k_pci_pm_resume); 3874 #endif 3875 3876 static struct pci_driver ath10k_pci_driver = { 3877 .name = "ath10k_pci", 3878 .id_table = ath10k_pci_id_table, 3879 .probe = ath10k_pci_probe, 3880 .remove = ath10k_pci_remove, 3881 #ifdef CONFIG_PM 3882 .driver.pm = &ath10k_pci_pm_ops, 3883 #endif 3884 #if defined(__FreeBSD__) 3885 .bsddriver.name = KBUILD_MODNAME, 3886 /* Allow a possible native driver to attach. */ 3887 .bsd_probe_return = (BUS_PROBE_DEFAULT - 1), 3888 #endif 3889 }; 3890 3891 static int __init ath10k_pci_init(void) 3892 { 3893 int ret; 3894 3895 ret = pci_register_driver(&ath10k_pci_driver); 3896 if (ret) 3897 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3898 ret); 3899 3900 ret = ath10k_ahb_init(); 3901 if (ret) 3902 printk(KERN_ERR "ahb init failed: %d\n", ret); 3903 3904 return ret; 3905 } 3906 module_init(ath10k_pci_init); 3907 3908 static void __exit ath10k_pci_exit(void) 3909 { 3910 pci_unregister_driver(&ath10k_pci_driver); 3911 ath10k_ahb_exit(); 3912 } 3913 3914 module_exit(ath10k_pci_exit); 3915 3916 MODULE_AUTHOR("Qualcomm Atheros"); 3917 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3918 MODULE_LICENSE("Dual BSD/GPL"); 3919 #if defined(__FreeBSD__) 3920 MODULE_VERSION(ath10k_pci, 1); 3921 MODULE_DEPEND(ath10k_pci, linuxkpi, 1, 1, 1); 3922 MODULE_DEPEND(ath10k_pci, linuxkpi_wlan, 1, 1, 1); 3923 MODULE_DEPEND(ath10k_pci, athk_common, 1, 1, 1); 3924 #ifdef CONFIG_ATH10K_DEBUGFS 3925 MODULE_DEPEND(ath10k_pci, debugfs, 1, 1, 1); 3926 #endif 3927 #endif 3928 3929 /* QCA988x 2.0 firmware files */ 3930 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3931 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3932 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3933 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3934 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3935 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3936 3937 /* QCA9887 1.0 firmware files */ 3938 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3939 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3940 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3941 3942 /* QCA6174 2.1 firmware files */ 3943 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3944 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3945 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3946 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3947 3948 /* QCA6174 3.1 firmware files */ 3949 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3950 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3951 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3952 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3953 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3954 3955 /* QCA9377 1.0 firmware files */ 3956 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3957 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3958 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3959