1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "coredump.h" 8 9 #include <linux/devcoredump.h> 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 #include <linux/utsname.h> 13 14 #include "debug.h" 15 #include "hw.h" 16 17 static const struct ath10k_mem_section qca6174_hw21_register_sections[] = { 18 {0x800, 0x810}, 19 {0x820, 0x82C}, 20 {0x830, 0x8F4}, 21 {0x90C, 0x91C}, 22 {0xA14, 0xA18}, 23 {0xA84, 0xA94}, 24 {0xAA8, 0xAD4}, 25 {0xADC, 0xB40}, 26 {0x1000, 0x10A4}, 27 {0x10BC, 0x111C}, 28 {0x1134, 0x1138}, 29 {0x1144, 0x114C}, 30 {0x1150, 0x115C}, 31 {0x1160, 0x1178}, 32 {0x1240, 0x1260}, 33 {0x2000, 0x207C}, 34 {0x3000, 0x3014}, 35 {0x4000, 0x4014}, 36 {0x5000, 0x5124}, 37 {0x6000, 0x6040}, 38 {0x6080, 0x60CC}, 39 {0x6100, 0x611C}, 40 {0x6140, 0x61D8}, 41 {0x6200, 0x6238}, 42 {0x6240, 0x628C}, 43 {0x62C0, 0x62EC}, 44 {0x6380, 0x63E8}, 45 {0x6400, 0x6440}, 46 {0x6480, 0x64CC}, 47 {0x6500, 0x651C}, 48 {0x6540, 0x6580}, 49 {0x6600, 0x6638}, 50 {0x6640, 0x668C}, 51 {0x66C0, 0x66EC}, 52 {0x6780, 0x67E8}, 53 {0x7080, 0x708C}, 54 {0x70C0, 0x70C8}, 55 {0x7400, 0x741C}, 56 {0x7440, 0x7454}, 57 {0x7800, 0x7818}, 58 {0x8000, 0x8004}, 59 {0x8010, 0x8064}, 60 {0x8080, 0x8084}, 61 {0x80A0, 0x80A4}, 62 {0x80C0, 0x80C4}, 63 {0x80E0, 0x80F4}, 64 {0x8100, 0x8104}, 65 {0x8110, 0x812C}, 66 {0x9000, 0x9004}, 67 {0x9800, 0x982C}, 68 {0x9830, 0x9838}, 69 {0x9840, 0x986C}, 70 {0x9870, 0x9898}, 71 {0x9A00, 0x9C00}, 72 {0xD580, 0xD59C}, 73 {0xF000, 0xF0E0}, 74 {0xF140, 0xF190}, 75 {0xF250, 0xF25C}, 76 {0xF260, 0xF268}, 77 {0xF26C, 0xF2A8}, 78 {0x10008, 0x1000C}, 79 {0x10014, 0x10018}, 80 {0x1001C, 0x10020}, 81 {0x10024, 0x10028}, 82 {0x10030, 0x10034}, 83 {0x10040, 0x10054}, 84 {0x10058, 0x1007C}, 85 {0x10080, 0x100C4}, 86 {0x100C8, 0x10114}, 87 {0x1012C, 0x10130}, 88 {0x10138, 0x10144}, 89 {0x10200, 0x10220}, 90 {0x10230, 0x10250}, 91 {0x10260, 0x10280}, 92 {0x10290, 0x102B0}, 93 {0x102C0, 0x102DC}, 94 {0x102E0, 0x102F4}, 95 {0x102FC, 0x1037C}, 96 {0x10380, 0x10390}, 97 {0x10800, 0x10828}, 98 {0x10840, 0x10844}, 99 {0x10880, 0x10884}, 100 {0x108C0, 0x108E8}, 101 {0x10900, 0x10928}, 102 {0x10940, 0x10944}, 103 {0x10980, 0x10984}, 104 {0x109C0, 0x109E8}, 105 {0x10A00, 0x10A28}, 106 {0x10A40, 0x10A50}, 107 {0x11000, 0x11028}, 108 {0x11030, 0x11034}, 109 {0x11038, 0x11068}, 110 {0x11070, 0x11074}, 111 {0x11078, 0x110A8}, 112 {0x110B0, 0x110B4}, 113 {0x110B8, 0x110E8}, 114 {0x110F0, 0x110F4}, 115 {0x110F8, 0x11128}, 116 {0x11138, 0x11144}, 117 {0x11178, 0x11180}, 118 {0x111B8, 0x111C0}, 119 {0x111F8, 0x11200}, 120 {0x11238, 0x1123C}, 121 {0x11270, 0x11274}, 122 {0x11278, 0x1127C}, 123 {0x112B0, 0x112B4}, 124 {0x112B8, 0x112BC}, 125 {0x112F0, 0x112F4}, 126 {0x112F8, 0x112FC}, 127 {0x11338, 0x1133C}, 128 {0x11378, 0x1137C}, 129 {0x113B8, 0x113BC}, 130 {0x113F8, 0x113FC}, 131 {0x11438, 0x11440}, 132 {0x11478, 0x11480}, 133 {0x114B8, 0x114BC}, 134 {0x114F8, 0x114FC}, 135 {0x11538, 0x1153C}, 136 {0x11578, 0x1157C}, 137 {0x115B8, 0x115BC}, 138 {0x115F8, 0x115FC}, 139 {0x11638, 0x1163C}, 140 {0x11678, 0x1167C}, 141 {0x116B8, 0x116BC}, 142 {0x116F8, 0x116FC}, 143 {0x11738, 0x1173C}, 144 {0x11778, 0x1177C}, 145 {0x117B8, 0x117BC}, 146 {0x117F8, 0x117FC}, 147 {0x17000, 0x1701C}, 148 {0x17020, 0x170AC}, 149 {0x18000, 0x18050}, 150 {0x18054, 0x18074}, 151 {0x18080, 0x180D4}, 152 {0x180DC, 0x18104}, 153 {0x18108, 0x1813C}, 154 {0x18144, 0x18148}, 155 {0x18168, 0x18174}, 156 {0x18178, 0x18180}, 157 {0x181C8, 0x181E0}, 158 {0x181E4, 0x181E8}, 159 {0x181EC, 0x1820C}, 160 {0x1825C, 0x18280}, 161 {0x18284, 0x18290}, 162 {0x18294, 0x182A0}, 163 {0x18300, 0x18304}, 164 {0x18314, 0x18320}, 165 {0x18328, 0x18350}, 166 {0x1835C, 0x1836C}, 167 {0x18370, 0x18390}, 168 {0x18398, 0x183AC}, 169 {0x183BC, 0x183D8}, 170 {0x183DC, 0x183F4}, 171 {0x18400, 0x186F4}, 172 {0x186F8, 0x1871C}, 173 {0x18720, 0x18790}, 174 {0x19800, 0x19830}, 175 {0x19834, 0x19840}, 176 {0x19880, 0x1989C}, 177 {0x198A4, 0x198B0}, 178 {0x198BC, 0x19900}, 179 {0x19C00, 0x19C88}, 180 {0x19D00, 0x19D20}, 181 {0x19E00, 0x19E7C}, 182 {0x19E80, 0x19E94}, 183 {0x19E98, 0x19EAC}, 184 {0x19EB0, 0x19EBC}, 185 {0x19F70, 0x19F74}, 186 {0x19F80, 0x19F8C}, 187 {0x19FA0, 0x19FB4}, 188 {0x19FC0, 0x19FD8}, 189 {0x1A000, 0x1A200}, 190 {0x1A204, 0x1A210}, 191 {0x1A228, 0x1A22C}, 192 {0x1A230, 0x1A248}, 193 {0x1A250, 0x1A270}, 194 {0x1A280, 0x1A290}, 195 {0x1A2A0, 0x1A2A4}, 196 {0x1A2C0, 0x1A2EC}, 197 {0x1A300, 0x1A3BC}, 198 {0x1A3F0, 0x1A3F4}, 199 {0x1A3F8, 0x1A434}, 200 {0x1A438, 0x1A444}, 201 {0x1A448, 0x1A468}, 202 {0x1A580, 0x1A58C}, 203 {0x1A644, 0x1A654}, 204 {0x1A670, 0x1A698}, 205 {0x1A6AC, 0x1A6B0}, 206 {0x1A6D0, 0x1A6D4}, 207 {0x1A6EC, 0x1A70C}, 208 {0x1A710, 0x1A738}, 209 {0x1A7C0, 0x1A7D0}, 210 {0x1A7D4, 0x1A7D8}, 211 {0x1A7DC, 0x1A7E4}, 212 {0x1A7F0, 0x1A7F8}, 213 {0x1A888, 0x1A89C}, 214 {0x1A8A8, 0x1A8AC}, 215 {0x1A8C0, 0x1A8DC}, 216 {0x1A8F0, 0x1A8FC}, 217 {0x1AE04, 0x1AE08}, 218 {0x1AE18, 0x1AE24}, 219 {0x1AF80, 0x1AF8C}, 220 {0x1AFA0, 0x1AFB4}, 221 {0x1B000, 0x1B200}, 222 {0x1B284, 0x1B288}, 223 {0x1B2D0, 0x1B2D8}, 224 {0x1B2DC, 0x1B2EC}, 225 {0x1B300, 0x1B340}, 226 {0x1B374, 0x1B378}, 227 {0x1B380, 0x1B384}, 228 {0x1B388, 0x1B38C}, 229 {0x1B404, 0x1B408}, 230 {0x1B420, 0x1B428}, 231 {0x1B440, 0x1B444}, 232 {0x1B448, 0x1B44C}, 233 {0x1B450, 0x1B458}, 234 {0x1B45C, 0x1B468}, 235 {0x1B584, 0x1B58C}, 236 {0x1B68C, 0x1B690}, 237 {0x1B6AC, 0x1B6B0}, 238 {0x1B7F0, 0x1B7F8}, 239 {0x1C800, 0x1CC00}, 240 {0x1CE00, 0x1CE04}, 241 {0x1CF80, 0x1CF84}, 242 {0x1D200, 0x1D800}, 243 {0x1E000, 0x20014}, 244 {0x20100, 0x20124}, 245 {0x21400, 0x217A8}, 246 {0x21800, 0x21BA8}, 247 {0x21C00, 0x21FA8}, 248 {0x22000, 0x223A8}, 249 {0x22400, 0x227A8}, 250 {0x22800, 0x22BA8}, 251 {0x22C00, 0x22FA8}, 252 {0x23000, 0x233A8}, 253 {0x24000, 0x24034}, 254 {0x26000, 0x26064}, 255 {0x27000, 0x27024}, 256 {0x34000, 0x3400C}, 257 {0x34400, 0x3445C}, 258 {0x34800, 0x3485C}, 259 {0x34C00, 0x34C5C}, 260 {0x35000, 0x3505C}, 261 {0x35400, 0x3545C}, 262 {0x35800, 0x3585C}, 263 {0x35C00, 0x35C5C}, 264 {0x36000, 0x3605C}, 265 {0x38000, 0x38064}, 266 {0x38070, 0x380E0}, 267 {0x3A000, 0x3A064}, 268 {0x40000, 0x400A4}, 269 {0x80000, 0x8000C}, 270 {0x80010, 0x80020}, 271 }; 272 273 static const struct ath10k_mem_section qca6174_hw30_sdio_register_sections[] = { 274 {0x800, 0x810}, 275 {0x820, 0x82C}, 276 {0x830, 0x8F4}, 277 {0x90C, 0x91C}, 278 {0xA14, 0xA18}, 279 {0xA84, 0xA94}, 280 {0xAA8, 0xAD4}, 281 {0xADC, 0xB40}, 282 {0x1000, 0x10A4}, 283 {0x10BC, 0x111C}, 284 {0x1134, 0x1138}, 285 {0x1144, 0x114C}, 286 {0x1150, 0x115C}, 287 {0x1160, 0x1178}, 288 {0x1240, 0x1260}, 289 {0x2000, 0x207C}, 290 {0x3000, 0x3014}, 291 {0x4000, 0x4014}, 292 {0x5000, 0x5124}, 293 {0x6000, 0x6040}, 294 {0x6080, 0x60CC}, 295 {0x6100, 0x611C}, 296 {0x6140, 0x61D8}, 297 {0x6200, 0x6238}, 298 {0x6240, 0x628C}, 299 {0x62C0, 0x62EC}, 300 {0x6380, 0x63E8}, 301 {0x6400, 0x6440}, 302 {0x6480, 0x64CC}, 303 {0x6500, 0x651C}, 304 {0x6540, 0x6580}, 305 {0x6600, 0x6638}, 306 {0x6640, 0x668C}, 307 {0x66C0, 0x66EC}, 308 {0x6780, 0x67E8}, 309 {0x7080, 0x708C}, 310 {0x70C0, 0x70C8}, 311 {0x7400, 0x741C}, 312 {0x7440, 0x7454}, 313 {0x7800, 0x7818}, 314 {0x8010, 0x8060}, 315 {0x8080, 0x8084}, 316 {0x80A0, 0x80A4}, 317 {0x80C0, 0x80C4}, 318 {0x80E0, 0x80ec}, 319 {0x8110, 0x8128}, 320 {0x9000, 0x9004}, 321 {0xF000, 0xF0E0}, 322 {0xF140, 0xF190}, 323 {0xF250, 0xF25C}, 324 {0xF260, 0xF268}, 325 {0xF26C, 0xF2A8}, 326 {0x10008, 0x1000C}, 327 {0x10014, 0x10018}, 328 {0x1001C, 0x10020}, 329 {0x10024, 0x10028}, 330 {0x10030, 0x10034}, 331 {0x10040, 0x10054}, 332 {0x10058, 0x1007C}, 333 {0x10080, 0x100C4}, 334 {0x100C8, 0x10114}, 335 {0x1012C, 0x10130}, 336 {0x10138, 0x10144}, 337 {0x10200, 0x10220}, 338 {0x10230, 0x10250}, 339 {0x10260, 0x10280}, 340 {0x10290, 0x102B0}, 341 {0x102C0, 0x102DC}, 342 {0x102E0, 0x102F4}, 343 {0x102FC, 0x1037C}, 344 {0x10380, 0x10390}, 345 {0x10800, 0x10828}, 346 {0x10840, 0x10844}, 347 {0x10880, 0x10884}, 348 {0x108C0, 0x108E8}, 349 {0x10900, 0x10928}, 350 {0x10940, 0x10944}, 351 {0x10980, 0x10984}, 352 {0x109C0, 0x109E8}, 353 {0x10A00, 0x10A28}, 354 {0x10A40, 0x10A50}, 355 {0x11000, 0x11028}, 356 {0x11030, 0x11034}, 357 {0x11038, 0x11068}, 358 {0x11070, 0x11074}, 359 {0x11078, 0x110A8}, 360 {0x110B0, 0x110B4}, 361 {0x110B8, 0x110E8}, 362 {0x110F0, 0x110F4}, 363 {0x110F8, 0x11128}, 364 {0x11138, 0x11144}, 365 {0x11178, 0x11180}, 366 {0x111B8, 0x111C0}, 367 {0x111F8, 0x11200}, 368 {0x11238, 0x1123C}, 369 {0x11270, 0x11274}, 370 {0x11278, 0x1127C}, 371 {0x112B0, 0x112B4}, 372 {0x112B8, 0x112BC}, 373 {0x112F0, 0x112F4}, 374 {0x112F8, 0x112FC}, 375 {0x11338, 0x1133C}, 376 {0x11378, 0x1137C}, 377 {0x113B8, 0x113BC}, 378 {0x113F8, 0x113FC}, 379 {0x11438, 0x11440}, 380 {0x11478, 0x11480}, 381 {0x114B8, 0x114BC}, 382 {0x114F8, 0x114FC}, 383 {0x11538, 0x1153C}, 384 {0x11578, 0x1157C}, 385 {0x115B8, 0x115BC}, 386 {0x115F8, 0x115FC}, 387 {0x11638, 0x1163C}, 388 {0x11678, 0x1167C}, 389 {0x116B8, 0x116BC}, 390 {0x116F8, 0x116FC}, 391 {0x11738, 0x1173C}, 392 {0x11778, 0x1177C}, 393 {0x117B8, 0x117BC}, 394 {0x117F8, 0x117FC}, 395 {0x17000, 0x1701C}, 396 {0x17020, 0x170AC}, 397 {0x18000, 0x18050}, 398 {0x18054, 0x18074}, 399 {0x18080, 0x180D4}, 400 {0x180DC, 0x18104}, 401 {0x18108, 0x1813C}, 402 {0x18144, 0x18148}, 403 {0x18168, 0x18174}, 404 {0x18178, 0x18180}, 405 {0x181C8, 0x181E0}, 406 {0x181E4, 0x181E8}, 407 {0x181EC, 0x1820C}, 408 {0x1825C, 0x18280}, 409 {0x18284, 0x18290}, 410 {0x18294, 0x182A0}, 411 {0x18300, 0x18304}, 412 {0x18314, 0x18320}, 413 {0x18328, 0x18350}, 414 {0x1835C, 0x1836C}, 415 {0x18370, 0x18390}, 416 {0x18398, 0x183AC}, 417 {0x183BC, 0x183D8}, 418 {0x183DC, 0x183F4}, 419 {0x18400, 0x186F4}, 420 {0x186F8, 0x1871C}, 421 {0x18720, 0x18790}, 422 {0x19800, 0x19830}, 423 {0x19834, 0x19840}, 424 {0x19880, 0x1989C}, 425 {0x198A4, 0x198B0}, 426 {0x198BC, 0x19900}, 427 {0x19C00, 0x19C88}, 428 {0x19D00, 0x19D20}, 429 {0x19E00, 0x19E7C}, 430 {0x19E80, 0x19E94}, 431 {0x19E98, 0x19EAC}, 432 {0x19EB0, 0x19EBC}, 433 {0x19F70, 0x19F74}, 434 {0x19F80, 0x19F8C}, 435 {0x19FA0, 0x19FB4}, 436 {0x19FC0, 0x19FD8}, 437 {0x1A000, 0x1A200}, 438 {0x1A204, 0x1A210}, 439 {0x1A228, 0x1A22C}, 440 {0x1A230, 0x1A248}, 441 {0x1A250, 0x1A270}, 442 {0x1A280, 0x1A290}, 443 {0x1A2A0, 0x1A2A4}, 444 {0x1A2C0, 0x1A2EC}, 445 {0x1A300, 0x1A3BC}, 446 {0x1A3F0, 0x1A3F4}, 447 {0x1A3F8, 0x1A434}, 448 {0x1A438, 0x1A444}, 449 {0x1A448, 0x1A468}, 450 {0x1A580, 0x1A58C}, 451 {0x1A644, 0x1A654}, 452 {0x1A670, 0x1A698}, 453 {0x1A6AC, 0x1A6B0}, 454 {0x1A6D0, 0x1A6D4}, 455 {0x1A6EC, 0x1A70C}, 456 {0x1A710, 0x1A738}, 457 {0x1A7C0, 0x1A7D0}, 458 {0x1A7D4, 0x1A7D8}, 459 {0x1A7DC, 0x1A7E4}, 460 {0x1A7F0, 0x1A7F8}, 461 {0x1A888, 0x1A89C}, 462 {0x1A8A8, 0x1A8AC}, 463 {0x1A8C0, 0x1A8DC}, 464 {0x1A8F0, 0x1A8FC}, 465 {0x1AE04, 0x1AE08}, 466 {0x1AE18, 0x1AE24}, 467 {0x1AF80, 0x1AF8C}, 468 {0x1AFA0, 0x1AFB4}, 469 {0x1B000, 0x1B200}, 470 {0x1B284, 0x1B288}, 471 {0x1B2D0, 0x1B2D8}, 472 {0x1B2DC, 0x1B2EC}, 473 {0x1B300, 0x1B340}, 474 {0x1B374, 0x1B378}, 475 {0x1B380, 0x1B384}, 476 {0x1B388, 0x1B38C}, 477 {0x1B404, 0x1B408}, 478 {0x1B420, 0x1B428}, 479 {0x1B440, 0x1B444}, 480 {0x1B448, 0x1B44C}, 481 {0x1B450, 0x1B458}, 482 {0x1B45C, 0x1B468}, 483 {0x1B584, 0x1B58C}, 484 {0x1B68C, 0x1B690}, 485 {0x1B6AC, 0x1B6B0}, 486 {0x1B7F0, 0x1B7F8}, 487 {0x1C800, 0x1CC00}, 488 {0x1CE00, 0x1CE04}, 489 {0x1CF80, 0x1CF84}, 490 {0x1D200, 0x1D800}, 491 {0x1E000, 0x20014}, 492 {0x20100, 0x20124}, 493 {0x21400, 0x217A8}, 494 {0x21800, 0x21BA8}, 495 {0x21C00, 0x21FA8}, 496 {0x22000, 0x223A8}, 497 {0x22400, 0x227A8}, 498 {0x22800, 0x22BA8}, 499 {0x22C00, 0x22FA8}, 500 {0x23000, 0x233A8}, 501 {0x24000, 0x24034}, 502 503 /* EFUSE0,1,2 is disabled here 504 * because its state may be reset 505 * 506 * {0x24800, 0x24804}, 507 * {0x25000, 0x25004}, 508 * {0x25800, 0x25804}, 509 */ 510 511 {0x26000, 0x26064}, 512 {0x27000, 0x27024}, 513 {0x34000, 0x3400C}, 514 {0x34400, 0x3445C}, 515 {0x34800, 0x3485C}, 516 {0x34C00, 0x34C5C}, 517 {0x35000, 0x3505C}, 518 {0x35400, 0x3545C}, 519 {0x35800, 0x3585C}, 520 {0x35C00, 0x35C5C}, 521 {0x36000, 0x3605C}, 522 {0x38000, 0x38064}, 523 {0x38070, 0x380E0}, 524 {0x3A000, 0x3A074}, 525 526 /* DBI windows is skipped here, it can be only accessed when pcie 527 * is active (not in reset) and CORE_CTRL_PCIE_LTSSM_EN = 0 && 528 * PCIE_CTRL_APP_LTSSM_ENALBE=0. 529 * {0x3C000 , 0x3C004}, 530 */ 531 532 {0x40000, 0x400A4}, 533 534 /* SI register is skiped here. 535 * Because it will cause bus hang 536 * 537 * {0x50000, 0x50018}, 538 */ 539 540 {0x80000, 0x8000C}, 541 {0x80010, 0x80020}, 542 }; 543 544 static const struct ath10k_mem_section qca6174_hw30_register_sections[] = { 545 {0x800, 0x810}, 546 {0x820, 0x82C}, 547 {0x830, 0x8F4}, 548 {0x90C, 0x91C}, 549 {0xA14, 0xA18}, 550 {0xA84, 0xA94}, 551 {0xAA8, 0xAD4}, 552 {0xADC, 0xB40}, 553 {0x1000, 0x10A4}, 554 {0x10BC, 0x111C}, 555 {0x1134, 0x1138}, 556 {0x1144, 0x114C}, 557 {0x1150, 0x115C}, 558 {0x1160, 0x1178}, 559 {0x1240, 0x1260}, 560 {0x2000, 0x207C}, 561 {0x3000, 0x3014}, 562 {0x4000, 0x4014}, 563 {0x5000, 0x5124}, 564 {0x6000, 0x6040}, 565 {0x6080, 0x60CC}, 566 {0x6100, 0x611C}, 567 {0x6140, 0x61D8}, 568 {0x6200, 0x6238}, 569 {0x6240, 0x628C}, 570 {0x62C0, 0x62EC}, 571 {0x6380, 0x63E8}, 572 {0x6400, 0x6440}, 573 {0x6480, 0x64CC}, 574 {0x6500, 0x651C}, 575 {0x6540, 0x6580}, 576 {0x6600, 0x6638}, 577 {0x6640, 0x668C}, 578 {0x66C0, 0x66EC}, 579 {0x6780, 0x67E8}, 580 {0x7080, 0x708C}, 581 {0x70C0, 0x70C8}, 582 {0x7400, 0x741C}, 583 {0x7440, 0x7454}, 584 {0x7800, 0x7818}, 585 {0x8000, 0x8004}, 586 {0x8010, 0x8064}, 587 {0x8080, 0x8084}, 588 {0x80A0, 0x80A4}, 589 {0x80C0, 0x80C4}, 590 {0x80E0, 0x80F4}, 591 {0x8100, 0x8104}, 592 {0x8110, 0x812C}, 593 {0x9000, 0x9004}, 594 {0x9800, 0x982C}, 595 {0x9830, 0x9838}, 596 {0x9840, 0x986C}, 597 {0x9870, 0x9898}, 598 {0x9A00, 0x9C00}, 599 {0xD580, 0xD59C}, 600 {0xF000, 0xF0E0}, 601 {0xF140, 0xF190}, 602 {0xF250, 0xF25C}, 603 {0xF260, 0xF268}, 604 {0xF26C, 0xF2A8}, 605 {0x10008, 0x1000C}, 606 {0x10014, 0x10018}, 607 {0x1001C, 0x10020}, 608 {0x10024, 0x10028}, 609 {0x10030, 0x10034}, 610 {0x10040, 0x10054}, 611 {0x10058, 0x1007C}, 612 {0x10080, 0x100C4}, 613 {0x100C8, 0x10114}, 614 {0x1012C, 0x10130}, 615 {0x10138, 0x10144}, 616 {0x10200, 0x10220}, 617 {0x10230, 0x10250}, 618 {0x10260, 0x10280}, 619 {0x10290, 0x102B0}, 620 {0x102C0, 0x102DC}, 621 {0x102E0, 0x102F4}, 622 {0x102FC, 0x1037C}, 623 {0x10380, 0x10390}, 624 {0x10800, 0x10828}, 625 {0x10840, 0x10844}, 626 {0x10880, 0x10884}, 627 {0x108C0, 0x108E8}, 628 {0x10900, 0x10928}, 629 {0x10940, 0x10944}, 630 {0x10980, 0x10984}, 631 {0x109C0, 0x109E8}, 632 {0x10A00, 0x10A28}, 633 {0x10A40, 0x10A50}, 634 {0x11000, 0x11028}, 635 {0x11030, 0x11034}, 636 {0x11038, 0x11068}, 637 {0x11070, 0x11074}, 638 {0x11078, 0x110A8}, 639 {0x110B0, 0x110B4}, 640 {0x110B8, 0x110E8}, 641 {0x110F0, 0x110F4}, 642 {0x110F8, 0x11128}, 643 {0x11138, 0x11144}, 644 {0x11178, 0x11180}, 645 {0x111B8, 0x111C0}, 646 {0x111F8, 0x11200}, 647 {0x11238, 0x1123C}, 648 {0x11270, 0x11274}, 649 {0x11278, 0x1127C}, 650 {0x112B0, 0x112B4}, 651 {0x112B8, 0x112BC}, 652 {0x112F0, 0x112F4}, 653 {0x112F8, 0x112FC}, 654 {0x11338, 0x1133C}, 655 {0x11378, 0x1137C}, 656 {0x113B8, 0x113BC}, 657 {0x113F8, 0x113FC}, 658 {0x11438, 0x11440}, 659 {0x11478, 0x11480}, 660 {0x114B8, 0x114BC}, 661 {0x114F8, 0x114FC}, 662 {0x11538, 0x1153C}, 663 {0x11578, 0x1157C}, 664 {0x115B8, 0x115BC}, 665 {0x115F8, 0x115FC}, 666 {0x11638, 0x1163C}, 667 {0x11678, 0x1167C}, 668 {0x116B8, 0x116BC}, 669 {0x116F8, 0x116FC}, 670 {0x11738, 0x1173C}, 671 {0x11778, 0x1177C}, 672 {0x117B8, 0x117BC}, 673 {0x117F8, 0x117FC}, 674 {0x17000, 0x1701C}, 675 {0x17020, 0x170AC}, 676 {0x18000, 0x18050}, 677 {0x18054, 0x18074}, 678 {0x18080, 0x180D4}, 679 {0x180DC, 0x18104}, 680 {0x18108, 0x1813C}, 681 {0x18144, 0x18148}, 682 {0x18168, 0x18174}, 683 {0x18178, 0x18180}, 684 {0x181C8, 0x181E0}, 685 {0x181E4, 0x181E8}, 686 {0x181EC, 0x1820C}, 687 {0x1825C, 0x18280}, 688 {0x18284, 0x18290}, 689 {0x18294, 0x182A0}, 690 {0x18300, 0x18304}, 691 {0x18314, 0x18320}, 692 {0x18328, 0x18350}, 693 {0x1835C, 0x1836C}, 694 {0x18370, 0x18390}, 695 {0x18398, 0x183AC}, 696 {0x183BC, 0x183D8}, 697 {0x183DC, 0x183F4}, 698 {0x18400, 0x186F4}, 699 {0x186F8, 0x1871C}, 700 {0x18720, 0x18790}, 701 {0x19800, 0x19830}, 702 {0x19834, 0x19840}, 703 {0x19880, 0x1989C}, 704 {0x198A4, 0x198B0}, 705 {0x198BC, 0x19900}, 706 {0x19C00, 0x19C88}, 707 {0x19D00, 0x19D20}, 708 {0x19E00, 0x19E7C}, 709 {0x19E80, 0x19E94}, 710 {0x19E98, 0x19EAC}, 711 {0x19EB0, 0x19EBC}, 712 {0x19F70, 0x19F74}, 713 {0x19F80, 0x19F8C}, 714 {0x19FA0, 0x19FB4}, 715 {0x19FC0, 0x19FD8}, 716 {0x1A000, 0x1A200}, 717 {0x1A204, 0x1A210}, 718 {0x1A228, 0x1A22C}, 719 {0x1A230, 0x1A248}, 720 {0x1A250, 0x1A270}, 721 {0x1A280, 0x1A290}, 722 {0x1A2A0, 0x1A2A4}, 723 {0x1A2C0, 0x1A2EC}, 724 {0x1A300, 0x1A3BC}, 725 {0x1A3F0, 0x1A3F4}, 726 {0x1A3F8, 0x1A434}, 727 {0x1A438, 0x1A444}, 728 {0x1A448, 0x1A468}, 729 {0x1A580, 0x1A58C}, 730 {0x1A644, 0x1A654}, 731 {0x1A670, 0x1A698}, 732 {0x1A6AC, 0x1A6B0}, 733 {0x1A6D0, 0x1A6D4}, 734 {0x1A6EC, 0x1A70C}, 735 {0x1A710, 0x1A738}, 736 {0x1A7C0, 0x1A7D0}, 737 {0x1A7D4, 0x1A7D8}, 738 {0x1A7DC, 0x1A7E4}, 739 {0x1A7F0, 0x1A7F8}, 740 {0x1A888, 0x1A89C}, 741 {0x1A8A8, 0x1A8AC}, 742 {0x1A8C0, 0x1A8DC}, 743 {0x1A8F0, 0x1A8FC}, 744 {0x1AE04, 0x1AE08}, 745 {0x1AE18, 0x1AE24}, 746 {0x1AF80, 0x1AF8C}, 747 {0x1AFA0, 0x1AFB4}, 748 {0x1B000, 0x1B200}, 749 {0x1B284, 0x1B288}, 750 {0x1B2D0, 0x1B2D8}, 751 {0x1B2DC, 0x1B2EC}, 752 {0x1B300, 0x1B340}, 753 {0x1B374, 0x1B378}, 754 {0x1B380, 0x1B384}, 755 {0x1B388, 0x1B38C}, 756 {0x1B404, 0x1B408}, 757 {0x1B420, 0x1B428}, 758 {0x1B440, 0x1B444}, 759 {0x1B448, 0x1B44C}, 760 {0x1B450, 0x1B458}, 761 {0x1B45C, 0x1B468}, 762 {0x1B584, 0x1B58C}, 763 {0x1B68C, 0x1B690}, 764 {0x1B6AC, 0x1B6B0}, 765 {0x1B7F0, 0x1B7F8}, 766 {0x1C800, 0x1CC00}, 767 {0x1CE00, 0x1CE04}, 768 {0x1CF80, 0x1CF84}, 769 {0x1D200, 0x1D800}, 770 {0x1E000, 0x20014}, 771 {0x20100, 0x20124}, 772 {0x21400, 0x217A8}, 773 {0x21800, 0x21BA8}, 774 {0x21C00, 0x21FA8}, 775 {0x22000, 0x223A8}, 776 {0x22400, 0x227A8}, 777 {0x22800, 0x22BA8}, 778 {0x22C00, 0x22FA8}, 779 {0x23000, 0x233A8}, 780 {0x24000, 0x24034}, 781 {0x26000, 0x26064}, 782 {0x27000, 0x27024}, 783 {0x34000, 0x3400C}, 784 {0x34400, 0x3445C}, 785 {0x34800, 0x3485C}, 786 {0x34C00, 0x34C5C}, 787 {0x35000, 0x3505C}, 788 {0x35400, 0x3545C}, 789 {0x35800, 0x3585C}, 790 {0x35C00, 0x35C5C}, 791 {0x36000, 0x3605C}, 792 {0x38000, 0x38064}, 793 {0x38070, 0x380E0}, 794 {0x3A000, 0x3A074}, 795 {0x40000, 0x400A4}, 796 {0x80000, 0x8000C}, 797 {0x80010, 0x80020}, 798 }; 799 800 static const struct ath10k_mem_region qca6174_hw10_mem_regions[] = { 801 { 802 .type = ATH10K_MEM_REGION_TYPE_DRAM, 803 .start = 0x400000, 804 .len = 0x70000, 805 .name = "DRAM", 806 .section_table = { 807 .sections = NULL, 808 .size = 0, 809 }, 810 }, 811 { 812 .type = ATH10K_MEM_REGION_TYPE_REG, 813 814 /* RTC_SOC_BASE_ADDRESS */ 815 .start = 0x0, 816 817 /* WLAN_MBOX_BASE_ADDRESS - RTC_SOC_BASE_ADDRESS */ 818 .len = 0x800 - 0x0, 819 820 .name = "REG_PART1", 821 .section_table = { 822 .sections = NULL, 823 .size = 0, 824 }, 825 }, 826 { 827 .type = ATH10K_MEM_REGION_TYPE_REG, 828 829 /* STEREO_BASE_ADDRESS */ 830 .start = 0x27000, 831 832 /* USB_BASE_ADDRESS - STEREO_BASE_ADDRESS */ 833 .len = 0x60000 - 0x27000, 834 835 .name = "REG_PART2", 836 .section_table = { 837 .sections = NULL, 838 .size = 0, 839 }, 840 }, 841 }; 842 843 static const struct ath10k_mem_region qca6174_hw21_mem_regions[] = { 844 { 845 .type = ATH10K_MEM_REGION_TYPE_DRAM, 846 .start = 0x400000, 847 .len = 0x70000, 848 .name = "DRAM", 849 .section_table = { 850 .sections = NULL, 851 .size = 0, 852 }, 853 }, 854 { 855 .type = ATH10K_MEM_REGION_TYPE_AXI, 856 .start = 0xa0000, 857 .len = 0x18000, 858 .name = "AXI", 859 .section_table = { 860 .sections = NULL, 861 .size = 0, 862 }, 863 }, 864 { 865 .type = ATH10K_MEM_REGION_TYPE_REG, 866 .start = 0x800, 867 .len = 0x80020 - 0x800, 868 .name = "REG_TOTAL", 869 .section_table = { 870 .sections = qca6174_hw21_register_sections, 871 .size = ARRAY_SIZE(qca6174_hw21_register_sections), 872 }, 873 }, 874 }; 875 876 static const struct ath10k_mem_region qca6174_hw30_sdio_mem_regions[] = { 877 { 878 .type = ATH10K_MEM_REGION_TYPE_DRAM, 879 .start = 0x400000, 880 .len = 0xa8000, 881 .name = "DRAM", 882 .section_table = { 883 .sections = NULL, 884 .size = 0, 885 }, 886 }, 887 { 888 .type = ATH10K_MEM_REGION_TYPE_AXI, 889 .start = 0xa0000, 890 .len = 0x18000, 891 .name = "AXI", 892 .section_table = { 893 .sections = NULL, 894 .size = 0, 895 }, 896 }, 897 { 898 .type = ATH10K_MEM_REGION_TYPE_IRAM1, 899 .start = 0x00980000, 900 .len = 0x00080000, 901 .name = "IRAM1", 902 .section_table = { 903 .sections = NULL, 904 .size = 0, 905 }, 906 }, 907 { 908 .type = ATH10K_MEM_REGION_TYPE_IRAM2, 909 .start = 0x00a00000, 910 .len = 0x00040000, 911 .name = "IRAM2", 912 .section_table = { 913 .sections = NULL, 914 .size = 0, 915 }, 916 }, 917 { 918 .type = ATH10K_MEM_REGION_TYPE_REG, 919 .start = 0x800, 920 .len = 0x80020 - 0x800, 921 .name = "REG_TOTAL", 922 .section_table = { 923 .sections = qca6174_hw30_sdio_register_sections, 924 .size = ARRAY_SIZE(qca6174_hw30_sdio_register_sections), 925 }, 926 }, 927 }; 928 929 static const struct ath10k_mem_region qca6174_hw30_mem_regions[] = { 930 { 931 .type = ATH10K_MEM_REGION_TYPE_DRAM, 932 .start = 0x400000, 933 .len = 0xa8000, 934 .name = "DRAM", 935 .section_table = { 936 .sections = NULL, 937 .size = 0, 938 }, 939 }, 940 { 941 .type = ATH10K_MEM_REGION_TYPE_AXI, 942 .start = 0xa0000, 943 .len = 0x18000, 944 .name = "AXI", 945 .section_table = { 946 .sections = NULL, 947 .size = 0, 948 }, 949 }, 950 { 951 .type = ATH10K_MEM_REGION_TYPE_REG, 952 .start = 0x800, 953 .len = 0x80020 - 0x800, 954 .name = "REG_TOTAL", 955 .section_table = { 956 .sections = qca6174_hw30_register_sections, 957 .size = ARRAY_SIZE(qca6174_hw30_register_sections), 958 }, 959 }, 960 961 /* IRAM dump must be put last */ 962 { 963 .type = ATH10K_MEM_REGION_TYPE_IRAM1, 964 .start = 0x00980000, 965 .len = 0x00080000, 966 .name = "IRAM1", 967 .section_table = { 968 .sections = NULL, 969 .size = 0, 970 }, 971 }, 972 { 973 .type = ATH10K_MEM_REGION_TYPE_IRAM2, 974 .start = 0x00a00000, 975 .len = 0x00040000, 976 .name = "IRAM2", 977 .section_table = { 978 .sections = NULL, 979 .size = 0, 980 }, 981 }, 982 }; 983 984 static const struct ath10k_mem_region qca988x_hw20_mem_regions[] = { 985 { 986 .type = ATH10K_MEM_REGION_TYPE_DRAM, 987 .start = 0x400000, 988 .len = 0x50000, 989 .name = "DRAM", 990 .section_table = { 991 .sections = NULL, 992 .size = 0, 993 }, 994 }, 995 { 996 .type = ATH10K_MEM_REGION_TYPE_REG, 997 .start = 0x4000, 998 .len = 0x2000, 999 .name = "REG_PART1", 1000 .section_table = { 1001 .sections = NULL, 1002 .size = 0, 1003 }, 1004 }, 1005 { 1006 .type = ATH10K_MEM_REGION_TYPE_REG, 1007 .start = 0x8000, 1008 .len = 0x58000, 1009 .name = "REG_PART2", 1010 .section_table = { 1011 .sections = NULL, 1012 .size = 0, 1013 }, 1014 }, 1015 }; 1016 1017 static const struct ath10k_mem_region qca99x0_hw20_mem_regions[] = { 1018 { 1019 .type = ATH10K_MEM_REGION_TYPE_DRAM, 1020 .start = 0x400000, 1021 .len = 0x60000, 1022 .name = "DRAM", 1023 .section_table = { 1024 .sections = NULL, 1025 .size = 0, 1026 }, 1027 }, 1028 { 1029 .type = ATH10K_MEM_REGION_TYPE_REG, 1030 .start = 0x980000, 1031 .len = 0x50000, 1032 .name = "IRAM", 1033 .section_table = { 1034 .sections = NULL, 1035 .size = 0, 1036 }, 1037 }, 1038 { 1039 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 1040 .start = 0xC0000, 1041 .len = 0x40000, 1042 .name = "SRAM", 1043 .section_table = { 1044 .sections = NULL, 1045 .size = 0, 1046 }, 1047 }, 1048 { 1049 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1050 .start = 0x30000, 1051 .len = 0x7000, 1052 .name = "APB REG 1", 1053 .section_table = { 1054 .sections = NULL, 1055 .size = 0, 1056 }, 1057 }, 1058 { 1059 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1060 .start = 0x3f000, 1061 .len = 0x3000, 1062 .name = "APB REG 2", 1063 .section_table = { 1064 .sections = NULL, 1065 .size = 0, 1066 }, 1067 }, 1068 { 1069 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1070 .start = 0x43000, 1071 .len = 0x3000, 1072 .name = "WIFI REG", 1073 .section_table = { 1074 .sections = NULL, 1075 .size = 0, 1076 }, 1077 }, 1078 { 1079 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1080 .start = 0x4A000, 1081 .len = 0x5000, 1082 .name = "CE REG", 1083 .section_table = { 1084 .sections = NULL, 1085 .size = 0, 1086 }, 1087 }, 1088 { 1089 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1090 .start = 0x80000, 1091 .len = 0x6000, 1092 .name = "SOC REG", 1093 .section_table = { 1094 .sections = NULL, 1095 .size = 0, 1096 }, 1097 }, 1098 }; 1099 1100 static const struct ath10k_mem_region qca9984_hw10_mem_regions[] = { 1101 { 1102 .type = ATH10K_MEM_REGION_TYPE_DRAM, 1103 .start = 0x400000, 1104 .len = 0x80000, 1105 .name = "DRAM", 1106 .section_table = { 1107 .sections = NULL, 1108 .size = 0, 1109 }, 1110 }, 1111 { 1112 .type = ATH10K_MEM_REGION_TYPE_REG, 1113 .start = 0x980000, 1114 .len = 0x50000, 1115 .name = "IRAM", 1116 .section_table = { 1117 .sections = NULL, 1118 .size = 0, 1119 }, 1120 }, 1121 { 1122 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 1123 .start = 0xC0000, 1124 .len = 0x40000, 1125 .name = "SRAM", 1126 .section_table = { 1127 .sections = NULL, 1128 .size = 0, 1129 }, 1130 }, 1131 { 1132 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1133 .start = 0x30000, 1134 .len = 0x7000, 1135 .name = "APB REG 1", 1136 .section_table = { 1137 .sections = NULL, 1138 .size = 0, 1139 }, 1140 }, 1141 { 1142 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1143 .start = 0x3f000, 1144 .len = 0x3000, 1145 .name = "APB REG 2", 1146 .section_table = { 1147 .sections = NULL, 1148 .size = 0, 1149 }, 1150 }, 1151 { 1152 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1153 .start = 0x43000, 1154 .len = 0x3000, 1155 .name = "WIFI REG", 1156 .section_table = { 1157 .sections = NULL, 1158 .size = 0, 1159 }, 1160 }, 1161 { 1162 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1163 .start = 0x4A000, 1164 .len = 0x5000, 1165 .name = "CE REG", 1166 .section_table = { 1167 .sections = NULL, 1168 .size = 0, 1169 }, 1170 }, 1171 { 1172 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1173 .start = 0x80000, 1174 .len = 0x6000, 1175 .name = "SOC REG", 1176 .section_table = { 1177 .sections = NULL, 1178 .size = 0, 1179 }, 1180 }, 1181 }; 1182 1183 static const struct ath10k_mem_section ipq4019_soc_reg_range[] = { 1184 {0x080000, 0x080004}, 1185 {0x080020, 0x080024}, 1186 {0x080028, 0x080050}, 1187 {0x0800d4, 0x0800ec}, 1188 {0x08010c, 0x080118}, 1189 {0x080284, 0x080290}, 1190 {0x0802a8, 0x0802b8}, 1191 {0x0802dc, 0x08030c}, 1192 {0x082000, 0x083fff} 1193 }; 1194 1195 static const struct ath10k_mem_region qca4019_hw10_mem_regions[] = { 1196 { 1197 .type = ATH10K_MEM_REGION_TYPE_DRAM, 1198 .start = 0x400000, 1199 .len = 0x68000, 1200 .name = "DRAM", 1201 .section_table = { 1202 .sections = NULL, 1203 .size = 0, 1204 }, 1205 }, 1206 { 1207 .type = ATH10K_MEM_REGION_TYPE_REG, 1208 .start = 0xC0000, 1209 .len = 0x40000, 1210 .name = "SRAM", 1211 .section_table = { 1212 .sections = NULL, 1213 .size = 0, 1214 }, 1215 }, 1216 { 1217 .type = ATH10K_MEM_REGION_TYPE_REG, 1218 .start = 0x980000, 1219 .len = 0x50000, 1220 .name = "IRAM", 1221 .section_table = { 1222 .sections = NULL, 1223 .size = 0, 1224 }, 1225 }, 1226 { 1227 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1228 .start = 0x30000, 1229 .len = 0x7000, 1230 .name = "APB REG 1", 1231 .section_table = { 1232 .sections = NULL, 1233 .size = 0, 1234 }, 1235 }, 1236 { 1237 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1238 .start = 0x3f000, 1239 .len = 0x3000, 1240 .name = "APB REG 2", 1241 .section_table = { 1242 .sections = NULL, 1243 .size = 0, 1244 }, 1245 }, 1246 { 1247 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1248 .start = 0x43000, 1249 .len = 0x3000, 1250 .name = "WIFI REG", 1251 .section_table = { 1252 .sections = NULL, 1253 .size = 0, 1254 }, 1255 }, 1256 { 1257 .type = ATH10K_MEM_REGION_TYPE_IOREG, 1258 .start = 0x4A000, 1259 .len = 0x5000, 1260 .name = "CE REG", 1261 .section_table = { 1262 .sections = NULL, 1263 .size = 0, 1264 }, 1265 }, 1266 { 1267 .type = ATH10K_MEM_REGION_TYPE_REG, 1268 .start = 0x080000, 1269 .len = 0x083fff - 0x080000, 1270 .name = "REG_TOTAL", 1271 .section_table = { 1272 .sections = ipq4019_soc_reg_range, 1273 .size = ARRAY_SIZE(ipq4019_soc_reg_range), 1274 }, 1275 }, 1276 }; 1277 1278 static const struct ath10k_mem_region wcn399x_hw10_mem_regions[] = { 1279 { 1280 /* MSA region start is not fixed, hence it is assigned at runtime */ 1281 .type = ATH10K_MEM_REGION_TYPE_MSA, 1282 .len = 0x100000, 1283 .name = "DRAM", 1284 .section_table = { 1285 .sections = NULL, 1286 .size = 0, 1287 }, 1288 }, 1289 }; 1290 1291 static const struct ath10k_hw_mem_layout hw_mem_layouts[] = { 1292 { 1293 .hw_id = QCA6174_HW_1_0_VERSION, 1294 .hw_rev = ATH10K_HW_QCA6174, 1295 .bus = ATH10K_BUS_PCI, 1296 .region_table = { 1297 .regions = qca6174_hw10_mem_regions, 1298 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 1299 }, 1300 }, 1301 { 1302 .hw_id = QCA6174_HW_1_1_VERSION, 1303 .hw_rev = ATH10K_HW_QCA6174, 1304 .bus = ATH10K_BUS_PCI, 1305 .region_table = { 1306 .regions = qca6174_hw10_mem_regions, 1307 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 1308 }, 1309 }, 1310 { 1311 .hw_id = QCA6174_HW_1_3_VERSION, 1312 .hw_rev = ATH10K_HW_QCA6174, 1313 .bus = ATH10K_BUS_PCI, 1314 .region_table = { 1315 .regions = qca6174_hw10_mem_regions, 1316 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 1317 }, 1318 }, 1319 { 1320 .hw_id = QCA6174_HW_2_1_VERSION, 1321 .hw_rev = ATH10K_HW_QCA6174, 1322 .bus = ATH10K_BUS_PCI, 1323 .region_table = { 1324 .regions = qca6174_hw21_mem_regions, 1325 .size = ARRAY_SIZE(qca6174_hw21_mem_regions), 1326 }, 1327 }, 1328 { 1329 .hw_id = QCA6174_HW_3_0_VERSION, 1330 .hw_rev = ATH10K_HW_QCA6174, 1331 .bus = ATH10K_BUS_PCI, 1332 .region_table = { 1333 .regions = qca6174_hw30_mem_regions, 1334 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1335 }, 1336 }, 1337 { 1338 .hw_id = QCA6174_HW_3_2_VERSION, 1339 .hw_rev = ATH10K_HW_QCA6174, 1340 .bus = ATH10K_BUS_PCI, 1341 .region_table = { 1342 .regions = qca6174_hw30_mem_regions, 1343 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1344 }, 1345 }, 1346 { 1347 .hw_id = QCA6174_HW_3_2_VERSION, 1348 .hw_rev = ATH10K_HW_QCA6174, 1349 .bus = ATH10K_BUS_SDIO, 1350 .region_table = { 1351 .regions = qca6174_hw30_sdio_mem_regions, 1352 .size = ARRAY_SIZE(qca6174_hw30_sdio_mem_regions), 1353 }, 1354 }, 1355 { 1356 .hw_id = QCA9377_HW_1_1_DEV_VERSION, 1357 .hw_rev = ATH10K_HW_QCA9377, 1358 .bus = ATH10K_BUS_PCI, 1359 .region_table = { 1360 .regions = qca6174_hw30_mem_regions, 1361 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1362 }, 1363 }, 1364 { 1365 .hw_id = QCA988X_HW_2_0_VERSION, 1366 .hw_rev = ATH10K_HW_QCA988X, 1367 .bus = ATH10K_BUS_PCI, 1368 .region_table = { 1369 .regions = qca988x_hw20_mem_regions, 1370 .size = ARRAY_SIZE(qca988x_hw20_mem_regions), 1371 }, 1372 }, 1373 { 1374 .hw_id = QCA9984_HW_1_0_DEV_VERSION, 1375 .hw_rev = ATH10K_HW_QCA9984, 1376 .bus = ATH10K_BUS_PCI, 1377 .region_table = { 1378 .regions = qca9984_hw10_mem_regions, 1379 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1380 }, 1381 }, 1382 { 1383 .hw_id = QCA9888_HW_2_0_DEV_VERSION, 1384 .hw_rev = ATH10K_HW_QCA9888, 1385 .bus = ATH10K_BUS_PCI, 1386 .region_table = { 1387 .regions = qca9984_hw10_mem_regions, 1388 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1389 }, 1390 }, 1391 { 1392 .hw_id = QCA99X0_HW_2_0_DEV_VERSION, 1393 .hw_rev = ATH10K_HW_QCA99X0, 1394 .bus = ATH10K_BUS_PCI, 1395 .region_table = { 1396 .regions = qca99x0_hw20_mem_regions, 1397 .size = ARRAY_SIZE(qca99x0_hw20_mem_regions), 1398 }, 1399 }, 1400 { 1401 .hw_id = QCA4019_HW_1_0_DEV_VERSION, 1402 .hw_rev = ATH10K_HW_QCA4019, 1403 .bus = ATH10K_BUS_AHB, 1404 .region_table = { 1405 .regions = qca4019_hw10_mem_regions, 1406 .size = ARRAY_SIZE(qca4019_hw10_mem_regions), 1407 }, 1408 }, 1409 { 1410 .hw_id = WCN3990_HW_1_0_DEV_VERSION, 1411 .hw_rev = ATH10K_HW_WCN3990, 1412 .bus = ATH10K_BUS_SNOC, 1413 .region_table = { 1414 .regions = wcn399x_hw10_mem_regions, 1415 .size = ARRAY_SIZE(wcn399x_hw10_mem_regions), 1416 }, 1417 }, 1418 }; 1419 1420 static u32 ath10k_coredump_get_ramdump_size(struct ath10k *ar) 1421 { 1422 const struct ath10k_hw_mem_layout *hw; 1423 const struct ath10k_mem_region *mem_region; 1424 size_t size = 0; 1425 int i; 1426 1427 hw = ath10k_coredump_get_mem_layout(ar); 1428 1429 if (!hw) 1430 return 0; 1431 1432 mem_region = &hw->region_table.regions[0]; 1433 1434 for (i = 0; i < hw->region_table.size; i++) { 1435 size += mem_region->len; 1436 mem_region++; 1437 } 1438 1439 /* reserve space for the headers */ 1440 size += hw->region_table.size * sizeof(struct ath10k_dump_ram_data_hdr); 1441 1442 /* make sure it is aligned 16 bytes for debug message print out */ 1443 size = ALIGN(size, 16); 1444 1445 return size; 1446 } 1447 1448 const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar) 1449 { 1450 if (!test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1451 return NULL; 1452 1453 return _ath10k_coredump_get_mem_layout(ar); 1454 } 1455 EXPORT_SYMBOL(ath10k_coredump_get_mem_layout); 1456 1457 const struct ath10k_hw_mem_layout *_ath10k_coredump_get_mem_layout(struct ath10k *ar) 1458 { 1459 int i; 1460 1461 if (WARN_ON(ar->target_version == 0)) 1462 return NULL; 1463 1464 for (i = 0; i < ARRAY_SIZE(hw_mem_layouts); i++) { 1465 if (ar->target_version == hw_mem_layouts[i].hw_id && 1466 ar->hw_rev == hw_mem_layouts[i].hw_rev && 1467 hw_mem_layouts[i].bus == ar->hif.bus) 1468 return &hw_mem_layouts[i]; 1469 } 1470 1471 return NULL; 1472 } 1473 1474 struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar) 1475 { 1476 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1477 1478 lockdep_assert_held(&ar->dump_mutex); 1479 1480 if (ath10k_coredump_mask == 0) 1481 /* coredump disabled */ 1482 return NULL; 1483 1484 guid_gen(&crash_data->guid); 1485 ktime_get_real_ts64(&crash_data->timestamp); 1486 1487 return crash_data; 1488 } 1489 EXPORT_SYMBOL(ath10k_coredump_new); 1490 1491 static struct ath10k_dump_file_data *ath10k_coredump_build(struct ath10k *ar) 1492 { 1493 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1494 struct ath10k_ce_crash_hdr *ce_hdr; 1495 struct ath10k_dump_file_data *dump_data; 1496 struct ath10k_tlv_dump_data *dump_tlv; 1497 size_t hdr_len = sizeof(*dump_data); 1498 size_t len, sofar = 0; 1499 unsigned char *buf; 1500 1501 len = hdr_len; 1502 1503 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) 1504 len += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1505 1506 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) 1507 len += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1508 CE_COUNT * sizeof(ce_hdr->entries[0]); 1509 1510 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1511 len += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1512 1513 sofar += hdr_len; 1514 1515 /* This is going to get big when we start dumping FW RAM and such, 1516 * so go ahead and use vmalloc. 1517 */ 1518 buf = vzalloc(len); 1519 if (!buf) 1520 return NULL; 1521 1522 mutex_lock(&ar->dump_mutex); 1523 1524 dump_data = (struct ath10k_dump_file_data *)(buf); 1525 strscpy(dump_data->df_magic, "ATH10K-FW-DUMP", 1526 sizeof(dump_data->df_magic)); 1527 dump_data->len = cpu_to_le32(len); 1528 1529 dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION); 1530 1531 guid_copy(&dump_data->guid, &crash_data->guid); 1532 dump_data->chip_id = cpu_to_le32(ar->bus_param.chip_id); 1533 dump_data->bus_type = cpu_to_le32(0); 1534 dump_data->target_version = cpu_to_le32(ar->target_version); 1535 dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major); 1536 dump_data->fw_version_minor = cpu_to_le32(ar->fw_version_minor); 1537 dump_data->fw_version_release = cpu_to_le32(ar->fw_version_release); 1538 dump_data->fw_version_build = cpu_to_le32(ar->fw_version_build); 1539 dump_data->phy_capability = cpu_to_le32(ar->phy_capability); 1540 dump_data->hw_min_tx_power = cpu_to_le32(ar->hw_min_tx_power); 1541 dump_data->hw_max_tx_power = cpu_to_le32(ar->hw_max_tx_power); 1542 dump_data->ht_cap_info = cpu_to_le32(ar->ht_cap_info); 1543 dump_data->vht_cap_info = cpu_to_le32(ar->vht_cap_info); 1544 dump_data->num_rf_chains = cpu_to_le32(ar->num_rf_chains); 1545 1546 strscpy(dump_data->fw_ver, ar->hw->wiphy->fw_version, 1547 sizeof(dump_data->fw_ver)); 1548 1549 dump_data->kernel_ver_code = 0; 1550 strscpy(dump_data->kernel_ver, init_utsname()->release, 1551 sizeof(dump_data->kernel_ver)); 1552 1553 dump_data->tv_sec = cpu_to_le64(crash_data->timestamp.tv_sec); 1554 dump_data->tv_nsec = cpu_to_le64(crash_data->timestamp.tv_nsec); 1555 1556 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) { 1557 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1558 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_REGISTERS); 1559 dump_tlv->tlv_len = cpu_to_le32(sizeof(crash_data->registers)); 1560 memcpy(dump_tlv->tlv_data, &crash_data->registers, 1561 sizeof(crash_data->registers)); 1562 sofar += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1563 } 1564 1565 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) { 1566 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1567 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_CE_DATA); 1568 dump_tlv->tlv_len = cpu_to_le32(struct_size(ce_hdr, entries, 1569 CE_COUNT)); 1570 ce_hdr = (struct ath10k_ce_crash_hdr *)(dump_tlv->tlv_data); 1571 ce_hdr->ce_count = cpu_to_le32(CE_COUNT); 1572 memset(ce_hdr->reserved, 0, sizeof(ce_hdr->reserved)); 1573 memcpy(ce_hdr->entries, crash_data->ce_crash_data, 1574 CE_COUNT * sizeof(ce_hdr->entries[0])); 1575 sofar += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1576 CE_COUNT * sizeof(ce_hdr->entries[0]); 1577 } 1578 1579 /* Gather ram dump */ 1580 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1581 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1582 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_RAM_DATA); 1583 dump_tlv->tlv_len = cpu_to_le32(crash_data->ramdump_buf_len); 1584 if (crash_data->ramdump_buf_len) { 1585 memcpy(dump_tlv->tlv_data, crash_data->ramdump_buf, 1586 crash_data->ramdump_buf_len); 1587 sofar += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1588 } 1589 } 1590 1591 mutex_unlock(&ar->dump_mutex); 1592 1593 return dump_data; 1594 } 1595 1596 int ath10k_coredump_submit(struct ath10k *ar) 1597 { 1598 struct ath10k_dump_file_data *dump; 1599 1600 if (ath10k_coredump_mask == 0) 1601 /* coredump disabled */ 1602 return 0; 1603 1604 dump = ath10k_coredump_build(ar); 1605 if (!dump) { 1606 ath10k_warn(ar, "no crash dump data found for devcoredump"); 1607 return -ENODATA; 1608 } 1609 1610 dev_coredumpv(ar->dev, dump, le32_to_cpu(dump->len), GFP_KERNEL); 1611 1612 return 0; 1613 } 1614 1615 int ath10k_coredump_create(struct ath10k *ar) 1616 { 1617 if (ath10k_coredump_mask == 0) 1618 /* coredump disabled */ 1619 return 0; 1620 1621 ar->coredump.fw_crash_data = vzalloc(sizeof(*ar->coredump.fw_crash_data)); 1622 if (!ar->coredump.fw_crash_data) 1623 return -ENOMEM; 1624 1625 return 0; 1626 } 1627 1628 int ath10k_coredump_register(struct ath10k *ar) 1629 { 1630 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1631 1632 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1633 crash_data->ramdump_buf_len = ath10k_coredump_get_ramdump_size(ar); 1634 1635 if (!crash_data->ramdump_buf_len) 1636 return 0; 1637 1638 crash_data->ramdump_buf = vzalloc(crash_data->ramdump_buf_len); 1639 if (!crash_data->ramdump_buf) 1640 return -ENOMEM; 1641 } 1642 1643 return 0; 1644 } 1645 1646 void ath10k_coredump_unregister(struct ath10k *ar) 1647 { 1648 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1649 1650 vfree(crash_data->ramdump_buf); 1651 } 1652 1653 void ath10k_coredump_destroy(struct ath10k *ar) 1654 { 1655 if (ar->coredump.fw_crash_data->ramdump_buf) { 1656 vfree(ar->coredump.fw_crash_data->ramdump_buf); 1657 ar->coredump.fw_crash_data->ramdump_buf = NULL; 1658 ar->coredump.fw_crash_data->ramdump_buf_len = 0; 1659 } 1660 1661 vfree(ar->coredump.fw_crash_data); 1662 ar->coredump.fw_crash_data = NULL; 1663 } 1664