1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <linux/if_ether.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 #if defined(__FreeBSD__) 26 #include <linux/stddef.h> 27 #endif 28 29 /* 30 * The key cache is used for h/w cipher state and also for 31 * tracking station state such as the current tx antenna. 32 * We also setup a mapping table between key cache slot indices 33 * and station state to short-circuit node lookups on rx. 34 * Different parts have different size key caches. We handle 35 * up to ATH_KEYMAX entries (could dynamically allocate state). 36 */ 37 #define ATH_KEYMAX 128 /* max key cache size we handle */ 38 39 struct ath_ani { 40 bool caldone; 41 unsigned int longcal_timer; 42 unsigned int shortcal_timer; 43 unsigned int resetcal_timer; 44 unsigned int checkani_timer; 45 struct timer_list timer; 46 }; 47 48 struct ath_cycle_counters { 49 u32 cycles; 50 u32 rx_busy; 51 u32 rx_frame; 52 u32 tx_frame; 53 }; 54 55 enum ath_device_state { 56 ATH_HW_UNAVAILABLE, 57 ATH_HW_INITIALIZED, 58 }; 59 60 enum ath_op_flags { 61 ATH_OP_INVALID, 62 ATH_OP_BEACONS, 63 ATH_OP_ANI_RUN, 64 ATH_OP_PRIM_STA_VIF, 65 ATH_OP_HW_RESET, 66 ATH_OP_SCANNING, 67 ATH_OP_MULTI_CHANNEL, 68 ATH_OP_WOW_ENABLED, 69 }; 70 71 enum ath_bus_type { 72 ATH_PCI, 73 ATH_AHB, 74 ATH_USB, 75 }; 76 77 struct reg_dmn_pair_mapping { 78 u16 reg_domain; 79 u16 reg_5ghz_ctl; 80 u16 reg_2ghz_ctl; 81 }; 82 83 struct ath_regulatory { 84 char alpha2[2]; 85 enum nl80211_dfs_regions region; 86 u16 country_code; 87 u16 max_power_level; 88 u16 current_rd; 89 int16_t power_limit; 90 struct reg_dmn_pair_mapping *regpair; 91 }; 92 93 enum ath_crypt_caps { 94 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 95 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 96 }; 97 98 struct ath_keyval { 99 u8 kv_type; 100 u8 kv_pad; 101 u16 kv_len; 102 struct_group(kv_values, 103 u8 kv_val[16]; /* TK */ 104 u8 kv_mic[8]; /* Michael MIC key */ 105 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 106 * supports both MIC keys in the same key cache entry; 107 * in that case, kv_mic is the RX key) */ 108 ); 109 }; 110 111 enum ath_cipher { 112 ATH_CIPHER_WEP = 0, 113 ATH_CIPHER_AES_OCB = 1, 114 ATH_CIPHER_AES_CCM = 2, 115 ATH_CIPHER_CKIP = 3, 116 ATH_CIPHER_TKIP = 4, 117 ATH_CIPHER_CLR = 5, 118 ATH_CIPHER_MIC = 127 119 }; 120 121 /** 122 * struct ath_ops - Register read/write operations 123 * 124 * @read: Register read 125 * @multi_read: Multiple register read 126 * @write: Register write 127 * @enable_write_buffer: Enable multiple register writes 128 * @write_flush: flush buffered register writes and disable buffering 129 */ 130 struct ath_ops { 131 unsigned int (*read)(void *, u32 reg_offset); 132 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); 133 void (*write)(void *, u32 val, u32 reg_offset); 134 void (*enable_write_buffer)(void *); 135 void (*write_flush) (void *); 136 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); 137 void (*enable_rmw_buffer)(void *); 138 void (*rmw_flush) (void *); 139 140 }; 141 142 struct ath_common; 143 struct ath_bus_ops; 144 145 struct ath_ps_ops { 146 void (*wakeup)(struct ath_common *common); 147 void (*restore)(struct ath_common *common); 148 }; 149 150 struct ath_common { 151 void *ah; 152 void *priv; 153 struct ieee80211_hw *hw; 154 int debug_mask; 155 enum ath_device_state state; 156 unsigned long op_flags; 157 158 struct ath_ani ani; 159 160 u16 cachelsz; 161 u16 curaid; 162 u8 macaddr[ETH_ALEN]; 163 u8 curbssid[ETH_ALEN] __aligned(2); 164 u8 bssidmask[ETH_ALEN]; 165 166 u32 rx_bufsize; 167 168 u32 keymax; 169 DECLARE_BITMAP(keymap, ATH_KEYMAX); 170 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 171 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX); 172 enum ath_crypt_caps crypt_caps; 173 174 unsigned int clockrate; 175 176 spinlock_t cc_lock; 177 struct ath_cycle_counters cc_ani; 178 struct ath_cycle_counters cc_survey; 179 180 struct ath_regulatory regulatory; 181 struct ath_regulatory reg_world_copy; 182 const struct ath_ops *ops; 183 const struct ath_bus_ops *bus_ops; 184 const struct ath_ps_ops *ps_ops; 185 186 bool btcoex_enabled; 187 bool disable_ani; 188 bool bt_ant_diversity; 189 190 int last_rssi; 191 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 192 }; 193 194 static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) 195 { 196 return common->ps_ops; 197 } 198 199 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 200 u32 len, 201 gfp_t gfp_mask); 202 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr); 203 204 void ath_hw_setbssidmask(struct ath_common *common); 205 void ath_key_delete(struct ath_common *common, u8 hw_key_idx); 206 int ath_key_config(struct ath_common *common, 207 struct ieee80211_vif *vif, 208 struct ieee80211_sta *sta, 209 struct ieee80211_key_conf *key); 210 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 211 bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac); 212 void ath_hw_cycle_counters_update(struct ath_common *common); 213 int32_t ath_hw_get_listen_time(struct ath_common *common); 214 215 __printf(3, 4) 216 void ath_printk(const char *level, const struct ath_common *common, 217 const char *fmt, ...); 218 219 #define ath_emerg(common, fmt, ...) \ 220 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__) 221 #define ath_alert(common, fmt, ...) \ 222 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__) 223 #define ath_crit(common, fmt, ...) \ 224 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__) 225 #define ath_err(common, fmt, ...) \ 226 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__) 227 #define ath_warn(common, fmt, ...) \ 228 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__) 229 #define ath_notice(common, fmt, ...) \ 230 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__) 231 #define ath_info(common, fmt, ...) \ 232 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__) 233 234 /** 235 * enum ath_debug_level - atheros wireless debug level 236 * 237 * @ATH_DBG_RESET: reset processing 238 * @ATH_DBG_QUEUE: hardware queue management 239 * @ATH_DBG_EEPROM: eeprom processing 240 * @ATH_DBG_CALIBRATE: periodic calibration 241 * @ATH_DBG_INTERRUPT: interrupt processing 242 * @ATH_DBG_REGULATORY: regulatory processing 243 * @ATH_DBG_ANI: adaptive noise immunitive processing 244 * @ATH_DBG_XMIT: basic xmit operation 245 * @ATH_DBG_BEACON: beacon handling 246 * @ATH_DBG_CONFIG: configuration of the hardware 247 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT 248 * @ATH_DBG_PS: power save processing 249 * @ATH_DBG_HWTIMER: hardware timer handling 250 * @ATH_DBG_BTCOEX: bluetooth coexistance 251 * @ATH_DBG_BSTUCK: stuck beacons 252 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol 253 * used exclusively for WLAN-BT coexistence starting from 254 * AR9462. 255 * @ATH_DBG_DFS: radar datection 256 * @ATH_DBG_WOW: Wake on Wireless 257 * @ATH_DBG_DYNACK: dynack handling 258 * @ATH_DBG_SPECTRAL_SCAN: FFT spectral scan 259 * @ATH_DBG_ANY: enable all debugging 260 * 261 * The debug level is used to control the amount and type of debugging output 262 * we want to see. Each driver has its own method for enabling debugging and 263 * modifying debug level states -- but this is typically done through a 264 * module parameter 'debug' along with a respective 'debug' debugfs file 265 * entry. 266 */ 267 enum ATH_DEBUG { 268 ATH_DBG_RESET = 0x00000001, 269 ATH_DBG_QUEUE = 0x00000002, 270 ATH_DBG_EEPROM = 0x00000004, 271 ATH_DBG_CALIBRATE = 0x00000008, 272 ATH_DBG_INTERRUPT = 0x00000010, 273 ATH_DBG_REGULATORY = 0x00000020, 274 ATH_DBG_ANI = 0x00000040, 275 ATH_DBG_XMIT = 0x00000080, 276 ATH_DBG_BEACON = 0x00000100, 277 ATH_DBG_CONFIG = 0x00000200, 278 ATH_DBG_FATAL = 0x00000400, 279 ATH_DBG_PS = 0x00000800, 280 ATH_DBG_BTCOEX = 0x00001000, 281 ATH_DBG_WMI = 0x00002000, 282 ATH_DBG_BSTUCK = 0x00004000, 283 ATH_DBG_MCI = 0x00008000, 284 ATH_DBG_DFS = 0x00010000, 285 ATH_DBG_WOW = 0x00020000, 286 ATH_DBG_CHAN_CTX = 0x00040000, 287 ATH_DBG_DYNACK = 0x00080000, 288 ATH_DBG_SPECTRAL_SCAN = 0x00100000, 289 ATH_DBG_ANY = 0xffffffff 290 }; 291 292 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL) 293 #define ATH_DBG_MAX_LEN 512 294 295 #ifdef CONFIG_ATH_DEBUG 296 297 #define ath_dbg(common, dbg_mask, fmt, ...) \ 298 do { \ 299 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ 300 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ 301 } while (0) 302 303 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg) 304 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo) 305 306 #else 307 308 static inline __attribute__ ((format (printf, 3, 4))) 309 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, 310 const char *fmt, ...) 311 { 312 } 313 #define ath_dbg(common, dbg_mask, fmt, ...) \ 314 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) 315 316 #define ATH_DBG_WARN(foo, arg...) do {} while (0) 317 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ 318 int __ret_warn_once = !!(foo); \ 319 unlikely(__ret_warn_once); \ 320 }) 321 322 #endif /* CONFIG_ATH_DEBUG */ 323 324 /** Returns string describing opmode, or NULL if unknown mode. */ 325 #ifdef CONFIG_ATH_DEBUG 326 const char *ath_opmode_to_string(enum nl80211_iftype opmode); 327 #else 328 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode) 329 { 330 return "UNKNOWN"; 331 } 332 #endif 333 334 extern const char *ath_bus_type_strings[]; 335 static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype) 336 { 337 return ath_bus_type_strings[bustype]; 338 } 339 340 #endif /* ATH_H */ 341