1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 #ifndef __ar9300templateGeneric_h__ 26 #define __ar9300templateGeneric_h__ 27 28 static ar9300_eeprom_t ar9300_template_generic= 29 { 30 31 2, // eeprom_version; 32 33 ar9300_eeprom_template_generic, // template_version; 34 35 {0,2,3,4,5,6}, //mac_addr[6]; 36 37 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 38 39 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 40 41 //static OSPREY_BASE_EEP_HEADER base_eep_header= 42 43 { 44 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 45 0x77, // txrx_mask; //4 bits tx and 4 bits rx 46 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 47 0, // rf_silent; 48 0, // blue_tooth_options; 49 0, // device_cap; 50 5, // device_type; // takes lower byte in eeprom location 51 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 52 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 53 0x0c, //feature_enable; //bit0 - enable tx temp comp 54 //bit1 - enable tx volt comp 55 //bit2 - enable fastClock - default to 1 56 //bit3 - enable doubling - default to 1 57 //bit4 - enable internal regulator - default to 0 58 0, //misc_configuration: bit0 - turn down drivestrength 59 3, // eeprom_write_enable_gpio 60 0, // wlan_disable_gpio 61 8, // wlan_led_gpio 62 0xff, // rx_band_select_gpio 63 0, // txrxgain 64 0, // swreg 65 }, 66 67 68 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 69 { 70 71 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 72 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 73 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 74 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 75 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 76 36, // temp_slope; 77 0, // voltSlope; 78 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 79 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 80 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 81 0, // quick drop 82 0, // xpa_bias_lvl; // 1 83 0x0e, // tx_frame_to_data_start; // 1 84 0x0e, // tx_frame_to_pa_on; // 1 85 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 86 0, // antenna_gain; // 1 87 0x2c, // switchSettling; // 1 88 -30, // adcDesiredSize; // 1 89 0, // txEndToXpaOff; // 1 90 0x2, // txEndToRxOn; // 1 91 0xe, // tx_frame_to_xpa_on; // 1 92 28, // thresh62; // 1 93 0x0c80C080, // paprd_rate_mask_ht20 // 4 94 0x0080C080, // paprd_rate_mask_ht40 95 0, // switchcomspdt; // 2 96 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 97 0, // rf_gain_cap 98 0, // tx_gain_cap 99 {0,0,0,0,0} //futureModal[5]; 100 }, 101 102 { 103 0, // ant_div_control 104 {0,0}, // base_ext1 105 0, // misc_enable 106 {0,0,0,0,0,0,0,0}, // temp slop extension 107 0, // quick drop low 108 0, // quick drop high 109 }, 110 111 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 112 { 113 FREQ2FBIN(2412, 1), 114 FREQ2FBIN(2437, 1), 115 FREQ2FBIN(2472, 1) 116 }, 117 118 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 119 120 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 121 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 122 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 123 }, 124 125 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 126 127 { 128 FREQ2FBIN(2412, 1), 129 FREQ2FBIN(2484, 1) 130 }, 131 132 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 133 { 134 FREQ2FBIN(2412, 1), 135 FREQ2FBIN(2437, 1), 136 FREQ2FBIN(2472, 1) 137 }, 138 139 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 140 { 141 FREQ2FBIN(2412, 1), 142 FREQ2FBIN(2437, 1), 143 FREQ2FBIN(2472, 1) 144 }, 145 146 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 147 { 148 FREQ2FBIN(2412, 1), 149 FREQ2FBIN(2437, 1), 150 FREQ2FBIN(2472, 1) 151 }, 152 153 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 154 { 155 //1L-5L,5S,11L,11S 156 {{36,36,36,36}}, 157 {{36,36,36,36}} 158 }, 159 160 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 161 { 162 //6-24,36,48,54 163 {{32,32,28,24}}, 164 {{32,32,28,24}}, 165 {{32,32,28,24}}, 166 }, 167 168 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 169 { 170 //0_8_16,1-3_9-11_17-19, 171 // 4,5,6,7,12,13,14,15,20,21,22,23 172 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 173 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 174 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 175 }, 176 177 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 178 { 179 //0_8_16,1-3_9-11_17-19, 180 // 4,5,6,7,12,13,14,15,20,21,22,23 181 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 182 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 183 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 184 }, 185 186 //static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 187 188 { 189 190 0x11, 191 0x12, 192 0x15, 193 0x17, 194 0x41, 195 0x42, 196 0x45, 197 0x47, 198 0x31, 199 0x32, 200 0x35, 201 0x37 202 203 }, 204 205 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 206 207 { 208 {FREQ2FBIN(2412, 1), 209 FREQ2FBIN(2417, 1), 210 FREQ2FBIN(2457, 1), 211 FREQ2FBIN(2462, 1)}, 212 213 {FREQ2FBIN(2412, 1), 214 FREQ2FBIN(2417, 1), 215 FREQ2FBIN(2462, 1), 216 0xFF}, 217 218 {FREQ2FBIN(2412, 1), 219 FREQ2FBIN(2417, 1), 220 FREQ2FBIN(2462, 1), 221 0xFF}, 222 223 {FREQ2FBIN(2422, 1), 224 FREQ2FBIN(2427, 1), 225 FREQ2FBIN(2447, 1), 226 FREQ2FBIN(2452, 1)}, 227 228 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 229 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 230 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 231 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 232 233 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 234 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 235 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 236 0}, 237 238 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 239 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 240 FREQ2FBIN(2472, 1), 241 0}, 242 243 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 244 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 245 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 246 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 247 248 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 249 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 250 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 251 0}, 252 253 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 254 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 255 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 256 0}, 257 258 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 259 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 260 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 261 0}, 262 263 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 264 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 265 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 266 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 267 }, 268 269 270 //OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 271 272 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 273 { 274 275 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 277 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 278 279 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 280 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 283 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 285 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 286 287 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 288 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 289 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 290 291 }, 292 #else 293 { 294 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 296 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 297 298 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 302 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 305 306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 307 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 308 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 309 }, 310 #endif 311 312 //static OSPREY_MODAL_EEP_HEADER modal_header_5g= 313 314 { 315 316 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 317 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 318 {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 319 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 320 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 321 68, // temp_slope; 322 0, // voltSlope; 323 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 324 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 325 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 326 0, // quick drop 327 0, // xpa_bias_lvl; // 1 328 0x0e, // tx_frame_to_data_start; // 1 329 0x0e, // tx_frame_to_pa_on; // 1 330 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 331 0, // antenna_gain; // 1 332 0x2d, // switchSettling; // 1 333 -30, // adcDesiredSize; // 1 334 0, // txEndToXpaOff; // 1 335 0x2, // txEndToRxOn; // 1 336 0xe, // tx_frame_to_xpa_on; // 1 337 28, // thresh62; // 1 338 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 339 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 340 0, // switchcomspdt; // 2 341 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 342 0, // rf_gain_cap 343 0, // tx_gain_cap 344 {0,0,0,0,0} //futureModal[5]; 345 }, 346 347 { // base_ext2 348 0, 349 0, 350 {0,0,0}, 351 {0,0,0}, 352 {0,0,0}, 353 {0,0,0} 354 }, 355 356 //static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 357 { 358 //pPiers[0] = 359 FREQ2FBIN(5180, 0), 360 //pPiers[1] = 361 FREQ2FBIN(5220, 0), 362 //pPiers[2] = 363 FREQ2FBIN(5320, 0), 364 //pPiers[3] = 365 FREQ2FBIN(5400, 0), 366 //pPiers[4] = 367 FREQ2FBIN(5500, 0), 368 //pPiers[5] = 369 FREQ2FBIN(5600, 0), 370 //pPiers[6] = 371 FREQ2FBIN(5725, 0), 372 //pPiers[7] = 373 FREQ2FBIN(5825, 0) 374 }, 375 376 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 377 378 { 379 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 380 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 381 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 382 383 }, 384 385 //static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 386 387 { 388 FREQ2FBIN(5180, 0), 389 FREQ2FBIN(5220, 0), 390 FREQ2FBIN(5320, 0), 391 FREQ2FBIN(5400, 0), 392 FREQ2FBIN(5500, 0), 393 FREQ2FBIN(5600, 0), 394 FREQ2FBIN(5725, 0), 395 FREQ2FBIN(5825, 0) 396 }, 397 398 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 399 400 { 401 FREQ2FBIN(5180, 0), 402 FREQ2FBIN(5240, 0), 403 FREQ2FBIN(5320, 0), 404 FREQ2FBIN(5500, 0), 405 FREQ2FBIN(5700, 0), 406 FREQ2FBIN(5745, 0), 407 FREQ2FBIN(5725, 0), 408 FREQ2FBIN(5825, 0) 409 }, 410 411 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 412 413 { 414 FREQ2FBIN(5180, 0), 415 FREQ2FBIN(5240, 0), 416 FREQ2FBIN(5320, 0), 417 FREQ2FBIN(5500, 0), 418 FREQ2FBIN(5700, 0), 419 FREQ2FBIN(5745, 0), 420 FREQ2FBIN(5725, 0), 421 FREQ2FBIN(5825, 0) 422 }, 423 424 425 //static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 426 427 428 { 429 //6-24,36,48,54 430 {{20,20,20,10}}, 431 {{20,20,20,10}}, 432 {{20,20,20,10}}, 433 {{20,20,20,10}}, 434 {{20,20,20,10}}, 435 {{20,20,20,10}}, 436 {{20,20,20,10}}, 437 {{20,20,20,10}}, 438 }, 439 440 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 441 442 { 443 //0_8_16,1-3_9-11_17-19, 444 // 4,5,6,7,12,13,14,15,20,21,22,23 445 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 446 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 447 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 448 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 449 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 450 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 451 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 452 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 453 }, 454 455 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 456 { 457 //0_8_16,1-3_9-11_17-19, 458 // 4,5,6,7,12,13,14,15,20,21,22,23 459 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 460 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 461 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 462 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 463 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 464 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 465 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 466 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 467 }, 468 469 //static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 470 471 { 472 //pCtlIndex[0] = 473 0x10, 474 //pCtlIndex[1] = 475 0x16, 476 //pCtlIndex[2] = 477 0x18, 478 //pCtlIndex[3] = 479 0x40, 480 //pCtlIndex[4] = 481 0x46, 482 //pCtlIndex[5] = 483 0x48, 484 //pCtlIndex[6] = 485 0x30, 486 //pCtlIndex[7] = 487 0x36, 488 //pCtlIndex[8] = 489 0x38 490 }, 491 492 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 493 494 { 495 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 496 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 497 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 498 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 499 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 500 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 501 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 502 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 503 504 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 505 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 506 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 507 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 508 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 509 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 510 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 511 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 512 513 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 514 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 515 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 516 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 517 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 518 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 519 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 520 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 521 522 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 523 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 524 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 525 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 526 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 527 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 528 /* Data[3].ctl_edges[6].bChannel*/0xFF, 529 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 530 531 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 532 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 533 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 534 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 535 /* Data[4].ctl_edges[4].bChannel*/0xFF, 536 /* Data[4].ctl_edges[5].bChannel*/0xFF, 537 /* Data[4].ctl_edges[6].bChannel*/0xFF, 538 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 539 540 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 541 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 542 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 543 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 544 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 545 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 546 /* Data[5].ctl_edges[6].bChannel*/0xFF, 547 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 548 549 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 550 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 551 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 552 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 553 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 554 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 555 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 556 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 557 558 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 559 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 560 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 561 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 562 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 563 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 564 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 565 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 566 567 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 568 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 569 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 570 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 571 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 572 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 573 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 574 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 575 }, 576 577 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 578 579 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 580 { 581 {{{1, 60}, 582 {1, 60}, 583 {1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {0, 60}}}, 589 590 {{{1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {1, 60}, 597 {0, 60}}}, 598 599 {{{0, 60}, 600 {1, 60}, 601 {0, 60}, 602 {1, 60}, 603 {1, 60}, 604 {1, 60}, 605 {1, 60}, 606 {1, 60}}}, 607 608 {{{0, 60}, 609 {1, 60}, 610 {1, 60}, 611 {0, 60}, 612 {1, 60}, 613 {0, 60}, 614 {0, 60}, 615 {0, 60}}}, 616 617 {{{1, 60}, 618 {1, 60}, 619 {1, 60}, 620 {0, 60}, 621 {0, 60}, 622 {0, 60}, 623 {0, 60}, 624 {0, 60}}}, 625 626 {{{1, 60}, 627 {1, 60}, 628 {1, 60}, 629 {1, 60}, 630 {1, 60}, 631 {0, 60}, 632 {0, 60}, 633 {0, 60}}}, 634 635 {{{1, 60}, 636 {1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}}}, 643 644 {{{1, 60}, 645 {1, 60}, 646 {0, 60}, 647 {1, 60}, 648 {1, 60}, 649 {1, 60}, 650 {1, 60}, 651 {0, 60}}}, 652 653 {{{1, 60}, 654 {0, 60}, 655 {1, 60}, 656 {1, 60}, 657 {1, 60}, 658 {1, 60}, 659 {0, 60}, 660 {1, 60}}}, 661 } 662 #else 663 { 664 {{{60, 1}, 665 {60, 1}, 666 {60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 0}}}, 672 673 {{{60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 1}, 680 {60, 0}}}, 681 682 {{{60, 0}, 683 {60, 1}, 684 {60, 0}, 685 {60, 1}, 686 {60, 1}, 687 {60, 1}, 688 {60, 1}, 689 {60, 1}}}, 690 691 {{{60, 0}, 692 {60, 1}, 693 {60, 1}, 694 {60, 0}, 695 {60, 1}, 696 {60, 0}, 697 {60, 0}, 698 {60, 0}}}, 699 700 {{{60, 1}, 701 {60, 1}, 702 {60, 1}, 703 {60, 0}, 704 {60, 0}, 705 {60, 0}, 706 {60, 0}, 707 {60, 0}}}, 708 709 {{{60, 1}, 710 {60, 1}, 711 {60, 1}, 712 {60, 1}, 713 {60, 1}, 714 {60, 0}, 715 {60, 0}, 716 {60, 0}}}, 717 718 {{{60, 1}, 719 {60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}}}, 726 727 {{{60, 1}, 728 {60, 1}, 729 {60, 0}, 730 {60, 1}, 731 {60, 1}, 732 {60, 1}, 733 {60, 1}, 734 {60, 0}}}, 735 736 {{{60, 1}, 737 {60, 0}, 738 {60, 1}, 739 {60, 1}, 740 {60, 1}, 741 {60, 1}, 742 {60, 0}, 743 {60, 1}}}, 744 } 745 #endif 746 }; 747 748 #endif 749