1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 /* 19 * READ THIS NOTICE! 20 * 21 * Values defined in this file may only be changed under exceptional circumstances. 22 * 23 * Please ask Fiona Cain before making any changes. 24 */ 25 26 #ifndef __ar9300templateAphrodite_h__ 27 #define __ar9300templateAphrodite_h__ 28 29 /* Ensure that AH_BYTE_ORDER is defined */ 30 #ifndef AH_BYTE_ORDER 31 #error AH_BYTE_ORDER needs to be defined! 32 #endif 33 34 static ar9300_eeprom_t ar9300_template_aphrodite= 35 { 36 37 0, // eeprom_version; 38 39 ar9300_eeprom_template_aphrodite, // template_version; 40 41 {0x00,0x03,0x7f,0x0,0x0,0x11}, //mac_addr[6]; 42 43 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 44 45 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 46 47 //static OSPREY_BASE_EEP_HEADER base_eep_header= 48 49 { 50 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 51 0x11, // txrx_mask; //4 bits tx and 4 bits rx 52 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 53 0, // rf_silent; 54 0, // blue_tooth_options; 55 0, // device_cap; 56 4, // device_type; // takes lower byte in eeprom location 57 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 59 0x10, //feature_enable; //bit0 - enable tx temp comp 60 //bit1 - enable tx volt comp 61 //bit2 - enable fastClock - default to 1 62 //bit3 - enable doubling - default to 1 63 //bit4 - enable internal regulator - default to 0 64 0, //misc_configuration: bit0 - turn down drivestrength 65 3, // eeprom_write_enable_gpio 66 0, // wlan_disable_gpio 67 8, // wlan_led_gpio 68 0xff, // rx_band_select_gpio 69 0, // txrxgain 70 0, // swreg 71 }, 72 73 74 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 75 { 76 77 0x0, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 78 0x0, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 79 {0x0,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 80 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 81 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 82 36, // temp_slope; 83 0, // voltSlope; 84 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 85 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 86 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 87 0, // quick drop 88 0, // xpa_bias_lvl; // 1 89 0x0e, // tx_frame_to_data_start; // 1 90 0x0e, // tx_frame_to_pa_on; // 1 91 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 92 0, // antenna_gain; // 1 93 0x2c, // switchSettling; // 1 94 -30, // adcDesiredSize; // 1 95 0, // txEndToXpaOff; // 1 96 0x2, // txEndToRxOn; // 1 97 0xe, // tx_frame_to_xpa_on; // 1 98 28, // thresh62; // 1 99 0x0c80C080, // paprd_rate_mask_ht20 // 4 100 0x0080C080, // paprd_rate_mask_ht40 101 0, // switchcomspdt; // 2 102 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 103 0, // rf_gain_cap 104 0, // tx_gain_cap 105 {0,0,0,0,0} //futureModal[5]; 106 }, 107 108 { 109 0, // ant_div_control 110 {0,0}, // base_ext1 111 0, // misc_enable 112 {0,0,0,0,0,0,0,0}, // temp slop extension 113 0, // quick drop low 114 0, // quick drop high 115 }, 116 117 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 118 { 119 FREQ2FBIN(2412, 1), 120 FREQ2FBIN(2437, 1), 121 FREQ2FBIN(2472, 1) 122 }, 123 124 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 125 126 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 127 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 128 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 129 }, 130 131 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 132 133 { 134 FREQ2FBIN(2412, 1), 135 FREQ2FBIN(2484, 1) 136 }, 137 138 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 139 { 140 FREQ2FBIN(2412, 1), 141 FREQ2FBIN(2437, 1), 142 FREQ2FBIN(2472, 1) 143 }, 144 145 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 146 { 147 FREQ2FBIN(2412, 1), 148 FREQ2FBIN(2437, 1), 149 FREQ2FBIN(2472, 1) 150 }, 151 152 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 153 { 154 FREQ2FBIN(2412, 1), 155 FREQ2FBIN(2437, 1), 156 FREQ2FBIN(2472, 1) 157 }, 158 159 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 160 { 161 //1L-5L,5S,11L,11S 162 {{36,36,36,36}}, 163 {{36,36,36,36}} 164 }, 165 166 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 167 { 168 //6-24,36,48,54 169 {{32,32,28,24}}, 170 {{32,32,28,24}}, 171 {{32,32,28,24}}, 172 }, 173 174 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 175 { 176 //0_8_16,1-3_9-11_17-19, 177 // 4,5,6,7,12,13,14,15,20,21,22,23 178 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 179 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 180 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 181 }, 182 183 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 184 { 185 //0_8_16,1-3_9-11_17-19, 186 // 4,5,6,7,12,13,14,15,20,21,22,23 187 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 188 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 189 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 190 }, 191 192 //static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 193 194 { 195 196 0x11, 197 0x12, 198 0x15, 199 0x17, 200 0x41, 201 0x42, 202 0x45, 203 0x47, 204 0x31, 205 0x32, 206 0x35, 207 0x37 208 209 }, 210 211 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 212 213 { 214 {FREQ2FBIN(2412, 1), 215 FREQ2FBIN(2417, 1), 216 FREQ2FBIN(2457, 1), 217 FREQ2FBIN(2462, 1)}, 218 219 {FREQ2FBIN(2412, 1), 220 FREQ2FBIN(2417, 1), 221 FREQ2FBIN(2462, 1), 222 0xFF}, 223 224 {FREQ2FBIN(2412, 1), 225 FREQ2FBIN(2417, 1), 226 FREQ2FBIN(2462, 1), 227 0xFF}, 228 229 {FREQ2FBIN(2422, 1), 230 FREQ2FBIN(2427, 1), 231 FREQ2FBIN(2447, 1), 232 FREQ2FBIN(2452, 1)}, 233 234 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 235 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 236 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 237 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 238 239 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 240 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 241 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 242 0}, 243 244 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 245 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 246 FREQ2FBIN(2472, 1), 247 0}, 248 249 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 250 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 251 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 252 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 253 254 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 255 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 256 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 257 0}, 258 259 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 260 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 261 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 262 0}, 263 264 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 265 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 266 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 267 0}, 268 269 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 270 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 271 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 272 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 273 }, 274 275 276 //OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 277 278 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 279 { 280 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 283 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 284 285 {{{1, 60}, {0, 60}, {0, 0}, {0, 0}}}, 286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 288 289 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 290 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 291 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 292 293 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 294 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 295 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 296 297 }, 298 #else 299 { 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 302 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 303 304 {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}}, 305 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 307 308 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 309 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 310 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 311 312 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 313 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 314 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 315 }, 316 #endif 317 318 //static OSPREY_MODAL_EEP_HEADER modal_header_5g= 319 320 { 321 322 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 323 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 324 {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 325 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 326 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 327 68, // temp_slope; 328 0, // voltSlope; 329 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 330 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 331 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 332 0, // quick drop 333 0, // xpa_bias_lvl; // 1 334 0x0e, // tx_frame_to_data_start; // 1 335 0x0e, // tx_frame_to_pa_on; // 1 336 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 337 0, // antenna_gain; // 1 338 0x2d, // switchSettling; // 1 339 -30, // adcDesiredSize; // 1 340 0, // txEndToXpaOff; // 1 341 0x2, // txEndToRxOn; // 1 342 0xe, // tx_frame_to_xpa_on; // 1 343 28, // thresh62; // 1 344 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 345 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 346 0, // switchcomspdt; // 2 347 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 348 0, // rf_gain_cap 349 0, // tx_gain_cap 350 {0,0,0,0,0} //futureModal[5]; 351 }, 352 353 { // base_ext2 354 0, 355 0, 356 {0,0,0}, 357 {0,0,0}, 358 {0,0,0}, 359 {0,0,0} 360 }, 361 362 //static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 363 { 364 //pPiers[0] = 365 FREQ2FBIN(5180, 0), 366 //pPiers[1] = 367 FREQ2FBIN(5220, 0), 368 //pPiers[2] = 369 FREQ2FBIN(5320, 0), 370 //pPiers[3] = 371 FREQ2FBIN(5400, 0), 372 //pPiers[4] = 373 FREQ2FBIN(5500, 0), 374 //pPiers[5] = 375 FREQ2FBIN(5600, 0), 376 //pPiers[6] = 377 FREQ2FBIN(5725, 0), 378 //pPiers[7] = 379 FREQ2FBIN(5825, 0) 380 }, 381 382 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 383 384 { 385 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 386 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 387 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 388 389 }, 390 391 //static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 392 393 { 394 FREQ2FBIN(5180, 0), 395 FREQ2FBIN(5220, 0), 396 FREQ2FBIN(5320, 0), 397 FREQ2FBIN(5400, 0), 398 FREQ2FBIN(5500, 0), 399 FREQ2FBIN(5600, 0), 400 FREQ2FBIN(5725, 0), 401 FREQ2FBIN(5825, 0) 402 }, 403 404 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 405 406 { 407 FREQ2FBIN(5180, 0), 408 FREQ2FBIN(5240, 0), 409 FREQ2FBIN(5320, 0), 410 FREQ2FBIN(5500, 0), 411 FREQ2FBIN(5700, 0), 412 FREQ2FBIN(5745, 0), 413 FREQ2FBIN(5725, 0), 414 FREQ2FBIN(5825, 0) 415 }, 416 417 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 418 419 { 420 FREQ2FBIN(5180, 0), 421 FREQ2FBIN(5240, 0), 422 FREQ2FBIN(5320, 0), 423 FREQ2FBIN(5500, 0), 424 FREQ2FBIN(5700, 0), 425 FREQ2FBIN(5745, 0), 426 FREQ2FBIN(5725, 0), 427 FREQ2FBIN(5825, 0) 428 }, 429 430 431 //static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 432 433 434 { 435 //6-24,36,48,54 436 {{20,20,20,10}}, 437 {{20,20,20,10}}, 438 {{20,20,20,10}}, 439 {{20,20,20,10}}, 440 {{20,20,20,10}}, 441 {{20,20,20,10}}, 442 {{20,20,20,10}}, 443 {{20,20,20,10}}, 444 }, 445 446 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 447 448 { 449 //0_8_16,1-3_9-11_17-19, 450 // 4,5,6,7,12,13,14,15,20,21,22,23 451 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 452 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 453 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 454 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 455 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 456 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 457 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 458 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 459 }, 460 461 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 462 { 463 //0_8_16,1-3_9-11_17-19, 464 // 4,5,6,7,12,13,14,15,20,21,22,23 465 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 466 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 467 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 468 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 469 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 470 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 471 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 472 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 473 }, 474 475 //static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 476 477 { 478 //pCtlIndex[0] = 479 0x10, 480 //pCtlIndex[1] = 481 0x16, 482 //pCtlIndex[2] = 483 0x18, 484 //pCtlIndex[3] = 485 0x40, 486 //pCtlIndex[4] = 487 0x46, 488 //pCtlIndex[5] = 489 0x48, 490 //pCtlIndex[6] = 491 0x30, 492 //pCtlIndex[7] = 493 0x36, 494 //pCtlIndex[8] = 495 0x38 496 }, 497 498 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 499 500 { 501 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 502 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 503 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 504 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 505 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 506 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 507 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 508 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 509 510 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 511 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 512 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 513 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 514 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 515 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 516 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 517 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 518 519 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 520 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 521 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 522 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 523 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 524 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 525 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 526 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 527 528 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 529 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 530 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 531 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 532 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 533 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 534 /* Data[3].ctl_edges[6].bChannel*/0xFF, 535 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 536 537 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 538 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 539 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 540 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 541 /* Data[4].ctl_edges[4].bChannel*/0xFF, 542 /* Data[4].ctl_edges[5].bChannel*/0xFF, 543 /* Data[4].ctl_edges[6].bChannel*/0xFF, 544 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 545 546 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 547 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 548 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 549 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 550 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 551 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 552 /* Data[5].ctl_edges[6].bChannel*/0xFF, 553 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 554 555 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 556 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 557 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 558 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 559 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 560 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 561 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 562 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 563 564 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 565 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 566 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 567 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 568 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 569 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 570 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 571 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 572 573 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 574 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 575 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 576 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 577 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 578 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 579 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 580 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 581 }, 582 583 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 584 585 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 586 { 587 {{{1, 60}, 588 {1, 60}, 589 {1, 60}, 590 {1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {0, 60}}}, 595 596 {{{1, 60}, 597 {1, 60}, 598 {1, 60}, 599 {1, 60}, 600 {1, 60}, 601 {1, 60}, 602 {1, 60}, 603 {0, 60}}}, 604 605 {{{0, 60}, 606 {1, 60}, 607 {0, 60}, 608 {1, 60}, 609 {1, 60}, 610 {1, 60}, 611 {1, 60}, 612 {1, 60}}}, 613 614 {{{0, 60}, 615 {1, 60}, 616 {1, 60}, 617 {0, 60}, 618 {1, 60}, 619 {0, 60}, 620 {0, 60}, 621 {0, 60}}}, 622 623 {{{1, 60}, 624 {1, 60}, 625 {1, 60}, 626 {0, 60}, 627 {0, 60}, 628 {0, 60}, 629 {0, 60}, 630 {0, 60}}}, 631 632 {{{1, 60}, 633 {1, 60}, 634 {1, 60}, 635 {1, 60}, 636 {1, 60}, 637 {0, 60}, 638 {0, 60}, 639 {0, 60}}}, 640 641 {{{1, 60}, 642 {1, 60}, 643 {1, 60}, 644 {1, 60}, 645 {1, 60}, 646 {1, 60}, 647 {1, 60}, 648 {1, 60}}}, 649 650 {{{1, 60}, 651 {1, 60}, 652 {0, 60}, 653 {1, 60}, 654 {1, 60}, 655 {1, 60}, 656 {1, 60}, 657 {0, 60}}}, 658 659 {{{1, 60}, 660 {0, 60}, 661 {1, 60}, 662 {1, 60}, 663 {1, 60}, 664 {1, 60}, 665 {0, 60}, 666 {1, 60}}}, 667 } 668 #else 669 { 670 {{{60, 1}, 671 {60, 1}, 672 {60, 1}, 673 {60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 0}}}, 678 679 {{{60, 1}, 680 {60, 1}, 681 {60, 1}, 682 {60, 1}, 683 {60, 1}, 684 {60, 1}, 685 {60, 1}, 686 {60, 0}}}, 687 688 {{{60, 0}, 689 {60, 1}, 690 {60, 0}, 691 {60, 1}, 692 {60, 1}, 693 {60, 1}, 694 {60, 1}, 695 {60, 1}}}, 696 697 {{{60, 0}, 698 {60, 1}, 699 {60, 1}, 700 {60, 0}, 701 {60, 1}, 702 {60, 0}, 703 {60, 0}, 704 {60, 0}}}, 705 706 {{{60, 1}, 707 {60, 1}, 708 {60, 1}, 709 {60, 0}, 710 {60, 0}, 711 {60, 0}, 712 {60, 0}, 713 {60, 0}}}, 714 715 {{{60, 1}, 716 {60, 1}, 717 {60, 1}, 718 {60, 1}, 719 {60, 1}, 720 {60, 0}, 721 {60, 0}, 722 {60, 0}}}, 723 724 {{{60, 1}, 725 {60, 1}, 726 {60, 1}, 727 {60, 1}, 728 {60, 1}, 729 {60, 1}, 730 {60, 1}, 731 {60, 1}}}, 732 733 {{{60, 1}, 734 {60, 1}, 735 {60, 0}, 736 {60, 1}, 737 {60, 1}, 738 {60, 1}, 739 {60, 1}, 740 {60, 0}}}, 741 742 {{{60, 1}, 743 {60, 0}, 744 {60, 1}, 745 {60, 1}, 746 {60, 1}, 747 {60, 1}, 748 {60, 0}, 749 {60, 1}}}, 750 } 751 #endif 752 }; 753 754 #endif 755