1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 #ifndef __ar9300templateAP121_h__ 26 #define __ar9300templateAP121_h__ 27 28 static ar9300_eeprom_t ar9300_template_ap121= 29 { 30 31 2, // eeprom_version; 32 33 ar9300_eeprom_template_ap121, // template_version; 34 35 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 36 37 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 38 39 {"ap121-010-00000"}, 40 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 41 42 //static OSPREY_BASE_EEP_HEADER base_eep_header= 43 44 { 45 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 46 0x11, // txrx_mask; //4 bits tx and 4 bits rx 47 {AR9300_OPFLAGS_11G , 0}, // op_cap_flags; 48 0, // rf_silent; 49 0, // blue_tooth_options; 50 0, // device_cap; 51 4, // device_type; // takes lower byte in eeprom location 52 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 53 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 54 0x0d, //feature_enable; //bit0 - enable tx temp comp 55 //bit1 - enable tx volt comp 56 //bit2 - enable fastClock - default to 1 57 //bit3 - enable doubling - default to 1 58 //bit4 - enable internal regulator - default to 0 59 //bit5 - enable paprd -- default to 0 60 0, //misc_configuration: bit0 - turn down drivestrength 61 6, // eeprom_write_enable_gpio 62 0, // wlan_disable_gpio 63 8, // wlan_led_gpio 64 0xff, // rx_band_select_gpio 65 0x10, // txrxgain 66 0, // swreg 67 }, 68 69 70 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 71 { 72 73 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 74 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 75 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 76 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 77 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 78 25, // temp_slope; 79 0, // voltSlope; 80 {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 81 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 82 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 83 0, // quick drop 84 0, // xpa_bias_lvl; // 1 85 0x0e, // tx_frame_to_data_start; // 1 86 0x0e, // tx_frame_to_pa_on; // 1 87 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 88 0, // antenna_gain; // 1 89 0x2c, // switchSettling; // 1 90 -30, // adcDesiredSize; // 1 91 0, // txEndToXpaOff; // 1 92 0x2, // txEndToRxOn; // 1 93 0xe, // tx_frame_to_xpa_on; // 1 94 28, // thresh62; // 1 95 0x80c0e0, // paprd_rate_mask_ht20 // 4 96 0x1ffffff, // paprd_rate_mask_ht40 97 0, // switchcomspdt; // 2 98 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 99 0, // rf_gain_cap 100 0, // tx_gain_cap 101 {0,0,0,0,0} //futureModal[5]; 102 }, 103 104 { 105 6, // ant_div_control 106 {0,0}, // base_ext1 107 0, // misc_enable 108 {0,0,0,0,0,0,0,0}, // temp slop extension 109 0, // quick drop low 110 0, // quick drop high 111 }, 112 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 113 { 114 FREQ2FBIN(2412, 1), 115 FREQ2FBIN(2437, 1), 116 FREQ2FBIN(2462, 1) 117 }, 118 119 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 120 121 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 122 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 123 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 124 }, 125 126 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 127 128 { 129 FREQ2FBIN(2412, 1), 130 FREQ2FBIN(2472, 1) 131 }, 132 133 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 134 { 135 FREQ2FBIN(2412, 1), 136 FREQ2FBIN(2437, 1), 137 FREQ2FBIN(2472, 1) 138 }, 139 140 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 141 { 142 FREQ2FBIN(2412, 1), 143 FREQ2FBIN(2437, 1), 144 FREQ2FBIN(2472, 1) 145 }, 146 147 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 148 { 149 FREQ2FBIN(2412, 1), 150 FREQ2FBIN(2437, 1), 151 FREQ2FBIN(2472, 1) 152 }, 153 154 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 155 { 156 //1L-5L,5S,11L,11S 157 {{34,34,34,34}}, 158 {{34,34,34,34}} 159 }, 160 161 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 162 { 163 //6-24,36,48,54 164 {{34,34,32,32}}, 165 {{34,34,32,32}}, 166 {{34,34,32,32}}, 167 }, 168 169 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 170 { 171 //0_8_16,1-3_9-11_17-19, 172 // 4,5,6,7,12,13,14,15,20,21,22,23 173 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 174 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 175 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 176 }, 177 178 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 179 { 180 //0_8_16,1-3_9-11_17-19, 181 // 4,5,6,7,12,13,14,15,20,21,22,23 182 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 183 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 184 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 185 }, 186 187 //static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 188 189 { 190 191 0x11, 192 0x12, 193 0x15, 194 0x17, 195 0x41, 196 0x42, 197 0x45, 198 0x47, 199 0x31, 200 0x32, 201 0x35, 202 0x37 203 204 }, 205 206 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 207 208 { 209 {FREQ2FBIN(2412, 1), 210 FREQ2FBIN(2417, 1), 211 FREQ2FBIN(2457, 1), 212 FREQ2FBIN(2462, 1)}, 213 214 {FREQ2FBIN(2412, 1), 215 FREQ2FBIN(2417, 1), 216 FREQ2FBIN(2462, 1), 217 0xFF}, 218 219 {FREQ2FBIN(2412, 1), 220 FREQ2FBIN(2417, 1), 221 FREQ2FBIN(2462, 1), 222 0xFF}, 223 224 {FREQ2FBIN(2422, 1), 225 FREQ2FBIN(2427, 1), 226 FREQ2FBIN(2447, 1), 227 FREQ2FBIN(2452, 1)}, 228 229 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 230 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 231 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 232 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 233 234 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 235 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 236 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 237 0}, 238 239 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 240 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 241 FREQ2FBIN(2472, 1), 242 0}, 243 244 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 245 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 246 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 247 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 248 249 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 250 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 251 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 252 0}, 253 254 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 255 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 256 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 257 0}, 258 259 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 260 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 261 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 262 0}, 263 264 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 265 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 266 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 267 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 268 }, 269 270 271 //OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 272 273 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 274 { 275 276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 278 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 279 280 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 283 284 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 285 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287 288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 289 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 290 291 }, 292 #else 293 { 294 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 296 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 297 298 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 302 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 305 306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 307 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 308 }, 309 #endif 310 311 //static OSPREY_MODAL_EEP_HEADER modal_header_5g= 312 313 { 314 315 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 316 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 317 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 318 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 319 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 320 45, // temp_slope; 321 0, // voltSlope; 322 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 323 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 324 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 325 0, // quick drop 326 0, // xpa_bias_lvl; // 1 327 0x0e, // tx_frame_to_data_start; // 1 328 0x0e, // tx_frame_to_pa_on; // 1 329 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 330 0, // antenna_gain; // 1 331 0x2d, // switchSettling; // 1 332 -30, // adcDesiredSize; // 1 333 0, // txEndToXpaOff; // 1 334 0x2, // txEndToRxOn; // 1 335 0xe, // tx_frame_to_xpa_on; // 1 336 28, // thresh62; // 1 337 0xf0e0e0, // paprd_rate_mask_ht20 // 4 338 0xf0e0e0, // paprd_rate_mask_ht40 // 4 339 0, // switchcomspdt; // 2 340 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 341 0, // rf_gain_cap 342 0, // tx_gain_cap 343 {0,0,0,0,0} //futureModal[5]; 344 }, 345 346 { // base_ext2 347 40, // temp_slope_low 348 50, // temp_slope_high 349 {0,0,0}, 350 {0,0,0}, 351 {0,0,0}, 352 {0,0,0} 353 }, 354 355 //static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 356 { 357 //pPiers[0] = 358 FREQ2FBIN(5180, 0), 359 //pPiers[1] = 360 FREQ2FBIN(5220, 0), 361 //pPiers[2] = 362 FREQ2FBIN(5320, 0), 363 //pPiers[3] = 364 FREQ2FBIN(5400, 0), 365 //pPiers[4] = 366 FREQ2FBIN(5500, 0), 367 //pPiers[5] = 368 FREQ2FBIN(5600, 0), 369 //pPiers[6] = 370 FREQ2FBIN(5700, 0), 371 //pPiers[7] = 372 FREQ2FBIN(5785, 0), 373 }, 374 375 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 376 377 { 378 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 379 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 380 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 381 382 }, 383 384 //static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 385 386 { 387 FREQ2FBIN(5180, 0), 388 FREQ2FBIN(5240, 0), 389 FREQ2FBIN(5320, 0), 390 FREQ2FBIN(5400, 0), 391 FREQ2FBIN(5500, 0), 392 FREQ2FBIN(5600, 0), 393 FREQ2FBIN(5700, 0), 394 FREQ2FBIN(5825, 0) 395 }, 396 397 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 398 399 { 400 FREQ2FBIN(5180, 0), 401 FREQ2FBIN(5240, 0), 402 FREQ2FBIN(5320, 0), 403 FREQ2FBIN(5400, 0), 404 FREQ2FBIN(5500, 0), 405 FREQ2FBIN(5700, 0), 406 FREQ2FBIN(5745, 0), 407 FREQ2FBIN(5825, 0) 408 }, 409 410 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 411 412 { 413 FREQ2FBIN(5180, 0), 414 FREQ2FBIN(5240, 0), 415 FREQ2FBIN(5320, 0), 416 FREQ2FBIN(5400, 0), 417 FREQ2FBIN(5500, 0), 418 FREQ2FBIN(5700, 0), 419 FREQ2FBIN(5745, 0), 420 FREQ2FBIN(5825, 0) 421 }, 422 423 424 //static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 425 426 427 { 428 //6-24,36,48,54 429 {{30,30,28,24}}, 430 {{30,30,28,24}}, 431 {{30,30,28,24}}, 432 {{30,30,28,24}}, 433 {{30,30,28,24}}, 434 {{30,30,28,24}}, 435 {{30,30,28,24}}, 436 {{30,30,28,24}}, 437 }, 438 439 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 440 441 { 442 //0_8_16,1-3_9-11_17-19, 443 // 4,5,6,7,12,13,14,15,20,21,22,23 444 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, 445 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, 446 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, 447 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, 448 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, 449 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, 450 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, 451 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, 452 }, 453 454 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 455 { 456 //0_8_16,1-3_9-11_17-19, 457 // 4,5,6,7,12,13,14,15,20,21,22,23 458 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, 459 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, 460 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, 461 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, 462 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, 463 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, 464 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, 465 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, 466 }, 467 468 //static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 469 470 { 471 //pCtlIndex[0] = 472 0x10, 473 //pCtlIndex[1] = 474 0x16, 475 //pCtlIndex[2] = 476 0x18, 477 //pCtlIndex[3] = 478 0x40, 479 //pCtlIndex[4] = 480 0x46, 481 //pCtlIndex[5] = 482 0x48, 483 //pCtlIndex[6] = 484 0x30, 485 //pCtlIndex[7] = 486 0x36, 487 //pCtlIndex[8] = 488 0x38 489 }, 490 491 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 492 493 { 494 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 495 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 496 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 497 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 498 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 499 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 500 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 501 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 502 503 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 504 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 505 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 506 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 507 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 508 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 509 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 510 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 511 512 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 513 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 514 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 515 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 516 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 517 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 518 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 519 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 520 521 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 522 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 523 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 524 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 525 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 526 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 527 /* Data[3].ctl_edges[6].bChannel*/0xFF, 528 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 529 530 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 531 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 532 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 533 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 534 /* Data[4].ctl_edges[4].bChannel*/0xFF, 535 /* Data[4].ctl_edges[5].bChannel*/0xFF, 536 /* Data[4].ctl_edges[6].bChannel*/0xFF, 537 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 538 539 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 540 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 541 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 542 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 543 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 544 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 545 /* Data[5].ctl_edges[6].bChannel*/0xFF, 546 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 547 548 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 549 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 550 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 551 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 552 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 553 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 554 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 555 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 556 557 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 558 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 559 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 560 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 561 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 562 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 563 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 564 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 565 566 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 567 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 568 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 569 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 570 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 571 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 572 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 573 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 574 }, 575 576 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 577 578 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 579 { 580 {{{1, 60}, 581 {1, 60}, 582 {1, 60}, 583 {1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {0, 60}}}, 588 589 {{{1, 60}, 590 {1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {0, 60}}}, 597 598 {{{0, 60}, 599 {1, 60}, 600 {0, 60}, 601 {1, 60}, 602 {1, 60}, 603 {1, 60}, 604 {1, 60}, 605 {1, 60}}}, 606 607 {{{0, 60}, 608 {1, 60}, 609 {1, 60}, 610 {0, 60}, 611 {1, 60}, 612 {0, 60}, 613 {0, 60}, 614 {0, 60}}}, 615 616 {{{1, 60}, 617 {1, 60}, 618 {1, 60}, 619 {0, 60}, 620 {0, 60}, 621 {0, 60}, 622 {0, 60}, 623 {0, 60}}}, 624 625 {{{1, 60}, 626 {1, 60}, 627 {1, 60}, 628 {1, 60}, 629 {1, 60}, 630 {0, 60}, 631 {0, 60}, 632 {0, 60}}}, 633 634 {{{1, 60}, 635 {1, 60}, 636 {1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}}}, 642 643 {{{1, 60}, 644 {1, 60}, 645 {0, 60}, 646 {1, 60}, 647 {1, 60}, 648 {1, 60}, 649 {1, 60}, 650 {0, 60}}}, 651 652 {{{1, 60}, 653 {0, 60}, 654 {1, 60}, 655 {1, 60}, 656 {1, 60}, 657 {1, 60}, 658 {0, 60}, 659 {1, 60}}}, 660 } 661 #else 662 { 663 {{{60, 1}, 664 {60, 1}, 665 {60, 1}, 666 {60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 0}}}, 671 672 {{{60, 1}, 673 {60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 0}}}, 680 681 {{{60, 0}, 682 {60, 1}, 683 {60, 0}, 684 {60, 1}, 685 {60, 1}, 686 {60, 1}, 687 {60, 1}, 688 {60, 1}}}, 689 690 {{{60, 0}, 691 {60, 1}, 692 {60, 1}, 693 {60, 0}, 694 {60, 1}, 695 {60, 0}, 696 {60, 0}, 697 {60, 0}}}, 698 699 {{{60, 1}, 700 {60, 1}, 701 {60, 1}, 702 {60, 0}, 703 {60, 0}, 704 {60, 0}, 705 {60, 0}, 706 {60, 0}}}, 707 708 {{{60, 1}, 709 {60, 1}, 710 {60, 1}, 711 {60, 1}, 712 {60, 1}, 713 {60, 0}, 714 {60, 0}, 715 {60, 0}}}, 716 717 {{{60, 1}, 718 {60, 1}, 719 {60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}}}, 725 726 {{{60, 1}, 727 {60, 1}, 728 {60, 0}, 729 {60, 1}, 730 {60, 1}, 731 {60, 1}, 732 {60, 1}, 733 {60, 0}}}, 734 735 {{{60, 1}, 736 {60, 0}, 737 {60, 1}, 738 {60, 1}, 739 {60, 1}, 740 {60, 1}, 741 {60, 0}, 742 {60, 1}}}, 743 } 744 #endif 745 }; 746 747 #endif 748 749