1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 /* 17 * Copyright (c) 2002-2005 Atheros Communications, Inc. 18 * All Rights Reserved. 19 * 20 * Copyright (c) 2011 Qualcomm Atheros, Inc. 21 * All Rights Reserved. 22 * Qualcomm Atheros Confidential and Proprietary. 23 * 24 */ 25 26 #ifndef _ATH_AR9300PHY_H_ 27 #define _ATH_AR9300PHY_H_ 28 29 #include "osprey_reg_map.h" 30 31 /* 32 * BB PHY register map 33 */ 34 #define AR_PHY_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) /* base address of phy regs */ 35 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 36 37 /* 38 * Channel Register Map 39 */ 40 #define AR_CHAN_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) 41 #define AR_CHAN_OFFSET(_x) (AR_CHAN_BASE + offsetof(struct chn_reg_map, _x)) 42 43 #define AR_PHY_TIMING1 AR_CHAN_OFFSET(BB_timing_controls_1) 44 #define AR_PHY_TIMING2 AR_CHAN_OFFSET(BB_timing_controls_2) 45 #define AR_PHY_TIMING3 AR_CHAN_OFFSET(BB_timing_controls_3) 46 #define AR_PHY_TIMING4 AR_CHAN_OFFSET(BB_timing_control_4) 47 #define AR_PHY_TIMING5 AR_CHAN_OFFSET(BB_timing_control_5) 48 #define AR_PHY_TIMING6 AR_CHAN_OFFSET(BB_timing_control_6) 49 #define AR_PHY_TIMING11 AR_CHAN_OFFSET(BB_timing_control_11) 50 #define AR_PHY_SPUR_REG AR_CHAN_OFFSET(BB_spur_mask_controls) 51 #define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_OFFSET(BB_rx_iq_corr_b0) 52 #define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_OFFSET(BB_txiqcal_control_3) 53 54 /* BB_timing_control_11 */ 55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 56 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 57 58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 60 61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 62 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30 63 64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 65 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31 66 67 /* BB_spur_mask_controls */ 68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000 69 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26 70 71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 72 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17 73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF 74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 76 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8 77 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000 78 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 79 80 /* BB_rx_iq_corr_b0 */ 81 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 82 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 83 /* BB_txiqcal_control_3 */ 84 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 85 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 86 87 #if 0 88 /* enable vit puncture per rate, 8 bits, lsb is low rate */ 89 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 90 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 91 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 92 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 93 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 94 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 95 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 96 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 97 #endif 98 99 #define AR_PHY_FIND_SIG_LOW AR_CHAN_OFFSET(BB_find_signal_low) 100 #define AR_PHY_SFCORR AR_CHAN_OFFSET(BB_sfcorr) 101 #if 0 102 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 103 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 104 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 105 #define AR_PHY_SFCORR_M1_THRESH_S 17 106 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 107 #define AR_PHY_SFCORR_M2_THRESH_S 24 108 #endif 109 110 #define AR_PHY_SFCORR_LOW AR_CHAN_OFFSET(BB_self_corr_low) 111 #define AR_PHY_SFCORR_EXT AR_CHAN_OFFSET(BB_ext_chan_scorr_thr) 112 #if 0 113 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] 114 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 115 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] 116 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 117 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] 118 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 119 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] 120 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 121 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 122 #endif 123 124 #define AR_PHY_EXT_CCA AR_CHAN_OFFSET(BB_ext_chan_pwr_thr_2_b0) 125 #define AR_PHY_RADAR_0 AR_CHAN_OFFSET(BB_radar_detection) /* radar detection settings */ 126 #define AR_PHY_RADAR_1 AR_CHAN_OFFSET(BB_radar_detection_2) 127 #define AR_PHY_RADAR_1_CF_BIN_THRESH 0x07000000 128 #define AR_PHY_RADAR_1_CF_BIN_THRESH_S 24 129 #define AR_PHY_RADAR_EXT AR_CHAN_OFFSET(BB_extension_radar) /* extension channel radar settings */ 130 #define AR_PHY_MULTICHAIN_CTRL AR_CHAN_OFFSET(BB_multichain_control) 131 #define AR_PHY_PERCHAIN_CSD AR_CHAN_OFFSET(BB_per_chain_csd) 132 133 #define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_OFFSET(BB_tx_phase_ramp_b0) 134 #define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_OFFSET(BB_adc_gain_dc_corr_b0) 135 #define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b0) 136 #define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b0) 137 #define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b0) 138 #define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b0) 139 140 #define AR_PHY_TX_IQ_CORR_0 AR_CHAN_OFFSET(BB_tx_iq_corr_b0) 141 #define AR_PHY_TX_CRC AR_CHAN_OFFSET(BB_tx_crc) 142 #define AR_PHY_TST_DAC_CONST AR_CHAN_OFFSET(BB_tstdac_constant) 143 #define AR_PHY_SPUR_REPORT_0 AR_CHAN_OFFSET(BB_spur_report_b0) 144 #define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_OFFSET(BB_chan_info_chan_tab_b0) 145 146 147 /* 148 * Channel Field Definitions 149 */ 150 /* BB_timing_controls_2 */ 151 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 152 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff 153 #define AR_PHY_TIMING2_HT_Fine_Timing_EN 0x80000000 154 #define AR_PHY_TIMING2_DC_OFFSET 0x08000000 155 #define AR_PHY_TIMING2_DC_OFFSET_S 27 156 157 /* BB_timing_controls_3 */ 158 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 159 #define AR_PHY_TIMING3_DSC_MAN_S 17 160 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 161 #define AR_PHY_TIMING3_DSC_EXP_S 13 162 /* BB_timing_control_4 */ 163 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 164 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 165 #define AR_PHY_TIMING4_DO_CAL 0x10000 /* perform calibration */ 166 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 167 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28 168 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 169 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29 170 171 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 172 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30 173 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 174 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31 175 176 /* BB_adc_gain_dc_corr_b0 */ 177 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 178 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 179 /* BB_self_corr_low */ 180 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 181 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 182 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 183 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 184 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 185 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 186 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 187 /* BB_sfcorr */ 188 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 189 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 190 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 191 #define AR_PHY_SFCORR_M1_THRESH_S 17 192 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 193 #define AR_PHY_SFCORR_M2_THRESH_S 24 194 /* BB_ext_chan_scorr_thr */ 195 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] 196 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 197 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] 198 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 199 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] 200 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 201 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] 202 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 203 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 204 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28 205 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 206 /* BB_ext_chan_pwr_thr_2_b0 */ 207 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 208 #define AR_PHY_EXT_CCA_THRESH62_S 16 209 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 210 #define AR_PHY_EXT_MINCCA_PWR_S 16 211 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L // [15:09] 212 #define AR_PHY_EXT_CYCPWR_THR1_S 9 213 /* BB_timing_control_5 */ 214 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 215 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 216 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 217 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 218 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 219 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 220 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) 221 #define AR_PHY_TIMING5_RSSI_THR1A_S 16 222 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) 223 /* BB_radar_detection) */ 224 #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ 225 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 /* Enable FFT data */ 226 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ 227 #define AR_PHY_RADAR_0_INBAND_S 1 228 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ 229 #define AR_PHY_RADAR_0_PRSSI_S 6 230 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ 231 #define AR_PHY_RADAR_0_HEIGHT_S 12 232 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ 233 #define AR_PHY_RADAR_0_RRSSI_S 18 234 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ 235 #define AR_PHY_RADAR_0_FIRPWR_S 24 236 /* BB_radar_detection_2 */ 237 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */ 238 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power 239 * measured over 128 cycles 240 */ 241 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */ 242 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 243 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak OFDM 244 * sig or pkt is immediately after tx to rx 245 * transition 246 */ 247 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */ 248 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */ 249 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */ 250 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 251 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */ 252 #define AR_PHY_RADAR_1_MAXLEN_S 0 253 /* BB_extension_radar */ 254 #define AR_PHY_RADAR_EXT_ENA 0x00004000 /* Enable extension channel radar detection */ 255 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 256 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 257 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 258 #define AR_PHY_RADAR_LB_DC_CAP_S 23 259 /* per chain csd*/ 260 #define AR_PHY_PERCHAIN_CSD_chn1_2chains 0x0000001f 261 #define AR_PHY_PERCHAIN_CSD_chn1_2chains_S 0 262 #define AR_PHY_PERCHAIN_CSD_chn1_3chains 0x000003e0 263 #define AR_PHY_PERCHAIN_CSD_chn1_3chains_S 5 264 #define AR_PHY_PERCHAIN_CSD_chn2_3chains 0x00007c00 265 #define AR_PHY_PERCHAIN_CSD_chn2_3chains_S 10 266 /* BB_find_signal_low */ 267 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) 268 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 269 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) 270 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 271 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 272 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f 273 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 274 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 275 /* BB_chan_info_chan_tab_b* */ 276 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 277 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 278 /* BB_rx_iq_corr_b* */ 279 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction */ 280 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 281 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 /* Mask for sin_theta for i correction */ 282 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 /* Shift for sin_theta for i correction */ 283 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 /* enable IQ correction */ 284 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 285 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 286 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 287 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 288 289 /* 290 * MRC Register Map 291 */ 292 #define AR_MRC_BASE offsetof(struct bb_reg_map, bb_mrc_reg_map) 293 #define AR_MRC_OFFSET(_x) (AR_MRC_BASE + offsetof(struct mrc_reg_map, _x)) 294 295 #define AR_PHY_TIMING_3A AR_MRC_OFFSET(BB_timing_control_3a) 296 #define AR_PHY_LDPC_CNTL1 AR_MRC_OFFSET(BB_ldpc_cntl1) 297 #define AR_PHY_LDPC_CNTL2 AR_MRC_OFFSET(BB_ldpc_cntl2) 298 #define AR_PHY_PILOT_SPUR_MASK AR_MRC_OFFSET(BB_pilot_spur_mask) 299 #define AR_PHY_CHAN_SPUR_MASK AR_MRC_OFFSET(BB_chan_spur_mask) 300 #define AR_PHY_SGI_DELTA AR_MRC_OFFSET(BB_short_gi_delta_slope) 301 #define AR_PHY_ML_CNTL_1 AR_MRC_OFFSET(BB_ml_cntl1) 302 #define AR_PHY_ML_CNTL_2 AR_MRC_OFFSET(BB_ml_cntl2) 303 #define AR_PHY_TST_ADC AR_MRC_OFFSET(BB_tstadc) 304 305 /* BB_pilot_spur_mask fields */ 306 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 307 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 308 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F 309 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 310 311 /* BB_chan_spur_mask fields */ 312 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 313 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 314 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F 315 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 316 317 /* 318 * MRC Feild Definitions 319 */ 320 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0 321 #define AR_PHY_SGI_DSC_MAN_S 4 322 #define AR_PHY_SGI_DSC_EXP 0x0000000F 323 #define AR_PHY_SGI_DSC_EXP_S 0 324 /* 325 * BBB Register Map 326 */ 327 #define AR_BBB_BASE offsetof(struct bb_reg_map, bb_bbb_reg_map) 328 #define AR_BBB_OFFSET(_x) (AR_BBB_BASE + offsetof(struct bbb_reg_map, _x)) 329 330 #define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) 331 332 /* 333 * AGC Register Map 334 */ 335 #define AR_AGC_BASE offsetof(struct bb_reg_map, bb_agc_reg_map) 336 #define AR_AGC_OFFSET(_x) (AR_AGC_BASE + offsetof(struct agc_reg_map, _x)) 337 338 #define AR_PHY_SETTLING AR_AGC_OFFSET(BB_settling_time) 339 #define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_OFFSET(BB_gain_force_max_gains_b0) 340 #define AR_PHY_GAINS_MINOFF0 AR_AGC_OFFSET(BB_gains_min_offsets_b0) 341 #define AR_PHY_DESIRED_SZ AR_AGC_OFFSET(BB_desired_sigsize) 342 #define AR_PHY_FIND_SIG AR_AGC_OFFSET(BB_find_signal) 343 #define AR_PHY_AGC AR_AGC_OFFSET(BB_agc) 344 #define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_OFFSET(BB_ext_atten_switch_ctl_b0) 345 #define AR_PHY_CCA_0 AR_AGC_OFFSET(BB_cca_b0) 346 #define AR_PHY_EXT_CCA0 AR_AGC_OFFSET(BB_cca_ctrl_2_b0) 347 #define AR_PHY_RESTART AR_AGC_OFFSET(BB_restart) 348 #define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) 349 #define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_OFFSET(BB_ext_chan_pwr_thr_1) 350 #define AR_PHY_EXT_CHN_WIN AR_AGC_OFFSET(BB_ext_chan_detect_win) 351 #define AR_PHY_20_40_DET_THR AR_AGC_OFFSET(BB_pwr_thr_20_40_det) 352 #define AR_PHY_RIFS_SRCH AR_AGC_OFFSET(BB_rifs_srch) 353 #define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_OFFSET(BB_peak_det_ctrl_1) 354 355 #define AR_PHY_PEAK_DET_ENABLE 0x00000002 356 357 #define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_OFFSET(BB_peak_det_ctrl_2) 358 #define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_OFFSET(BB_rx_gain_bounds_1) 359 #define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_OFFSET(BB_rx_gain_bounds_2) 360 #define AR_PHY_RSSI_0 AR_AGC_OFFSET(BB_rssi_b0) 361 #define AR_PHY_SPUR_CCK_REP0 AR_AGC_OFFSET(BB_spur_est_cck_report_b0) 362 #define AR_PHY_CCK_DETECT AR_AGC_OFFSET(BB_bbb_sig_detect) 363 #define AR_PHY_DAG_CTRLCCK AR_AGC_OFFSET(BB_bbb_dagc_ctrl) 364 #define AR_PHY_IQCORR_CTRL_CCK AR_AGC_OFFSET(BB_iqcorr_ctrl_cck) 365 #define AR_PHY_DIG_DC_STATUS_I_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_i_b0) 366 #define AR_PHY_DIG_DC_STATUS_Q_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_q_b0) 367 #define AR_PHY_DIG_DC_C1_RES 0x000001ff 368 #define AR_PHY_DIG_DC_C1_RES_S 0 369 #define AR_PHY_DIG_DC_C2_RES 0x0003fe00 370 #define AR_PHY_DIG_DC_C2_RES_S 9 371 #define AR_PHY_DIG_DC_C3_RES 0x07fc0000 372 #define AR_PHY_DIG_DC_C3_RES_S 18 373 374 #define AR_PHY_CCK_SPUR_MIT AR_AGC_OFFSET(BB_cck_spur_mit) 375 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe 376 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 377 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 378 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 379 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 380 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 381 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 382 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 383 384 #define AR_PHY_MRC_CCK_CTRL AR_AGC_OFFSET(BB_mrc_cck_ctrl) 385 #define AR_PHY_MRC_CCK_ENABLE 0x00000001 386 #define AR_PHY_MRC_CCK_ENABLE_S 0 387 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002 388 #define AR_PHY_MRC_CCK_MUX_REG_S 1 389 390 #define AR_PHY_RX_OCGAIN AR_AGC_OFFSET(BB_rx_ocgain) 391 392 #define AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ -110 393 #define AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ -115 394 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ -125 395 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ -125 396 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ -95 397 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ -100 398 #define AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ -105 399 400 #define AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ -127 401 #define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ -127 402 #define AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ -127 403 #define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ -127 404 405 #define AR_PHY_BT_COEX_4 AR_AGC_OFFSET(BB_bt_coex_4) 406 #define AR_PHY_BT_COEX_5 AR_AGC_OFFSET(BB_bt_coex_5) 407 408 /* 409 * Noise floor readings at least CW_INT_DELTA above the nominal NF 410 * indicate that CW interference is present. 411 */ 412 #define AR_PHY_CCA_CW_INT_DELTA 30 413 414 /* 415 * AGC Field Definitions 416 */ 417 /* BB_ext_atten_switch_ctl_b0 */ 418 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 419 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 420 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 421 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 422 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F 423 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 424 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 425 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 426 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 427 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 428 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 429 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 430 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F 431 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 432 /* BB_gain_force_max_gains_b0 */ 433 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 434 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 435 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 436 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 437 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 438 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 439 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 440 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 441 /* BB_settling_time */ 442 #define AR_PHY_SETTLING_SWITCH 0x00003F80 443 #define AR_PHY_SETTLING_SWITCH_S 7 444 /* BB_desired_sigsize */ 445 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 446 #define AR_PHY_DESIRED_SZ_ADC_S 0 447 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 448 #define AR_PHY_DESIRED_SZ_PGA_S 8 449 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 450 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 451 /* BB_cca_b0 */ 452 #define AR_PHY_MINCCA_PWR 0x1FF00000 453 #define AR_PHY_MINCCA_PWR_S 20 454 #define AR_PHY_CCA_THRESH62 0x0007F000 455 #define AR_PHY_CCA_THRESH62_S 12 456 #define AR9280_PHY_MINCCA_PWR 0x1FF00000 457 #define AR9280_PHY_MINCCA_PWR_S 20 458 #define AR9280_PHY_CCA_THRESH62 0x000FF000 459 #define AR9280_PHY_CCA_THRESH62_S 12 460 /* BB_cca_ctrl_2_b0 */ 461 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 462 #define AR_PHY_EXT_CCA0_THRESH62_S 0 463 /* BB_bbb_sig_detect */ 464 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 465 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 466 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch 467 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 468 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 469 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 470 471 /* BB_bbb_dagc_ctrl */ 472 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 473 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 474 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 475 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 476 477 /* BB_rifs_srch */ 478 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 479 480 /*B_tpc_7*/ 481 #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX 0x3f 482 #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX_S (0) 483 484 /* BB_agc */ 485 #define AR_PHY_AGC_QUICK_DROP_S (22) 486 #define AR_PHY_AGC_QUICK_DROP (0xf << AR_PHY_AGC_QUICK_DROP_S) 487 #define AR_PHY_AGC_COARSE_LOW 0x00007F80 488 #define AR_PHY_AGC_COARSE_LOW_S 7 489 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000 490 #define AR_PHY_AGC_COARSE_HIGH_S 15 491 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F 492 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 493 /* BB_find_signal */ 494 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 495 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 496 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 497 #define AR_PHY_FIND_SIG_FIRPWR_S 18 498 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 499 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) 500 #define AR_PHY_FIND_SIG_RELPWR_S 6 501 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 502 #define AR_PHY_FIND_SIG_RELSTEP 0x1f 503 #define AR_PHY_FIND_SIG_RELSTEP_S 0 504 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 505 /* BB_restart */ 506 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 507 #define AR_PHY_RESTART_DIV_GC_S 18 508 #define AR_PHY_RESTART_ENA 0x01 /* enable restart */ 509 #define AR_PHY_DC_RESTART_DIS 0x40000000 /* disable DC restart */ 510 511 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 //Mask BIT[31:24] 512 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 513 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 //Mask BIT[23:16] 514 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 515 516 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 //Mask BIT[25:24] 517 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 518 519 /* 520 * SM Register Map 521 */ 522 #define AR_SM_BASE offsetof(struct bb_reg_map, bb_sm_reg_map) 523 #define AR_SM_OFFSET(_x) (AR_SM_BASE + offsetof(struct sm_reg_map, _x)) 524 525 #define AR_PHY_D2_CHIP_ID AR_SM_OFFSET(BB_D2_chip_id) 526 #define AR_PHY_GEN_CTRL AR_SM_OFFSET(BB_gen_controls) 527 #define AR_PHY_MODE AR_SM_OFFSET(BB_modes_select) 528 #define AR_PHY_ACTIVE AR_SM_OFFSET(BB_active) 529 #define AR_PHY_SPUR_MASK_A AR_SM_OFFSET(BB_vit_spur_mask_A) 530 #define AR_PHY_SPUR_MASK_B AR_SM_OFFSET(BB_vit_spur_mask_B) 531 #define AR_PHY_SPECTRAL_SCAN AR_SM_OFFSET(BB_spectral_scan) 532 #define AR_PHY_RADAR_BW_FILTER AR_SM_OFFSET(BB_radar_bw_filter) 533 #define AR_PHY_SEARCH_START_DELAY AR_SM_OFFSET(BB_search_start_delay) 534 #define AR_PHY_MAX_RX_LEN AR_SM_OFFSET(BB_max_rx_length) 535 #define AR_PHY_FRAME_CTL AR_SM_OFFSET(BB_frame_control) 536 #define AR_PHY_RFBUS_REQ AR_SM_OFFSET(BB_rfbus_request) 537 #define AR_PHY_RFBUS_GRANT AR_SM_OFFSET(BB_rfbus_grant) 538 #define AR_PHY_RIFS AR_SM_OFFSET(BB_rifs) 539 #define AR_PHY_RX_CLR_DELAY AR_SM_OFFSET(BB_rx_clear_delay) 540 #define AR_PHY_RX_DELAY AR_SM_OFFSET(BB_analog_power_on_time) 541 #define AR_PHY_BB_POWERTX_RATE9 AR_SM_OFFSET(BB_powertx_rate9) 542 #define AR_PHY_TPC_7 AR_SM_OFFSET(BB_tpc_7) 543 #define AR_PHY_CL_MAP_0_B0 AR_SM_OFFSET(BB_cl_map_0_b0) 544 #define AR_PHY_CL_MAP_1_B0 AR_SM_OFFSET(BB_cl_map_1_b0) 545 #define AR_PHY_CL_MAP_2_B0 AR_SM_OFFSET(BB_cl_map_2_b0) 546 #define AR_PHY_CL_MAP_3_B0 AR_SM_OFFSET(BB_cl_map_3_b0) 547 548 #define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) 549 550 #define AR_PHY_XPA_TIMING_CTL AR_SM_OFFSET(BB_xpa_timing_control) 551 #define AR_PHY_MISC_PA_CTL AR_SM_OFFSET(BB_misc_pa_control) 552 #define AR_PHY_SWITCH_CHAIN_0 AR_SM_OFFSET(BB_switch_table_chn_b0) 553 #define AR_PHY_SWITCH_COM AR_SM_OFFSET(BB_switch_table_com1) 554 #define AR_PHY_SWITCH_COM_2 AR_SM_OFFSET(BB_switch_table_com2) 555 #define AR_PHY_RX_CHAINMASK AR_SM_OFFSET(BB_multichain_enable) 556 #define AR_PHY_CAL_CHAINMASK AR_SM_OFFSET(BB_cal_chain_mask) 557 #define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) 558 #define AR_PHY_CALMODE AR_SM_OFFSET(BB_iq_adc_cal_mode) 559 #define AR_PHY_FCAL_1 AR_SM_OFFSET(BB_fcal_1) 560 #define AR_PHY_FCAL_2_0 AR_SM_OFFSET(BB_fcal_2_b0) 561 #define AR_PHY_DFT_TONE_CTL_0 AR_SM_OFFSET(BB_dft_tone_ctrl_b0) 562 #define AR_PHY_CL_CAL_CTL AR_SM_OFFSET(BB_cl_cal_ctrl) 563 #define AR_PHY_BBGAINMAP_0_1_0 AR_SM_OFFSET(BB_cl_bbgain_map_0_1_b0) 564 #define AR_PHY_BBGAINMAP_2_3_0 AR_SM_OFFSET(BB_cl_bbgain_map_2_3_b0) 565 #define AR_PHY_CL_TAB_0 AR_SM_OFFSET(BB_cl_tab_b0) 566 #define AR_PHY_SYNTH_CONTROL AR_SM_OFFSET(BB_synth_control) 567 #define AR_PHY_ADDAC_CLK_SEL AR_SM_OFFSET(BB_addac_clk_select) 568 #define AR_PHY_PLL_CTL AR_SM_OFFSET(BB_pll_cntl) 569 #define AR_PHY_ANALOG_SWAP AR_SM_OFFSET(BB_analog_swap) 570 #define AR_PHY_ADDAC_PARA_CTL AR_SM_OFFSET(BB_addac_parallel_control) 571 #define AR_PHY_XPA_CFG AR_SM_OFFSET(BB_force_analog) 572 #define AR_PHY_AIC_CTRL_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_0_b0) 573 #define AR_PHY_AIC_CTRL_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_1_b0) 574 #define AR_PHY_AIC_CTRL_2_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_2_b0) 575 #define AR_PHY_AIC_CTRL_3_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_3_b0) 576 #define AR_PHY_AIC_STAT_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_0_b0) 577 #define AR_PHY_AIC_STAT_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_1_b0) 578 #define AR_PHY_AIC_CTRL_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_0_b0) 579 #define AR_PHY_AIC_CTRL_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_1_b0) 580 #define AR_PHY_AIC_CTRL_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_2_b0) 581 #define AR_PHY_AIC_CTRL_3_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_3_b0) 582 #define AR_PHY_AIC_CTRL_4_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_4_b0) 583 #define AR_PHY_AIC_STAT_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_0_b0) 584 #define AR_PHY_AIC_STAT_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_1_b0) 585 #define AR_PHY_AIC_STAT_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_2_b0) 586 #define AR_PHY_AIC_CTRL_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_0_b1) 587 #define AR_PHY_AIC_CTRL_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_1_b1) 588 #define AR_PHY_AIC_STAT_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_0_b1) 589 #define AR_PHY_AIC_STAT_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_1_b1) 590 #define AR_PHY_AIC_CTRL_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_0_b1) 591 #define AR_PHY_AIC_CTRL_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_1_b1) 592 #define AR_PHY_AIC_CTRL_4_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_4_b1) 593 #define AR_PHY_AIC_STAT_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_0_b1) 594 #define AR_PHY_AIC_STAT_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_1_b1) 595 #define AR_PHY_AIC_STAT_2_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_2_b1) 596 #define AR_PHY_AIC_SRAM_ADDR_B0 AR_SM_OFFSET(BB_tables_intf_addr_b0) 597 #define AR_PHY_AIC_SRAM_DATA_B0 AR_SM_OFFSET(BB_tables_intf_data_b0) 598 #define AR_PHY_AIC_SRAM_ADDR_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_addr_b1) 599 #define AR_PHY_AIC_SRAM_DATA_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_data_b1) 600 601 602 /* AIC fields */ 603 #define AR_PHY_AIC_MON_ENABLE 0x80000000 604 #define AR_PHY_AIC_MON_ENABLE_S 31 605 #define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 606 #define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 607 #define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 608 #define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 609 #define AR_PHY_AIC_F_WLAN 0x0001FC00 610 #define AR_PHY_AIC_F_WLAN_S 10 611 #define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 612 #define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 613 #define AR_PHY_AIC_CAL_ENABLE 0x00000100 614 #define AR_PHY_AIC_CAL_ENABLE_S 8 615 #define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE 616 #define AR_PHY_AIC_BTTX_PWR_THR_S 1 617 #define AR_PHY_AIC_ENABLE 0x00000001 618 #define AR_PHY_AIC_ENABLE_S 0 619 #define AR_PHY_AIC_CAL_BT_REF_DELAY 0x78000000 620 #define AR_PHY_AIC_CAL_BT_REF_DELAY_S 27 621 #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x07000000 622 #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 24 623 #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00F00000 624 #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 20 625 #define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 626 #define AR_PHY_AIC_BT_IDLE_CFG_S 19 627 #define AR_PHY_AIC_STDBY_COND 0x00060000 628 #define AR_PHY_AIC_STDBY_COND_S 17 629 #define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 630 #define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 631 #define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 632 #define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 633 #define AR_PHY_AIC_RSSI_MAX 0x000000F0 634 #define AR_PHY_AIC_RSSI_MAX_S 4 635 #define AR_PHY_AIC_RSSI_MIN 0x0000000F 636 #define AR_PHY_AIC_RSSI_MIN_S 0 637 #define AR_PHY_AIC_RADIO_DELAY 0x7F000000 638 #define AR_PHY_AIC_RADIO_DELAY_S 24 639 #define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 640 #define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 641 #define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 642 #define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 643 #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 644 #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 645 #define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 646 #define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 647 #define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 648 #define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 649 #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 650 #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 651 #define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF 652 #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 653 #define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x0FE00000 654 #define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 21 655 #define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x001FC000 656 #define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 14 657 #define AR_PHY_AIC_MON_PWR_EST_LONG 0x00002000 658 #define AR_PHY_AIC_MON_PWR_EST_LONG_S 13 659 #define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00001800 660 #define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 11 661 #define AR_PHY_AIC_MON_PERF_THR 0x000007C0 662 #define AR_PHY_AIC_MON_PERF_THR_S 6 663 #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000020 664 #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 5 665 #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 666 #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 667 #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 668 #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 669 #define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 670 #define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 671 #define AR_PHY_AIC_MON_DONE 0x80000000 672 #define AR_PHY_AIC_MON_DONE_S 31 673 #define AR_PHY_AIC_MON_ACTIVE 0x40000000 674 #define AR_PHY_AIC_MON_ACTIVE_S 30 675 #define AR_PHY_AIC_MEAS_COUNT 0x3F000000 676 #define AR_PHY_AIC_MEAS_COUNT_S 24 677 #define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 678 #define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 679 #define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 680 #define AR_PHY_AIC_CAL_HOP_COUNT_S 11 681 #define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 682 #define AR_PHY_AIC_CAL_VALID_COUNT_S 4 683 #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 684 #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 685 #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 686 #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 687 #define AR_PHY_AIC_CAL_DONE 0x00000002 688 #define AR_PHY_AIC_CAL_DONE_S 1 689 #define AR_PHY_AIC_CAL_ACTIVE 0x00000001 690 #define AR_PHY_AIC_CAL_ACTIVE_S 0 691 #define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 692 #define AR_PHY_AIC_MEAS_MAG_MIN_S 22 693 #define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 694 #define AR_PHY_AIC_MON_STALE_COUNT_S 15 695 #define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 696 #define AR_PHY_AIC_MON_HOP_COUNT_S 8 697 #define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 698 #define AR_PHY_AIC_CAL_AIC_SM_S 3 699 #define AR_PHY_AIC_SM 0x00000007 700 #define AR_PHY_AIC_SM_S 0 701 #define AR_PHY_AIC_SRAM_VALID 0x00000001 702 #define AR_PHY_AIC_SRAM_VALID_S 0 703 #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E 704 #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 705 #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 706 #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 707 #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 708 #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 709 #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 710 #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 711 #define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 712 #define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 713 714 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 715 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 716 717 /* BB_cl_tab_bx */ 718 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I 0x07FF0000 719 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I_S 16 720 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q 0x0000FFE0 721 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q_S 5 722 #define AR_PHY_CL_TAB_GAIN_MOD 0x0000001F 723 #define AR_PHY_CL_TAB_GAIN_MOD_S 0 724 725 /* BB_vit_spur_mask_A fields */ 726 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 727 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 728 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF 729 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 730 731 /* enable_flt_svd*/ 732 #define AR_PHY_ENABLE_FLT_SVD 0x00001000 733 #define AR_PHY_ENABLE_FLT_SVD_S 12 734 735 #define AR_PHY_TEST AR_SM_OFFSET(BB_test_controls) 736 737 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 738 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 /* bits 19 to 22 are cf_bbb_obs_sel*/ 739 740 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 741 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)// This is bit 5 for cf_rx_obs_sel 742 743 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 744 #define AR_PHY_TEST_CHAIN_SEL_S 30 /*bits 30 and 31 are tstdac_out_sel which selects which chain to drive out*/ 745 746 #define AR_PHY_TEST_CTL_STATUS AR_SM_OFFSET(BB_test_controls_status) 747 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 748 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 /*cf_tstdac_en, driver to tstdac bus, 0=disable, 1=enable*/ 749 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C 750 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 /* cf_tx_obs_sel, bits 2:4*/ 751 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 752 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 /* cf_tx_obs_sel, bits 5:6, setting to 11 selects ADC*/ 753 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100 754 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 /*cf_tstadc_en, driver to tstadc bus, 0=disable, 1=enable*/ 755 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 756 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 /* cf_tx_obs_sel, bits 10:13*/ 757 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 758 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 759 760 761 #define AR_PHY_TSTDAC AR_SM_OFFSET(BB_tstdac) 762 763 #define AR_PHY_CHAN_STATUS AR_SM_OFFSET(BB_channel_status) 764 #define AR_PHY_CHAN_INFO_MEMORY AR_SM_OFFSET(BB_chaninfo_ctrl) 765 #define AR_PHY_CHNINFO_NOISEPWR AR_SM_OFFSET(BB_chan_info_noise_pwr) 766 #define AR_PHY_CHNINFO_GAINDIFF AR_SM_OFFSET(BB_chan_info_gain_diff) 767 #define AR_PHY_CHNINFO_FINETIM AR_SM_OFFSET(BB_chan_info_fine_timing) 768 #define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_OFFSET(BB_chan_info_gain_b0) 769 #define AR_PHY_SCRAMBLER_SEED AR_SM_OFFSET(BB_scrambler_seed) 770 #define AR_PHY_CCK_TX_CTRL AR_SM_OFFSET(BB_bbb_tx_ctrl) 771 772 #define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) 773 774 #define AR_PHY_HEAVYCLIP_CTL AR_SM_OFFSET(BB_heavy_clip_ctrl) 775 #define AR_PHY_HEAVYCLIP_20 AR_SM_OFFSET(BB_heavy_clip_20) 776 #define AR_PHY_HEAVYCLIP_40 AR_SM_OFFSET(BB_heavy_clip_40) 777 #define AR_PHY_ILLEGAL_TXRATE AR_SM_OFFSET(BB_illegal_tx_rate) 778 779 #define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i) 780 781 #define AR_PHY_PWRTX_MAX AR_SM_OFFSET(BB_powertx_max) /* TPC register */ 782 #define AR_PHY_PWRTX_MAX_TPC_ENABLE 0x00000040 783 #define AR_PHY_POWER_TX_SUB AR_SM_OFFSET(BB_powertx_sub) 784 #define AR_PHY_PER_PACKET_POWERTX_MAX 0x00000040 785 #define AR_PHY_PER_PACKET_POWERTX_MAX_S 6 786 #define AR_PHY_POWER_TX_SUB_2_DISABLE 0xFFFFFFC0 /* 2 chain */ 787 #define AR_PHY_POWER_TX_SUB_3_DISABLE 0xFFFFF000 /* 3 chain */ 788 789 #define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* values 1-3, 7-10 and 12-15 */ 790 #define AR_PHY_TPC_4_B0 AR_SM_OFFSET(BB_tpc_4_b0) 791 #define AR_PHY_TPC_5_B0 AR_SM_OFFSET(BB_tpc_5_b0) 792 #define AR_PHY_TPC_6_B0 AR_SM_OFFSET(BB_tpc_6_b0) 793 #define AR_PHY_TPC_18 AR_SM_OFFSET(BB_tpc_18) 794 #define AR_PHY_TPC_19 AR_SM_OFFSET(BB_tpc_19) 795 796 #define AR_PHY_TX_FORCED_GAIN AR_SM_OFFSET(BB_tx_forced_gain) 797 798 #define AR_PHY_PDADC_TAB_0 AR_SM_OFFSET(BB_pdadc_tab_b0) 799 800 #define AR_PHY_RTT_CTRL AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_ctrl) 801 #define AR_PHY_RTT_TABLE_SW_INTF_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_b0) 802 #define AR_PHY_RTT_TABLE_SW_INTF_1_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_1_b0) 803 804 #define AR_PHY_TX_IQCAL_CONTROL_0(_ah) \ 805 (AR_SREV_POSEIDON(_ah) ? \ 806 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ 807 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_0)) 808 809 #define AR_PHY_TX_IQCAL_CONTROL_1(_ah) \ 810 (AR_SREV_POSEIDON(_ah) ? \ 811 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_1) : \ 812 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_1)) 813 814 #define AR_PHY_TX_IQCAL_START(_ah) \ 815 (AR_SREV_POSEIDON(_ah) ? \ 816 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ 817 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_start)) 818 819 #define AR_PHY_TX_IQCAL_STATUS_B0(_ah) \ 820 (AR_SREV_POSEIDON(_ah) ? \ 821 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_status_b0) : \ 822 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_status_b0)) 823 824 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_01_b0) 825 #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_23_b0) 826 #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_45_b0) 827 #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_67_b0) 828 829 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_01_b0) 830 #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_23_b0) 831 #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_45_b0) 832 #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_67_b0) 833 834 #define AR_PHY_TXGAIN_TAB(_i) AR_SM_OFFSET(BB_tx_gain_tab_##_i) /* values 1-22 */ 835 #define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ 836 #define AR_PHY_PANIC_WD_STATUS AR_SM_OFFSET(BB_panic_watchdog_status) 837 #define AR_PHY_PANIC_WD_CTL_1 AR_SM_OFFSET(BB_panic_watchdog_ctrl_1) 838 #define AR_PHY_PANIC_WD_CTL_2 AR_SM_OFFSET(BB_panic_watchdog_ctrl_2) 839 #define AR_PHY_BT_CTL AR_SM_OFFSET(BB_bluetooth_cntl) 840 #define AR_PHY_ONLY_WARMRESET AR_SM_OFFSET(BB_phyonly_warm_reset) 841 #define AR_PHY_ONLY_CTL AR_SM_OFFSET(BB_phyonly_control) 842 #define AR_PHY_ECO_CTRL AR_SM_OFFSET(BB_eco_ctrl) 843 #define AR_PHY_BB_THERM_ADC_1 AR_SM_OFFSET(BB_therm_adc_1) 844 #define AR_PHY_BB_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) 845 846 #define AR_PHY_65NM(_field) offsetof(struct radio65_reg, _field) 847 #define AR_PHY_65NM_CH0_TXRF1 AR_PHY_65NM(ch0_TXRF1) 848 #define AR_PHY_65NM_CH0_TXRF2 AR_PHY_65NM(ch0_TXRF2) 849 #define AR_PHY_65NM_CH0_TXRF2_DB2G 0x07000000 850 #define AR_PHY_65NM_CH0_TXRF2_DB2G_S 24 851 #define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK 0x00E00000 852 #define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK_S 21 853 #define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK 0x001C0000 854 #define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK_S 18 855 #define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM 0x00038000 856 #define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM_S 15 857 #define AR_PHY_65NM_CH0_TXRF3 AR_PHY_65NM(ch0_TXRF3) 858 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001E 859 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 860 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE 0x00000001 861 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE_S 0 862 #define AR_PHY_65NM_CH1_TXRF1 AR_PHY_65NM(ch1_TXRF1) 863 #define AR_PHY_65NM_CH1_TXRF2 AR_PHY_65NM(ch1_TXRF2) 864 #define AR_PHY_65NM_CH1_TXRF3 AR_PHY_65NM(ch1_TXRF3) 865 #define AR_PHY_65NM_CH2_TXRF1 AR_PHY_65NM(ch2_TXRF1) 866 #define AR_PHY_65NM_CH2_TXRF2 AR_PHY_65NM(ch2_TXRF2) 867 #define AR_PHY_65NM_CH2_TXRF3 AR_PHY_65NM(ch2_TXRF3) 868 869 #define AR_PHY_65NM_CH0_SYNTH4 AR_PHY_65NM(ch0_SYNTH4) 870 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 871 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 872 #define AR_PHY_65NM_CH0_SYNTH7 AR_PHY_65NM(ch0_SYNTH7) 873 #define AR_PHY_65NM_CH0_BIAS1 AR_PHY_65NM(ch0_BIAS1) 874 #define AR_PHY_65NM_CH0_BIAS2 AR_PHY_65NM(ch0_BIAS2) 875 #define AR_PHY_65NM_CH0_BIAS4 AR_PHY_65NM(ch0_BIAS4) 876 #define AR_PHY_65NM_CH0_RXTX4 AR_PHY_65NM(ch0_RXTX4) 877 #define AR_PHY_65NM_CH0_SYNTH12 AR_PHY_65NM(ch0_SYNTH12) 878 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000 879 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19 880 #define AR_PHY_65NM_CH1_RXTX4 AR_PHY_65NM(ch1_RXTX4) 881 #define AR_PHY_65NM_CH2_RXTX4 AR_PHY_65NM(ch2_RXTX4) 882 #define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000 883 #define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30 884 885 #define AR_PHY_65NM_CH0_TOP AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP) 886 #define AR_PHY_65NM_CH0_TOP_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_TOP1) 887 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL 0x00000300 888 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 889 #define AR_PHY_65NM_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP2) 890 891 #define AR_OSPREY_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_XTAL) 892 #define AR_OSPREY_CHO_XTAL_CAPINDAC 0x7F000000 893 #define AR_OSPREY_CHO_XTAL_CAPINDAC_S 24 894 #define AR_OSPREY_CHO_XTAL_CAPOUTDAC 0x00FE0000 895 #define AR_OSPREY_CHO_XTAL_CAPOUTDAC_S 17 896 897 #define AR_PHY_65NM_CH0_THERM AR_PHY_65NM(overlay_0x16180.Osprey.ch0_THERM) 898 #define AR_PHY_65NM_CH0_THERM_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_THERM) 899 900 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB 0x00000003 901 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 902 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 903 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND_S 2 904 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 905 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 906 #define AR_PHY_65NM_CH0_THERM_START 0x20000000 907 #define AR_PHY_65NM_CH0_THERM_START_S 29 908 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 909 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 910 911 #define AR_PHY_65NM_CH0_RXTX1 AR_PHY_65NM(ch0_RXTX1) 912 #define AR_PHY_65NM_CH0_RXTX2 AR_PHY_65NM(ch0_RXTX2) 913 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004 914 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2 915 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008 916 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3 917 #define AR_PHY_65NM_CH0_RXTX3 AR_PHY_65NM(ch0_RXTX3) 918 #define AR_PHY_65NM_CH1_RXTX1 AR_PHY_65NM(ch1_RXTX1) 919 #define AR_PHY_65NM_CH1_RXTX2 AR_PHY_65NM(ch1_RXTX2) 920 #define AR_PHY_65NM_CH1_RXTX3 AR_PHY_65NM(ch1_RXTX3) 921 #define AR_PHY_65NM_CH2_RXTX1 AR_PHY_65NM(ch2_RXTX1) 922 #define AR_PHY_65NM_CH2_RXTX2 AR_PHY_65NM(ch2_RXTX2) 923 #define AR_PHY_65NM_CH2_RXTX3 AR_PHY_65NM(ch2_RXTX3) 924 925 #define AR_PHY_65NM_CH0_BB1 AR_PHY_65NM(ch0_BB1) 926 #define AR_PHY_65NM_CH0_BB2 AR_PHY_65NM(ch0_BB2) 927 #define AR_PHY_65NM_CH0_BB3 AR_PHY_65NM(ch0_BB3) 928 #define AR_PHY_65NM_CH1_BB1 AR_PHY_65NM(ch1_BB1) 929 #define AR_PHY_65NM_CH1_BB2 AR_PHY_65NM(ch1_BB2) 930 #define AR_PHY_65NM_CH1_BB3 AR_PHY_65NM(ch1_BB3) 931 #define AR_PHY_65NM_CH2_BB1 AR_PHY_65NM(ch2_BB1) 932 #define AR_PHY_65NM_CH2_BB2 AR_PHY_65NM(ch2_BB2) 933 #define AR_PHY_CH_BB3_SEL_OFST_READBK 0x00000300 934 #define AR_PHY_CH_BB3_SEL_OFST_READBK_S 8 935 #define AR_PHY_CH_BB3_OFSTCORRI2VQ 0x03e00000 936 #define AR_PHY_CH_BB3_OFSTCORRI2VQ_S 21 937 #define AR_PHY_CH_BB3_OFSTCORRI2VI 0x7c000000 938 #define AR_PHY_CH_BB3_OFSTCORRI2VI_S 26 939 940 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 941 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 942 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 943 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 944 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 945 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 946 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 947 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 948 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 949 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 950 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 951 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 952 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 953 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 954 #define AR_PHY_MANTXGAIN_LONG_SHIFT 0x80000000 955 #define AR_PHY_MANTXGAIN_LONG_SHIFT_S 31 956 957 /* 958 * SM Field Definitions 959 */ 960 961 /* BB_cl_cal_ctrl - AR_PHY_CL_CAL_CTL */ 962 #define AR_PHY_CL_CAL_ENABLE 0x00000002 /* do carrier leak calibration after agc_calibrate_done */ 963 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 964 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 965 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 966 #define AR_PHY_CL_MAP_HW_GEN 0x80000000 967 #define AR_PHY_CL_MAP_HW_GEN_S 31 968 969 /* BB_addac_parallel_control - AR_PHY_ADDAC_PARA_CTL */ 970 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 971 972 /* BB_fcal_2_b0 - AR_PHY_FCAL_2_0 */ 973 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 974 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 975 976 /* BB_rfbus_request */ 977 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ 978 /* BB_rfbus_grant */ 979 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ 980 /* BB_gen_controls */ 981 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ 982 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ 983 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ 984 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 985 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 986 #define AR_PHY_GC_DYN2040_PRI_CH_S 4 987 988 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 989 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ 990 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 991 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 992 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 993 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ 994 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ 995 996 #define AR_PHY_MS_HALF_RATE 0x00000020 997 #define AR_PHY_MS_QUARTER_RATE 0x00000040 998 999 /* BB_analog_power_on_time */ 1000 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 1001 /* BB_agc_control */ 1002 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 1003 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ 1004 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ 1005 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ 1006 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ 1007 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 1008 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 1009 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 1010 #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 /* allow peak deteter calibration */ 1011 1012 #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 1013 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 1014 1015 /* BB_iq_adc_cal_mode */ 1016 #define AR_PHY_CALMODE_IQ 0x00000000 1017 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 1018 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 1019 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 1020 /* BB_analog_swap */ 1021 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 1022 /* BB_modes_select */ 1023 #define AR_PHY_MODE_OFDM 0x00000000 /* OFDM */ 1024 #define AR_PHY_MODE_CCK 0x00000001 /* CCK */ 1025 #define AR_PHY_MODE_DYNAMIC 0x00000004 /* dynamic CCK/OFDM mode */ 1026 #define AR_PHY_MODE_DYNAMIC_S 2 1027 #define AR_PHY_MODE_HALF 0x00000020 /* enable half rate */ 1028 #define AR_PHY_MODE_QUARTER 0x00000040 /* enable quarter rate */ 1029 #define AR_PHY_MAC_CLK_MODE 0x00000080 /* MAC runs at 128/141MHz clock */ 1030 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 /* Disable dynamic CCK detection */ 1031 #define AR_PHY_MODE_SVD_HALF 0x00000200 /* enable svd half rate */ 1032 #define AR_PHY_MODE_DISABLE_CCK 0x00000100 1033 #define AR_PHY_MODE_DISABLE_CCK_S 8 1034 /* BB_active */ 1035 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ 1036 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ 1037 /* BB_force_analog */ 1038 #define AR_PHY_FORCE_XPA_CFG 0x000000001 1039 #define AR_PHY_FORCE_XPA_CFG_S 0 1040 /* BB_xpa_timing_control */ 1041 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 1042 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 1043 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 1044 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 1045 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 1046 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 1047 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF 1048 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 1049 /* BB_tx_timing_3 */ 1050 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 1051 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 1052 /* BB_tx_timing_2 */ 1053 #define AR_PHY_TX_END_DATA_START 0x000000FF 1054 #define AR_PHY_TX_END_DATA_START_S 0 1055 #define AR_PHY_TX_END_PA_ON 0x0000FF00 1056 #define AR_PHY_TX_END_PA_ON_S 8 1057 /* BB_tpc_5_b0 */ 1058 /* ar2413 power control */ 1059 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 1060 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 1061 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 1062 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 1063 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 1064 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 1065 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 1066 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 1067 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 1068 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 1069 /* BB_tpc_1 */ 1070 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 1071 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 1072 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 1073 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 1074 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 1075 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 1076 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 1077 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 1078 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e 1079 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 1080 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 1081 1082 /* BB_tx_forced_gain */ 1083 #define AR_PHY_TXGAIN_FORCE 0x00000001 1084 #define AR_PHY_TXGAIN_FORCE_S 0 1085 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 1086 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 1087 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 1088 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 1089 #define AR_PHY_TXGAIN_FORCED_PADVGNRC 0x003c0000 1090 #define AR_PHY_TXGAIN_FORCED_PADVGNRC_S 18 1091 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 1092 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 1093 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 1094 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 1095 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e 1096 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 1097 #define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN 0x00000030 1098 #define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN_S 4 1099 1100 /* BB_powertx_rate1 */ 1101 #define AR_PHY_POWER_TX_RATE1 0x9934 1102 #define AR_PHY_POWER_TX_RATE2 0x9938 1103 #define AR_PHY_POWER_TX_RATE_MAX AR_PHY_PWRTX_MAX 1104 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 1105 /* BB_test_controls */ 1106 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ 1107 #define RFSILENT_BB 0x00002000 /* shush bb */ 1108 /* BB_chan_info_gain_diff */ 1109 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF /* PPM value is 12-bit signed integer */ 1110 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 /* Sign bit */ 1111 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 /* Maximum absolute value */ 1112 /* BB_chaninfo_ctrl */ 1113 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 1114 /* BB_search_start_delay */ 1115 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 1116 /* BB_bbb_tx_ctrl */ 1117 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 1118 /* BB_spectral_scan */ 1119 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 /* Enable spectral scan */ 1120 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 1121 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan */ 1122 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 1123 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports */ 1124 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 1125 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports */ 1126 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 1127 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000 /* Number of reports */ 1128 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 1129 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000 /* Short repeat */ 1130 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28 1131 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI 0x20000000 /* high priority */ 1132 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI_S 29 1133 /* BB_channel_status */ 1134 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 1135 /* BB_rtt_ctrl */ 1136 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 1137 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 1138 #define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E 1139 #define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1 1140 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080 1141 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7 1142 /* BB_rtt_table_sw_intf_b0 */ 1143 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0 0x00000001 1144 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0_S 0 1145 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0 0x00000002 1146 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0_S 1 1147 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0 0x0000001C 1148 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0_S 2 1149 /* BB_rtt_table_sw_intf_1_b0 */ 1150 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_0 0xFFFFFFF0 1151 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_0_S 4 1152 /* BB_txiqcal_control_0 */ 1153 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000 1154 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31 1155 /* BB_txiqcal_control_1 */ 1156 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 1157 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 1158 /* BB_txiqcal_start */ 1159 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 1160 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 1161 /* BB_txiqcal_start for Poseidon */ 1162 #define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON 0x80000000 1163 #define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON_S 31 1164 1165 /* Generic B0, B1, B2 IQ Cal bit fields */ 1166 /* BB_txiqcal_status_b* */ 1167 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 1168 #define AR_PHY_CALIBRATED_GAINS_0_S 1 1169 #define AR_PHY_CALIBRATED_GAINS_0 (0x1f<<AR_PHY_CALIBRATED_GAINS_0_S) 1170 /* BB_txiq_corr_coeff_01_b* */ 1171 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0 1172 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff 1173 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14 1174 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE (0x00003fff<<AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S) 1175 1176 /* temp compensation */ 1177 /* BB_tpc_18 */ 1178 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff //Mask bits 7:0 1179 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0 1180 /* BB_tpc_19 */ 1181 #define AR_PHY_TPC_19_ALPHA_THERM 0xff //Mask bits 7:0 1182 #define AR_PHY_TPC_19_ALPHA_THERM_S 0 1183 1184 /* ch0_RXTX4 */ 1185 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 1186 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 1187 1188 /* BB_therm_adc_1 */ 1189 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff 1190 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 1191 1192 /* BB_therm_adc_4 */ 1193 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM 0x000000ff 1194 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0 1195 1196 /* BB_switch_table_chn_b */ 1197 #define AR_PHY_SWITCH_TABLE_R0 0x00000010 1198 #define AR_PHY_SWITCH_TABLE_R0_S 4 1199 #define AR_PHY_SWITCH_TABLE_R1 0x00000040 1200 #define AR_PHY_SWITCH_TABLE_R1_S 6 1201 #define AR_PHY_SWITCH_TABLE_R12 0x00000100 1202 #define AR_PHY_SWITCH_TABLE_R12_S 8 1203 1204 /* 1205 * Channel 1 Register Map 1206 */ 1207 #define AR_CHAN1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_chn1_reg_map) 1208 #define AR_CHAN1_OFFSET(_x) (AR_CHAN1_BASE + offsetof(struct chn1_reg_map, _x)) 1209 1210 #define AR_PHY_TIMING4_1 AR_CHAN1_OFFSET(BB_timing_control_4_b1) 1211 #define AR_PHY_EXT_CCA_1 AR_CHAN1_OFFSET(BB_ext_chan_pwr_thr_2_b1) 1212 #define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_OFFSET(BB_tx_phase_ramp_b1) 1213 #define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_OFFSET(BB_adc_gain_dc_corr_b1) 1214 1215 #define AR_PHY_IQ_ADC_MEAS_0_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b1) 1216 #define AR_PHY_IQ_ADC_MEAS_1_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b1) 1217 #define AR_PHY_IQ_ADC_MEAS_2_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b1) 1218 #define AR_PHY_IQ_ADC_MEAS_3_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b1) 1219 1220 #define AR_PHY_TX_IQ_CORR_1 AR_CHAN1_OFFSET(BB_tx_iq_corr_b1) 1221 #define AR_PHY_SPUR_REPORT_1 AR_CHAN1_OFFSET(BB_spur_report_b1) 1222 #define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_OFFSET(BB_chan_info_chan_tab_b1) 1223 #define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_OFFSET(BB_rx_iq_corr_b1) 1224 1225 /* 1226 * Channel 1 Field Definitions 1227 */ 1228 /* BB_ext_chan_pwr_thr_2_b1 */ 1229 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 1230 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16 1231 1232 /* 1233 * AGC 1 Register Map 1234 */ 1235 #define AR_AGC1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_agc1_reg_map) 1236 #define AR_AGC1_OFFSET(_x) (AR_AGC1_BASE + offsetof(struct agc1_reg_map, _x)) 1237 1238 #define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_OFFSET(BB_gain_force_max_gains_b1) 1239 #define AR_PHY_GAINS_MINOFF_1 AR_AGC1_OFFSET(BB_gains_min_offsets_b1) 1240 #define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_OFFSET(BB_ext_atten_switch_ctl_b1) 1241 #define AR_PHY_CCA_1 AR_AGC1_OFFSET(BB_cca_b1) 1242 #define AR_PHY_CCA_CTRL_1 AR_AGC1_OFFSET(BB_cca_ctrl_2_b1) 1243 #define AR_PHY_RSSI_1 AR_AGC1_OFFSET(BB_rssi_b1) 1244 #define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_OFFSET(BB_spur_est_cck_report_b1) 1245 #define AR_PHY_RX_OCGAIN_2 AR_AGC1_OFFSET(BB_rx_ocgain2) 1246 #define AR_PHY_DIG_DC_STATUS_I_B1 AR_AGC1_OFFSET(BB_agc_dig_dc_status_i_b1) 1247 #define AR_PHY_DIG_DC_STATUS_Q_B1 AR_AGC1_OFFSET(BB_agc_dig_dc_status_q_b1) 1248 1249 /* 1250 * AGC 1 Register Map for Poseidon 1251 */ 1252 #define AR_AGC1_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_agc1_reg_map) 1253 #define AR_AGC1_OFFSET_POSEIDON(_x) (AR_AGC1_BASE_POSEIDON + offsetof(struct agc1_reg_map, _x)) 1254 1255 #define AR_PHY_FORCEMAX_GAINS_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_gain_force_max_gains_b1) 1256 #define AR_PHY_EXT_ATTEN_CTL_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_ext_atten_switch_ctl_b1) 1257 #define AR_PHY_RSSI_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_rssi_b1) 1258 #define AR_PHY_RX_OCGAIN_2_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_rx_ocgain2) 1259 1260 /* 1261 * AGC 1 Field Definitions 1262 */ 1263 /* BB_cca_b1 */ 1264 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000 1265 #define AR_PHY_CH1_MINCCA_PWR_S 20 1266 1267 /* 1268 * SM 1 Register Map 1269 */ 1270 #define AR_SM1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_sm1_reg_map) 1271 #define AR_SM1_OFFSET(_x) (AR_SM1_BASE + offsetof(struct sm1_reg_map, _x)) 1272 1273 #define AR_PHY_SWITCH_CHAIN_1 AR_SM1_OFFSET(BB_switch_table_chn_b1) 1274 #define AR_PHY_FCAL_2_1 AR_SM1_OFFSET(BB_fcal_2_b1) 1275 #define AR_PHY_DFT_TONE_CTL_1 AR_SM1_OFFSET(BB_dft_tone_ctrl_b1) 1276 #define AR_PHY_BBGAINMAP_0_1_1 AR_SM1_OFFSET(BB_cl_bbgain_map_0_1_b1) 1277 #define AR_PHY_BBGAINMAP_2_3_1 AR_SM1_OFFSET(BB_cl_bbgain_map_2_3_b1) 1278 #define AR_PHY_CL_TAB_1 AR_SM1_OFFSET(BB_cl_tab_b1) 1279 #define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_OFFSET(BB_chan_info_gain_b1) 1280 #define AR_PHY_TPC_4_B1 AR_SM1_OFFSET(BB_tpc_4_b1) 1281 #define AR_PHY_TPC_5_B1 AR_SM1_OFFSET(BB_tpc_5_b1) 1282 #define AR_PHY_TPC_6_B1 AR_SM1_OFFSET(BB_tpc_6_b1) 1283 #define AR_PHY_TPC_11_B1 AR_SM1_OFFSET(BB_tpc_11_b1) 1284 #define AR_SCORPION_PHY_TPC_19_B1 AR_SM1_OFFSET(overlay_b440.Scorpion.BB_tpc_19_b1) 1285 #define AR_PHY_PDADC_TAB_1 AR_SM1_OFFSET(overlay_b440.BB_pdadc_tab_b1) 1286 1287 1288 #define AR_PHY_RTT_TABLE_SW_INTF_B1 AR_SM1_OFFSET(overlay_b440.Jupiter_20.BB_rtt_table_sw_intf_b1) 1289 #define AR_PHY_RTT_TABLE_SW_INTF_1_B1 AR_SM1_OFFSET(overlay_b440.Jupiter_20.BB_rtt_table_sw_intf_1_b1) 1290 1291 #define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_OFFSET(BB_txiqcal_status_b1) 1292 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_01_b1) 1293 #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_23_b1) 1294 #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_45_b1) 1295 #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_67_b1) 1296 #define AR_PHY_CL_MAP_0_B1 AR_SM1_OFFSET(BB_cl_map_0_b1) 1297 #define AR_PHY_CL_MAP_1_B1 AR_SM1_OFFSET(BB_cl_map_1_b1) 1298 #define AR_PHY_CL_MAP_2_B1 AR_SM1_OFFSET(BB_cl_map_2_b1) 1299 #define AR_PHY_CL_MAP_3_B1 AR_SM1_OFFSET(BB_cl_map_3_b1) 1300 /* 1301 * SM 1 Field Definitions 1302 */ 1303 /* BB_rtt_table_sw_intf_b1 */ 1304 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1 0x00000001 1305 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1_S 0 1306 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_1 0x00000002 1307 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_1_S 1 1308 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_1 0x0000001C 1309 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_1_S 2 1310 /* BB_rtt_table_sw_intf_1_b1 */ 1311 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_1 0xFFFFFFF0 1312 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_1_S 4 1313 1314 /* 1315 * SM 1 Register Map for Poseidon 1316 */ 1317 #define AR_SM1_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_sm1_reg_map) 1318 #define AR_SM1_OFFSET_POSEIDON(_x) (AR_SM1_BASE_POSEIDON + offsetof(struct sm1_reg_map, _x)) 1319 1320 #define AR_PHY_SWITCH_CHAIN_1_POSEIDON AR_SM1_OFFSET_POSEIDON(BB_switch_table_chn_b1) 1321 1322 /* 1323 * Channel 2 Register Map 1324 */ 1325 #define AR_CHAN2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_chn2_reg_map) 1326 #define AR_CHAN2_OFFSET(_x) (AR_CHAN2_BASE + offsetof(struct chn2_reg_map, _x)) 1327 1328 #define AR_PHY_TIMING4_2 AR_CHAN2_OFFSET(BB_timing_control_4_b2) 1329 #define AR_PHY_EXT_CCA_2 AR_CHAN2_OFFSET(BB_ext_chan_pwr_thr_2_b2) 1330 #define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_OFFSET(BB_tx_phase_ramp_b2) 1331 #define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_OFFSET(BB_adc_gain_dc_corr_b2) 1332 1333 #define AR_PHY_IQ_ADC_MEAS_0_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b2) 1334 #define AR_PHY_IQ_ADC_MEAS_1_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b2) 1335 #define AR_PHY_IQ_ADC_MEAS_2_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b2) 1336 #define AR_PHY_IQ_ADC_MEAS_3_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b2) 1337 1338 #define AR_PHY_TX_IQ_CORR_2 AR_CHAN2_OFFSET(BB_tx_iq_corr_b2) 1339 #define AR_PHY_SPUR_REPORT_2 AR_CHAN2_OFFSET(BB_spur_report_b2) 1340 #define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_OFFSET(BB_chan_info_chan_tab_b2) 1341 #define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_OFFSET(BB_rx_iq_corr_b2) 1342 1343 /* 1344 * Channel 2 Field Definitions 1345 */ 1346 /* BB_ext_chan_pwr_thr_2_b2 */ 1347 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000 1348 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16 1349 /* 1350 * AGC 2 Register Map 1351 */ 1352 #define AR_AGC2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_agc2_reg_map) 1353 #define AR_AGC2_OFFSET(_x) (AR_AGC2_BASE + offsetof(struct agc2_reg_map, _x)) 1354 1355 #define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_OFFSET(BB_gain_force_max_gains_b2) 1356 #define AR_PHY_GAINS_MINOFF_2 AR_AGC2_OFFSET(BB_gains_min_offsets_b2) 1357 #define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_OFFSET(BB_ext_atten_switch_ctl_b2) 1358 #define AR_PHY_CCA_2 AR_AGC2_OFFSET(BB_cca_b2) 1359 #define AR_PHY_CCA_CTRL_2 AR_AGC2_OFFSET(BB_cca_ctrl_2_b2) 1360 #define AR_PHY_RSSI_2 AR_AGC2_OFFSET(BB_rssi_b2) 1361 #define AR_PHY_SPUR_CCK_REP_2 AR_AGC2_OFFSET(BB_spur_est_cck_report_b2) 1362 1363 /* 1364 * AGC 2 Field Definitions 1365 */ 1366 /* BB_cca_b2 */ 1367 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000 1368 #define AR_PHY_CH2_MINCCA_PWR_S 20 1369 1370 /* 1371 * SM 2 Register Map 1372 */ 1373 #define AR_SM2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_sm2_reg_map) 1374 #define AR_SM2_OFFSET(_x) (AR_SM2_BASE + offsetof(struct sm2_reg_map, _x)) 1375 1376 #define AR_PHY_SWITCH_CHAIN_2 AR_SM2_OFFSET(BB_switch_table_chn_b2) 1377 #define AR_PHY_FCAL_2_2 AR_SM2_OFFSET(BB_fcal_2_b2) 1378 #define AR_PHY_DFT_TONE_CTL_2 AR_SM2_OFFSET(BB_dft_tone_ctrl_b2) 1379 #define AR_PHY_BBGAINMAP_0_1_2 AR_SM2_OFFSET(BB_cl_bbgain_map_0_1_b2) 1380 #define AR_PHY_BBGAINMAP_2_3_2 AR_SM2_OFFSET(BB_cl_bbgain_map_2_3_b2) 1381 #define AR_PHY_CL_TAB_2 AR_SM2_OFFSET(BB_cl_tab_b2) 1382 #define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_OFFSET(BB_chan_info_gain_b2) 1383 #define AR_PHY_TPC_4_B2 AR_SM2_OFFSET(BB_tpc_4_b2) 1384 #define AR_PHY_TPC_5_B2 AR_SM2_OFFSET(BB_tpc_5_b2) 1385 #define AR_PHY_TPC_6_B2 AR_SM2_OFFSET(BB_tpc_6_b2) 1386 #define AR_PHY_TPC_11_B2 AR_SM2_OFFSET(BB_tpc_11_b2) 1387 #define AR_SCORPION_PHY_TPC_19_B2 AR_SM2_OFFSET(overlay_c440.Scorpion.BB_tpc_19_b2) 1388 #define AR_PHY_PDADC_TAB_2 AR_SM2_OFFSET(overlay_c440.BB_pdadc_tab_b2) 1389 #define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_OFFSET(BB_txiqcal_status_b2) 1390 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_01_b2) 1391 #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_23_b2) 1392 #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_45_b2) 1393 #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_67_b2) 1394 1395 /* 1396 * bb_chn_ext_reg_map 1397 */ 1398 #define AR_CHN_EXT_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_chn_ext_reg_map) 1399 #define AR_CHN_EXT_OFFSET_POSEIDON(_x) (AR_CHN_EXT_BASE_POSEIDON + offsetof(struct chn_ext_reg_map, _x)) 1400 1401 #define AR_PHY_PAPRD_VALID_OBDB_POSEIDON AR_CHN_EXT_OFFSET_POSEIDON(BB_paprd_valid_obdb_b0) 1402 #define AR_PHY_PAPRD_VALID_OBDB_0 0x3f 1403 #define AR_PHY_PAPRD_VALID_OBDB_0_S 0 1404 #define AR_PHY_PAPRD_VALID_OBDB_1 0x3f 1405 #define AR_PHY_PAPRD_VALID_OBDB_1_S 6 1406 #define AR_PHY_PAPRD_VALID_OBDB_2 0x3f 1407 #define AR_PHY_PAPRD_VALID_OBDB_2_S 12 1408 #define AR_PHY_PAPRD_VALID_OBDB_3 0x3f 1409 #define AR_PHY_PAPRD_VALID_OBDB_3_S 18 1410 #define AR_PHY_PAPRD_VALID_OBDB_4 0x3f 1411 #define AR_PHY_PAPRD_VALID_OBDB_4_S 24 1412 1413 /* BB_txiqcal_status_b1 */ 1414 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 1415 1416 /* 1417 * AGC 3 Register Map 1418 */ 1419 #define AR_AGC3_BASE offsetof(struct bb_reg_map, bb_agc3_reg_map) 1420 #define AR_AGC3_OFFSET(_x) (AR_AGC3_BASE + offsetof(struct agc3_reg_map, _x)) 1421 1422 #define AR_PHY_RSSI_3 AR_AGC3_OFFSET(BB_rssi_b3) 1423 1424 /* 1425 * Misc helper defines 1426 */ 1427 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE) 1428 1429 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1430 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1431 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1432 1433 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1434 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1435 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1436 1437 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1438 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1439 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1440 #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1441 1442 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ 1443 #define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 1444 #define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 1445 #define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */ 1446 1447 /* BB Panic Watchdog control register 1 */ 1448 #define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001 1449 #define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002 1450 #define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000 1451 #define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC 1452 /* BB Panic Watchdog control register 2 */ 1453 #define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002 1454 #define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004 1455 #define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9 1456 /* BB Panic Watchdog status register */ 1457 #define AR_PHY_BB_WD_STATUS 0x00000007 /* snapshot of r_panic_watchdog_sm */ 1458 #define AR_PHY_BB_WD_STATUS_S 0 1459 #define AR_PHY_BB_WD_DET_HANG 0x00000008 /* panic_watchdog_det_hang */ 1460 #define AR_PHY_BB_WD_DET_HANG_S 3 1461 #define AR_PHY_BB_WD_RADAR_SM 0x000000F0 /* snapshot of radar state machine r_rdr_sm */ 1462 #define AR_PHY_BB_WD_RADAR_SM_S 4 1463 #define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00 /* snapshot of rx state machine (OFDM) r_rx_sm */ 1464 #define AR_PHY_BB_WD_RX_OFDM_SM_S 8 1465 #define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000 /* snapshot of rx state machine (CCK) r_rx_sm_cck */ 1466 #define AR_PHY_BB_WD_RX_CCK_SM_S 12 1467 #define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000 /* snapshot of tx state machine (OFDM) r_tx_sm */ 1468 #define AR_PHY_BB_WD_TX_OFDM_SM_S 16 1469 #define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000 /* snapshot of tx state machine (CCK) r_tx_sm_cck */ 1470 #define AR_PHY_BB_WD_TX_CCK_SM_S 20 1471 #define AR_PHY_BB_WD_AGC_SM 0x0F000000 /* snapshot of AGC state machine r_agc_sm */ 1472 #define AR_PHY_BB_WD_AGC_SM_S 24 1473 #define AR_PHY_BB_WD_SRCH_SM 0xF0000000 /* snapshot of agc search state machine r_srch_sm */ 1474 #define AR_PHY_BB_WD_SRCH_SM_S 28 1475 1476 #define AR_PHY_BB_WD_STATUS_CLR 0x00000008 /* write 0 to reset watchdog */ 1477 1478 1479 /***** PAPRD *****/ 1480 #define AR_PHY_PAPRD_AM2AM AR_CHAN_OFFSET(BB_paprd_am2am_mask) 1481 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff 1482 #define AR_PHY_PAPRD_AM2AM_MASK_S 0 1483 1484 #define AR_PHY_PAPRD_AM2PM AR_CHAN_OFFSET(BB_paprd_am2pm_mask) 1485 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff 1486 #define AR_PHY_PAPRD_AM2PM_MASK_S 0 1487 1488 #define AR_PHY_PAPRD_HT40 AR_CHAN_OFFSET(BB_paprd_ht40_mask) 1489 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff 1490 #define AR_PHY_PAPRD_HT40_MASK_S 0 1491 1492 #define AR_PHY_PAPRD_CTRL0_B0 AR_CHAN_OFFSET(BB_paprd_ctrl0_b0) 1493 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0 1 1494 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_S 0 1495 #define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK 0x00000001 1496 #define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK_S 0x00000001 1497 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0 0x1F 1498 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0_S 27 1499 1500 #define AR_PHY_PAPRD_CTRL1_B0 AR_CHAN_OFFSET(BB_paprd_ctrl1_b0) 1501 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0 0x3f 1502 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0_S 3 1503 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0 1 1504 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0_S 2 1505 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0 1 1506 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0_S 1 1507 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA 1 1508 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA_S 0 1509 #define AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK 0xFF 1510 #define AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK_S 9 1511 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0 0x7FF 1512 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0_S 17 1513 1514 #define AR_PHY_PAPRD_CTRL0_B1 AR_CHAN1_OFFSET(BB_paprd_ctrl0_b1) 1515 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1 0x1F 1516 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1_S 27 1517 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1 1 1518 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1_S 1 1519 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1 1 1520 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_S 0 1521 1522 #define AR_PHY_PAPRD_CTRL1_B1 AR_CHAN1_OFFSET(BB_paprd_ctrl1_b1) 1523 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1 0x3f 1524 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1_S 3 1525 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1 1 1526 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1_S 2 1527 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1 1 1528 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1_S 1 1529 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA 1 1530 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA_S 0 1531 #define AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK 0xFF 1532 #define AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK_S 9 1533 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1 0x7FF 1534 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1_S 17 1535 1536 #define AR_PHY_PAPRD_CTRL0_B2 AR_CHAN2_OFFSET(BB_paprd_ctrl0_b2) 1537 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2 0x1F 1538 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2_S 27 1539 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2 1 1540 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2_S 1 1541 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2 1 1542 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_S 0 1543 1544 1545 #define AR_PHY_PAPRD_CTRL1_B2 AR_CHAN2_OFFSET(BB_paprd_ctrl1_b2) 1546 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2 0x3f 1547 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2_S 3 1548 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2 1 1549 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2_S 2 1550 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2 1 1551 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2_S 1 1552 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA 1 1553 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA_S 0 1554 #define AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK 0xFF 1555 #define AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK_S 9 1556 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2 0x7FF 1557 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2_S 17 1558 1559 #define AR_PHY_PAPRD_TRAINER_CNTL1 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl1) 1560 #define AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl1) 1561 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x3f 1562 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 1563 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 1 1564 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11 1565 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 1 1566 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10 1567 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 1 1568 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9 1569 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 1 1570 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8 1571 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x3F 1572 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1 1573 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 1 1574 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 1575 1576 #define AR_PHY_PAPRD_TRAINER_CNTL2 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl2) 1577 #define AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl2) 1578 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF 1579 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 1580 1581 #define AR_PHY_PAPRD_TRAINER_CNTL3 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl3) 1582 #define AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl3) 1583 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 1 1584 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 1585 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0xF 1586 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24 1587 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF 1588 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20 1589 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF 1590 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20 1591 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x7 1592 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17 1593 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x1F 1594 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12 1595 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x3F 1596 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6 1597 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x3F 1598 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 1599 1600 #define AR_PHY_PAPRD_TRAINER_CNTL4 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl4) 1601 #define AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl4) 1602 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x3FF 1603 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 1604 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0xF 1605 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12 1606 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0xFFF 1607 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0 1608 1609 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_0_b0) 1610 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0 0x3FFFF 1611 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0_S 0 1612 1613 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_1_b0) 1614 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0 0x3FFFF 1615 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0_S 0 1616 1617 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_2_b0) 1618 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0 0x3FFFF 1619 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0_S 0 1620 1621 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_3_b0) 1622 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0 0x3FFFF 1623 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0_S 0 1624 1625 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_4_b0) 1626 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0 0x3FFFF 1627 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0_S 0 1628 1629 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_5_b0) 1630 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0 0x3FFFF 1631 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0_S 0 1632 1633 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_6_b0) 1634 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0 0x3FFFF 1635 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0_S 0 1636 1637 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_7_b0) 1638 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0 0x3FFFF 1639 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0_S 0 1640 1641 #define AR_PHY_PAPRD_TRAINER_STAT1 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat1) 1642 #define AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat1) 1643 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0xff 1644 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9 1645 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x1f 1646 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4 1647 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x1 1648 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3 1649 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x1 1650 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2 1651 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x1 1652 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1 1653 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 1 1654 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0 1655 1656 #define AR_PHY_PAPRD_TRAINER_STAT2 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat2) 1657 #define AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat2) 1658 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x3 1659 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21 1660 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x1F 1661 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16 1662 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0xffff 1663 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0 1664 1665 #define AR_PHY_PAPRD_TRAINER_STAT3 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat3) 1666 #define AR_PHY_PAPRD_TRAINER_STAT3_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat3) 1667 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0xfffff 1668 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0 1669 1670 #define AR_PHY_TPC_12 AR_SM_OFFSET(BB_tpc_12) 1671 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x1F 1672 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25 1673 1674 #define AR_PHY_TPC_19_ALT_ALPHA_VOLT 0x1f 1675 #define AR_PHY_TPC_19_ALT_ALPHA_VOLT_S 16 1676 1677 #define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE 0xff 1678 #define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE_S 0 1679 1680 #define AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE 0xff 1681 #define AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE_S 8 1682 1683 #define AR_PHY_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) 1684 #define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE 0xFF 1685 #define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE_S 0 1686 #define AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE 0xFF 1687 #define AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE_S 8 1688 1689 1690 #define AR_PHY_TPC_11_B0 AR_SM_OFFSET(BB_tpc_11_b0) 1691 #define AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0 0xFF 1692 #define AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0_S 16 1693 1694 #define AR_PHY_TPC_11_B1 AR_SM1_OFFSET(BB_tpc_11_b1) 1695 #define AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1 0xFF 1696 #define AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1_S 16 1697 1698 #define AR_PHY_TPC_11_B2 AR_SM2_OFFSET(BB_tpc_11_b2) 1699 #define AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2 0xFF 1700 #define AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2_S 16 1701 1702 1703 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x7 1704 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1 1705 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x3 1706 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4 1707 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0xf 1708 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6 1709 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0xf 1710 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10 1711 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0xf 1712 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14 1713 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0xf 1714 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18 1715 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x3 1716 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22 1717 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 1 1718 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24 1719 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 1 1720 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0 1721 1722 #define AR_PHY_TPC_1 AR_SM_OFFSET(BB_tpc_1) 1723 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x1f 1724 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1 1725 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 1 1726 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0 1727 1728 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 1 1729 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 1730 1731 #define AR_PHY_PAPRD_MEM_TAB_B0 AR_CHAN_OFFSET(BB_paprd_mem_tab_b0) 1732 #define AR_PHY_PAPRD_MEM_TAB_B1 AR_CHAN1_OFFSET(BB_paprd_mem_tab_b1) 1733 #define AR_PHY_PAPRD_MEM_TAB_B2 AR_CHAN2_OFFSET(BB_paprd_mem_tab_b2) 1734 1735 #define AR_PHY_PA_GAIN123_B0 AR_CHAN_OFFSET(BB_pa_gain123_b0) 1736 #define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0 0x3FF 1737 #define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0_S 0 1738 1739 #define AR_PHY_PA_GAIN123_B1 AR_CHAN1_OFFSET(BB_pa_gain123_b1) 1740 #define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1 0x3FF 1741 #define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1_S 0 1742 1743 #define AR_PHY_PA_GAIN123_B2 AR_CHAN2_OFFSET(BB_pa_gain123_b2) 1744 #define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2 0x3FF 1745 #define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2_S 0 1746 1747 //Legacy 54M 1748 #define AR_PHY_POWERTX_RATE2 AR_SM_OFFSET(BB_powertx_rate2) 1749 #define AR_PHY_POWERTX_RATE2_POWERTX54M_7 0x3F 1750 #define AR_PHY_POWERTX_RATE2_POWERTX54M_7_S 24 1751 1752 #define AR_PHY_POWERTX_RATE5 AR_SM_OFFSET(BB_powertx_rate5) 1753 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F 1754 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0 1755 //HT20 MCS5 1756 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_3 0x3F 1757 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_3_S 24 1758 1759 //HT20 MCS7 1760 #define AR_PHY_POWERTX_RATE6 AR_SM_OFFSET(BB_powertx_rate6) 1761 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F 1762 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8 1763 //HT20 MCS6 1764 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_4 0x3F 1765 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_4_S 0 1766 1767 #define AR_PHY_POWERTX_RATE7 AR_SM_OFFSET(BB_powertx_rate7) 1768 //HT40 MCS5 1769 #define AR_PHY_POWERTX_RATE7_POWERTXHT40_3 0x3F 1770 #define AR_PHY_POWERTX_RATE7_POWERTXHT40_3_S 24 1771 1772 //HT40 MCS7 1773 #define AR_PHY_POWERTX_RATE8 AR_SM_OFFSET(BB_powertx_rate8) 1774 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F 1775 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8 1776 //HT40 MCS6 1777 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_4 0x3F 1778 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_4_S 0 1779 1780 //HT20 MCS15 1781 #define AR_PHY_POWERTX_RATE10 AR_SM_OFFSET(BB_powertx_rate10) 1782 #define AR_PHY_POWERTX_RATE10_POWERTXHT20_9 0x3F 1783 #define AR_PHY_POWERTX_RATE10_POWERTXHT20_9_S 8 1784 1785 //HT20 MCS23 1786 #define AR_PHY_POWERTX_RATE11 AR_SM_OFFSET(BB_powertx_rate11) 1787 #define AR_PHY_POWERTX_RATE11_POWERTXHT20_13 0x3F 1788 #define AR_PHY_POWERTX_RATE11_POWERTXHT20_13_S 8 1789 1790 #define AR_PHY_CL_TAB_0_CL_GAIN_MOD 0x1F 1791 #define AR_PHY_CL_TAB_0_CL_GAIN_MOD_S 0 1792 1793 #define AR_PHY_CL_TAB_1_CL_GAIN_MOD 0x1F 1794 #define AR_PHY_CL_TAB_1_CL_GAIN_MOD_S 0 1795 1796 #define AR_PHY_CL_TAB_2_CL_GAIN_MOD 0x1F 1797 #define AR_PHY_CL_TAB_2_CL_GAIN_MOD_S 0 1798 1799 /* 1800 * Hornet/Poseidon Analog Registers 1801 */ 1802 #define AR_HORNET_CH0_TOP AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP) 1803 #define AR_HORNET_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP2) 1804 #define AR_HORNET_CH0_TOP2_XPABIASLVL 0xf000 1805 #define AR_HORNET_CH0_TOP2_XPABIASLVL_S 12 1806 1807 #define AR_SCORPION_CH0_TOP AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP) 1808 #define AR_SCORPION_CH0_TOP_XPABIASLVL 0x3c0 1809 #define AR_SCORPION_CH0_TOP_XPABIASLVL_S 6 1810 1811 #define AR_SCORPION_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_XTAL) 1812 1813 #define AR_HORNET_CH0_THERM AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_THERM) 1814 1815 #define AR_HORNET_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_XTAL) 1816 #define AR_HORNET_CHO_XTAL_CAPINDAC 0x7F000000 1817 #define AR_HORNET_CHO_XTAL_CAPINDAC_S 24 1818 #define AR_HORNET_CHO_XTAL_CAPOUTDAC 0x00FE0000 1819 #define AR_HORNET_CHO_XTAL_CAPOUTDAC_S 17 1820 1821 #define AR_HORNET_CH0_DDR_DPLL2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_DDR_DPLL2) 1822 #define AR_HORNET_CH0_DDR_DPLL3 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_DDR_DPLL3) 1823 #define AR_PHY_CCA_NOM_VAL_HORNET_2GHZ -118 1824 1825 #define AR_PHY_BB_DPLL1 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL1) 1826 #define AR_PHY_BB_DPLL1_REFDIV 0xF8000000 1827 #define AR_PHY_BB_DPLL1_REFDIV_S 27 1828 #define AR_PHY_BB_DPLL1_NINI 0x07FC0000 1829 #define AR_PHY_BB_DPLL1_NINI_S 18 1830 #define AR_PHY_BB_DPLL1_NFRAC 0x0003FFFF 1831 #define AR_PHY_BB_DPLL1_NFRAC_S 0 1832 1833 #define AR_PHY_BB_DPLL2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL2) 1834 #define AR_PHY_BB_DPLL2_RANGE 0x80000000 1835 #define AR_PHY_BB_DPLL2_RANGE_S 31 1836 #define AR_PHY_BB_DPLL2_LOCAL_PLL 0x40000000 1837 #define AR_PHY_BB_DPLL2_LOCAL_PLL_S 30 1838 #define AR_PHY_BB_DPLL2_KI 0x3C000000 1839 #define AR_PHY_BB_DPLL2_KI_S 26 1840 #define AR_PHY_BB_DPLL2_KD 0x03F80000 1841 #define AR_PHY_BB_DPLL2_KD_S 19 1842 #define AR_PHY_BB_DPLL2_EN_NEGTRIG 0x00040000 1843 #define AR_PHY_BB_DPLL2_EN_NEGTRIG_S 18 1844 #define AR_PHY_BB_DPLL2_SEL_1SDM 0x00020000 1845 #define AR_PHY_BB_DPLL2_SEL_1SDM_S 17 1846 #define AR_PHY_BB_DPLL2_PLL_PWD 0x00010000 1847 #define AR_PHY_BB_DPLL2_PLL_PWD_S 16 1848 #define AR_PHY_BB_DPLL2_OUTDIV 0x0000E000 1849 #define AR_PHY_BB_DPLL2_OUTDIV_S 13 1850 #define AR_PHY_BB_DPLL2_DELTA 0x00001F80 1851 #define AR_PHY_BB_DPLL2_DELTA_S 7 1852 #define AR_PHY_BB_DPLL2_SPARE 0x0000007F 1853 #define AR_PHY_BB_DPLL2_SPARE_S 0 1854 1855 #define AR_PHY_BB_DPLL3 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL3) 1856 #define AR_PHY_BB_DPLL3_MEAS_AT_TXON 0x80000000 1857 #define AR_PHY_BB_DPLL3_MEAS_AT_TXON_S 31 1858 #define AR_PHY_BB_DPLL3_DO_MEAS 0x40000000 1859 #define AR_PHY_BB_DPLL3_DO_MEAS_S 30 1860 #define AR_PHY_BB_DPLL3_PHASE_SHIFT 0x3F800000 1861 #define AR_PHY_BB_DPLL3_PHASE_SHIFT_S 23 1862 #define AR_PHY_BB_DPLL3_SQSUM_DVC 0x007FFFF8 1863 #define AR_PHY_BB_DPLL3_SQSUM_DVC_S 3 1864 #define AR_PHY_BB_DPLL3_SPARE 0x00000007 1865 #define AR_PHY_BB_DPLL3_SPARE_S 0x0 1866 1867 #define AR_PHY_BB_DPLL4 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL4) 1868 #define AR_PHY_BB_DPLL4_MEAN_DVC 0xFFE00000 1869 #define AR_PHY_BB_DPLL4_MEAN_DVC_S 21 1870 #define AR_PHY_BB_DPLL4_VC_MEAS0 0x001FFFF0 1871 #define AR_PHY_BB_DPLL4_VC_MEAS0_S 4 1872 #define AR_PHY_BB_DPLL4_MEAS_DONE 0x00000008 1873 #define AR_PHY_BB_DPLL4_MEAS_DONE_S 3 1874 #define AR_PHY_BB_DPLL4_SPARE 0x00000007 1875 #define AR_PHY_BB_DPLL4_SPARE_S 0 1876 1877 /* 1878 * Wasp Analog Registers 1879 */ 1880 #define AR_PHY_PLL_CONTROL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_pll_cntl) 1881 #define AR_PHY_PLL_MODE AR_PHY_65NM(overlay_0x16180.Osprey.ch0_pll_mode) 1882 #define AR_PHY_PLL_BB_DPLL3 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_bb_dpll3) 1883 #define AR_PHY_PLL_BB_DPLL4 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_bb_dpll4) 1884 1885 /* 1886 * PMU Register Map 1887 */ 1888 #define AR_PHY_PMU(_field) offsetof(struct pmu_reg, _field) 1889 #define AR_PHY_PMU1 AR_PHY_PMU(ch0_PMU1) 1890 #define AR_PHY_PMU2 AR_PHY_PMU(ch0_PMU2) 1891 #define AR_PHY_JUPITER_PMU(_field) offsetof(struct radio65_reg, _field) 1892 #define AR_PHY_PMU1_JUPITER AR_PHY_JUPITER_PMU(overlay_0x16180.Jupiter.ch0_PMU1) 1893 #define AR_PHY_PMU2_JUPITER AR_PHY_JUPITER_PMU(overlay_0x16180.Jupiter.ch0_PMU2) 1894 1895 /* 1896 * GLB Register Map 1897 */ 1898 #define AR_PHY_GLB(_field) offsetof(struct glb_reg, _field) 1899 #define AR_PHY_GLB_CONTROL_JUPITER AR_PHY_GLB(overlap_0x20044.Jupiter.GLB_CONTROL) 1900 1901 /* 1902 * PMU Field Definitions 1903 */ 1904 /* ch0_PMU1 */ 1905 #define AR_PHY_PMU1_PWD 0x00000001 /* power down switch regulator */ 1906 #define AR_PHY_PMU1_PWD_S 0 1907 1908 /* ch0_PMU2 */ 1909 #define AR_PHY_PMU2_PGM 0x00200000 1910 #define AR_PHY_PMU2_PGM_S 21 1911 1912 /* ch0_PHY_CTRL2 */ 1913 #define AR_PHY_CTRL2_TX_MAN_CAL 0x03C00000 1914 #define AR_PHY_CTRL2_TX_MAN_CAL_S 22 1915 #define AR_PHY_CTRL2_TX_CAL_SEL 0x00200000 1916 #define AR_PHY_CTRL2_TX_CAL_SEL_S 21 1917 #define AR_PHY_CTRL2_TX_CAL_EN 0x00100000 1918 #define AR_PHY_CTRL2_TX_CAL_EN_S 20 1919 1920 #define PCIE_CO_ERR_CTR_CTRL 0x40e8 1921 #define PCIE_CO_ERR_CTR_CTR0 0x40e0 1922 #define PCIE_CO_ERR_CTR_CTR1 0x40e4 1923 1924 1925 #define RCVD_ERR_CTR_RUN 0x0001 1926 #define RCVD_ERR_CTR_AUTO_STOP 0x0002 1927 #define BAD_TLP_ERR_CTR_RUN 0x0004 1928 #define BAD_TLP_ERR_CTR_AUTO_STOP 0x0008 1929 #define BAD_DLLP_ERR_CTR_RUN 0x0010 1930 #define BAD_DLLP_ERR_CTR_AUTO_STOP 0x0020 1931 #define RPLY_TO_ERR_CTR_RUN 0x0040 1932 #define RPLY_TO_ERR_CTR_AUTO_STOP 0x0080 1933 #define RPLY_NUM_RO_ERR_CTR_RUN 0x0100 1934 #define RPLY_NUM_RO_ERR_CTR_AUTO_STOP 0x0200 1935 1936 #define RCVD_ERR_MASK 0x000000ff 1937 #define RCVD_ERR_MASK_S 0 1938 #define BAD_TLP_ERR_MASK 0x0000ff00 1939 #define BAD_TLP_ERR_MASK_S 8 1940 #define BAD_DLLP_ERR_MASK 0x00ff0000 1941 #define BAD_DLLP_ERR_MASK_S 16 1942 1943 #define RPLY_TO_ERR_MASK 0x000000ff 1944 #define RPLY_TO_ERR_MASK_S 0 1945 #define RPLY_NUM_RO_ERR_MASK 0x0000ff00 1946 #define RPLY_NUM_RO_ERR_MASK_S 8 1947 1948 #define AR_MERLIN_RADIO_SYNTH4 offsetof(struct merlin2_0_radio_reg_map, SYNTH4) 1949 #define AR_MERLIN_RADIO_SYNTH6 offsetof(struct merlin2_0_radio_reg_map, SYNTH6) 1950 #define AR_MERLIN_RADIO_SYNTH7 offsetof(struct merlin2_0_radio_reg_map, SYNTH7) 1951 #define AR_MERLIN_RADIO_TOP0 offsetof(struct merlin2_0_radio_reg_map, TOP0) 1952 #define AR_MERLIN_RADIO_TOP1 offsetof(struct merlin2_0_radio_reg_map, TOP1) 1953 #define AR_MERLIN_RADIO_TOP2 offsetof(struct merlin2_0_radio_reg_map, TOP2) 1954 #define AR_MERLIN_RADIO_TOP3 offsetof(struct merlin2_0_radio_reg_map, TOP3) 1955 #endif /* _ATH_AR9300PHY_H_ */ 1956