1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _ATH_AR9300_EEP_H_ 18 #define _ATH_AR9300_EEP_H_ 19 20 #include "opt_ah.h" 21 #include "ah.h" 22 23 #if defined(WIN32) || defined(WIN64) 24 #pragma pack (push, ar9300, 1) 25 #endif 26 27 /* Ensure that AH_BYTE_ORDER is defined */ 28 #ifndef AH_BYTE_ORDER 29 #error AH_BYTE_ORDER needs to be defined! 30 #endif 31 32 /* FreeBSD extras - should be in ah_eeprom.h ? */ 33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 34 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 36 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 37 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 38 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 40 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 41 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 42 43 44 #define MSTATE 100 45 #define MOUTPUT 2048 46 #define MDEFAULT 15 47 #define MVALUE 100 48 49 enum CompressAlgorithm 50 { 51 _compress_none = 0, 52 _compress_lzma, 53 _compress_pairs, 54 _compress_block, 55 _compress4, 56 _compress5, 57 _compress6, 58 _compress7, 59 }; 60 61 62 enum 63 { 64 calibration_data_none = 0, 65 calibration_data_dram, 66 calibration_data_flash, 67 calibration_data_eeprom, 68 calibration_data_otp, 69 #ifdef ATH_CAL_NAND_FLASH 70 calibration_data_nand, 71 #endif 72 CalibrationDataDontLoad, 73 }; 74 #define HOST_CALDATA_SIZE (16*1024) 75 76 // 77 // DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS. 78 // Add additional definitions to the end. 79 // Yes, the first one is 2. Do not use 0 or 1. 80 // 81 enum Ar9300EepromTemplate 82 { 83 ar9300_eeprom_template_generic = 2, 84 ar9300_eeprom_template_hb112 = 3, 85 ar9300_eeprom_template_hb116 = 4, 86 ar9300_eeprom_template_xb112 = 5, 87 ar9300_eeprom_template_xb113 = 6, 88 ar9300_eeprom_template_xb114 = 7, 89 ar9300_eeprom_template_tb417 = 8, 90 ar9300_eeprom_template_ap111 = 9, 91 ar9300_eeprom_template_ap121 = 10, 92 ar9300_eeprom_template_hornet_generic = 11, 93 ar9300_eeprom_template_wasp_2 = 12, 94 ar9300_eeprom_template_wasp_k31 = 13, 95 ar9300_eeprom_template_osprey_k31 = 14, 96 ar9300_eeprom_template_aphrodite = 15 97 }; 98 99 #define ar9300_eeprom_template_default ar9300_eeprom_template_generic 100 #define Ar9300EepromFormatDefault 2 101 102 #define reference_current 0 103 #define compression_header_length 4 104 #define compression_checksum_length 2 105 106 #define OSPREY_EEP_VER 0xD000 107 #define OSPREY_EEP_VER_MINOR_MASK 0xFFF 108 #define OSPREY_EEP_MINOR_VER_1 0x1 109 #define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1 110 111 // 16-bit offset location start of calibration struct 112 #define OSPREY_EEP_START_LOC 256 113 #define OSPREY_NUM_5G_CAL_PIERS 8 114 #define OSPREY_NUM_2G_CAL_PIERS 3 115 #define OSPREY_NUM_5G_20_TARGET_POWERS 8 116 #define OSPREY_NUM_5G_40_TARGET_POWERS 8 117 #define OSPREY_NUM_2G_CCK_TARGET_POWERS 2 118 #define OSPREY_NUM_2G_20_TARGET_POWERS 3 119 #define OSPREY_NUM_2G_40_TARGET_POWERS 3 120 //#define OSPREY_NUM_CTLS 21 121 #define OSPREY_NUM_CTLS_5G 9 122 #define OSPREY_NUM_CTLS_2G 12 123 #define OSPREY_CTL_MODE_M 0xF 124 #define OSPREY_NUM_BAND_EDGES_5G 8 125 #define OSPREY_NUM_BAND_EDGES_2G 4 126 #define OSPREY_NUM_PD_GAINS 4 127 #define OSPREY_PD_GAINS_IN_MASK 4 128 #define OSPREY_PD_GAIN_ICEPTS 5 129 #define OSPREY_EEPROM_MODAL_SPURS 5 130 #define OSPREY_MAX_RATE_POWER 63 131 #define OSPREY_NUM_PDADC_VALUES 128 132 #define OSPREY_NUM_RATES 16 133 #define OSPREY_BCHAN_UNUSED 0xFF 134 #define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64 135 #define OSPREY_OPFLAGS_11A 0x01 136 #define OSPREY_OPFLAGS_11G 0x02 137 #define OSPREY_OPFLAGS_5G_HT40 0x04 138 #define OSPREY_OPFLAGS_2G_HT40 0x08 139 #define OSPREY_OPFLAGS_5G_HT20 0x10 140 #define OSPREY_OPFLAGS_2G_HT20 0x20 141 #define OSPREY_EEPMISC_BIG_ENDIAN 0x01 142 #define OSPREY_EEPMISC_WOW 0x02 143 #define OSPREY_CUSTOMER_DATA_SIZE 20 144 145 #define FREQ2FBIN(x,y) \ 146 (u_int8_t)(((y) == HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5)) 147 #define FBIN2FREQ(x,y) \ 148 (((y) == HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x)) 149 #define OSPREY_MAX_CHAINS 3 150 #define OSPREY_ANT_16S 25 151 #define OSPREY_FUTURE_MODAL_SZ 6 152 153 #define OSPREY_NUM_ANT_CHAIN_FIELDS 7 154 #define OSPREY_NUM_ANT_COMMON_FIELDS 4 155 #define OSPREY_SIZE_ANT_CHAIN_FIELD 3 156 #define OSPREY_SIZE_ANT_COMMON_FIELD 4 157 #define OSPREY_ANT_CHAIN_MASK 0x7 158 #define OSPREY_ANT_COMMON_MASK 0xf 159 #define OSPREY_CHAIN_0_IDX 0 160 #define OSPREY_CHAIN_1_IDX 1 161 #define OSPREY_CHAIN_2_IDX 2 162 #define OSPREY_1_CHAINMASK 1 163 #define OSPREY_2LOHI_CHAINMASK 5 164 #define OSPREY_2LOMID_CHAINMASK 3 165 #define OSPREY_3_CHAINMASK 7 166 167 #define AR928X_NUM_ANT_CHAIN_FIELDS 6 168 #define AR928X_SIZE_ANT_CHAIN_FIELD 2 169 #define AR928X_ANT_CHAIN_MASK 0x3 170 171 /* Delta from which to start power to pdadc table */ 172 /* This offset is used in both open loop and closed loop power control 173 * schemes. In open loop power control, it is not really needed, but for 174 * the "sake of consistency" it was kept. 175 * For certain AP designs, this value is overwritten by the value in the flag 176 * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers. 177 */ 178 #define OSPREY_PWR_TABLE_OFFSET 0 179 180 //enable flags for voltage and temp compensation 181 #define ENABLE_TEMP_COMPENSATION 0x01 182 #define ENABLE_VOLT_COMPENSATION 0x02 183 184 #define FLASH_BASE_CALDATA_OFFSET 0x1000 185 #define AR9300_EEPROM_SIZE 16*1024 // byte addressable 186 #define FIXED_CCA_THRESHOLD 15 187 188 typedef struct eepFlags { 189 u_int8_t op_flags; 190 u_int8_t eepMisc; 191 } __packed EEP_FLAGS; 192 193 typedef enum targetPowerHTRates { 194 HT_TARGET_RATE_0_8_16, 195 HT_TARGET_RATE_1_3_9_11_17_19, 196 HT_TARGET_RATE_4, 197 HT_TARGET_RATE_5, 198 HT_TARGET_RATE_6, 199 HT_TARGET_RATE_7, 200 HT_TARGET_RATE_12, 201 HT_TARGET_RATE_13, 202 HT_TARGET_RATE_14, 203 HT_TARGET_RATE_15, 204 HT_TARGET_RATE_20, 205 HT_TARGET_RATE_21, 206 HT_TARGET_RATE_22, 207 HT_TARGET_RATE_23 208 }TARGET_POWER_HT_RATES; 209 210 const static int mapRate2Index[24]= 211 { 212 0,1,1,1,2, 213 3,4,5,0,1, 214 1,1,6,7,8, 215 9,0,1,1,1, 216 10,11,12,13 217 }; 218 219 typedef enum targetPowerLegacyRates { 220 LEGACY_TARGET_RATE_6_24, 221 LEGACY_TARGET_RATE_36, 222 LEGACY_TARGET_RATE_48, 223 LEGACY_TARGET_RATE_54 224 }TARGET_POWER_LEGACY_RATES; 225 226 typedef enum targetPowerCckRates { 227 LEGACY_TARGET_RATE_1L_5L, 228 LEGACY_TARGET_RATE_5S, 229 LEGACY_TARGET_RATE_11L, 230 LEGACY_TARGET_RATE_11S 231 }TARGET_POWER_CCK_RATES; 232 233 #define MAX_MODAL_RESERVED 11 234 #define MAX_MODAL_FUTURE 5 235 #define MAX_BASE_EXTENSION_FUTURE 2 236 #define MAX_TEMP_SLOPE 8 237 #define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1) 238 239 typedef struct osprey_BaseEepHeader { 240 u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 241 u_int8_t txrx_mask; //4 bits tx and 4 bits rx 242 EEP_FLAGS op_cap_flags; 243 u_int8_t rf_silent; 244 u_int8_t blue_tooth_options; 245 u_int8_t device_cap; 246 u_int8_t device_type; // takes lower byte in eeprom location 247 int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 248 u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don 249 u_int8_t feature_enable; //bit0 - enable tx temp comp 250 //bit1 - enable tx volt comp 251 //bit2 - enable fastClock - default to 1 252 //bit3 - enable doubling - default to 1 253 //bit4 - enable internal regulator - default to 1 254 //bit5 - enable paprd - default to 0 255 //bit6 - enable TuningCaps - default to 0 256 //bit7 - enable tx_frame_to_xpa_on - default to 0 257 u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength 258 // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2 259 // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates 260 // bit 4 - enable quick drop 261 // bit 5 - enable 8 temp slop 262 // bit 6; enable xLNA_bias_strength 263 // bit 7; enable rf_gain_cap 264 u_int8_t eeprom_write_enable_gpio; 265 u_int8_t wlan_disable_gpio; 266 u_int8_t wlan_led_gpio; 267 u_int8_t rx_band_select_gpio; 268 u_int8_t txrxgain; 269 u_int32_t swreg; // SW controlled internal regulator fields 270 } __packed OSPREY_BASE_EEP_HEADER; 271 272 typedef struct osprey_BaseExtension_1 { 273 u_int8_t ant_div_control; 274 u_int8_t future[MAX_BASE_EXTENSION_FUTURE]; 275 u_int8_t misc_enable; 276 int8_t tempslopextension[MAX_TEMP_SLOPE]; 277 int8_t quick_drop_low; 278 int8_t quick_drop_high; 279 } __packed OSPREY_BASE_EXTENSION_1; 280 281 typedef struct osprey_BaseExtension_2 { 282 int8_t temp_slope_low; 283 int8_t temp_slope_high; 284 u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 285 u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 286 u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 287 u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 288 } __packed OSPREY_BASE_EXTENSION_2; 289 290 typedef struct spurChanStruct { 291 u_int16_t spur_chan; 292 u_int8_t spurRangeLow; 293 u_int8_t spurRangeHigh; 294 } __packed SPUR_CHAN; 295 296 //Note the order of the fields in this structure has been optimized to put all fields likely to change together 297 typedef struct ospreyModalEepHeader { 298 u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 299 u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 300 u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 301 u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 302 u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 303 int8_t temp_slope; 304 int8_t voltSlope; 305 u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 306 int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain 307 u_int8_t reserved[MAX_MODAL_RESERVED]; 308 int8_t quick_drop; 309 u_int8_t xpa_bias_lvl; // 1 310 u_int8_t tx_frame_to_data_start; // 1 311 u_int8_t tx_frame_to_pa_on; // 1 312 u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 313 int8_t antenna_gain; // 1 314 u_int8_t switchSettling; // 1 315 int8_t adcDesiredSize; // 1 316 u_int8_t tx_end_to_xpa_off; // 1 317 u_int8_t txEndToRxOn; // 1 318 u_int8_t tx_frame_to_xpa_on; // 1 319 u_int8_t thresh62; // 1 320 u_int32_t paprd_rate_mask_ht20; 321 u_int32_t paprd_rate_mask_ht40; 322 u_int16_t switchcomspdt; 323 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 324 u_int8_t rf_gain_cap; 325 u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain) 326 u_int8_t futureModal[MAX_MODAL_FUTURE]; 327 // last 12 bytes stolen and moved to newly created base extension structure 328 } __packed OSPREY_MODAL_EEP_HEADER; // == 100 B 329 330 typedef struct ospCalDataPerFreqOpLoop { 331 int8_t ref_power; /* */ 332 u_int8_t volt_meas; /* pdadc voltage at power measurement */ 333 u_int8_t temp_meas; /* pcdac used for power measurement */ 334 int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */ 335 int8_t rx_noisefloor_power; /*range is same as noisefloor */ 336 u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */ 337 } __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP; 338 339 typedef struct CalTargetPowerLegacy { 340 u_int8_t t_pow2x[4]; 341 } __packed CAL_TARGET_POWER_LEG; 342 343 typedef struct ospCalTargetPowerHt { 344 u_int8_t t_pow2x[14]; 345 } __packed OSP_CAL_TARGET_POWER_HT; 346 347 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 348 typedef struct CalCtlEdgePwr { 349 u_int8_t flag :2, 350 t_power :6; 351 } __packed CAL_CTL_EDGE_PWR; 352 #elif AH_BYTE_ORDER == AH_LITTLE_ENDIAN 353 typedef struct CalCtlEdgePwr { 354 u_int8_t t_power :6, 355 flag :2; 356 } __packed CAL_CTL_EDGE_PWR; 357 #else 358 #error AH_BYTE_ORDER undefined! 359 #endif 360 361 typedef struct ospCalCtlData_5G { 362 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G]; 363 } __packed OSP_CAL_CTL_DATA_5G; 364 365 typedef struct ospCalCtlData_2G { 366 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G]; 367 } __packed OSP_CAL_CTL_DATA_2G; 368 369 typedef struct ospreyEeprom { 370 u_int8_t eeprom_version; 371 u_int8_t template_version; 372 u_int8_t mac_addr[6]; 373 u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE]; 374 375 OSPREY_BASE_EEP_HEADER base_eep_header; 376 377 OSPREY_MODAL_EEP_HEADER modal_header_2g; 378 OSPREY_BASE_EXTENSION_1 base_ext1; 379 u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]; 380 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]; 381 u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 382 u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 383 u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 384 u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 385 CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 386 CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 387 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 388 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 389 u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G]; 390 u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 391 OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 392 393 OSPREY_MODAL_EEP_HEADER modal_header_5g; 394 OSPREY_BASE_EXTENSION_2 base_ext2; 395 u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]; 396 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]; 397 u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 398 u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 399 u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 400 CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 401 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 402 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 403 u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G]; 404 u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 405 OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G]; 406 } __packed ar9300_eeprom_t; 407 408 409 /* 410 ** SWAP Functions 411 ** used to read EEPROM data, which is apparently stored in little 412 ** endian form. We have included both forms of the swap functions, 413 ** one for big endian and one for little endian. The indices of the 414 ** array elements are the differences 415 */ 416 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 417 418 #define AR9300_EEPROM_MAGIC 0x5aa5 419 #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\ 420 ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) ) 421 422 #define SWAP32(_x) ((u_int32_t)( \ 423 (((const u_int8_t *)(&_x))[0]) | \ 424 (((const u_int8_t *)(&_x))[1]<< 8) | \ 425 (((const u_int8_t *)(&_x))[2]<<16) | \ 426 (((const u_int8_t *)(&_x))[3]<<24))) 427 428 #else // AH_BYTE_ORDER 429 430 #define AR9300_EEPROM_MAGIC 0xa55a 431 #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\ 432 ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) ) 433 434 #define SWAP32(_x) ((u_int32_t)( \ 435 (((const u_int8_t *)(&_x))[3]) | \ 436 (((const u_int8_t *)(&_x))[2]<< 8) | \ 437 (((const u_int8_t *)(&_x))[1]<<16) | \ 438 (((const u_int8_t *)(&_x))[0]<<24))) 439 440 #endif // AH_BYTE_ORDER 441 442 // OTP registers for OSPREY 443 444 #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register 445 #define OTP_MEM_START_ADDRESS 0x14000 446 #define OTP_STATUS0_OTP_SM_BUSY 0x00015f18 447 #define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c 448 449 #define OTP_LDO_CONTROL_ENABLE 0x00015f24 450 #define OTP_LDO_STATUS_POWER_ON 0x00015f2c 451 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00 452 // OTP register for Jupiter 453 #define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020 454 #define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028 455 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34 456 457 // OTP register for Jupiter BT 458 #define BTOTP_MEM_START_ADDRESS 0x64000 459 #define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18 460 #define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c 461 #define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00 462 #define BTOTP_INTF2 0x00065f08 463 #define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34 464 #define BT_RESET_CTL 0x44000 465 #define BT_CLOCK_CONTROL 0x44028 466 467 468 // OTP register for WASP 469 #define OTP_MEM_START_ADDRESS_WASP 0x00030000 470 #define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018) 471 #define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C) 472 #define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024) 473 #define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C) 474 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000) 475 // Below control the access timing of OTP read/write 476 #define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008) 477 #define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C) 478 #define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030) 479 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034) 480 #define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038) 481 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C) 482 483 #define AR9300_EEPROM_MAGIC_OFFSET 0x0 484 /* reg_off = 4 * (eep_off) */ 485 #define AR9300_EEPROM_S 2 486 #define AR9300_EEPROM_OFFSET 0x2000 487 #ifdef AR9100 488 #define AR9300_EEPROM_START_ADDR 0x1fff1000 489 #else 490 #define AR9300_EEPROM_START_ADDR 0x503f1200 491 #endif 492 #define AR9300_FLASH_CAL_START_OFFSET 0x1000 493 #define AR9300_EEPROM_MAX 0xae0 494 #define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3) 495 496 #define ar9300_get_ntxchains(_txchainmask) \ 497 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 498 499 /* RF silent fields in \ */ 500 #define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */ 501 #define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */ 502 #define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ 503 #define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ 504 #define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */ 505 #define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */ 506 #define AR9300_EEP_VER 0xE 507 #define AR9300_BCHAN_UNUSED 0xFF 508 #define AR9300_MAX_RATE_POWER 63 509 510 typedef enum { 511 CALDATA_AUTO=0, 512 CALDATA_EEPROM, 513 CALDATA_FLASH, 514 CALDATA_OTP 515 } CALDATA_TYPE; 516 517 typedef enum { 518 EEP_NFTHRESH_5, 519 EEP_NFTHRESH_2, 520 EEP_MAC_MSW, 521 EEP_MAC_MID, 522 EEP_MAC_LSW, 523 EEP_REG_0, 524 EEP_REG_1, 525 EEP_OP_CAP, 526 EEP_OP_MODE, 527 EEP_RF_SILENT, 528 EEP_OB_5, 529 EEP_DB_5, 530 EEP_OB_2, 531 EEP_DB_2, 532 EEP_MINOR_REV, 533 EEP_TX_MASK, 534 EEP_RX_MASK, 535 EEP_FSTCLK_5G, 536 EEP_RXGAIN_TYPE, 537 EEP_OL_PWRCTRL, 538 EEP_TXGAIN_TYPE, 539 EEP_RC_CHAIN_MASK, 540 EEP_DAC_HPWR_5G, 541 EEP_FRAC_N_5G, 542 EEP_DEV_TYPE, 543 EEP_TEMPSENSE_SLOPE, 544 EEP_TEMPSENSE_SLOPE_PAL_ON, 545 EEP_PWR_TABLE_OFFSET, 546 EEP_DRIVE_STRENGTH, 547 EEP_INTERNAL_REGULATOR, 548 EEP_SWREG, 549 EEP_PAPRD_ENABLED, 550 EEP_ANTDIV_control, 551 EEP_CHAIN_MASK_REDUCE, 552 } EEPROM_PARAM; 553 554 #define AR9300_RATES_OFDM_OFFSET 0 555 #define AR9300_RATES_CCK_OFFSET 4 556 #define AR9300_RATES_HT20_OFFSET 8 557 #define AR9300_RATES_HT40_OFFSET 22 558 typedef enum ar9300_Rates { 559 ALL_TARGET_LEGACY_6_24, 560 ALL_TARGET_LEGACY_36, 561 ALL_TARGET_LEGACY_48, 562 ALL_TARGET_LEGACY_54, 563 ALL_TARGET_LEGACY_1L_5L, 564 ALL_TARGET_LEGACY_5S, 565 ALL_TARGET_LEGACY_11L, 566 ALL_TARGET_LEGACY_11S, 567 ALL_TARGET_HT20_0_8_16, 568 ALL_TARGET_HT20_1_3_9_11_17_19, 569 ALL_TARGET_HT20_4, 570 ALL_TARGET_HT20_5, 571 ALL_TARGET_HT20_6, 572 ALL_TARGET_HT20_7, 573 ALL_TARGET_HT20_12, 574 ALL_TARGET_HT20_13, 575 ALL_TARGET_HT20_14, 576 ALL_TARGET_HT20_15, 577 ALL_TARGET_HT20_20, 578 ALL_TARGET_HT20_21, 579 ALL_TARGET_HT20_22, 580 ALL_TARGET_HT20_23, 581 ALL_TARGET_HT40_0_8_16, 582 ALL_TARGET_HT40_1_3_9_11_17_19, 583 ALL_TARGET_HT40_4, 584 ALL_TARGET_HT40_5, 585 ALL_TARGET_HT40_6, 586 ALL_TARGET_HT40_7, 587 ALL_TARGET_HT40_12, 588 ALL_TARGET_HT40_13, 589 ALL_TARGET_HT40_14, 590 ALL_TARGET_HT40_15, 591 ALL_TARGET_HT40_20, 592 ALL_TARGET_HT40_21, 593 ALL_TARGET_HT40_22, 594 ALL_TARGET_HT40_23, 595 ar9300_rate_size 596 } AR9300_RATES; 597 598 599 /************************************************************************** 600 * fbin2freq 601 * 602 * Get channel value from binary representation held in eeprom 603 * RETURNS: the frequency in MHz 604 */ 605 static inline u_int16_t 606 fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz) 607 { 608 /* 609 * Reserved value 0xFF provides an empty definition both as 610 * an fbin and as a frequency - do not convert 611 */ 612 if (fbin == AR9300_BCHAN_UNUSED) 613 { 614 return fbin; 615 } 616 617 return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin)); 618 } 619 620 extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 621 extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr); 622 extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah); 623 extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/); 624 extern int ar9300_eeprom_base_address(struct ath_hal *ah); 625 extern int ar9300_eeprom_volatile(struct ath_hal *ah); 626 extern int ar9300_eeprom_low_limit(struct ath_hal *ah); 627 extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize); 628 extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 629 630 extern u_int16_t ar9300_eeprom_struct_size(void); 631 extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index); 632 extern ar9300_eeprom_t *ar9300EepromStructGet(void); 633 extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index); 634 extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver); 635 extern int ar9300_eeprom_struct_default_many(void); 636 extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain, 637 int pwrCorrection, int volt_meas, int temp_meas); 638 extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature); 639 640 extern void ar9300EepromDisplayCalData(int for2GHz); 641 extern void ar9300EepromDisplayAll(void); 642 extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, 643 u_int8_t *target_power_val_t2); 644 extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah, 645 ar9300_eeprom_t *p_eep_data, 646 const struct ieee80211_channel *chan, 647 u_int8_t *p_pwr_array, 648 u_int16_t cfg_ctl, 649 u_int16_t antenna_reduction, 650 u_int16_t twice_max_regulatory_power, 651 u_int16_t power_limit, 652 u_int8_t chainmask); 653 extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array); 654 655 extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 656 extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 657 extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 658 extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq); 659 extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah); 660 extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah); 661 extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel); 662 extern int32_t ar9300_thermometer_get(struct ath_hal *ah); 663 extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah); 664 extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 665 extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 666 667 extern int32_t ar9300MacAdressGet(u_int8_t *mac); 668 extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len); 669 extern int32_t ar9300ReconfigDriveStrengthGet(void); 670 extern int32_t ar9300EnableTempCompensationGet(void); 671 extern int32_t ar9300EnableVoltCompensationGet(void); 672 extern int32_t ar9300FastClockEnableGet(void); 673 extern int32_t ar9300EnableDoublingGet(void); 674 675 extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah); 676 extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah); 677 extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah); 678 extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah); 679 extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah); 680 extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah); 681 extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah); 682 extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 683 extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 684 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 685 extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 686 extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz); 687 extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 688 /* since valid noise floor values are negative, returns 1 on error */ 689 extern int32_t ar9300_noise_floor_cal_or_power_get( 690 struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal); 691 #define ar9300NoiseFloorGet(ah, frequency, ichain) \ 692 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/) 693 #define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \ 694 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/) 695 extern void ar9300_eeprom_template_preference(int32_t value); 696 extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value); 697 extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source); 698 extern int32_t ar9300_calibration_data_get(struct ath_hal *ah); 699 extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah); 700 extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source); 701 extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 702 extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 703 extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi); 704 extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 705 extern int32_t ar9300_eeprom_size(struct ath_hal *ah); 706 extern int32_t ar9300_otp_size(struct ath_hal *ah); 707 extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many); 708 709 710 711 #if defined(WIN32) || defined(WIN64) 712 #pragma pack (pop, ar9300) 713 #endif 714 715 #endif /* _ATH_AR9300_EEP_H_ */ 716