1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 /* Contains descriptor definitions for Osprey */ 19 20 21 #ifndef _ATH_AR9300_DESC_H_ 22 #define _ATH_AR9300_DESC_H_ 23 24 #ifdef _KERNEL 25 #include "ar9300_freebsd_inc.h" 26 #endif 27 28 /* Osprey Status Descriptor. */ 29 struct ar9300_txs { 30 u_int32_t ds_info; 31 u_int32_t status1; 32 u_int32_t status2; 33 u_int32_t status3; 34 u_int32_t status4; 35 u_int32_t status5; 36 u_int32_t status6; 37 u_int32_t status7; 38 u_int32_t status8; 39 }; 40 41 struct ar9300_rxs { 42 u_int32_t ds_info; 43 u_int32_t status1; 44 u_int32_t status2; 45 u_int32_t status3; 46 u_int32_t status4; 47 u_int32_t status5; 48 u_int32_t status6; 49 u_int32_t status7; 50 u_int32_t status8; 51 u_int32_t status9; 52 u_int32_t status10; 53 u_int32_t status11; 54 }; 55 56 /* Transmit Control Descriptor */ 57 struct ar9300_txc { 58 u_int32_t ds_info; /* descriptor information */ 59 u_int32_t ds_link; /* link pointer */ 60 u_int32_t ds_data0; /* data pointer to 1st buffer */ 61 u_int32_t ds_ctl3; /* DMA control 3 */ 62 u_int32_t ds_data1; /* data pointer to 2nd buffer */ 63 u_int32_t ds_ctl5; /* DMA control 5 */ 64 u_int32_t ds_data2; /* data pointer to 3rd buffer */ 65 u_int32_t ds_ctl7; /* DMA control 7 */ 66 u_int32_t ds_data3; /* data pointer to 4th buffer */ 67 u_int32_t ds_ctl9; /* DMA control 9 */ 68 u_int32_t ds_ctl10; /* DMA control 10 */ 69 u_int32_t ds_ctl11; /* DMA control 11 */ 70 u_int32_t ds_ctl12; /* DMA control 12 */ 71 u_int32_t ds_ctl13; /* DMA control 13 */ 72 u_int32_t ds_ctl14; /* DMA control 14 */ 73 u_int32_t ds_ctl15; /* DMA control 15 */ 74 u_int32_t ds_ctl16; /* DMA control 16 */ 75 u_int32_t ds_ctl17; /* DMA control 17 */ 76 u_int32_t ds_ctl18; /* DMA control 18 */ 77 u_int32_t ds_ctl19; /* DMA control 19 */ 78 u_int32_t ds_ctl20; /* DMA control 20 */ 79 u_int32_t ds_ctl21; /* DMA control 21 */ 80 u_int32_t ds_ctl22; /* DMA control 22 */ 81 u_int32_t ds_ctl23; /* DMA control 23 */ 82 u_int32_t ds_pad[8]; /* pad to cache line (128 bytes/32 dwords) */ 83 }; 84 85 86 #define AR9300RXS(_rxs) ((struct ar9300_rxs *)(_rxs)) 87 #define AR9300TXS(_txs) ((struct ar9300_txs *)(_txs)) 88 #define AR9300TXC(_ds) ((struct ar9300_txc *)(_ds)) 89 90 #define AR9300TXC_CONST(_ds) ((const struct ar9300_txc *)(_ds)) 91 92 93 /* ds_info */ 94 #define AR_desc_len 0x000000ff 95 #define AR_rx_priority 0x00000100 96 #define AR_tx_qcu_num 0x00000f00 97 #define AR_tx_qcu_num_S 8 98 #define AR_ctrl_stat 0x00004000 99 #define AR_ctrl_stat_S 14 100 #define AR_tx_rx_desc 0x00008000 101 #define AR_tx_rx_desc_S 15 102 #define AR_desc_id 0xffff0000 103 #define AR_desc_id_S 16 104 105 /*********** 106 * TX Desc * 107 ***********/ 108 109 /* ds_ctl3 */ 110 /* ds_ctl5 */ 111 /* ds_ctl7 */ 112 /* ds_ctl9 */ 113 #define AR_buf_len 0x0fff0000 114 #define AR_buf_len_S 16 115 116 /* ds_ctl10 */ 117 #define AR_tx_desc_id 0xffff0000 118 #define AR_tx_desc_id_S 16 119 #define AR_tx_ptr_chk_sum 0x0000ffff 120 121 /* ds_ctl11 */ 122 #define AR_frame_len 0x00000fff 123 #define AR_virt_more_frag 0x00001000 124 #define AR_tx_ctl_rsvd00 0x00002000 125 #define AR_low_rx_chain 0x00004000 126 #define AR_tx_clear_retry 0x00008000 127 #define AR_xmit_power0 0x003f0000 128 #define AR_xmit_power0_S 16 129 #define AR_rts_enable 0x00400000 130 #define AR_veol 0x00800000 131 #define AR_clr_dest_mask 0x01000000 132 #define AR_tx_bf0 0x02000000 133 #define AR_tx_bf1 0x04000000 134 #define AR_tx_bf2 0x08000000 135 #define AR_tx_bf3 0x10000000 136 #define AR_TxBfSteered 0x1e000000 /* for tx_bf*/ 137 #define AR_tx_intr_req 0x20000000 138 #define AR_dest_idx_valid 0x40000000 139 #define AR_cts_enable 0x80000000 140 141 /* ds_ctl12 */ 142 #define AR_tx_ctl_rsvd02 0x000001ff 143 #define AR_paprd_chain_mask 0x00000e00 144 #define AR_paprd_chain_mask_S 9 145 #define AR_tx_more 0x00001000 146 #define AR_dest_idx 0x000fe000 147 #define AR_dest_idx_S 13 148 #define AR_frame_type 0x00f00000 149 #define AR_frame_type_S 20 150 #define AR_no_ack 0x01000000 151 #define AR_insert_ts 0x02000000 152 #define AR_corrupt_fcs 0x04000000 153 #define AR_ext_only 0x08000000 154 #define AR_ext_and_ctl 0x10000000 155 #define AR_more_aggr 0x20000000 156 #define AR_is_aggr 0x40000000 157 #define AR_more_rifs 0x80000000 158 #define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */ 159 160 /* ds_ctl13 */ 161 #define AR_burst_dur 0x00007fff 162 #define AR_burst_dur_S 0 163 #define AR_dur_update_ena 0x00008000 164 #define AR_xmit_data_tries0 0x000f0000 165 #define AR_xmit_data_tries0_S 16 166 #define AR_xmit_data_tries1 0x00f00000 167 #define AR_xmit_data_tries1_S 20 168 #define AR_xmit_data_tries2 0x0f000000 169 #define AR_xmit_data_tries2_S 24 170 #define AR_xmit_data_tries3 0xf0000000 171 #define AR_xmit_data_tries3_S 28 172 173 /* ds_ctl14 */ 174 #define AR_xmit_rate0 0x000000ff 175 #define AR_xmit_rate0_S 0 176 #define AR_xmit_rate1 0x0000ff00 177 #define AR_xmit_rate1_S 8 178 #define AR_xmit_rate2 0x00ff0000 179 #define AR_xmit_rate2_S 16 180 #define AR_xmit_rate3 0xff000000 181 #define AR_xmit_rate3_S 24 182 183 /* ds_ctl15 */ 184 #define AR_packet_dur0 0x00007fff 185 #define AR_packet_dur0_S 0 186 #define AR_rts_cts_qual0 0x00008000 187 #define AR_packet_dur1 0x7fff0000 188 #define AR_packet_dur1_S 16 189 #define AR_rts_cts_qual1 0x80000000 190 191 /* ds_ctl16 */ 192 #define AR_packet_dur2 0x00007fff 193 #define AR_packet_dur2_S 0 194 #define AR_rts_cts_qual2 0x00008000 195 #define AR_packet_dur3 0x7fff0000 196 #define AR_packet_dur3_S 16 197 #define AR_rts_cts_qual3 0x80000000 198 199 /* ds_ctl17 */ 200 #define AR_aggr_len 0x0000ffff 201 #define AR_aggr_len_S 0 202 #define AR_tx_ctl_rsvd60 0x00030000 203 #define AR_pad_delim 0x03fc0000 204 #define AR_pad_delim_S 18 205 #define AR_encr_type 0x1c000000 206 #define AR_encr_type_S 26 207 #define AR_tx_dc_ap_sta_sel 0x40000000 208 #define AR_tx_ctl_rsvd61 0xc0000000 209 #define AR_calibrating 0x40000000 210 #define AR_ldpc 0x80000000 211 212 /* ds_ctl18 */ 213 #define AR_2040_0 0x00000001 214 #define AR_gi0 0x00000002 215 #define AR_chain_sel0 0x0000001c 216 #define AR_chain_sel0_S 2 217 #define AR_2040_1 0x00000020 218 #define AR_gi1 0x00000040 219 #define AR_chain_sel1 0x00000380 220 #define AR_chain_sel1_S 7 221 #define AR_2040_2 0x00000400 222 #define AR_gi2 0x00000800 223 #define AR_chain_sel2 0x00007000 224 #define AR_chain_sel2_S 12 225 #define AR_2040_3 0x00008000 226 #define AR_gi3 0x00010000 227 #define AR_chain_sel3 0x000e0000 228 #define AR_chain_sel3_S 17 229 #define AR_rts_cts_rate 0x0ff00000 230 #define AR_rts_cts_rate_S 20 231 #define AR_stbc0 0x10000000 232 #define AR_stbc1 0x20000000 233 #define AR_stbc2 0x40000000 234 #define AR_stbc3 0x80000000 235 236 /* ds_ctl19 */ 237 #define AR_tx_ant0 0x00ffffff 238 #define AR_tx_ant_sel0 0x80000000 239 #define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/ 240 #define AR_not_sounding 0x20000000 241 #define AR_ness 0xc0000000 242 #define AR_ness_S 30 243 244 /* ds_ctl20 */ 245 #define AR_tx_ant1 0x00ffffff 246 #define AR_xmit_power1 0x3f000000 247 #define AR_xmit_power1_S 24 248 #define AR_tx_ant_sel1 0x80000000 249 #define AR_ness1 0xc0000000 250 #define AR_ness1_S 30 251 252 /* ds_ctl21 */ 253 #define AR_tx_ant2 0x00ffffff 254 #define AR_xmit_power2 0x3f000000 255 #define AR_xmit_power2_S 24 256 #define AR_tx_ant_sel2 0x80000000 257 #define AR_ness2 0xc0000000 258 #define AR_ness2_S 30 259 260 /* ds_ctl22 */ 261 #define AR_tx_ant3 0x00ffffff 262 #define AR_xmit_power3 0x3f000000 263 #define AR_xmit_power3_S 24 264 #define AR_tx_ant_sel3 0x80000000 265 #define AR_ness3 0xc0000000 266 #define AR_ness3_S 30 267 268 /************* 269 * TX Status * 270 *************/ 271 272 /* ds_status1 */ 273 #define AR_tx_status_rsvd 0x0000ffff 274 275 /* ds_status2 */ 276 #define AR_tx_rssi_ant00 0x000000ff 277 #define AR_tx_rssi_ant00_S 0 278 #define AR_tx_rssi_ant01 0x0000ff00 279 #define AR_tx_rssi_ant01_S 8 280 #define AR_tx_rssi_ant02 0x00ff0000 281 #define AR_tx_rssi_ant02_S 16 282 #define AR_tx_status_rsvd00 0x3f000000 283 #define AR_tx_ba_status 0x40000000 284 #define AR_tx_status_rsvd01 0x80000000 285 286 /* ds_status3 */ 287 #define AR_frm_xmit_ok 0x00000001 288 #define AR_excessive_retries 0x00000002 289 #define AR_fifounderrun 0x00000004 290 #define AR_filtered 0x00000008 291 #define AR_rts_fail_cnt 0x000000f0 292 #define AR_rts_fail_cnt_S 4 293 #define AR_data_fail_cnt 0x00000f00 294 #define AR_data_fail_cnt_S 8 295 #define AR_virt_retry_cnt 0x0000f000 296 #define AR_virt_retry_cnt_S 12 297 #define AR_tx_delim_underrun 0x00010000 298 #define AR_tx_data_underrun 0x00020000 299 #define AR_desc_cfg_err 0x00040000 300 #define AR_tx_timer_expired 0x00080000 301 #define AR_tx_status_rsvd10 0xfff00000 302 303 /* ds_status7 */ 304 #define AR_tx_rssi_ant10 0x000000ff 305 #define AR_tx_rssi_ant10_S 0 306 #define AR_tx_rssi_ant11 0x0000ff00 307 #define AR_tx_rssi_ant11_S 8 308 #define AR_tx_rssi_ant12 0x00ff0000 309 #define AR_tx_rssi_ant12_S 16 310 #define AR_tx_rssi_combined 0xff000000 311 #define AR_tx_rssi_combined_S 24 312 313 /* ds_status8 */ 314 #define AR_tx_done 0x00000001 315 #define AR_seq_num 0x00001ffe 316 #define AR_seq_num_S 1 317 #define AR_tx_status_rsvd80 0x0001e000 318 #define AR_tx_op_exceeded 0x00020000 319 #define AR_tx_status_rsvd81 0x001c0000 320 #define AR_TXBFStatus 0x001c0000 321 #define AR_TXBFStatus_S 18 322 #define AR_tx_bf_bw_mismatch 0x00040000 323 #define AR_tx_bf_stream_miss 0x00080000 324 #define AR_final_tx_idx 0x00600000 325 #define AR_final_tx_idx_S 21 326 #define AR_tx_bf_dest_miss 0x00800000 327 #define AR_tx_bf_expired 0x01000000 328 #define AR_power_mgmt 0x02000000 329 #define AR_tx_status_rsvd83 0x0c000000 330 #define AR_tx_tid 0xf0000000 331 #define AR_tx_tid_S 28 332 #define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */ 333 334 335 /************* 336 * Rx Status * 337 *************/ 338 339 /* ds_status1 */ 340 #define AR_rx_rssi_ant00 0x000000ff 341 #define AR_rx_rssi_ant00_S 0 342 #define AR_rx_rssi_ant01 0x0000ff00 343 #define AR_rx_rssi_ant01_S 8 344 #define AR_rx_rssi_ant02 0x00ff0000 345 #define AR_rx_rssi_ant02_S 16 346 #define AR_rx_rate 0xff000000 347 #define AR_rx_rate_S 24 348 349 /* ds_status2 */ 350 #define AR_data_len 0x00000fff 351 #define AR_data_len_S 0 352 #define AR_rx_more 0x00001000 353 #define AR_num_delim 0x003fc000 354 #define AR_num_delim_S 14 355 #define AR_hw_upload_data 0x00400000 356 #define AR_hw_upload_data_S 22 357 #define AR_rx_status_rsvd10 0xff800000 358 359 360 /* ds_status4 */ 361 #define AR_gi 0x00000001 362 #define AR_2040 0x00000002 363 #define AR_parallel40 0x00000004 364 #define AR_parallel40_S 2 365 #define AR_rx_stbc 0x00000008 366 #define AR_rx_not_sounding 0x00000010 367 #define AR_rx_ness 0x00000060 368 #define AR_rx_ness_S 5 369 #define AR_hw_upload_data_valid 0x00000080 370 #define AR_hw_upload_data_valid_S 7 371 #define AR_rx_antenna 0xffffff00 372 #define AR_rx_antenna_S 8 373 374 /* ds_status5 */ 375 #define AR_rx_rssi_ant10 0x000000ff 376 #define AR_rx_rssi_ant10_S 0 377 #define AR_rx_rssi_ant11 0x0000ff00 378 #define AR_rx_rssi_ant11_S 8 379 #define AR_rx_rssi_ant12 0x00ff0000 380 #define AR_rx_rssi_ant12_S 16 381 #define AR_rx_rssi_combined 0xff000000 382 #define AR_rx_rssi_combined_S 24 383 384 /* ds_status6 */ 385 #define AR_rx_evm0 status6 386 387 /* ds_status7 */ 388 #define AR_rx_evm1 status7 389 390 /* ds_status8 */ 391 #define AR_rx_evm2 status8 392 393 /* ds_status9 */ 394 #define AR_rx_evm3 status9 395 396 /* ds_status11 */ 397 #define AR_rx_done 0x00000001 398 #define AR_rx_frame_ok 0x00000002 399 #define AR_crc_err 0x00000004 400 #define AR_decrypt_crc_err 0x00000008 401 #define AR_phyerr 0x00000010 402 #define AR_michael_err 0x00000020 403 #define AR_pre_delim_crc_err 0x00000040 404 #define AR_apsd_trig 0x00000080 405 #define AR_rx_key_idx_valid 0x00000100 406 #define AR_key_idx 0x0000fe00 407 #define AR_key_idx_S 9 408 #define AR_phy_err_code 0x0000ff00 409 #define AR_phy_err_code_S 8 410 #define AR_rx_more_aggr 0x00010000 411 #define AR_rx_aggr 0x00020000 412 #define AR_post_delim_crc_err 0x00040000 413 #define AR_rx_status_rsvd71 0x01f80000 414 #define AR_hw_upload_data_type 0x06000000 415 #define AR_hw_upload_data_type_S 25 416 #define AR_position_bit 0x08000000 /* positioning bit */ 417 #define AR_hi_rx_chain 0x10000000 418 #define AR_rx_first_aggr 0x20000000 419 #define AR_decrypt_busy_err 0x40000000 420 #define AR_key_miss 0x80000000 421 422 #define TXCTL_OFFSET(ah) 11 423 #define TXCTL_NUMWORDS(ah) 12 424 #define TXSTATUS_OFFSET(ah) 2 425 #define TXSTATUS_NUMWORDS(ah) 7 426 427 #define RXCTL_OFFSET(ah) 0 428 #define RXCTL_NUMWORDS(ah) 0 429 #define RXSTATUS_OFFSET(ah) 1 430 #define RXSTATUS_NUMWORDS(ah) 11 431 432 433 #define TXC_INFO(_qcu, _desclen) (ATHEROS_VENDOR_ID << AR_desc_id_S) \ 434 | (1 << AR_tx_rx_desc_S) \ 435 | (1 << AR_ctrl_stat_S) \ 436 | (_qcu << AR_tx_qcu_num_S) \ 437 | (_desclen) 438 439 #define VALID_KEY_TYPES \ 440 ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ 441 (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) 442 #define is_valid_key_type(_t) ((1 << (_t)) & VALID_KEY_TYPES) 443 444 #define set_11n_tries(_series, _index) \ 445 (SM((_series)[_index].Tries, AR_xmit_data_tries##_index)) 446 447 #define set_11n_rate(_series, _index) \ 448 (SM((_series)[_index].Rate, AR_xmit_rate##_index)) 449 450 #define set_11n_pkt_dur_rts_cts(_series, _index) \ 451 (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\ 452 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ 453 AR_rts_cts_qual##_index : 0)) 454 455 #define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88)) 456 457 #define set_11n_tx_bf_ldpc( _series) \ 458 ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \ 459 (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \ 460 && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \ 461 ? AR_ldpc : 0) 462 463 #define set_11n_rate_flags(_series, _index) \ 464 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ 465 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \ 466 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \ 467 |SM((_series)[_index].ChSel, AR_chain_sel##_index) 468 469 #define set_11n_tx_power(_index, _txpower) \ 470 SM(_txpower, AR_xmit_power##_index) 471 472 #define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7) 473 /* 474 * Descriptor Access Functions 475 */ 476 /* XXX valid Tx rates will change for 3 stream support */ 477 #define VALID_PKT_TYPES \ 478 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\ 479 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\ 480 (1<<HAL_PKT_TYPE_BEACON)) 481 #define is_valid_pkt_type(_t) ((1<<(_t)) & VALID_PKT_TYPES) 482 #define VALID_TX_RATES \ 483 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\ 484 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\ 485 (1<<0x1d)|(1<<0x18)|(1<<0x1c)) 486 #define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES) 487 488 489 #ifdef _KERNEL 490 /* TX common functions */ 491 492 extern HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *, 493 HAL_BOOL IncTrigLevel); 494 extern u_int16_t ar9300_get_tx_trig_level(struct ath_hal *); 495 extern HAL_BOOL ar9300_set_tx_queue_props(struct ath_hal *ah, int q, 496 const HAL_TXQ_INFO *q_info); 497 extern HAL_BOOL ar9300_get_tx_queue_props(struct ath_hal *ah, int q, 498 HAL_TXQ_INFO *q_info); 499 extern int ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 500 const HAL_TXQ_INFO *q_info); 501 extern HAL_BOOL ar9300_release_tx_queue(struct ath_hal *ah, u_int q); 502 extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q); 503 extern u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q); 504 extern HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp); 505 extern HAL_BOOL ar9300_start_tx_dma(struct ath_hal *ah, u_int q); 506 extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); 507 extern HAL_BOOL ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout); 508 extern HAL_BOOL ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout); 509 extern HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah); 510 extern void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *); 511 512 extern void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds); 513 extern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, HAL_DMA_ADDR *buf_addr, 514 u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg, 515 HAL_BOOL last_seg, const void *ds0); 516 extern void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link); 517 extern void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link); 518 extern void ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds); 519 #ifdef ATH_SWRETRY 520 extern void ar9300_clear_dest_mask(struct ath_hal *ah, void *ds); 521 #endif 522 extern HAL_STATUS ar9300_proc_tx_desc(struct ath_hal *ah, void *); 523 extern void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *); 524 extern void ar9300_get_tx_rate_code(struct ath_hal *ah, void *, struct ath_tx_status *); 525 extern u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *, 526 HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes); 527 extern void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t); 528 extern void ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num); 529 HAL_STATUS ar9300_is_tx_done(struct ath_hal *ah); 530 extern void ar9300_set_11n_tx_desc(struct ath_hal *ah, void *ds, 531 u_int pkt_len, HAL_PKT_TYPE type, u_int tx_power, 532 u_int key_ix, HAL_KEY_TYPE key_type, u_int flags); 533 extern void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask); 534 extern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit); 535 536 /* for tx_bf*/ 537 #define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 538 /* for tx_bf*/ 539 540 extern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds, 541 void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[], 542 u_int nseries, u_int flags, u_int32_t smartAntenna); 543 extern void ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 544 u_int aggr_len, u_int num_delims); 545 extern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 546 u_int num_delims); 547 extern void ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 548 extern void ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 549 extern void ar9300_set_11n_burst_duration(struct ath_hal *ah, 550 struct ath_desc *ds, u_int burst_duration); 551 extern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds); 552 extern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds); 553 extern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds); 554 extern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds); 555 extern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, 556 struct ath_desc *ds, u_int vmf); 557 #ifdef AH_PRIVATE_DIAG 558 extern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode); 559 #endif 560 561 /* RX common functions */ 562 563 extern u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype); 564 extern void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype); 565 extern void ar9300_enable_receive(struct ath_hal *ah); 566 extern HAL_BOOL ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout); 567 extern void ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning); 568 extern void ar9300_stop_pcu_receive(struct ath_hal *ah); 569 extern void ar9300_set_multicast_filter(struct ath_hal *ah, 570 u_int32_t filter0, u_int32_t filter1); 571 extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); 572 extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); 573 extern HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL); 574 extern HAL_BOOL ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL); 575 576 extern HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah, 577 struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *); 578 extern HAL_STATUS ar9300_get_rx_key_idx(struct ath_hal *ah, 579 struct ath_desc *, u_int8_t *, u_int8_t *); 580 extern HAL_STATUS ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *, 581 u_int32_t, struct ath_desc *, struct ath_rx_status *, void *); 582 583 extern void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable); 584 extern void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 585 extern void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t ); 586 587 #endif 588 589 #endif /* _ATH_AR9300_DESC_H_ */ 590