1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 /* Contains descriptor definitions for Osprey */ 19 20 21 #ifndef _ATH_AR9300_DESC_H_ 22 #define _ATH_AR9300_DESC_H_ 23 24 #ifdef _KERNEL 25 #include "ar9300_freebsd_inc.h" 26 #endif 27 28 /* Osprey Status Descriptor. */ 29 struct ar9300_txs { 30 u_int32_t ds_info; 31 u_int32_t status1; 32 u_int32_t status2; 33 u_int32_t status3; 34 u_int32_t status4; 35 u_int32_t status5; 36 u_int32_t status6; 37 u_int32_t status7; 38 u_int32_t status8; 39 }; 40 41 struct ar9300_rxs { 42 u_int32_t ds_info; 43 u_int32_t status1; 44 u_int32_t status2; 45 u_int32_t status3; 46 u_int32_t status4; 47 u_int32_t status5; 48 u_int32_t status6; 49 u_int32_t status7; 50 u_int32_t status8; 51 u_int32_t status9; 52 u_int32_t status10; 53 u_int32_t status11; 54 }; 55 56 /* Transmit Control Descriptor */ 57 struct ar9300_txc { 58 u_int32_t ds_info; /* descriptor information */ 59 u_int32_t ds_link; /* link pointer */ 60 u_int32_t ds_data0; /* data pointer to 1st buffer */ 61 u_int32_t ds_ctl3; /* DMA control 3 */ 62 u_int32_t ds_data1; /* data pointer to 2nd buffer */ 63 u_int32_t ds_ctl5; /* DMA control 5 */ 64 u_int32_t ds_data2; /* data pointer to 3rd buffer */ 65 u_int32_t ds_ctl7; /* DMA control 7 */ 66 u_int32_t ds_data3; /* data pointer to 4th buffer */ 67 u_int32_t ds_ctl9; /* DMA control 9 */ 68 u_int32_t ds_ctl10; /* DMA control 10 */ 69 u_int32_t ds_ctl11; /* DMA control 11 */ 70 u_int32_t ds_ctl12; /* DMA control 12 */ 71 u_int32_t ds_ctl13; /* DMA control 13 */ 72 u_int32_t ds_ctl14; /* DMA control 14 */ 73 u_int32_t ds_ctl15; /* DMA control 15 */ 74 u_int32_t ds_ctl16; /* DMA control 16 */ 75 u_int32_t ds_ctl17; /* DMA control 17 */ 76 u_int32_t ds_ctl18; /* DMA control 18 */ 77 u_int32_t ds_ctl19; /* DMA control 19 */ 78 u_int32_t ds_ctl20; /* DMA control 20 */ 79 u_int32_t ds_ctl21; /* DMA control 21 */ 80 u_int32_t ds_ctl22; /* DMA control 22 */ 81 u_int32_t ds_pad[9]; /* pad to cache line (128 bytes/32 dwords) */ 82 }; 83 84 85 #define AR9300RXS(_rxs) ((struct ar9300_rxs *)(_rxs)) 86 #define AR9300TXS(_txs) ((struct ar9300_txs *)(_txs)) 87 #define AR9300TXC(_ds) ((struct ar9300_txc *)(_ds)) 88 89 #define AR9300TXC_CONST(_ds) ((const struct ar9300_txc *)(_ds)) 90 91 92 /* ds_info */ 93 #define AR_desc_len 0x000000ff 94 #define AR_rx_priority 0x00000100 95 #define AR_tx_qcu_num 0x00000f00 96 #define AR_tx_qcu_num_S 8 97 #define AR_ctrl_stat 0x00004000 98 #define AR_ctrl_stat_S 14 99 #define AR_tx_rx_desc 0x00008000 100 #define AR_tx_rx_desc_S 15 101 #define AR_desc_id 0xffff0000 102 #define AR_desc_id_S 16 103 104 /*********** 105 * TX Desc * 106 ***********/ 107 108 /* ds_ctl3 */ 109 /* ds_ctl5 */ 110 /* ds_ctl7 */ 111 /* ds_ctl9 */ 112 #define AR_buf_len 0x0fff0000 113 #define AR_buf_len_S 16 114 115 /* ds_ctl10 */ 116 #define AR_tx_desc_id 0xffff0000 117 #define AR_tx_desc_id_S 16 118 #define AR_tx_ptr_chk_sum 0x0000ffff 119 120 /* ds_ctl11 */ 121 #define AR_frame_len 0x00000fff 122 #define AR_virt_more_frag 0x00001000 123 #define AR_tx_ctl_rsvd00 0x00002000 124 #define AR_low_rx_chain 0x00004000 125 #define AR_tx_clear_retry 0x00008000 126 #define AR_xmit_power0 0x003f0000 127 #define AR_xmit_power0_S 16 128 #define AR_rts_enable 0x00400000 129 #define AR_veol 0x00800000 130 #define AR_clr_dest_mask 0x01000000 131 #define AR_tx_bf0 0x02000000 132 #define AR_tx_bf1 0x04000000 133 #define AR_tx_bf2 0x08000000 134 #define AR_tx_bf3 0x10000000 135 #define AR_TxBfSteered 0x1e000000 /* for tx_bf*/ 136 #define AR_tx_intr_req 0x20000000 137 #define AR_dest_idx_valid 0x40000000 138 #define AR_cts_enable 0x80000000 139 140 /* ds_ctl12 */ 141 #define AR_tx_ctl_rsvd02 0x000001ff 142 #define AR_paprd_chain_mask 0x00000e00 143 #define AR_paprd_chain_mask_S 9 144 #define AR_tx_more 0x00001000 145 #define AR_dest_idx 0x000fe000 146 #define AR_dest_idx_S 13 147 #define AR_frame_type 0x00f00000 148 #define AR_frame_type_S 20 149 #define AR_no_ack 0x01000000 150 #define AR_insert_ts 0x02000000 151 #define AR_corrupt_fcs 0x04000000 152 #define AR_ext_only 0x08000000 153 #define AR_ext_and_ctl 0x10000000 154 #define AR_more_aggr 0x20000000 155 #define AR_is_aggr 0x40000000 156 #define AR_more_rifs 0x80000000 157 #define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */ 158 159 /* ds_ctl13 */ 160 #define AR_burst_dur 0x00007fff 161 #define AR_burst_dur_S 0 162 #define AR_dur_update_ena 0x00008000 163 #define AR_xmit_data_tries0 0x000f0000 164 #define AR_xmit_data_tries0_S 16 165 #define AR_xmit_data_tries1 0x00f00000 166 #define AR_xmit_data_tries1_S 20 167 #define AR_xmit_data_tries2 0x0f000000 168 #define AR_xmit_data_tries2_S 24 169 #define AR_xmit_data_tries3 0xf0000000 170 #define AR_xmit_data_tries3_S 28 171 172 /* ds_ctl14 */ 173 #define AR_xmit_rate0 0x000000ff 174 #define AR_xmit_rate0_S 0 175 #define AR_xmit_rate1 0x0000ff00 176 #define AR_xmit_rate1_S 8 177 #define AR_xmit_rate2 0x00ff0000 178 #define AR_xmit_rate2_S 16 179 #define AR_xmit_rate3 0xff000000 180 #define AR_xmit_rate3_S 24 181 182 /* ds_ctl15 */ 183 #define AR_packet_dur0 0x00007fff 184 #define AR_packet_dur0_S 0 185 #define AR_rts_cts_qual0 0x00008000 186 #define AR_packet_dur1 0x7fff0000 187 #define AR_packet_dur1_S 16 188 #define AR_rts_cts_qual1 0x80000000 189 190 /* ds_ctl16 */ 191 #define AR_packet_dur2 0x00007fff 192 #define AR_packet_dur2_S 0 193 #define AR_rts_cts_qual2 0x00008000 194 #define AR_packet_dur3 0x7fff0000 195 #define AR_packet_dur3_S 16 196 #define AR_rts_cts_qual3 0x80000000 197 198 /* ds_ctl17 */ 199 #define AR_aggr_len 0x0000ffff 200 #define AR_aggr_len_S 0 201 #define AR_tx_ctl_rsvd60 0x00030000 202 #define AR_pad_delim 0x03fc0000 203 #define AR_pad_delim_S 18 204 #define AR_encr_type 0x1c000000 205 #define AR_encr_type_S 26 206 #define AR_tx_dc_ap_sta_sel 0x40000000 207 #define AR_tx_ctl_rsvd61 0xc0000000 208 #define AR_calibrating 0x40000000 209 #define AR_ldpc 0x80000000 210 211 /* ds_ctl18 */ 212 #define AR_2040_0 0x00000001 213 #define AR_gi0 0x00000002 214 #define AR_chain_sel0 0x0000001c 215 #define AR_chain_sel0_S 2 216 #define AR_2040_1 0x00000020 217 #define AR_gi1 0x00000040 218 #define AR_chain_sel1 0x00000380 219 #define AR_chain_sel1_S 7 220 #define AR_2040_2 0x00000400 221 #define AR_gi2 0x00000800 222 #define AR_chain_sel2 0x00007000 223 #define AR_chain_sel2_S 12 224 #define AR_2040_3 0x00008000 225 #define AR_gi3 0x00010000 226 #define AR_chain_sel3 0x000e0000 227 #define AR_chain_sel3_S 17 228 #define AR_rts_cts_rate 0x0ff00000 229 #define AR_rts_cts_rate_S 20 230 #define AR_stbc0 0x10000000 231 #define AR_stbc1 0x20000000 232 #define AR_stbc2 0x40000000 233 #define AR_stbc3 0x80000000 234 235 /* ds_ctl19 */ 236 #define AR_tx_ant0 0x00ffffff 237 #define AR_tx_ant_sel0 0x80000000 238 #define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/ 239 #define AR_not_sounding 0x20000000 240 #define AR_ness 0xc0000000 241 #define AR_ness_S 30 242 243 /* ds_ctl20 */ 244 #define AR_tx_ant1 0x00ffffff 245 #define AR_xmit_power1 0x3f000000 246 #define AR_xmit_power1_S 24 247 #define AR_tx_ant_sel1 0x80000000 248 #define AR_ness1 0xc0000000 249 #define AR_ness1_S 30 250 251 /* ds_ctl21 */ 252 #define AR_tx_ant2 0x00ffffff 253 #define AR_xmit_power2 0x3f000000 254 #define AR_xmit_power2_S 24 255 #define AR_tx_ant_sel2 0x80000000 256 #define AR_ness2 0xc0000000 257 #define AR_ness2_S 30 258 259 /* ds_ctl22 */ 260 #define AR_tx_ant3 0x00ffffff 261 #define AR_xmit_power3 0x3f000000 262 #define AR_xmit_power3_S 24 263 #define AR_tx_ant_sel3 0x80000000 264 #define AR_ness3 0xc0000000 265 #define AR_ness3_S 30 266 267 /************* 268 * TX Status * 269 *************/ 270 271 /* ds_status1 */ 272 #define AR_tx_status_rsvd 0x0000ffff 273 274 /* ds_status2 */ 275 #define AR_tx_rssi_ant00 0x000000ff 276 #define AR_tx_rssi_ant00_S 0 277 #define AR_tx_rssi_ant01 0x0000ff00 278 #define AR_tx_rssi_ant01_S 8 279 #define AR_tx_rssi_ant02 0x00ff0000 280 #define AR_tx_rssi_ant02_S 16 281 #define AR_tx_status_rsvd00 0x3f000000 282 #define AR_tx_ba_status 0x40000000 283 #define AR_tx_status_rsvd01 0x80000000 284 285 /* ds_status3 */ 286 #define AR_frm_xmit_ok 0x00000001 287 #define AR_excessive_retries 0x00000002 288 #define AR_fifounderrun 0x00000004 289 #define AR_filtered 0x00000008 290 #define AR_rts_fail_cnt 0x000000f0 291 #define AR_rts_fail_cnt_S 4 292 #define AR_data_fail_cnt 0x00000f00 293 #define AR_data_fail_cnt_S 8 294 #define AR_virt_retry_cnt 0x0000f000 295 #define AR_virt_retry_cnt_S 12 296 #define AR_tx_delim_underrun 0x00010000 297 #define AR_tx_data_underrun 0x00020000 298 #define AR_desc_cfg_err 0x00040000 299 #define AR_tx_timer_expired 0x00080000 300 #define AR_tx_status_rsvd10 0xfff00000 301 302 /* ds_status7 */ 303 #define AR_tx_rssi_ant10 0x000000ff 304 #define AR_tx_rssi_ant10_S 0 305 #define AR_tx_rssi_ant11 0x0000ff00 306 #define AR_tx_rssi_ant11_S 8 307 #define AR_tx_rssi_ant12 0x00ff0000 308 #define AR_tx_rssi_ant12_S 16 309 #define AR_tx_rssi_combined 0xff000000 310 #define AR_tx_rssi_combined_S 24 311 312 /* ds_status8 */ 313 #define AR_tx_done 0x00000001 314 #define AR_seq_num 0x00001ffe 315 #define AR_seq_num_S 1 316 #define AR_tx_status_rsvd80 0x0001e000 317 #define AR_tx_op_exceeded 0x00020000 318 #define AR_tx_status_rsvd81 0x001c0000 319 #define AR_TXBFStatus 0x001c0000 320 #define AR_TXBFStatus_S 18 321 #define AR_tx_bf_bw_mismatch 0x00040000 322 #define AR_tx_bf_stream_miss 0x00080000 323 #define AR_final_tx_idx 0x00600000 324 #define AR_final_tx_idx_S 21 325 #define AR_tx_bf_dest_miss 0x00800000 326 #define AR_tx_bf_expired 0x01000000 327 #define AR_power_mgmt 0x02000000 328 #define AR_tx_status_rsvd83 0x0c000000 329 #define AR_tx_tid 0xf0000000 330 #define AR_tx_tid_S 28 331 #define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */ 332 333 334 /************* 335 * Rx Status * 336 *************/ 337 338 /* ds_status1 */ 339 #define AR_rx_rssi_ant00 0x000000ff 340 #define AR_rx_rssi_ant00_S 0 341 #define AR_rx_rssi_ant01 0x0000ff00 342 #define AR_rx_rssi_ant01_S 8 343 #define AR_rx_rssi_ant02 0x00ff0000 344 #define AR_rx_rssi_ant02_S 16 345 #define AR_rx_rate 0xff000000 346 #define AR_rx_rate_S 24 347 348 /* ds_status2 */ 349 #define AR_data_len 0x00000fff 350 #define AR_data_len_S 0 351 #define AR_rx_more 0x00001000 352 #define AR_num_delim 0x003fc000 353 #define AR_num_delim_S 14 354 #define AR_hw_upload_data 0x00400000 355 #define AR_hw_upload_data_S 22 356 #define AR_rx_status_rsvd10 0xff800000 357 358 359 /* ds_status4 */ 360 #define AR_gi 0x00000001 361 #define AR_2040 0x00000002 362 #define AR_parallel40 0x00000004 363 #define AR_parallel40_S 2 364 #define AR_rx_stbc 0x00000008 365 #define AR_rx_not_sounding 0x00000010 366 #define AR_rx_ness 0x00000060 367 #define AR_rx_ness_S 5 368 #define AR_hw_upload_data_valid 0x00000080 369 #define AR_hw_upload_data_valid_S 7 370 #define AR_rx_antenna 0xffffff00 371 #define AR_rx_antenna_S 8 372 373 /* ds_status5 */ 374 #define AR_rx_rssi_ant10 0x000000ff 375 #define AR_rx_rssi_ant10_S 0 376 #define AR_rx_rssi_ant11 0x0000ff00 377 #define AR_rx_rssi_ant11_S 8 378 #define AR_rx_rssi_ant12 0x00ff0000 379 #define AR_rx_rssi_ant12_S 16 380 #define AR_rx_rssi_combined 0xff000000 381 #define AR_rx_rssi_combined_S 24 382 383 /* ds_status6 */ 384 #define AR_rx_evm0 status6 385 386 /* ds_status7 */ 387 #define AR_rx_evm1 status7 388 389 /* ds_status8 */ 390 #define AR_rx_evm2 status8 391 392 /* ds_status9 */ 393 #define AR_rx_evm3 status9 394 395 /* ds_status11 */ 396 #define AR_rx_done 0x00000001 397 #define AR_rx_frame_ok 0x00000002 398 #define AR_crc_err 0x00000004 399 #define AR_decrypt_crc_err 0x00000008 400 #define AR_phyerr 0x00000010 401 #define AR_michael_err 0x00000020 402 #define AR_pre_delim_crc_err 0x00000040 403 #define AR_apsd_trig 0x00000080 404 #define AR_rx_key_idx_valid 0x00000100 405 #define AR_key_idx 0x0000fe00 406 #define AR_key_idx_S 9 407 #define AR_phy_err_code 0x0000ff00 408 #define AR_phy_err_code_S 8 409 #define AR_rx_more_aggr 0x00010000 410 #define AR_rx_aggr 0x00020000 411 #define AR_post_delim_crc_err 0x00040000 412 #define AR_rx_status_rsvd71 0x01f80000 413 #define AR_hw_upload_data_type 0x06000000 414 #define AR_hw_upload_data_type_S 25 415 #define AR_position_bit 0x08000000 /* positioning bit */ 416 #define AR_hi_rx_chain 0x10000000 417 #define AR_rx_first_aggr 0x20000000 418 #define AR_decrypt_busy_err 0x40000000 419 #define AR_key_miss 0x80000000 420 421 #define TXCTL_OFFSET(ah) 11 422 #define TXCTL_NUMWORDS(ah) 12 423 #define TXSTATUS_OFFSET(ah) 2 424 #define TXSTATUS_NUMWORDS(ah) 7 425 426 #define RXCTL_OFFSET(ah) 0 427 #define RXCTL_NUMWORDS(ah) 0 428 #define RXSTATUS_OFFSET(ah) 1 429 #define RXSTATUS_NUMWORDS(ah) 11 430 431 432 #define TXC_INFO(_qcu) (ATHEROS_VENDOR_ID << AR_desc_id_S) \ 433 | (1 << AR_tx_rx_desc_S) \ 434 | (1 << AR_ctrl_stat_S) \ 435 | (_qcu << AR_tx_qcu_num_S) \ 436 | (0x17) 437 438 #define VALID_KEY_TYPES \ 439 ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ 440 (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) 441 #define is_valid_key_type(_t) ((1 << (_t)) & VALID_KEY_TYPES) 442 443 #define set_11n_tries(_series, _index) \ 444 (SM((_series)[_index].Tries, AR_xmit_data_tries##_index)) 445 446 #define set_11n_rate(_series, _index) \ 447 (SM((_series)[_index].Rate, AR_xmit_rate##_index)) 448 449 #define set_11n_pkt_dur_rts_cts(_series, _index) \ 450 (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\ 451 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ 452 AR_rts_cts_qual##_index : 0)) 453 454 #define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88)) 455 456 #define set_11n_tx_bf_ldpc( _series) \ 457 ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \ 458 (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \ 459 && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \ 460 ? AR_ldpc : 0) 461 462 #define set_11n_rate_flags(_series, _index) \ 463 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ 464 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \ 465 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \ 466 |SM((_series)[_index].ChSel, AR_chain_sel##_index) 467 468 #define set_11n_tx_power(_index, _txpower) \ 469 SM(_txpower, AR_xmit_power##_index) 470 471 #define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7) 472 /* 473 * Descriptor Access Functions 474 */ 475 /* XXX valid Tx rates will change for 3 stream support */ 476 #define VALID_PKT_TYPES \ 477 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\ 478 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\ 479 (1<<HAL_PKT_TYPE_BEACON)) 480 #define is_valid_pkt_type(_t) ((1<<(_t)) & VALID_PKT_TYPES) 481 #define VALID_TX_RATES \ 482 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\ 483 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\ 484 (1<<0x1d)|(1<<0x18)|(1<<0x1c)) 485 #define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES) 486 487 488 #ifdef _KERNEL 489 /* TX common functions */ 490 491 extern HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *, 492 HAL_BOOL IncTrigLevel); 493 extern u_int16_t ar9300_get_tx_trig_level(struct ath_hal *); 494 extern HAL_BOOL ar9300_set_tx_queue_props(struct ath_hal *ah, int q, 495 const HAL_TXQ_INFO *q_info); 496 extern HAL_BOOL ar9300_get_tx_queue_props(struct ath_hal *ah, int q, 497 HAL_TXQ_INFO *q_info); 498 extern int ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 499 const HAL_TXQ_INFO *q_info); 500 extern HAL_BOOL ar9300_release_tx_queue(struct ath_hal *ah, u_int q); 501 extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q); 502 extern u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q); 503 extern HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp); 504 extern HAL_BOOL ar9300_start_tx_dma(struct ath_hal *ah, u_int q); 505 extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); 506 extern HAL_BOOL ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout); 507 extern HAL_BOOL ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout); 508 extern HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah); 509 extern void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *); 510 511 extern void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds); 512 extern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, HAL_DMA_ADDR *buf_addr, 513 u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg, 514 HAL_BOOL last_seg, const void *ds0); 515 extern void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link); 516 extern void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link); 517 extern void ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds); 518 #ifdef ATH_SWRETRY 519 extern void ar9300_clear_dest_mask(struct ath_hal *ah, void *ds); 520 #endif 521 extern HAL_STATUS ar9300_proc_tx_desc(struct ath_hal *ah, void *); 522 extern void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *); 523 extern void ar9300_get_tx_rate_code(struct ath_hal *ah, void *, struct ath_tx_status *); 524 extern u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *, 525 HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes); 526 extern void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t); 527 extern void ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num); 528 HAL_STATUS ar9300_is_tx_done(struct ath_hal *ah); 529 extern void ar9300_set_11n_tx_desc(struct ath_hal *ah, void *ds, 530 u_int pkt_len, HAL_PKT_TYPE type, u_int tx_power, 531 u_int key_ix, HAL_KEY_TYPE key_type, u_int flags); 532 extern void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask); 533 extern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit); 534 535 /* for tx_bf*/ 536 #define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 537 /* for tx_bf*/ 538 539 extern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds, 540 void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[], 541 u_int nseries, u_int flags, u_int32_t smartAntenna); 542 extern void ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 543 u_int aggr_len, u_int num_delims); 544 extern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 545 u_int num_delims); 546 extern void ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 547 extern void ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 548 extern void ar9300_set_11n_burst_duration(struct ath_hal *ah, 549 struct ath_desc *ds, u_int burst_duration); 550 extern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds); 551 extern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds); 552 extern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds); 553 extern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds); 554 extern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, 555 struct ath_desc *ds, u_int vmf); 556 #ifdef AH_PRIVATE_DIAG 557 extern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode); 558 #endif 559 560 /* RX common functions */ 561 562 extern u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype); 563 extern void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype); 564 extern void ar9300_enable_receive(struct ath_hal *ah); 565 extern HAL_BOOL ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout); 566 extern void ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning); 567 extern void ar9300_stop_pcu_receive(struct ath_hal *ah); 568 extern void ar9300_set_multicast_filter(struct ath_hal *ah, 569 u_int32_t filter0, u_int32_t filter1); 570 extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); 571 extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); 572 extern HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL); 573 extern HAL_BOOL ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL); 574 575 extern HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah, 576 struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *); 577 extern HAL_STATUS ar9300_get_rx_key_idx(struct ath_hal *ah, 578 struct ath_desc *, u_int8_t *, u_int8_t *); 579 extern HAL_STATUS ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *, 580 u_int32_t, struct ath_desc *, struct ath_rx_status *, void *); 581 582 extern void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable); 583 extern void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 584 extern void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t ); 585 586 #endif 587 588 #endif /* _ATH_AR9300_DESC_H_ */ 589