1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_desc.h" 21 #include "ah_internal.h" 22 23 #include "ar9300/ar9300.h" 24 #include "ar9300/ar9300reg.h" 25 #include "ar9300/ar9300desc.h" 26 27 /* 28 * Get the RXDP. 29 */ 30 u_int32_t 31 ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype) 32 { 33 if (qtype == HAL_RX_QUEUE_HP) { 34 return OS_REG_READ(ath, AR_HP_RXDP); 35 } else { 36 return OS_REG_READ(ath, AR_LP_RXDP); 37 } 38 } 39 40 /* 41 * Set the rx_dp. 42 */ 43 void 44 ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype) 45 { 46 HALASSERT((qtype == HAL_RX_QUEUE_HP) || (qtype == HAL_RX_QUEUE_LP)); 47 48 if (qtype == HAL_RX_QUEUE_HP) { 49 OS_REG_WRITE(ah, AR_HP_RXDP, rxdp); 50 } else { 51 OS_REG_WRITE(ah, AR_LP_RXDP, rxdp); 52 } 53 } 54 55 /* 56 * Set Receive Enable bits. 57 */ 58 void 59 ar9300_enable_receive(struct ath_hal *ah) 60 { 61 OS_REG_WRITE(ah, AR_CR, 0); 62 } 63 64 /* 65 * Set the RX abort bit. 66 */ 67 HAL_BOOL 68 ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL set) 69 { 70 if (set) { 71 /* Set the force_rx_abort bit */ 72 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 73 74 if ( AH9300(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){ 75 /* depending upon the BB panic status, rx state may not return to 0, 76 * so skipping the wait for BB panic reset */ 77 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 78 return AH_FALSE; 79 } else { 80 HAL_BOOL okay; 81 okay = ath_hal_wait( 82 ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0); 83 /* Wait for Rx state to return to 0 */ 84 if (!okay) { 85 /* abort: chip rx failed to go idle in 10 ms */ 86 OS_REG_CLR_BIT(ah, AR_DIAG_SW, 87 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 88 89 HALDEBUG(ah, HAL_DEBUG_RX, 90 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", 91 __func__, OS_REG_READ(ah, AR_OBS_BUS_1)); 92 93 return AH_FALSE; /* failure */ 94 } 95 } 96 } else { 97 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 98 } 99 100 return AH_TRUE; /* success */ 101 } 102 103 /* 104 * Stop Receive at the DMA engine 105 */ 106 HAL_BOOL 107 ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout) 108 { 109 int wait; 110 HAL_BOOL status, okay; 111 u_int32_t org_value; 112 113 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 114 #define AH_TIME_QUANTUM 100 /* usec */ 115 116 if (timeout == 0) { 117 timeout = AH_RX_STOP_DMA_TIMEOUT; 118 } 119 120 org_value = OS_REG_READ(ah, AR_MACMISC); 121 122 OS_REG_WRITE(ah, AR_MACMISC, 123 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 124 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 125 126 okay = ath_hal_wait( 127 ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0); 128 /* wait for Rx DMA state machine to become idle */ 129 if (!okay) { 130 HALDEBUG(ah, HAL_DEBUG_RX, 131 "reg AR_DMADBG_7 is not 0, instead 0x%08x\n", 132 OS_REG_READ(ah, AR_DMADBG_7)); 133 } 134 135 /* Set receive disable bit */ 136 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); 137 138 /* Wait for rx enable bit to go low */ 139 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 140 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { 141 break; 142 } 143 OS_DELAY(AH_TIME_QUANTUM); 144 } 145 146 if (wait == 0) { 147 HALDEBUG(ah, HAL_DEBUG_RX, "%s: dma failed to stop in %d ms\n" 148 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 149 __func__, 150 timeout / 1000, 151 OS_REG_READ(ah, AR_CR), 152 OS_REG_READ(ah, AR_DIAG_SW)); 153 status = AH_FALSE; 154 } else { 155 status = AH_TRUE; 156 } 157 158 OS_REG_WRITE(ah, AR_MACMISC, org_value); 159 160 return status; 161 #undef AH_RX_STOP_DMA_TIMEOUT 162 #undef AH_TIME_QUANTUM 163 } 164 165 /* 166 * Start Transmit at the PCU engine (unpause receive) 167 */ 168 void 169 ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning) 170 { 171 ar9300_enable_mib_counters(ah); 172 ar9300_ani_reset(ah, is_scanning); 173 /* Clear RX_DIS and RX_ABORT after enabling phy errors in ani_reset */ 174 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 175 } 176 177 /* 178 * Stop Transmit at the PCU engine (pause receive) 179 */ 180 void 181 ar9300_stop_pcu_receive(struct ath_hal *ah) 182 { 183 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 184 ar9300_disable_mib_counters(ah); 185 } 186 187 /* 188 * Set multicast filter 0 (lower 32-bits) 189 * filter 1 (upper 32-bits) 190 */ 191 void 192 ar9300_set_multicast_filter( 193 struct ath_hal *ah, 194 u_int32_t filter0, 195 u_int32_t filter1) 196 { 197 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 198 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 199 } 200 201 /* 202 * Get the receive filter. 203 */ 204 u_int32_t 205 ar9300_get_rx_filter(struct ath_hal *ah) 206 { 207 u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 208 u_int32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 209 if (phybits & AR_PHY_ERR_RADAR) { 210 bits |= HAL_RX_FILTER_PHYRADAR; 211 } 212 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) { 213 bits |= HAL_RX_FILTER_PHYERR; 214 } 215 return bits; 216 } 217 218 /* 219 * Set the receive filter. 220 */ 221 void 222 ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits) 223 { 224 u_int32_t phybits; 225 226 if (AR_SREV_SCORPION(ah)) { 227 /* Enable Rx for 4 address frames */ 228 bits |= AR_RX_4ADDRESS; 229 } 230 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 231 /* HW fix for rx hang and corruption. */ 232 bits |= AR_RX_CONTROL_WRAPPER; 233 } 234 OS_REG_WRITE(ah, AR_RX_FILTER, 235 bits | AR_RX_UNCOM_BA_BAR | AR_RX_COMPR_BAR); 236 phybits = 0; 237 if (bits & HAL_RX_FILTER_PHYRADAR) { 238 phybits |= AR_PHY_ERR_RADAR; 239 } 240 if (bits & HAL_RX_FILTER_PHYERR) { 241 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 242 } 243 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 244 if (phybits) { 245 OS_REG_WRITE(ah, AR_RXCFG, 246 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 247 } else { 248 OS_REG_WRITE(ah, AR_RXCFG, 249 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 250 } 251 } 252 253 /* 254 * Select to pass PLCP headr or EVM data. 255 */ 256 HAL_BOOL 257 ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL sel_evm, HAL_BOOL just_query) 258 { 259 struct ath_hal_9300 *ahp = AH9300(ah); 260 HAL_BOOL old_value = ahp->ah_get_plcp_hdr == 0; 261 262 if (just_query) { 263 return old_value; 264 } 265 if (sel_evm) { 266 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM); 267 } else { 268 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM); 269 } 270 271 ahp->ah_get_plcp_hdr = !sel_evm; 272 273 return old_value; 274 } 275 276 void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable) 277 { 278 u_int32_t reg_val = 0; 279 reg_val = OS_REG_READ(ah, AR_RX_FILTER); 280 if (enable){ 281 reg_val |= AR_RX_PROM; 282 } else{ /*Disable promisc mode */ 283 reg_val &= ~AR_RX_PROM; 284 } 285 OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); 286 } 287 288 void 289 ar9300_read_pktlog_reg( 290 struct ath_hal *ah, 291 u_int32_t *rxfilter_val, 292 u_int32_t *rxcfg_val, 293 u_int32_t *phy_err_mask_val, 294 u_int32_t *mac_pcu_phy_err_regval) 295 { 296 *rxfilter_val = OS_REG_READ(ah, AR_RX_FILTER); 297 *rxcfg_val = OS_REG_READ(ah, AR_RXCFG); 298 *phy_err_mask_val = OS_REG_READ(ah, AR_PHY_ERR); 299 *mac_pcu_phy_err_regval = OS_REG_READ(ah, 0x8338); 300 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 301 "%s[%d] rxfilter_val 0x%08x , rxcfg_val 0x%08x, " 302 "phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n", 303 __func__, __LINE__, 304 *rxfilter_val, *rxcfg_val, *phy_err_mask_val, *mac_pcu_phy_err_regval); 305 } 306 307 void 308 ar9300_write_pktlog_reg( 309 struct ath_hal *ah, 310 HAL_BOOL enable, 311 u_int32_t rxfilter_val, 312 u_int32_t rxcfg_val, 313 u_int32_t phy_err_mask_val, 314 u_int32_t mac_pcu_phy_err_reg_val) 315 { 316 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 317 /* HW fix for rx hang and corruption. */ 318 rxfilter_val |= AR_RX_CONTROL_WRAPPER; 319 } 320 if (enable) { /* Enable pktlog phyerr setting */ 321 OS_REG_WRITE(ah, AR_RX_FILTER, 0xffff | AR_RX_COMPR_BAR | rxfilter_val); 322 OS_REG_WRITE(ah, AR_PHY_ERR, 0xFFFFFFFF); 323 OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val | AR_RXCFG_ZLFDMA); 324 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val | 0xFF); 325 } else { /* Disable phyerr and Restore regs */ 326 OS_REG_WRITE(ah, AR_RX_FILTER, rxfilter_val); 327 OS_REG_WRITE(ah, AR_PHY_ERR, phy_err_mask_val); 328 OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val); 329 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val); 330 } 331 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 332 "%s[%d] ena %d rxfilter_val 0x%08x , rxcfg_val 0x%08x, " 333 "phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n", 334 __func__, __LINE__, 335 enable, rxfilter_val, rxcfg_val, 336 phy_err_mask_val, mac_pcu_phy_err_reg_val); 337 } 338