1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 #include "ar9300/ar9300desc.h" 30 31 static u_int32_t ar9300_read_loc_timer(struct ath_hal *ah); 32 33 void 34 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 35 { 36 struct ath_hal_9300 *ahp = AH9300(ah); 37 *hangs = 0; 38 39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 40 *hangs |= HAL_RIFS_BB_HANG_WAR; 41 } 42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 43 *hangs |= HAL_DFS_BB_HANG_WAR; 44 } 45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 46 == HAL_OK) 47 { 48 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 49 } 50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 51 *hangs |= HAL_MAC_HANG_WAR; 52 } 53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 54 == HAL_OK) 55 { 56 *hangs |= HAL_PHYRESTART_CLR_WAR; 57 } 58 59 ahp->ah_hang_wars = *hangs; 60 } 61 62 /* 63 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 64 * HT20, HT40, fast-clock, turbo mode, etc. 65 */ 66 static u_int 67 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 68 { 69 #if 0 70 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 71 72 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 73 return (ath_hal_mac_usec(ah, clks) / 2); 74 } else { 75 return (ath_hal_mac_usec(ah, clks)); 76 } 77 #endif 78 return (ath_hal_mac_usec(ah, clks)); 79 } 80 81 u_int 82 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 83 { 84 #if 0 85 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 86 87 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 88 return (ath_hal_mac_clks(ah, usecs) * 2); 89 } else { 90 return (ath_hal_mac_clks(ah, usecs)); 91 } 92 #endif 93 return (ath_hal_mac_clks(ah, usecs)); 94 } 95 96 void 97 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 98 { 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 101 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 102 } 103 104 HAL_BOOL 105 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 106 { 107 struct ath_hal_9300 *ahp = AH9300(ah); 108 109 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 110 return AH_TRUE; 111 } 112 113 void 114 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 115 { 116 struct ath_hal_9300 *ahp = AH9300(ah); 117 118 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 119 } 120 121 HAL_BOOL 122 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 123 { 124 struct ath_hal_9300 *ahp = AH9300(ah); 125 126 /* save it since it must be rewritten on reset */ 127 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 128 129 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 130 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 131 return AH_TRUE; 132 } 133 134 /* 135 * Attempt to change the cards operating regulatory domain to the given value 136 * Returns: A_EINVAL for an unsupported regulatory domain. 137 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 138 */ 139 HAL_BOOL 140 ar9300_set_regulatory_domain(struct ath_hal *ah, 141 u_int16_t reg_domain, HAL_STATUS *status) 142 { 143 HAL_STATUS ecode; 144 145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 146 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 147 return AH_TRUE; 148 } 149 ecode = HAL_EIO; 150 151 #if 0 152 bad: 153 #endif 154 if (status) { 155 *status = ecode; 156 } 157 return AH_FALSE; 158 } 159 160 /* 161 * Return the wireless modes (a,b,g,t) supported by hardware. 162 * 163 * This value is what is actually supported by the hardware 164 * and is unaffected by regulatory/country code settings. 165 * 166 */ 167 u_int 168 ar9300_get_wireless_modes(struct ath_hal *ah) 169 { 170 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 171 } 172 173 /* 174 * Set the interrupt and GPIO values so the ISR can disable RF 175 * on a switch signal. Assumes GPIO port and interrupt polarity 176 * are set prior to call. 177 */ 178 void 179 ar9300_enable_rf_kill(struct ath_hal *ah) 180 { 181 /* TODO - can this really be above the hal on the GPIO interface for 182 * TODO - the client only? 183 */ 184 struct ath_hal_9300 *ahp = AH9300(ah); 185 186 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 187 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 188 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 190 AR_RFSILENT_FORCE); 191 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 192 } 193 else { 194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 195 AR_RFSILENT_FORCE); 196 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 197 } 198 } 199 else { 200 /* Connect rfsilent_bb_l to baseband */ 201 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 202 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 203 204 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 AR_GPIO_INPUT_MUX2_RFSILENT); 207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 208 (ahp->ah_gpio_select & 0x0f) << 4); 209 210 /* 211 * Configure the desired GPIO port for input and 212 * enable baseband rf silence 213 */ 214 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 215 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 216 } 217 218 /* 219 * If radio disable switch connection to GPIO bit x is enabled 220 * program GPIO interrupt. 221 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 222 * verified that it is a later version of eeprom, it has a place for 223 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 224 * connection is present. 225 */ 226 /* 227 * RFKill uses polling not interrupt, 228 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 229 */ 230 if (ath_hal_hasrfkill_int(ah)) { 231 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 232 /* switch already closed, set to interrupt upon open */ 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 234 } else { 235 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 236 } 237 } 238 } 239 240 /* 241 * Change the LED blinking pattern to correspond to the connectivity 242 */ 243 void 244 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 245 { 246 static const u_int32_t ledbits[8] = { 247 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 250 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 251 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 252 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 253 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 254 AR_CFG_LED_ASSOC_NONE, 255 }; 256 257 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 258 } 259 260 /* 261 * Sets the Power LED on the cardbus without affecting the Network LED. 262 */ 263 void 264 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 265 { 266 u_int32_t val; 267 268 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 269 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 270 } 271 272 /* 273 * Sets the Network LED on the cardbus without affecting the Power LED. 274 */ 275 void 276 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 277 { 278 u_int32_t val; 279 280 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 281 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 282 } 283 284 /* 285 * Change association related fields programmed into the hardware. 286 * Writing a valid BSSID to the hardware effectively enables the hardware 287 * to synchronize its TSF to the correct beacons and receive frames coming 288 * from that BSSID. It is called by the SME JOIN operation. 289 */ 290 void 291 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 292 u_int16_t assoc_id) 293 { 294 struct ath_hal_9300 *ahp = AH9300(ah); 295 296 /* save bssid and assoc_id for restore on reset */ 297 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 298 ahp->ah_assoc_id = assoc_id; 299 300 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 301 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 302 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 303 } 304 305 /* 306 * Get the current hardware tsf for stamlme 307 */ 308 u_int64_t 309 ar9300_get_tsf64(struct ath_hal *ah) 310 { 311 u_int64_t tsf; 312 313 /* XXX sync multi-word read? */ 314 tsf = OS_REG_READ(ah, AR_TSF_U32); 315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 316 return tsf; 317 } 318 319 void 320 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 321 { 322 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 323 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 324 } 325 326 /* 327 * Get the current hardware tsf for stamlme 328 */ 329 u_int32_t 330 ar9300_get_tsf32(struct ath_hal *ah) 331 { 332 return OS_REG_READ(ah, AR_TSF_L32); 333 } 334 335 u_int32_t 336 ar9300_get_tsf2_32(struct ath_hal *ah) 337 { 338 return OS_REG_READ(ah, AR_TSF2_L32); 339 } 340 341 /* 342 * Reset the current hardware tsf for stamlme. 343 */ 344 void 345 ar9300_reset_tsf(struct ath_hal *ah) 346 { 347 int count; 348 349 count = 0; 350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 351 count++; 352 if (count > 10) { 353 HALDEBUG(ah, HAL_DEBUG_RESET, 354 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 355 break; 356 } 357 OS_DELAY(10); 358 } 359 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 360 } 361 362 /* 363 * Set or clear hardware basic rate bit 364 * Set hardware basic rate set if basic rate is found 365 * and basic rate is equal or less than 2Mbps 366 */ 367 void 368 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 369 { 370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 371 u_int32_t reg; 372 u_int8_t xset; 373 int i; 374 375 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 376 return; 377 } 378 xset = 0; 379 for (i = 0; i < rs->rs_count; i++) { 380 u_int8_t rset = rs->rs_rates[i]; 381 /* Basic rate defined? */ 382 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 383 xset = rset; 384 } 385 } 386 /* 387 * Set the h/w bit to reflect whether or not the basic 388 * rate is found to be equal or less than 2Mbps. 389 */ 390 reg = OS_REG_READ(ah, AR_STA_ID1); 391 if (xset && xset / 2 <= 2) { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 393 } else { 394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 395 } 396 } 397 398 /* 399 * Grab a semi-random value from hardware registers - may not 400 * change often 401 */ 402 u_int32_t 403 ar9300_get_random_seed(struct ath_hal *ah) 404 { 405 u_int32_t nf; 406 407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 408 if (nf & 0x100) { 409 nf = 0 - ((nf ^ 0x1ff) + 1); 410 } 411 return (OS_REG_READ(ah, AR_TSF_U32) ^ 412 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 413 } 414 415 /* 416 * Detect if our card is present 417 */ 418 HAL_BOOL 419 ar9300_detect_card_present(struct ath_hal *ah) 420 { 421 u_int16_t mac_version, mac_rev; 422 u_int32_t v; 423 424 /* 425 * Read the Silicon Revision register and compare that 426 * to what we read at attach time. If the same, we say 427 * a card/device is present. 428 */ 429 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 430 if (v == 0xFF) { 431 /* new SREV format */ 432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 433 /* 434 * Include 6-bit Chip Type (masked to 0) to differentiate 435 * from pre-Sowl versions 436 */ 437 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 438 mac_rev = MS(v, AR_SREV_REVISION2); 439 } else { 440 mac_version = MS(v, AR_SREV_VERSION); 441 mac_rev = v & AR_SREV_REVISION; 442 } 443 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 444 AH_PRIVATE(ah)->ah_macRev == mac_rev); 445 } 446 447 /* 448 * Update MIB Counters 449 */ 450 void 451 ar9300_update_mib_mac_stats(struct ath_hal *ah) 452 { 453 struct ath_hal_9300 *ahp = AH9300(ah); 454 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 455 456 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 457 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 458 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 459 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 460 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 461 } 462 463 void 464 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 465 { 466 struct ath_hal_9300 *ahp = AH9300(ah); 467 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 468 469 stats->ackrcv_bad = istats->ackrcv_bad; 470 stats->rts_bad = istats->rts_bad; 471 stats->fcs_bad = istats->fcs_bad; 472 stats->rts_good = istats->rts_good; 473 stats->beacons = istats->beacons; 474 } 475 476 /* 477 * Detect if the HW supports spreading a CCK signal on channel 14 478 */ 479 HAL_BOOL 480 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 481 { 482 return AH_TRUE; 483 } 484 485 /* 486 * Get the rssi of frame curently being received. 487 */ 488 u_int32_t 489 ar9300_get_cur_rssi(struct ath_hal *ah) 490 { 491 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 492 /* get combined RSSI */ 493 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 494 } 495 496 #if ATH_GEN_RANDOMNESS 497 /* 498 * Get the rssi value from BB on ctl chain0. 499 */ 500 u_int32_t 501 ar9300_get_rssi_chain0(struct ath_hal *ah) 502 { 503 /* get ctl chain0 RSSI */ 504 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 505 } 506 #endif 507 508 u_int 509 ar9300_get_def_antenna(struct ath_hal *ah) 510 { 511 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 512 } 513 514 /* Setup coverage class */ 515 void 516 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 517 { 518 } 519 520 void 521 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 522 { 523 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 524 } 525 526 HAL_BOOL 527 ar9300_set_antenna_switch(struct ath_hal *ah, 528 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 529 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 530 { 531 struct ath_hal_9300 *ahp = AH9300(ah); 532 533 /* 534 * Owl does not support diversity or changing antennas. 535 * 536 * Instead this API and function are defined differently for AR9300. 537 * To support Tablet PC's, this interface allows the system 538 * to dramatically reduce the TX power on a particular chain. 539 * 540 * Based on the value of (redefined) diversity_control, the 541 * reset code will decrease power on chain 0 or chain 1/2. 542 * 543 * Based on the value of bit 0 of antenna_switch_swap, 544 * the mapping between OID call and chain is defined as: 545 * 0: map A -> 0, B -> 1; 546 * 1: map A -> 1, B -> 0; 547 * 548 * NOTE: 549 * The devices that use this OID should use a tx_chain_mask and 550 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 551 * used in order to ensure an active transmit antenna. This 552 * API will allow the host to turn off the only transmitting 553 * antenna to ensure the antenna closest to the user's body is 554 * powered-down. 555 */ 556 /* 557 * Set antenna control for use during reset sequence by 558 * ar9300_decrease_chain_power() 559 */ 560 ahp->ah_diversity_control = settings; 561 562 return AH_TRUE; 563 } 564 565 HAL_BOOL 566 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 567 { 568 return AH_TRUE; 569 } 570 571 HAL_BOOL 572 ar9300_set_slot_time(struct ath_hal *ah, u_int us) 573 { 574 struct ath_hal_9300 *ahp = AH9300(ah); 575 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 576 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 577 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 578 return AH_FALSE; 579 } else { 580 /* convert to system clocks */ 581 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 582 ahp->ah_slot_time = us; 583 return AH_TRUE; 584 } 585 } 586 587 HAL_BOOL 588 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 589 { 590 struct ath_hal_9300 *ahp = AH9300(ah); 591 592 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 593 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 594 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 595 return AH_FALSE; 596 } else { 597 /* convert to system clocks */ 598 OS_REG_RMW_FIELD(ah, 599 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 600 ahp->ah_ack_timeout = us; 601 return AH_TRUE; 602 } 603 } 604 605 u_int 606 ar9300_get_ack_timeout(struct ath_hal *ah) 607 { 608 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 609 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 610 } 611 612 HAL_STATUS 613 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 614 u_int32_t next_start, HAL_QUIET_FLAG flag) 615 { 616 #define TU_TO_USEC(_tu) ((_tu) << 10) 617 HAL_STATUS status = HAL_EIO; 618 u_int32_t tsf = 0, j, next_start_us = 0; 619 if (flag & HAL_QUIET_ENABLE) { 620 for (j = 0; j < 2; j++) { 621 next_start_us = TU_TO_USEC(next_start); 622 tsf = OS_REG_READ(ah, AR_TSF_L32); 623 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 624 next_start_us += tsf; 625 } 626 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 627 next_start_us += 628 ah->ah_config.ah_sw_beacon_response_time; 629 } 630 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 631 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 632 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 633 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 634 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 635 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 636 status = HAL_OK; 637 break; 638 } 639 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 640 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 641 /* TSF shouldn't count twice or reg access is taking forever */ 642 HALASSERT(j < 1); 643 } 644 } else { 645 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 646 status = HAL_OK; 647 } 648 649 return status; 650 #undef TU_TO_USEC 651 } 652 653 //#ifdef ATH_SUPPORT_DFS 654 void 655 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 656 { 657 uint32_t reg1, reg2; 658 659 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 660 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 661 AH9300(ah)->ah_cac_quiet_enabled = enable; 662 663 if (enable) { 664 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 665 reg1 | AR_PCU_FORCE_QUIET_COLL); 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 667 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 668 } else { 669 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 670 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 671 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 672 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 673 } 674 } 675 //#endif /* ATH_SUPPORT_DFS */ 676 677 void 678 ar9300_set_pcu_config(struct ath_hal *ah) 679 { 680 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 681 } 682 683 HAL_STATUS 684 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 685 u_int32_t capability, u_int32_t *result) 686 { 687 struct ath_hal_9300 *ahp = AH9300(ah); 688 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 689 struct ar9300_ani_state *ani; 690 691 switch (type) { 692 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 693 switch (capability) { 694 case HAL_CIPHER_AES_CCM: 695 case HAL_CIPHER_AES_OCB: 696 case HAL_CIPHER_TKIP: 697 case HAL_CIPHER_WEP: 698 case HAL_CIPHER_MIC: 699 case HAL_CIPHER_CLR: 700 return HAL_OK; 701 default: 702 return HAL_ENOTSUPP; 703 } 704 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 705 switch (capability) { 706 case 0: /* hardware capability */ 707 return HAL_OK; 708 case 1: 709 return (ahp->ah_sta_id1_defaults & 710 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 711 default: 712 return HAL_ENOTSUPP; 713 } 714 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 715 switch (capability) { 716 case 0: /* hardware capability */ 717 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 718 case 1: /* current setting */ 719 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 720 HAL_ENXIO : HAL_OK; 721 default: 722 return HAL_ENOTSUPP; 723 } 724 case HAL_CAP_WME_TKIPMIC: 725 /* hardware can do TKIP MIC when WMM is turned on */ 726 return HAL_OK; 727 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 728 return HAL_OK; 729 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 730 switch (capability) { 731 case 0: /* hardware capability */ 732 return HAL_OK; 733 case 1: /* current setting */ 734 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 735 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 736 HAL_OK : HAL_ENXIO; 737 } 738 return HAL_EINVAL; 739 case HAL_CAP_TPC: 740 switch (capability) { 741 case 0: /* hardware capability */ 742 return HAL_OK; 743 case 1: 744 return ah->ah_config.ath_hal_desc_tpc ? 745 HAL_OK : HAL_ENXIO; 746 } 747 return HAL_OK; 748 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 749 return HAL_OK; 750 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 751 switch (capability) { 752 case 0: /* hardware capability */ 753 return HAL_OK; 754 case 1: 755 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 756 /* 757 * Owl and Merlin have problems in mcast key search. 758 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 759 * 26802 760 */ 761 return HAL_ENXIO; 762 } else { 763 return (ahp->ah_sta_id1_defaults & 764 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 765 } 766 } 767 return HAL_EINVAL; 768 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 769 switch (capability) { 770 case 0: /* hardware capability */ 771 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 772 case 1: 773 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 774 HAL_OK : HAL_ENXIO; 775 } 776 return HAL_EINVAL; 777 case HAL_CAP_RFSILENT: /* rfsilent support */ 778 if (capability == 3) { /* rfkill interrupt */ 779 /* 780 * XXX: Interrupt-based notification of RF Kill state 781 * changes not working yet. Report that this feature 782 * is not supported so that polling is used instead. 783 */ 784 return (HAL_ENOTSUPP); 785 } 786 return ath_hal_getcapability(ah, type, capability, result); 787 case HAL_CAP_4ADDR_AGGR: 788 return HAL_OK; 789 case HAL_CAP_BB_RIFS_HANG: 790 return HAL_ENOTSUPP; 791 case HAL_CAP_BB_DFS_HANG: 792 return HAL_ENOTSUPP; 793 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 794 /* Track chips that are known to have BB hangs related 795 * to rx_clear stuck low. 796 */ 797 return HAL_ENOTSUPP; 798 case HAL_CAP_MAC_HANG: 799 /* Track chips that are known to have MAC hangs. 800 */ 801 return HAL_OK; 802 case HAL_CAP_RIFS_RX_ENABLED: 803 /* Is RIFS RX currently enabled */ 804 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 805 #if 0 806 case HAL_CAP_ANT_CFG_2GHZ: 807 *result = p_cap->halNumAntCfg2Ghz; 808 return HAL_OK; 809 case HAL_CAP_ANT_CFG_5GHZ: 810 *result = p_cap->halNumAntCfg5Ghz; 811 return HAL_OK; 812 case HAL_CAP_RX_STBC: 813 *result = p_cap->hal_rx_stbc_support; 814 return HAL_OK; 815 case HAL_CAP_TX_STBC: 816 *result = p_cap->hal_tx_stbc_support; 817 return HAL_OK; 818 #endif 819 case HAL_CAP_LDPC: 820 *result = p_cap->halLDPCSupport; 821 return HAL_OK; 822 case HAL_CAP_DYNAMIC_SMPS: 823 return HAL_OK; 824 case HAL_CAP_DS: 825 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 826 (p_cap->halTxChainMask & 0x3) != 0x3 || 827 (p_cap->halRxChainMask & 0x3) != 0x3) ? 828 HAL_ENOTSUPP : HAL_OK; 829 case HAL_CAP_TS: 830 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 831 (p_cap->halTxChainMask & 0x7) != 0x7 || 832 (p_cap->halRxChainMask & 0x7) != 0x7) ? 833 HAL_ENOTSUPP : HAL_OK; 834 case HAL_CAP_OL_PWRCTRL: 835 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 836 HAL_OK : HAL_ENOTSUPP; 837 case HAL_CAP_CRDC: 838 #if ATH_SUPPORT_CRDC 839 return (AR_SREV_WASP(ah) && 840 ah->ah_config.ath_hal_crdc_enable) ? 841 HAL_OK : HAL_ENOTSUPP; 842 #else 843 return HAL_ENOTSUPP; 844 #endif 845 #if 0 846 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 850 *result = (u_int32_t)(-1); 851 return HAL_OK; 852 #endif 853 case HAL_CAP_BB_PANIC_WATCHDOG: 854 return HAL_OK; 855 case HAL_CAP_PHYRESTART_CLR_WAR: 856 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 857 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 858 { 859 return HAL_OK; 860 } 861 else 862 { 863 return HAL_ENOTSUPP; 864 } 865 case HAL_CAP_ENTERPRISE_MODE: 866 *result = ahp->ah_enterprise_mode >> 16; 867 /* 868 * WAR for EV 77658 - Add delimiters to first sub-frame when using 869 * RTS/CTS with aggregation and non-enterprise Osprey. 870 * 871 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 872 */ 873 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 874 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 875 AR_SREV_WASP_10(ah))) { 876 *result |= AH_ENT_RTSCTS_DELIM_WAR; 877 } 878 return HAL_OK; 879 case HAL_CAP_LDPCWAR: 880 /* WAR for RIFS+LDPC issue is required for all chips currently 881 * supported by ar9300 HAL. 882 */ 883 return HAL_OK; 884 case HAL_CAP_ENABLE_APM: 885 *result = p_cap->halApmEnable; 886 return HAL_OK; 887 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 888 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 889 case HAL_CAP_PCIE_LCR_OFFSET: 890 *result = p_cap->hal_pcie_lcr_offset; 891 return HAL_OK; 892 case HAL_CAP_SMARTANTENNA: 893 /* FIXME A request is pending with h/w team to add feature bit in 894 * caldata to detect if board has smart antenna or not, once added 895 * we need to fix his piece of code to read and return value without 896 * any compile flags 897 */ 898 #if UMAC_SUPPORT_SMARTANTENNA 899 /* enable smart antenna for Peacock, Wasp and scorpion 900 for future chips need to modify */ 901 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 902 return HAL_OK; 903 } else { 904 return HAL_ENOTSUPP; 905 } 906 #else 907 return HAL_ENOTSUPP; 908 #endif 909 910 #ifdef ATH_TRAFFIC_FAST_RECOVER 911 case HAL_CAP_TRAFFIC_FAST_RECOVER: 912 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 913 return HAL_OK; 914 } else { 915 return HAL_ENOTSUPP; 916 } 917 #endif 918 919 /* FreeBSD ANI */ 920 case HAL_CAP_INTMIT: /* interference mitigation */ 921 switch (capability) { 922 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 923 return HAL_OK; 924 case HAL_CAP_INTMIT_ENABLE: 925 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 926 HAL_OK : HAL_ENXIO; 927 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 928 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 929 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 930 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 931 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 932 ani = ar9300_ani_get_current_state(ah); 933 if (ani == AH_NULL) 934 return HAL_ENXIO; 935 switch (capability) { 936 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 937 case 2: *result = ani->ofdm_noise_immunity_level; break; 938 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 939 // case 4: *result = ani->cck_weak_sig_threshold; break; 940 case 5: *result = ani->firstep_level; break; 941 case 6: *result = ani->spur_immunity_level; break; 942 } 943 return HAL_OK; 944 } 945 return HAL_EINVAL; 946 case HAL_CAP_ENFORCE_TXOP: 947 if (capability == 0) 948 return (HAL_OK); 949 if (capability != 1) 950 return (HAL_ENOTSUPP); 951 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 952 return (HAL_OK); 953 case HAL_CAP_TOA_LOCATIONING: 954 if (capability == 0) 955 return HAL_OK; 956 if (capability == 2) { 957 *result = ar9300_read_loc_timer(ah); 958 return (HAL_OK); 959 } 960 return HAL_ENOTSUPP; 961 default: 962 return ath_hal_getcapability(ah, type, capability, result); 963 } 964 } 965 966 HAL_BOOL 967 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 968 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 969 { 970 struct ath_hal_9300 *ahp = AH9300(ah); 971 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 972 u_int32_t v; 973 974 switch (type) { 975 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 976 if (! p_cap->halTkipMicTxRxKeySupport) 977 return AH_FALSE; 978 979 if (setting) 980 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 981 else 982 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 983 984 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 985 return AH_TRUE; 986 987 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 988 if (setting) { 989 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 990 } else { 991 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 992 } 993 return AH_TRUE; 994 case HAL_CAP_DIVERSITY: 995 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 996 if (setting) { 997 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 998 } else { 999 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 1000 } 1001 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 1002 return AH_TRUE; 1003 case HAL_CAP_DIAG: /* hardware diagnostic support */ 1004 /* 1005 * NB: could split this up into virtual capabilities, 1006 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 1007 * seems worth the additional complexity. 1008 */ 1009 #ifdef AH_DEBUG 1010 AH_PRIVATE(ah)->ah_diagreg = setting; 1011 #else 1012 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 1013 #endif 1014 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 1015 return AH_TRUE; 1016 case HAL_CAP_TPC: 1017 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1018 return AH_TRUE; 1019 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1020 if (setting) { 1021 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1022 } else { 1023 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1024 } 1025 return AH_TRUE; 1026 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1027 if (p_cap->halTsfAddSupport) { 1028 if (setting) { 1029 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1030 } else { 1031 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1032 } 1033 return AH_TRUE; 1034 } 1035 return AH_FALSE; 1036 1037 /* FreeBSD interrupt mitigation / ANI */ 1038 case HAL_CAP_INTMIT: { /* interference mitigation */ 1039 /* This maps the public ANI commands to the internal ANI commands */ 1040 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1041 static const HAL_ANI_CMD cmds[] = { 1042 HAL_ANI_PRESENT, 1043 HAL_ANI_MODE, 1044 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1045 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1046 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1047 HAL_ANI_FIRSTEP_LEVEL, 1048 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1049 }; 1050 #define N(a) (sizeof(a) / sizeof(a[0])) 1051 return capability < N(cmds) ? 1052 ar9300_ani_control(ah, cmds[capability], setting) : 1053 AH_FALSE; 1054 #undef N 1055 } 1056 1057 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1058 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1059 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1060 return AH_TRUE; 1061 1062 case HAL_CAP_ENFORCE_TXOP: 1063 if (capability != 1) 1064 return AH_FALSE; 1065 if (setting) { 1066 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 1067 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1068 } else { 1069 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 1070 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1071 } 1072 return AH_TRUE; 1073 1074 case HAL_CAP_TOA_LOCATIONING: 1075 if (capability == 0) 1076 return AH_TRUE; 1077 if (capability == 1) { 1078 ar9300_update_loc_ctl_reg(ah, setting); 1079 return AH_TRUE; 1080 } 1081 return AH_FALSE; 1082 1083 #define owl_get_ntxchains(_txchainmask) \ 1084 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + \ 1085 (_txchainmask & 1)) 1086 1087 case HAL_CAP_RX_CHAINMASK: 1088 setting &= ar9300_eeprom_get(ahp, EEP_RX_MASK); 1089 p_cap->halRxChainMask = setting; 1090 p_cap->halRxStreams = owl_get_ntxchains(setting); 1091 if (p_cap->halRxStreams > 3) 1092 p_cap->halRxStreams = 3; 1093 else if (p_cap->halRxStreams < 1) 1094 p_cap->halRxStreams = 1; 1095 return AH_TRUE; 1096 1097 case HAL_CAP_TX_CHAINMASK: 1098 setting &= ar9300_eeprom_get(ahp, EEP_TX_MASK); 1099 p_cap->halTxChainMask = setting; 1100 p_cap->halTxStreams = owl_get_ntxchains(setting); 1101 if (p_cap->halTxStreams > 3) 1102 p_cap->halTxStreams = 3; 1103 else if (p_cap->halTxStreams < 1) 1104 p_cap->halTxStreams = 1; 1105 return AH_TRUE; 1106 1107 #undef owl_get_ntxchains 1108 1109 /* fall thru... */ 1110 default: 1111 return ath_hal_setcapability(ah, type, capability, setting, status); 1112 } 1113 } 1114 1115 #ifdef AH_DEBUG 1116 static void 1117 ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1118 { 1119 u_int32_t i = 0; 1120 1121 /* Read 0x80d0 to trigger pcie analyzer */ 1122 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1123 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1124 1125 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1126 struct ath_hal_9300 *ahp = AH9300(ah); 1127 u_int32_t tf, rf, rc, cc; 1128 1129 tf = OS_REG_READ(ah, AR_TFCNT); 1130 rf = OS_REG_READ(ah, AR_RFCNT); 1131 rc = OS_REG_READ(ah, AR_RCCNT); 1132 cc = OS_REG_READ(ah, AR_CCCNT); 1133 1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1135 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1136 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1137 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1138 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1139 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1140 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1141 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1142 1143 ahp->last_tf = tf; 1144 ahp->last_rf = rf; 1145 ahp->last_rc = rc; 1146 ahp->last_cc = cc; 1147 1148 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1149 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1150 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1151 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1152 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1153 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1154 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1155 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1156 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1157 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1158 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1159 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1160 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1161 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1162 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1163 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1164 } 1165 1166 if (args & HAL_DIAG_PRINT_REG_ALL) { 1167 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1168 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1169 i, OS_REG_READ(ah, i)); 1170 } 1171 1172 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1173 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1174 i, OS_REG_READ(ah, i)); 1175 } 1176 1177 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1178 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1179 1180 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1181 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1182 1183 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1184 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1185 i, OS_REG_READ(ah, i)); 1186 } 1187 1188 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1189 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1190 i, OS_REG_READ(ah, i)); 1191 } 1192 1193 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1194 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1195 i, OS_REG_READ(ah, i)); 1196 } 1197 1198 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1199 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1200 i, OS_REG_READ(ah, i)); 1201 } 1202 1203 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1204 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1205 i, OS_REG_READ(ah, i)); 1206 } 1207 1208 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1209 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1210 i, OS_REG_READ(ah, i)); 1211 } 1212 1213 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1214 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1215 i, OS_REG_READ(ah, i)); 1216 } 1217 1218 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1219 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1220 i, OS_REG_READ(ah, i)); 1221 } 1222 1223 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1224 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1225 i, OS_REG_READ(ah, i)); 1226 } 1227 1228 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1229 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1230 i, OS_REG_READ(ah, i)); 1231 } 1232 1233 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1234 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1235 i, OS_REG_READ(ah, i)); 1236 } 1237 } 1238 } 1239 #endif 1240 1241 HAL_BOOL 1242 ar9300_get_diag_state(struct ath_hal *ah, int request, 1243 const void *args, u_int32_t argsize, 1244 void **result, u_int32_t *resultsize) 1245 { 1246 struct ath_hal_9300 *ahp = AH9300(ah); 1247 struct ar9300_ani_state *ani; 1248 1249 (void) ahp; 1250 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1251 return AH_TRUE; 1252 } 1253 switch (request) { 1254 #ifdef AH_PRIVATE_DIAG 1255 case HAL_DIAG_EEPROM: 1256 *result = &ahp->ah_eeprom; 1257 *resultsize = sizeof(ar9300_eeprom_t); 1258 return AH_TRUE; 1259 1260 #if 0 /* XXX - TODO */ 1261 case HAL_DIAG_EEPROM_EXP_11A: 1262 case HAL_DIAG_EEPROM_EXP_11B: 1263 case HAL_DIAG_EEPROM_EXP_11G: 1264 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1265 *result = pe->p_channels; 1266 *resultsize = (*result == AH_NULL) ? 0 : 1267 roundup(sizeof(u_int16_t) * pe->num_channels, 1268 sizeof(u_int32_t)) + 1269 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1270 return AH_TRUE; 1271 #endif 1272 case HAL_DIAG_RFGAIN: 1273 *result = &ahp->ah_gain_values; 1274 *resultsize = sizeof(GAIN_VALUES); 1275 return AH_TRUE; 1276 case HAL_DIAG_RFGAIN_CURSTEP: 1277 *result = (void *) ahp->ah_gain_values.curr_step; 1278 *resultsize = (*result == AH_NULL) ? 1279 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1280 return AH_TRUE; 1281 #if 0 /* XXX - TODO */ 1282 case HAL_DIAG_PCDAC: 1283 *result = ahp->ah_pcdac_table; 1284 *resultsize = ahp->ah_pcdac_table_size; 1285 return AH_TRUE; 1286 #endif 1287 case HAL_DIAG_ANI_CURRENT: 1288 1289 ani = ar9300_ani_get_current_state(ah); 1290 if (ani == AH_NULL) 1291 return AH_FALSE; 1292 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1293 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1294 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1295 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1296 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1297 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1298 ahp->ext_ani_state.mrcCck = !! ani->mrc_cck_off; 1299 ahp->ext_ani_state.cckNoiseImmunityLevel = ani->cck_noise_immunity_level; 1300 1301 ahp->ext_ani_state.listenTime = ani->listen_time; 1302 1303 *result = &ahp->ext_ani_state; 1304 *resultsize = sizeof(ahp->ext_ani_state); 1305 #if 0 1306 *result = ar9300_ani_get_current_state(ah); 1307 *resultsize = (*result == AH_NULL) ? 1308 0 : sizeof(struct ar9300_ani_state); 1309 #endif 1310 return AH_TRUE; 1311 case HAL_DIAG_ANI_STATS: 1312 *result = ar9300_ani_get_current_stats(ah); 1313 *resultsize = (*result == AH_NULL) ? 1314 0 : sizeof(HAL_ANI_STATS); 1315 return AH_TRUE; 1316 case HAL_DIAG_ANI_CMD: 1317 { 1318 HAL_ANI_CMD savefunc = ahp->ah_ani_function; 1319 if (argsize != 2*sizeof(u_int32_t)) { 1320 return AH_FALSE; 1321 } 1322 /* temporarly allow all functions so we can override */ 1323 ahp->ah_ani_function = HAL_ANI_ALL; 1324 ar9300_ani_control( 1325 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1326 ahp->ah_ani_function = savefunc; 1327 return AH_TRUE; 1328 } 1329 #if 0 1330 case HAL_DIAG_TXCONT: 1331 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1332 return AH_TRUE; 1333 #endif /* 0 */ 1334 #endif /* AH_PRIVATE_DIAG */ 1335 case HAL_DIAG_CHANNELS: 1336 #if 0 1337 *result = &(ahp->ah_priv.ah_channels[0]); 1338 *resultsize = 1339 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1340 #endif 1341 return AH_TRUE; 1342 #ifdef AH_DEBUG 1343 case HAL_DIAG_PRINT_REG: 1344 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1345 return AH_TRUE; 1346 #endif 1347 default: 1348 break; 1349 } 1350 1351 return AH_FALSE; 1352 } 1353 1354 void 1355 ar9300_dma_reg_dump(struct ath_hal *ah) 1356 { 1357 #ifdef AH_DEBUG 1358 #define NUM_DMA_DEBUG_REGS 8 1359 #define NUM_QUEUES 10 1360 1361 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1362 int qcu_offset = 0, dcu_offset = 0; 1363 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1364 int i, j, k; 1365 int16_t nfarray[HAL_NUM_NF_READINGS]; 1366 #ifdef ATH_NF_PER_CHAN 1367 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1368 #endif /* ATH_NF_PER_CHAN */ 1369 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1370 1371 /* selecting DMA OBS 8 */ 1372 OS_REG_WRITE(ah, AR_MACMISC, 1373 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1374 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1375 1376 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1377 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1378 if (i % 4 == 0) { 1379 ath_hal_printf(ah, "\n"); 1380 } 1381 1382 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1383 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1384 } 1385 1386 ath_hal_printf(ah, "\n\n"); 1387 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1388 1389 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1390 if (i == 8) { 1391 /* only 8 QCU entries in val[0] */ 1392 qcu_offset = 0; 1393 qcu_base++; 1394 } 1395 1396 if (i == 6) { 1397 /* only 6 DCU entries in val[4] */ 1398 dcu_offset = 0; 1399 dcu_base++; 1400 } 1401 1402 ath_hal_printf(ah, 1403 "%2d %2x %1x %2x %2x\n", 1404 i, 1405 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1406 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1407 val[2] & (0x7 << (i * 3)) >> (i * 3), 1408 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1409 } 1410 1411 ath_hal_printf(ah, "\n"); 1412 ath_hal_printf(ah, 1413 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1414 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1415 ath_hal_printf(ah, 1416 "qcu_complete state: %2x dcu_complete state: %2x\n", 1417 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1418 ath_hal_printf(ah, 1419 "dcu_arb state: %2x dcu_fp state: %2x\n", 1420 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1421 ath_hal_printf(ah, 1422 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1423 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1424 ath_hal_printf(ah, 1425 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1426 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1427 ath_hal_printf(ah, 1428 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1429 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1430 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1431 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1432 1433 ar9300_upload_noise_floor(ah, 1, nfarray); 1434 ath_hal_printf(ah, "2G:\n"); 1435 ath_hal_printf(ah, "Min CCA Out:\n"); 1436 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1437 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1438 nfarray[0], nfarray[1], nfarray[2]); 1439 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1440 nfarray[3], nfarray[4], nfarray[5]); 1441 1442 ar9300_upload_noise_floor(ah, 0, nfarray); 1443 ath_hal_printf(ah, "5G:\n"); 1444 ath_hal_printf(ah, "Min CCA Out:\n"); 1445 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1446 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1447 nfarray[0], nfarray[1], nfarray[2]); 1448 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1449 nfarray[3], nfarray[4], nfarray[5]); 1450 1451 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1452 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1453 ((i < 3) ? "Control " : "Extension "), i%3); 1454 for (j = 0, k = h->base.curr_index; 1455 j < HAL_NF_CAL_HIST_LEN_FULL; 1456 j++, k++) { 1457 ath_hal_printf(ah, "Element %d: %d\n", 1458 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1459 } 1460 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1461 } 1462 1463 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1464 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1465 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1466 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1467 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1468 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1469 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1470 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1471 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1472 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1473 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1474 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1475 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1476 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1477 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1478 reg = OS_REG_READ(ah, AR_PHY_AGC); 1479 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1480 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1481 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1482 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1483 MS(reg, AR_PHY_AGC_COARSE_LOW), 1484 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1485 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1486 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1487 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1488 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1489 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1490 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1491 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1492 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1493 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1494 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1495 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1496 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1497 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1498 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1499 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1500 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1501 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1502 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1503 1504 1505 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1506 reg = OS_REG_READ(ah, 0xa360); 1507 reg &= ~0x00800000; 1508 OS_REG_WRITE(ah, 0xa360, reg); 1509 1510 /* Step 2a: Set register 0xa364 to 0x1000 */ 1511 reg = 0x1000; 1512 OS_REG_WRITE(ah, 0xa364, reg); 1513 1514 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1515 reg = OS_REG_READ(ah, 0x9c20); 1516 reg &= 0x0003ffff; 1517 ath_hal_printf(ah, 1518 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1519 __func__, reg); 1520 1521 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1522 reg = OS_REG_READ(ah, 0xa360); 1523 reg &= ~0x00800000; 1524 OS_REG_WRITE(ah, 0xa360, reg); 1525 1526 /* Step 2b: Set register 0xa364 to 0x1400 */ 1527 reg = 0x1400; 1528 OS_REG_WRITE(ah, 0xa364, reg); 1529 1530 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1531 reg = OS_REG_READ(ah, 0x9c20); 1532 reg &= 0x0003ffff; 1533 ath_hal_printf(ah, 1534 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1535 __func__, reg); 1536 1537 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1538 reg = OS_REG_READ(ah, 0xa360); 1539 reg &= ~0x00800000; 1540 OS_REG_WRITE(ah, 0xa360, reg); 1541 1542 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1543 reg = 0x3c00; 1544 OS_REG_WRITE(ah, 0xa364, reg); 1545 1546 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1547 reg = OS_REG_READ(ah, 0x9c20); 1548 reg &= 0x0003ffff; 1549 ath_hal_printf(ah, 1550 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1551 __func__, reg); 1552 1553 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1554 reg = OS_REG_READ(ah, 0xa360); 1555 reg &= ~0x001040000; 1556 OS_REG_WRITE(ah, 0xa360, reg); 1557 1558 /* Step 2d: Set register 0xa364 to 0x5005D */ 1559 reg = 0x5005D; 1560 OS_REG_WRITE(ah, 0xa364, reg); 1561 1562 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1563 reg = OS_REG_READ(ah, 0xa368); 1564 reg &= 0x0003ffff; 1565 ath_hal_printf(ah, 1566 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1567 __func__, reg); 1568 1569 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1570 reg = OS_REG_READ(ah, 0xa360); 1571 reg &= ~0x001040000; 1572 OS_REG_WRITE(ah, 0xa360, reg); 1573 1574 /* Step 2e: Set register 0xa364 to 0x7005D */ 1575 reg = 0x7005D; 1576 OS_REG_WRITE(ah, 0xa364, reg); 1577 1578 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1579 reg = OS_REG_READ(ah, 0xa368); 1580 reg &= 0x0003ffff; 1581 ath_hal_printf(ah, 1582 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1583 __func__, reg); 1584 1585 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1586 reg = OS_REG_READ(ah, 0xa360); 1587 reg &= ~0x001000000; 1588 reg |= 0x40000; 1589 OS_REG_WRITE(ah, 0xa360, reg); 1590 1591 /* Step 2f: Set register 0xa364 to 0x3005D */ 1592 reg = 0x3005D; 1593 OS_REG_WRITE(ah, 0xa364, reg); 1594 1595 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1596 reg = OS_REG_READ(ah, 0xa368); 1597 reg &= 0x0003ffff; 1598 ath_hal_printf(ah, 1599 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1600 __func__, reg); 1601 1602 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1603 reg = OS_REG_READ(ah, 0xa360); 1604 reg &= ~0x001000000; 1605 reg |= 0x40000; 1606 OS_REG_WRITE(ah, 0xa360, reg); 1607 1608 /* Step 2g: Set register 0xa364 to 0x6005D */ 1609 reg = 0x6005D; 1610 OS_REG_WRITE(ah, 0xa364, reg); 1611 1612 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1613 reg = OS_REG_READ(ah, 0xa368); 1614 reg &= 0x0003ffff; 1615 ath_hal_printf(ah, 1616 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1617 __func__, reg); 1618 #endif /* AH_DEBUG */ 1619 } 1620 1621 /* 1622 * Return the busy for rx_frame, rx_clear, and tx_frame 1623 */ 1624 u_int32_t 1625 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1626 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1627 { 1628 struct ath_hal_9300 *ahp = AH9300(ah); 1629 u_int32_t good = 1; 1630 1631 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1632 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1633 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1634 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1635 1636 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1637 /* 1638 * Cycle counter wrap (or initial call); it's not possible 1639 * to accurately calculate a value because the registers 1640 * right shift rather than wrap--so punt and return 0. 1641 */ 1642 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1643 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1644 good = 0; 1645 } else { 1646 u_int32_t cc_d = cc - ahp->ah_cycles; 1647 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1648 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1649 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1650 1651 if (cc_d != 0) { 1652 *rxc_pcnt = rc_d * 100 / cc_d; 1653 *rxf_pcnt = rf_d * 100 / cc_d; 1654 *txf_pcnt = tf_d * 100 / cc_d; 1655 } else { 1656 good = 0; 1657 } 1658 } 1659 1660 ahp->ah_cycles = cc; 1661 ahp->ah_rx_frame = rf; 1662 ahp->ah_rx_clear = rc; 1663 ahp->ah_tx_frame = tf; 1664 1665 return good; 1666 } 1667 1668 /* 1669 * Return approximation of extension channel busy over an time interval 1670 * 0% (clear) -> 100% (busy) 1671 * -1 for invalid estimate 1672 */ 1673 uint32_t 1674 ar9300_get_11n_ext_busy(struct ath_hal *ah) 1675 { 1676 /* 1677 * Overflow condition to check before multiplying to get % 1678 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1679 */ 1680 #define OVERFLOW_LIMIT 0x28F5C28 1681 #define ERROR_CODE -1 1682 1683 struct ath_hal_9300 *ahp = AH9300(ah); 1684 u_int32_t busy = 0; /* percentage */ 1685 int8_t busyper = 0; 1686 u_int32_t cycle_count, ctl_busy, ext_busy; 1687 1688 /* cycle_count will always be the first to wrap; therefore, read it last 1689 * This sequence of reads is not atomic, and MIB counter wrap 1690 * could happen during it ? 1691 */ 1692 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1693 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1694 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1695 1696 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1697 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1698 { 1699 /* 1700 * Cycle counter wrap (or initial call); it's not possible 1701 * to accurately calculate a value because the registers 1702 * right shift rather than wrap--so punt and return 0. 1703 */ 1704 busyper = ERROR_CODE; 1705 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1706 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1707 } else { 1708 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1709 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1710 1711 /* 1712 * Compute extension channel busy percentage 1713 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1714 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1715 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1716 * and shift necessitated by large ext_busy_delta. 1717 * Due to timing difference to read the registers and counter overflow, 1718 * it may still happen that cycle_delta >> 7 = 0. 1719 * 1720 */ 1721 if (cycle_delta) { 1722 if (ext_busy_delta > OVERFLOW_LIMIT) { 1723 if (cycle_delta >> 7) { 1724 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1725 } else { 1726 busyper = ERROR_CODE; 1727 } 1728 } else { 1729 busy = (ext_busy_delta * 100) / cycle_delta; 1730 } 1731 } else { 1732 busyper = ERROR_CODE; 1733 } 1734 1735 if (busy > 100) { 1736 busy = 100; 1737 } 1738 if ( busyper != ERROR_CODE ) { 1739 busyper = busy; 1740 } 1741 } 1742 1743 ahp->ah_cycle_count = cycle_count; 1744 ahp->ah_ctl_busy = ctl_busy; 1745 ahp->ah_ext_busy = ext_busy; 1746 1747 return busyper; 1748 #undef OVERFLOW_LIMIT 1749 #undef ERROR_CODE 1750 } 1751 1752 /* BB Panic Watchdog declarations */ 1753 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1754 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1755 1756 void 1757 ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1758 { 1759 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1760 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1761 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1762 u_int32_t val, idle_count; 1763 1764 if (idle_tmo_ms != 0) { 1765 /* enable IRQ, disable chip-reset for BB panic */ 1766 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1767 AR_PHY_BB_PANIC_CNTL2_MASK; 1768 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1769 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1770 /* bound limit to 10 secs */ 1771 if (idle_tmo_ms > 10000) { 1772 idle_tmo_ms = 10000; 1773 } 1774 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1775 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1776 } else { 1777 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1778 } 1779 /* 1780 * enable panic in non-IDLE mode, 1781 * disable in IDLE mode, 1782 * set idle time-out 1783 */ 1784 1785 // EV92527 : Enable IDLE mode panic 1786 1787 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1788 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1789 AR_PHY_BB_PANIC_IDLE_ENABLE | 1790 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1791 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1792 } else { 1793 /* disable IRQ, disable chip-reset for BB panic */ 1794 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1795 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1796 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1797 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1798 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1799 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1800 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1801 } 1802 1803 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1804 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1805 #undef HAL_BB_PANIC_IDLE_TIME_OUT 1806 } 1807 1808 1809 void 1810 ar9300_handle_bb_panic(struct ath_hal *ah) 1811 { 1812 u_int32_t status; 1813 /* 1814 * we want to avoid printing in ISR context so we save 1815 * panic watchdog status to be printed later in DPC context 1816 */ 1817 AH9300(ah)->ah_bb_panic_last_status = status = 1818 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1819 /* 1820 * panic watchdog timer should reset on status read 1821 * but to make sure we write 0 to the watchdog status bit 1822 */ 1823 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1824 } 1825 1826 int 1827 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1828 { 1829 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1830 1831 /* 1832 * For signature 04000539 do not print anything. 1833 * This is a very common occurence as a compromise between 1834 * BB Panic and AH_FALSE detects (EV71009). It indicates 1835 * radar hang, which can be cleared by reprogramming 1836 * radar related register and does not requre a chip reset 1837 */ 1838 1839 /* Suppress BB Status mesg following signature */ 1840 switch (bb_panic->status) { 1841 case 0x04000539: 1842 case 0x04008009: 1843 case 0x04000b09: 1844 case 0x1300000a: 1845 return -1; 1846 } 1847 1848 bb_panic->tsf = ar9300_get_tsf32(ah); 1849 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1850 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1851 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1852 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1853 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1854 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1855 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1856 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1857 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1858 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1859 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1860 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1861 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1862 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1863 &bb_panic->rxc_pcnt, 1864 &bb_panic->rxf_pcnt, 1865 &bb_panic->txf_pcnt); 1866 1867 if (ah->ah_config.ath_hal_show_bb_panic) { 1868 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1869 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1870 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1871 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1872 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1873 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1874 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1875 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1876 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1877 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1878 bb_panic->phy_gen_ctrl); 1879 if (bb_panic->cycles) { 1880 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1881 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1882 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1883 } 1884 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1885 } 1886 1887 return 0; //The returned data will be stored for athstats to retrieve it 1888 } 1889 1890 /* set the reason for HAL reset */ 1891 void 1892 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1893 { 1894 AH9300(ah)->ah_reset_reason = resetreason; 1895 } 1896 1897 /* 1898 * Configure 20/40 operation 1899 * 1900 * 20/40 = joint rx clear (control and extension) 1901 * 20 = rx clear (control) 1902 * 1903 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1904 * when changing from 20/40 => 20 only 1905 */ 1906 void 1907 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1908 { 1909 u_int32_t macmode; 1910 1911 /* Configure MAC for 20/40 operation */ 1912 if (mode == HAL_HT_MACMODE_2040 && 1913 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1914 macmode = AR_2040_JOINED_RX_CLEAR; 1915 } else { 1916 macmode = 0; 1917 } 1918 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1919 } 1920 1921 /* 1922 * Get Rx clear (control/extension channel) 1923 * 1924 * Returns active low (busy) for ctrl/ext channel 1925 * Owl 2.0 1926 */ 1927 HAL_HT_RXCLEAR 1928 ar9300_get_11n_rx_clear(struct ath_hal *ah) 1929 { 1930 HAL_HT_RXCLEAR rxclear = 0; 1931 u_int32_t val; 1932 1933 val = OS_REG_READ(ah, AR_DIAG_SW); 1934 1935 /* control channel */ 1936 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1937 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1938 } 1939 /* extension channel */ 1940 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1941 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1942 } 1943 return rxclear; 1944 } 1945 1946 /* 1947 * Set Rx clear (control/extension channel) 1948 * 1949 * Useful for forcing the channel to appear busy for 1950 * debugging/diagnostics 1951 * Owl 2.0 1952 */ 1953 void 1954 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1955 { 1956 /* control channel */ 1957 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1958 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1959 } else { 1960 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1961 } 1962 /* extension channel */ 1963 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1964 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1965 } else { 1966 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1967 } 1968 } 1969 1970 1971 /* 1972 * HAL support code for force ppm tracking workaround. 1973 */ 1974 1975 u_int32_t 1976 ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1977 { 1978 u_int32_t retval; 1979 u_int32_t off1; 1980 u_int32_t off2; 1981 1982 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1983 off1 = 0x2000; 1984 off2 = 0x1000; 1985 } else { 1986 off1 = 0x1000; 1987 off2 = 0x2000; 1988 } 1989 1990 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1991 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1992 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1993 1994 return retval; 1995 } 1996 1997 u_int32_t 1998 ar9300_ppm_force(struct ath_hal *ah) 1999 { 2000 u_int32_t data_fine; 2001 u_int32_t data4; 2002 //u_int32_t off1; 2003 //u_int32_t off2; 2004 HAL_BOOL signed_val = AH_FALSE; 2005 2006 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 2007 // off1 = 0x2000; 2008 // off2 = 0x1000; 2009 // } else { 2010 // off1 = 0x1000; 2011 // off2 = 0x2000; 2012 // } 2013 data_fine = 2014 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 2015 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 2016 2017 /* 2018 * bit [11-0] is new ppm value. bit 11 is the signed bit. 2019 * So check value from bit[10:0]. 2020 * Now get the abs val of the ppm value read in bit[0:11]. 2021 * After that do bound check on abs value. 2022 * if value is off limit, CAP the value and and restore signed bit. 2023 */ 2024 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 2025 { 2026 /* get the positive value */ 2027 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 2028 signed_val = AH_TRUE; 2029 } 2030 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 2031 { 2032 HALDEBUG(ah, HAL_DEBUG_REGIO, 2033 "%s Correcting ppm out of range %x\n", 2034 __func__, (data_fine & 0x7ff)); 2035 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 2036 } 2037 /* 2038 * Restore signed value if changed above. 2039 * Use typecast to avoid compilation errors 2040 */ 2041 if (signed_val) { 2042 data_fine = (-(int32_t)data_fine) & 2043 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 2044 } 2045 2046 /* write value */ 2047 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 2048 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2049 OS_REG_WRITE(ah, AR_PHY_TIMING2, 2050 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 2051 2052 return data_fine; 2053 } 2054 2055 void 2056 ar9300_ppm_un_force(struct ath_hal *ah) 2057 { 2058 u_int32_t data4; 2059 2060 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 2061 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 2062 } 2063 2064 u_int32_t 2065 ar9300_ppm_arm_trigger(struct ath_hal *ah) 2066 { 2067 u_int32_t val; 2068 u_int32_t ret; 2069 2070 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2071 ret = OS_REG_READ(ah, AR_TSF_L32); 2072 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2073 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2074 2075 /* return low word of TSF at arm time */ 2076 return ret; 2077 } 2078 2079 int 2080 ar9300_ppm_get_trigger(struct ath_hal *ah) 2081 { 2082 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2083 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2084 { 2085 /* has not triggered yet, return AH_FALSE */ 2086 return 0; 2087 } 2088 2089 /* else triggered, return AH_TRUE */ 2090 return 1; 2091 } 2092 2093 void 2094 ar9300_mark_phy_inactive(struct ath_hal *ah) 2095 { 2096 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2097 } 2098 2099 /* DEBUG */ 2100 u_int32_t 2101 ar9300_ppm_get_force_state(struct ath_hal *ah) 2102 { 2103 return 2104 OS_REG_READ(ah, AR_PHY_TIMING2) & 2105 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2106 } 2107 2108 /* 2109 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2110 */ 2111 HAL_BOOL 2112 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2113 { 2114 /* 2115 * XXX FreeBSD todo: reimplement this 2116 */ 2117 #if 0 2118 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2119 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2120 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2121 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2122 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2123 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2124 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2125 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2126 #endif 2127 return AH_FALSE; 2128 } 2129 2130 void 2131 ar9300_clear_mib_counters(struct ath_hal *ah) 2132 { 2133 u_int32_t reg_val; 2134 2135 reg_val = OS_REG_READ(ah, AR_MIBC); 2136 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2137 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2138 } 2139 2140 2141 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2142 HAL_BOOL 2143 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2144 { 2145 struct ath_hal_9300 *ahp = AH9300(ah); 2146 HAL_CHANNEL_INTERNAL *ichan = 2147 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2148 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2149 u_int32_t tmp = 0; 2150 2151 if (enable) { 2152 if (ahp->ah_rifs_enabled == AH_TRUE) { 2153 return AH_TRUE; 2154 } 2155 2156 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2157 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2158 ahp->ah_rifs_reg[1]); 2159 2160 ahp->ah_rifs_enabled = AH_TRUE; 2161 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2162 } else { 2163 if (ahp->ah_rifs_enabled == AH_TRUE) { 2164 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2165 AR_PHY_SEARCH_START_DELAY); 2166 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2167 } 2168 /* Change rifs init delay to 0 */ 2169 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2170 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2171 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2172 if (is_chan_2g) { 2173 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2174 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2175 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2176 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2177 } 2178 } else { 2179 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2180 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2181 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2182 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2183 } 2184 } 2185 2186 ahp->ah_rifs_enabled = AH_FALSE; 2187 } 2188 return AH_TRUE; 2189 2190 } /* ar9300_set_rifs_delay () */ 2191 2192 /* Set the current RIFS Rx setting */ 2193 HAL_BOOL 2194 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2195 { 2196 /* Non-Owl 11n chips */ 2197 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2198 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2199 return ar9300_set_rifs_delay(ah, enable); 2200 } 2201 return AH_FALSE; 2202 } 2203 2204 return AH_TRUE; 2205 } /* ar9300_set_11n_rx_rifs () */ 2206 2207 static hal_mac_hangs_t 2208 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2209 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2210 { 2211 int i = 0; 2212 hal_mac_hangs_t found_hangs = 0; 2213 2214 if (hangs & dcu_chain_state) { 2215 for (i = 0; i < 6; i++) { 2216 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2217 hang_check.dcu_chain_state) 2218 { 2219 found_hangs |= dcu_chain_state; 2220 *dcu_chain = i; 2221 } 2222 } 2223 for (i = 0; i < 4; i++) { 2224 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2225 hang_check.dcu_chain_state) 2226 { 2227 found_hangs |= dcu_chain_state; 2228 *dcu_chain = i + 6; 2229 } 2230 } 2231 } 2232 2233 if (hangs & dcu_complete_state) { 2234 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2235 found_hangs |= dcu_complete_state; 2236 } 2237 } 2238 2239 return found_hangs; 2240 2241 } /* end - ar9300_compare_dbg_hang */ 2242 2243 #define NUM_STATUS_READS 50 2244 HAL_BOOL 2245 ar9300_detect_mac_hang(struct ath_hal *ah) 2246 { 2247 struct ath_hal_9300 *ahp = AH9300(ah); 2248 mac_dbg_regs_t mac_dbg; 2249 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2250 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2251 int i = 0; 2252 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2253 2254 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2255 return AH_FALSE; 2256 } 2257 2258 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2259 2260 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2261 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2262 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2263 2264 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2265 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2266 mac_dbg.dma_dbg_6); 2267 2268 if (hang_sig1 != 2269 ar9300_compare_dbg_hang(ah, mac_dbg, 2270 hang_sig1_val, hang_sig1, &dcu_chain)) 2271 { 2272 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2273 return AH_FALSE; 2274 } 2275 2276 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2277 shift_val *= 5; 2278 2279 for (i = 1; i <= NUM_STATUS_READS; i++) { 2280 if (dcu_chain < 6) { 2281 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2282 current_dcu_chain_state = 2283 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2284 } else { 2285 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2286 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2287 } 2288 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2289 2290 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2291 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2292 return AH_FALSE; 2293 } 2294 } 2295 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2296 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2297 ahp->ah_hang[MAC_HANG_SIG1]++; 2298 return AH_TRUE; 2299 2300 } /* end - ar9300_detect_mac_hang */ 2301 2302 /* Determine if the baseband is hung by reading the Observation Bus Register */ 2303 HAL_BOOL 2304 ar9300_detect_bb_hang(struct ath_hal *ah) 2305 { 2306 #define N(a) (sizeof(a) / sizeof(a[0])) 2307 struct ath_hal_9300 *ahp = AH9300(ah); 2308 u_int32_t hang_sig = 0; 2309 int i = 0; 2310 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2311 * 2312 * 4 known BB hang signatures - 2313 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2314 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2315 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2316 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2317 * Rx State (bits 20-24) is 0x7. 2318 */ 2319 hal_hw_hang_check_t hang_list [] = 2320 { 2321 /* Offset Reg Value Reg Mask Hang Offset */ 2322 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2323 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2324 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2325 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2326 }; 2327 2328 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2329 HAL_DFS_BB_HANG_WAR | 2330 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2331 return AH_FALSE; 2332 } 2333 2334 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2335 for (i = 1; i <= NUM_STATUS_READS; i++) { 2336 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2337 return AH_FALSE; 2338 } 2339 } 2340 2341 for (i = 0; i < N(hang_list); i++) { 2342 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2343 ahp->ah_hang[hang_list[i].hang_offset]++; 2344 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2345 "sig3count=%d sig4count=%d\n", __func__, 2346 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2347 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2348 return AH_TRUE; 2349 } 2350 } 2351 2352 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2353 "<0x806c>=0x%x\n", __func__, hang_sig); 2354 2355 return AH_FALSE; 2356 2357 #undef N 2358 } /* end - ar9300_detect_bb_hang () */ 2359 2360 #undef NUM_STATUS_READS 2361 2362 HAL_STATUS 2363 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2364 { 2365 struct ath_hal_9300 *ahp = AH9300(ah); 2366 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2367 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2368 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2369 u_int16_t ant_config; 2370 u_int32_t hal_num_ant_config; 2371 2372 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2373 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2374 2375 if (cfg < hal_num_ant_config) { 2376 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2377 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2378 return HAL_OK; 2379 } 2380 } 2381 2382 return HAL_EINVAL; 2383 } 2384 2385 /* 2386 * Functions to get/set DCS mode 2387 */ 2388 void 2389 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2390 { 2391 AH9300(ah)->ah_dcs_enable = mode; 2392 } 2393 2394 u_int32_t 2395 ar9300_get_dcs_mode(struct ath_hal *ah) 2396 { 2397 return AH9300(ah)->ah_dcs_enable; 2398 } 2399 2400 #if ATH_BT_COEX 2401 void 2402 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2403 { 2404 struct ath_hal_9300 *ahp = AH9300(ah); 2405 2406 ahp->ah_bt_module = btinfo->bt_module; 2407 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2408 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2409 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2410 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2411 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2412 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2413 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2414 } 2415 2416 void 2417 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2418 { 2419 struct ath_hal_9300 *ahp = AH9300(ah); 2420 HAL_BOOL rx_clear_polarity; 2421 2422 /* 2423 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2424 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2425 */ 2426 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2427 2428 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2429 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2430 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2431 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2432 SM(btconf->bt_mode, AR_BT_MODE) | 2433 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2434 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2435 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2436 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2437 2438 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2439 2440 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2441 /* Enable ACK to go out even though BT has higher priority. */ 2442 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2443 } 2444 } 2445 2446 void 2447 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2448 { 2449 struct ath_hal_9300 *ahp = AH9300(ah); 2450 2451 /* clear the old value, then set the new value */ 2452 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2453 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2454 } 2455 2456 void 2457 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2458 { 2459 struct ath_hal_9300 *ahp = AH9300(ah); 2460 2461 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2462 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2463 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2464 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2465 2466 switch (stomp_type) { 2467 case HAL_BT_COEX_STOMP_ALL: 2468 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2469 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2470 break; 2471 case HAL_BT_COEX_STOMP_LOW: 2472 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2473 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2474 break; 2475 case HAL_BT_COEX_STOMP_ALL_FORCE: 2476 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2477 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2478 break; 2479 case HAL_BT_COEX_STOMP_LOW_FORCE: 2480 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2481 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2482 break; 2483 case HAL_BT_COEX_STOMP_NONE: 2484 case HAL_BT_COEX_NO_STOMP: 2485 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2486 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2487 break; 2488 default: 2489 /* There is a force_weight from registry */ 2490 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2491 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2492 break; 2493 } 2494 } 2495 2496 void 2497 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2498 { 2499 struct ath_hal_9300 *ahp = AH9300(ah); 2500 2501 /* clear the old value, then set the new value */ 2502 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2503 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2504 } 2505 2506 static void 2507 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2508 { 2509 struct ath_hal_9300 *ahp = AH9300(ah); 2510 #if ATH_ANT_DIV_COMB 2511 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2512 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2513 #endif 2514 2515 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value); 2516 2517 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2518 { 2519 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2520 { 2521 /* Config antenna diversity */ 2522 #if ATH_ANT_DIV_COMB 2523 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2524 #endif 2525 } 2526 } 2527 } 2528 2529 2530 void 2531 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2532 u_int32_t value) 2533 { 2534 struct ath_hal_9300 *ahp = AH9300(ah); 2535 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2536 2537 switch (type) { 2538 case HAL_BT_COEX_SET_ACK_PWR: 2539 if (value) { 2540 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2541 } else { 2542 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2543 } 2544 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2545 ahpriv->ah_extraTxPow, 0); 2546 break; 2547 2548 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2549 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2550 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2551 if (value) { 2552 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2553 } 2554 else { 2555 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2556 } 2557 ar9300_bt_coex_antenna_diversity(ah, value); 2558 } 2559 break; 2560 case HAL_BT_COEX_LOWER_TX_PWR: 2561 if (value) { 2562 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2563 } 2564 else { 2565 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2566 } 2567 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2568 ahpriv->ah_extraTxPow, 0); 2569 break; 2570 #if ATH_SUPPORT_MCI 2571 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2572 if ((ah->ah_config.ath_hal_mci_config & 2573 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2574 { 2575 if (value) { 2576 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2577 ahp->ah_mci_concur_tx_en = AH_TRUE; 2578 } 2579 else { 2580 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2581 ahp->ah_mci_concur_tx_en = AH_FALSE; 2582 } 2583 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2584 ahpriv->ah_extraTxPow, 0); 2585 } 2586 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2587 ahp->ah_mci_concur_tx_en); 2588 break; 2589 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2590 if (value) { 2591 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2592 } 2593 else { 2594 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2595 } 2596 break; 2597 #endif 2598 default: 2599 break; 2600 } 2601 } 2602 2603 void 2604 ar9300_bt_coex_disable(struct ath_hal *ah) 2605 { 2606 struct ath_hal_9300 *ahp = AH9300(ah); 2607 2608 /* Always drive rx_clear_external output as 0 */ 2609 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2610 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2611 2612 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2613 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2614 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2615 } 2616 2617 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2618 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2619 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2620 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2621 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2622 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2623 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2624 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2625 2626 ahp->ah_bt_coex_enabled = AH_FALSE; 2627 } 2628 2629 int 2630 ar9300_bt_coex_enable(struct ath_hal *ah) 2631 { 2632 struct ath_hal_9300 *ahp = AH9300(ah); 2633 2634 /* Program coex mode and weight registers to actually enable coex */ 2635 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2636 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2637 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2638 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2639 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2640 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2641 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2642 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2643 2644 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2645 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2646 } else { 2647 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2648 } 2649 2650 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2651 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2652 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2653 } else { 2654 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2655 } 2656 2657 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2658 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2659 ath_hal_gpioCfgOutput(ah, 2660 ahp->ah_wlan_active_gpio_select, 2661 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2662 } 2663 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2664 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2665 { 2666 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2667 ath_hal_gpioCfgOutput(ah, 2668 ahp->ah_wlan_active_gpio_select, 2669 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2670 } 2671 2672 /* 2673 * Enable a weak pull down on BT_ACTIVE. 2674 * When BT device is disabled, BT_ACTIVE might be floating. 2675 */ 2676 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2677 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2678 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2679 2680 ahp->ah_bt_coex_enabled = AH_TRUE; 2681 2682 return 0; 2683 } 2684 2685 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2686 { 2687 return 0; 2688 } 2689 2690 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2691 { 2692 return bOn; 2693 } 2694 2695 void 2696 ar9300_init_bt_coex(struct ath_hal *ah) 2697 { 2698 struct ath_hal_9300 *ahp = AH9300(ah); 2699 2700 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2701 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2702 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2703 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2704 2705 /* 2706 * Set input mux for bt_prority_async and 2707 * bt_active_async to GPIO pins 2708 */ 2709 OS_REG_RMW_FIELD(ah, 2710 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2711 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2712 ahp->ah_bt_active_gpio_select); 2713 OS_REG_RMW_FIELD(ah, 2714 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2715 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2716 ahp->ah_bt_priority_gpio_select); 2717 2718 /* Configure the desired GPIO ports for input */ 2719 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2720 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2721 2722 if (ahp->ah_bt_coex_enabled) { 2723 ar9300_bt_coex_enable(ah); 2724 } else { 2725 ar9300_bt_coex_disable(ah); 2726 } 2727 } 2728 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2729 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2730 { 2731 /* 2-wire */ 2732 if (ahp->ah_bt_coex_enabled) { 2733 /* Connect bt_active_async to baseband */ 2734 OS_REG_CLR_BIT(ah, 2735 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2736 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2737 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2738 OS_REG_SET_BIT(ah, 2739 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2740 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2741 2742 /* 2743 * Set input mux for bt_prority_async and 2744 * bt_active_async to GPIO pins 2745 */ 2746 OS_REG_RMW_FIELD(ah, 2747 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2748 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2749 ahp->ah_bt_active_gpio_select); 2750 2751 /* Configure the desired GPIO ports for input */ 2752 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2753 2754 /* Enable coexistence on initialization */ 2755 ar9300_bt_coex_enable(ah); 2756 } 2757 } 2758 #if ATH_SUPPORT_MCI 2759 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2760 if (ahp->ah_bt_coex_enabled) { 2761 ar9300_mci_bt_coex_enable(ah); 2762 } 2763 else { 2764 ar9300_mci_bt_coex_disable(ah); 2765 } 2766 } 2767 #endif /* ATH_SUPPORT_MCI */ 2768 } 2769 2770 #endif /* ATH_BT_COEX */ 2771 2772 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2773 { 2774 u_int32_t val; 2775 int wasp_mm_rev; 2776 2777 #define AR_SOC_RST_REVISION_ID 0xB8060090 2778 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2779 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2780 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2781 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2782 #undef AR_SOC_RST_REVISION_ID 2783 #undef REG_READ 2784 2785 /* 2786 * Azimuth (ProxySTA) Mode is only supported correctly by 2787 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2788 * 2789 * Enable this feature for Scorpion at this time. The silicon 2790 * still needs to be validated. 2791 */ 2792 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2793 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2794 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2795 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2796 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2797 wasp_mm_rev >= 0 /* 1 */)))) 2798 { 2799 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2800 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2801 __func__, AH_PRIVATE((ah))->ah_macVersion, 2802 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2803 return HAL_ENOTSUPP; 2804 } 2805 2806 OS_REG_WRITE(ah, 2807 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2808 2809 /* turn on mode bit[24] for proxy sta */ 2810 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2811 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2812 2813 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2814 if (enable) { 2815 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2816 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2817 AR_AZIMUTH_BA_USES_AD1; 2818 /* turn off filter pass hold (bit 9) */ 2819 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2820 } else { 2821 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2822 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2823 AR_AZIMUTH_BA_USES_AD1); 2824 } 2825 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2826 2827 /* enable promiscous mode */ 2828 OS_REG_WRITE(ah, AR_RX_FILTER, 2829 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2830 /* enable promiscous in azimuth mode */ 2831 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2832 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2833 2834 /* turn on filter pass hold (bit 9) */ 2835 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2836 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2837 2838 return HAL_OK; 2839 } 2840 2841 #if 0 2842 void ar9300_mat_enable(struct ath_hal *ah, int enable) 2843 { 2844 /* 2845 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2846 * mitigation and turn on key search always for better performance. 2847 */ 2848 struct ath_hal_9300 *ahp = AH9300(ah); 2849 struct ath_hal_private *ap = AH_PRIVATE(ah); 2850 2851 ahp->ah_intr_mitigation_rx = !enable; 2852 if (ahp->ah_intr_mitigation_rx) { 2853 /* 2854 * Enable Interrupt Mitigation for Rx. 2855 * If no build-specific limits for the rx interrupt mitigation 2856 * timer have been specified, use conservative defaults. 2857 */ 2858 #ifndef AH_RIMT_VAL_LAST 2859 #define AH_RIMT_LAST_MICROSEC 500 2860 #endif 2861 #ifndef AH_RIMT_VAL_FIRST 2862 #define AH_RIMT_FIRST_MICROSEC 2000 2863 #endif 2864 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2865 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2866 } else { 2867 OS_REG_WRITE(ah, AR_RIMT, 0); 2868 } 2869 2870 ahp->ah_enable_keysearch_always = !!enable; 2871 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2872 } 2873 #endif 2874 2875 void ar9300_enable_tpc(struct ath_hal *ah) 2876 { 2877 u_int32_t val = 0; 2878 2879 ah->ah_config.ath_hal_desc_tpc = 1; 2880 2881 /* Enable TPC */ 2882 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2883 2884 /* 2885 * Disable per chain power reduction since we are already 2886 * accounting for this in our calculations 2887 */ 2888 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2889 if (AR_SREV_WASP(ah)) { 2890 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2891 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2892 } else { 2893 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2894 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2895 } 2896 } 2897 2898 2899 /* 2900 * ar9300_force_tsf_sync 2901 * This function forces the TSF sync to the given bssid, this is implemented 2902 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2903 * mode of operation, where we sync the TSF to RootAP TSF values 2904 */ 2905 void 2906 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2907 u_int16_t assoc_id) 2908 { 2909 ar9300_set_operating_mode(ah, HAL_M_STA); 2910 ar9300_write_associd(ah, bssid, assoc_id); 2911 } 2912 2913 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2914 { 2915 struct ath_hal_9300 *ahp = AH9300(ah); 2916 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2917 u_int32_t temp_powertx_rate9_reg_val; 2918 int8_t olpc_power_offset = 0; 2919 int8_t tmp_olpc_val = 0; 2920 HAL_RSSI_TX_POWER old_greentx_status; 2921 u_int8_t target_power_val_t[ar9300_rate_size]; 2922 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2923 2924 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2925 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2926 return; 2927 } 2928 2929 old_greentx_status = AH9300(ah)->green_tx_status; 2930 if (ahp->ah_hw_green_tx_enable) { 2931 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2932 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2933 } else { 2934 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2935 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2936 } 2937 2938 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2939 && (rssi > tmp_rss1_thr1)) 2940 { 2941 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2942 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2943 } 2944 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2945 && (rssi > tmp_rss1_thr2)) 2946 { 2947 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2948 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2949 } 2950 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2951 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2952 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2953 } 2954 } 2955 2956 /* If status is not change, don't do anything */ 2957 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2958 return; 2959 } 2960 2961 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2962 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2963 && AR_SREV_POSEIDON(ah)) 2964 { 2965 if (ahp->ah_hw_green_tx_enable) { 2966 switch (AH9300(ah)->green_tx_status) { 2967 case HAL_RSSI_TX_POWER_SHORT: 2968 /* 1. TxPower Config */ 2969 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2970 sizeof(target_power_val_t)); 2971 /* 1.1 Store OLPC Delta Calibration Offset*/ 2972 olpc_power_offset = 0; 2973 /* 2. Store OB/DB */ 2974 /* 3. Store TPC settting */ 2975 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2976 SM(14, AR_TPC_CTS) | 2977 SM(14, AR_TPC_CHIRP) | 2978 SM(14, AR_TPC_RPT)); 2979 /* 4. Store BB_powertx_rate9 value */ 2980 temp_powertx_rate9_reg_val = 2981 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2982 break; 2983 case HAL_RSSI_TX_POWER_MIDDLE: 2984 /* 1. TxPower Config */ 2985 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2986 sizeof(target_power_val_t)); 2987 /* 1.1 Store OLPC Delta Calibration Offset*/ 2988 olpc_power_offset = 0; 2989 /* 2. Store OB/DB */ 2990 /* 3. Store TPC settting */ 2991 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2992 SM(18, AR_TPC_CTS) | 2993 SM(18, AR_TPC_CHIRP) | 2994 SM(18, AR_TPC_RPT)); 2995 /* 4. Store BB_powertx_rate9 value */ 2996 temp_powertx_rate9_reg_val = 2997 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2998 break; 2999 case HAL_RSSI_TX_POWER_LONG: 3000 default: 3001 /* 1. TxPower Config */ 3002 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3003 sizeof(target_power_val_t)); 3004 /* 1.1 Store OLPC Delta Calibration Offset*/ 3005 olpc_power_offset = 0; 3006 /* 2. Store OB/DB1/DB2 */ 3007 /* 3. Store TPC settting */ 3008 temp_tcp_reg_val = 3009 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3010 /* 4. Store BB_powertx_rate9 value */ 3011 temp_powertx_rate9_reg_val = 3012 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3013 break; 3014 } 3015 } else { 3016 switch (AH9300(ah)->green_tx_status) { 3017 case HAL_RSSI_TX_POWER_SHORT: 3018 /* 1. TxPower Config */ 3019 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 3020 sizeof(target_power_val_t)); 3021 /* 1.1 Store OLPC Delta Calibration Offset*/ 3022 olpc_power_offset = 3023 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 3024 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3025 /* 2. Store OB/DB */ 3026 temp_obdb_reg_val = 3027 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3028 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3029 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3030 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3031 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3032 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3033 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3034 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3035 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3036 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3037 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3038 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3039 /* 3. Store TPC settting */ 3040 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 3041 SM(6, AR_TPC_CTS) | 3042 SM(6, AR_TPC_CHIRP) | 3043 SM(6, AR_TPC_RPT)); 3044 /* 4. Store BB_powertx_rate9 value */ 3045 temp_powertx_rate9_reg_val = 3046 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 3047 break; 3048 case HAL_RSSI_TX_POWER_MIDDLE: 3049 /* 1. TxPower Config */ 3050 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 3051 sizeof(target_power_val_t)); 3052 /* 1.1 Store OLPC Delta Calibration Offset*/ 3053 olpc_power_offset = 3054 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 3055 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3056 /* 2. Store OB/DB */ 3057 temp_obdb_reg_val = 3058 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3059 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3060 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3061 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3062 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3063 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3064 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3065 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3066 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3067 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3068 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3069 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3070 /* 3. Store TPC settting */ 3071 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3072 SM(14, AR_TPC_CTS) | 3073 SM(14, AR_TPC_CHIRP) | 3074 SM(14, AR_TPC_RPT)); 3075 /* 4. Store BB_powertx_rate9 value */ 3076 temp_powertx_rate9_reg_val = 3077 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3078 break; 3079 case HAL_RSSI_TX_POWER_LONG: 3080 default: 3081 /* 1. TxPower Config */ 3082 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3083 sizeof(target_power_val_t)); 3084 /* 1.1 Store OLPC Delta Calibration Offset*/ 3085 olpc_power_offset = 3086 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3087 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3088 /* 2. Store OB/DB1/DB2 */ 3089 temp_obdb_reg_val = 3090 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3091 /* 3. Store TPC settting */ 3092 temp_tcp_reg_val = 3093 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3094 /* 4. Store BB_powertx_rate9 value */ 3095 temp_powertx_rate9_reg_val = 3096 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3097 break; 3098 } 3099 } 3100 /* 1.1 Do OLPC Delta Calibration Offset */ 3101 tmp_olpc_val = 3102 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3103 tmp_olpc_val += olpc_power_offset; 3104 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3105 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3106 AR_PHY_TPC_OLPC_GAIN_DELTA); 3107 3108 /* 1.2 TxPower Config */ 3109 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3110 /* 2. Config OB/DB */ 3111 if (!ahp->ah_hw_green_tx_enable) { 3112 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3113 } 3114 /* 3. config TPC settting */ 3115 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3116 /* 4. config BB_powertx_rate9 value */ 3117 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3118 } 3119 } 3120 3121 #if 0 3122 void 3123 ar9300_get_vow_stats( 3124 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3125 { 3126 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3127 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3128 } 3129 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3130 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3131 } 3132 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3133 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3134 } 3135 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3136 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3137 } 3138 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3139 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3140 } 3141 } 3142 #endif 3143 3144 /* 3145 * ar9300_is_skip_paprd_by_greentx 3146 * 3147 * This function check if we need to skip PAPRD tuning 3148 * when GreenTx in specific state. 3149 */ 3150 HAL_BOOL 3151 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3152 { 3153 if (AR_SREV_POSEIDON(ah) && 3154 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3155 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3156 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3157 { 3158 return AH_TRUE; 3159 } 3160 return AH_FALSE; 3161 } 3162 3163 void 3164 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3165 { 3166 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3167 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3168 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3169 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3170 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3171 struct ath_hal_9300 *ahp = AH9300(ah); 3172 3173 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3174 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3175 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3176 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3177 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3178 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3179 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3180 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3181 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3182 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3183 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3184 } 3185 } 3186 3187 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3188 { 3189 struct ath_hal_9300 *ahp = AH9300(ah); 3190 3191 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3192 if ((value == 0) || (value == 1)) { 3193 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3194 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3195 } 3196 } 3197 } 3198 3199 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3200 { 3201 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3202 } 3203 3204 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3205 { 3206 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3207 3208 /* RSSI format is 8.4. Ignore lowest four bits */ 3209 val = val >> 4; 3210 return val; 3211 } 3212 3213 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3214 u_int32_t rssi_threshold) 3215 { 3216 struct ath_hal_9300 *ahp = AH9300(ah); 3217 3218 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3219 3220 /* save value for restoring after chip reset */ 3221 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3222 } 3223 3224 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3225 { 3226 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3227 } 3228 3229 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3230 { 3231 if (on) { 3232 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3233 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3234 } 3235 else { 3236 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3237 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3238 } 3239 } 3240 /* 3241 * Gets the contents of the specified key cache entry. 3242 */ 3243 HAL_BOOL 3244 ar9300_print_keycache(struct ath_hal *ah) 3245 { 3246 3247 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3248 u_int32_t key0, key1, key2, key3, key4; 3249 u_int32_t mac_hi, mac_lo; 3250 u_int16_t entry = 0; 3251 u_int32_t valid = 0; 3252 u_int32_t key_type; 3253 3254 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3255 3256 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3257 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3258 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3259 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3260 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3261 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3262 3263 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3264 3265 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3266 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3267 3268 if (mac_hi & AR_KEYTABLE_VALID) { 3269 valid = 1; 3270 } else { 3271 valid = 0; 3272 } 3273 3274 if ((mac_hi != 0) && (mac_lo != 0)) { 3275 mac_hi &= ~0x8000; 3276 mac_hi <<= 1; 3277 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3278 mac_lo <<= 1; 3279 } 3280 3281 ath_hal_printf(ah, 3282 "%03d " 3283 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3284 " %02d %02d " 3285 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3286 entry, 3287 (key0 << 24) >> 24, (key0 << 16) >> 24, 3288 (key0 << 8) >> 24, key0 >> 24, 3289 (key1 << 24) >> 24, (key1 << 16) >> 24, 3290 //(key1 << 8) >> 24, key1 >> 24, 3291 (key2 << 24) >> 24, (key2 << 16) >> 24, 3292 (key2 << 8) >> 24, key2 >> 24, 3293 (key3 << 24) >> 24, (key3 << 16) >> 24, 3294 //(key3 << 8) >> 24, key3 >> 24, 3295 (key4 << 24) >> 24, (key4 << 16) >> 24, 3296 (key4 << 8) >> 24, key4 >> 24, 3297 valid, key_type, 3298 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3299 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3300 } 3301 3302 return AH_TRUE; 3303 } 3304 3305 /* enable/disable smart antenna mode */ 3306 HAL_BOOL 3307 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3308 { 3309 struct ath_hal_9300 *ahp = AH9300(ah); 3310 3311 if (enable) { 3312 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3313 } else { 3314 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3315 } 3316 3317 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3318 * and swcom2 with 0 3319 * FIXME Ideally these registers need to be made read from caldata. 3320 * Until the calibration team gets them, keep them along with board 3321 * configuration. 3322 */ 3323 if (enable && AR_SREV_SCORPION(ah) && 3324 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3325 3326 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3327 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3328 } 3329 3330 ahp->ah_smartantenna_enable = enable; 3331 return 1; 3332 } 3333 3334 #ifdef ATH_TX99_DIAG 3335 #ifndef ATH_SUPPORT_HTC 3336 void 3337 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3338 u_int32_t txpower) 3339 { 3340 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3341 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3342 int32_t i; 3343 3344 /* The max power is limited to 63 */ 3345 if (txpower <= AR9300_MAX_RATE_POWER) { 3346 for (i = 0; i < ar9300_rate_size; i++) { 3347 p_pwr_array[i] = txpower; 3348 } 3349 } else { 3350 for (i = 0; i < ar9300_rate_size; i++) { 3351 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3352 } 3353 } 3354 3355 OS_REG_WRITE(ah, 0xa458, 0); 3356 3357 /* Write the OFDM power per rate set */ 3358 /* 6 (LSB), 9, 12, 18 (MSB) */ 3359 OS_REG_WRITE(ah, 0xa3c0, 3360 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3361 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3362 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3363 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3364 ); 3365 /* 24 (LSB), 36, 48, 54 (MSB) */ 3366 OS_REG_WRITE(ah, 0xa3c4, 3367 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3368 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3369 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3370 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3371 ); 3372 3373 /* Write the CCK power per rate set */ 3374 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3375 OS_REG_WRITE(ah, 0xa3c8, 3376 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3377 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3378 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3379 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3380 ); 3381 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3382 OS_REG_WRITE(ah, 0xa3cc, 3383 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3384 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3385 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3386 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3387 ); 3388 3389 /* Write the HT20 power per rate set */ 3390 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3391 OS_REG_WRITE(ah, 0xa3d0, 3392 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3393 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3394 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3395 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3396 ); 3397 3398 /* 6 (LSB), 7, 12, 13 (MSB) */ 3399 OS_REG_WRITE(ah, 0xa3d4, 3400 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3401 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3402 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3403 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3404 ); 3405 3406 /* 14 (LSB), 15, 20, 21 */ 3407 OS_REG_WRITE(ah, 0xa3e4, 3408 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3409 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3410 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3411 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3412 ); 3413 3414 /* Mixed HT20 and HT40 rates */ 3415 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3416 OS_REG_WRITE(ah, 0xa3e8, 3417 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3418 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3419 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3420 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3421 ); 3422 3423 /* Write the HT40 power per rate set */ 3424 /* correct PAR difference between HT40 and HT20/LEGACY */ 3425 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3426 OS_REG_WRITE(ah, 0xa3d8, 3427 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3428 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3429 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3430 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3431 ); 3432 3433 /* 6 (LSB), 7, 12, 13 (MSB) */ 3434 OS_REG_WRITE(ah, 0xa3dc, 3435 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3436 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3437 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3438 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3439 ); 3440 3441 /* 14 (LSB), 15, 20, 21 */ 3442 OS_REG_WRITE(ah, 0xa3ec, 3443 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3444 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3445 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3446 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3447 ); 3448 #undef PWR_MAS 3449 } 3450 3451 void 3452 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3453 { 3454 if (tx_chainmask == 0x5) { 3455 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3456 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3457 } 3458 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3459 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3460 3461 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3462 if (tx_chainmask == 0x5) { 3463 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3464 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3465 } 3466 } 3467 3468 void 3469 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3470 int chtype) 3471 { 3472 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3473 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3474 OS_REG_WRITE(ah, 0xa350, 3475 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3476 3477 /* 11G mode */ 3478 if (!chtype) { 3479 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3480 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3481 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3482 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3483 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3484 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3485 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3486 | (0x1 << 26) | (0x7 << 24)) 3487 & ~(0x1 << 22)); 3488 } else { 3489 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3490 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3491 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3492 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3493 | (0x1 << 26) | (0x7 << 24)) 3494 & ~(0x1 << 22)); 3495 } 3496 3497 /* chain zero */ 3498 if ((tx_chain_mask & 0x01) == 0x01) { 3499 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3500 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3501 | (0x1 << 31) | (0x5 << 15) 3502 | (0x3 << 9)) & ~(0x1 << 27) 3503 & ~(0x1 << 12)); 3504 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3505 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3506 | (0x1 << 12) | (0x1 << 10) 3507 | (0x1 << 9) | (0x1 << 8) 3508 | (0x1 << 7)) & ~(0x1 << 11)); 3509 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3510 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3511 | (0x1 << 29) | (0x1 << 25) 3512 | (0x1 << 23) | (0x1 << 19) 3513 | (0x1 << 10) | (0x1 << 9) 3514 | (0x1 << 8) | (0x1 << 3)) 3515 & ~(0x1 << 28)& ~(0x1 << 24) 3516 & ~(0x1 << 22)& ~(0x1 << 7)); 3517 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3518 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3519 | (0x1 << 23))& ~(0x1 << 21)); 3520 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3521 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3522 | (0x1 << 12) | (0x1 << 10) 3523 | (0x1 << 9) | (0x1 << 8) 3524 | (0x1 << 6) | (0x1 << 5) 3525 | (0x1 << 4) | (0x1 << 3) 3526 | (0x1 << 2)); 3527 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3528 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3529 } 3530 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3531 /* chain one */ 3532 if ((tx_chain_mask & 0x02) == 0x02 ) { 3533 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3534 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3535 | (0x1 << 31) | (0x5 << 15) 3536 | (0x3 << 9)) & ~(0x1 << 27) 3537 & ~(0x1 << 12)); 3538 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3539 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3540 | (0x1 << 12) | (0x1 << 10) 3541 | (0x1 << 9) | (0x1 << 8) 3542 | (0x1 << 7)) & ~(0x1 << 11)); 3543 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3544 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3545 | (0x1 << 29) | (0x1 << 25) 3546 | (0x1 << 23) | (0x1 << 19) 3547 | (0x1 << 10) | (0x1 << 9) 3548 | (0x1 << 8) | (0x1 << 3)) 3549 & ~(0x1 << 28)& ~(0x1 << 24) 3550 & ~(0x1 << 22)& ~(0x1 << 7)); 3551 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3552 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3553 | (0x1 << 23))& ~(0x1 << 21)); 3554 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3555 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3556 | (0x1 << 12) | (0x1 << 10) 3557 | (0x1 << 9) | (0x1 << 8) 3558 | (0x1 << 6) | (0x1 << 5) 3559 | (0x1 << 4) | (0x1 << 3) 3560 | (0x1 << 2)); 3561 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3562 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3563 } 3564 } 3565 if (AR_SREV_OSPREY(ah)) { 3566 /* chain two */ 3567 if ((tx_chain_mask & 0x04) == 0x04 ) { 3568 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3569 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3570 | (0x1 << 31) | (0x5 << 15) 3571 | (0x3 << 9)) & ~(0x1 << 27) 3572 & ~(0x1 << 12)); 3573 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3574 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3575 | (0x1 << 12) | (0x1 << 10) 3576 | (0x1 << 9) | (0x1 << 8) 3577 | (0x1 << 7)) & ~(0x1 << 11)); 3578 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3579 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3580 | (0x1 << 29) | (0x1 << 25) 3581 | (0x1 << 23) | (0x1 << 19) 3582 | (0x1 << 10) | (0x1 << 9) 3583 | (0x1 << 8) | (0x1 << 3)) 3584 & ~(0x1 << 28)& ~(0x1 << 24) 3585 & ~(0x1 << 22)& ~(0x1 << 7)); 3586 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3587 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3588 | (0x1 << 23))& ~(0x1 << 21)); 3589 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3590 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3591 | (0x1 << 12) | (0x1 << 10) 3592 | (0x1 << 9) | (0x1 << 8) 3593 | (0x1 << 6) | (0x1 << 5) 3594 | (0x1 << 4) | (0x1 << 3) 3595 | (0x1 << 2)); 3596 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3597 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3598 } 3599 } 3600 3601 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3602 OS_REG_WRITE(ah, 0xa288, 0x111); 3603 } else { 3604 /* chain zero */ 3605 if ((tx_chain_mask & 0x01) == 0x01) { 3606 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3607 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3608 | (0x1 << 31) | (0x1 << 27) 3609 | (0x3 << 23) | (0x1 << 19) 3610 | (0x1 << 15) | (0x3 << 9)) 3611 & ~(0x1 << 12)); 3612 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3613 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3614 | (0x1 << 12) | (0x1 << 10) 3615 | (0x1 << 9) | (0x1 << 8) 3616 | (0x1 << 7) | (0x1 << 3) 3617 | (0x1 << 2) | (0x1 << 1)) 3618 & ~(0x1 << 11)& ~(0x1 << 0)); 3619 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3620 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3621 | (0x1 << 29) | (0x1 << 25) 3622 | (0x1 << 23) | (0x1 << 19) 3623 | (0x1 << 10) | (0x1 << 9) 3624 | (0x1 << 8) | (0x1 << 3)) 3625 & ~(0x1 << 28)& ~(0x1 << 24) 3626 & ~(0x1 << 22)& ~(0x1 << 7)); 3627 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3628 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3629 | (0x1 << 23))& ~(0x1 << 21)); 3630 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3631 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3632 | (0x3 << 3) | (0x3 << 0)); 3633 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3634 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3635 | (0x3 << 29) | (0x3 << 26) 3636 | (0x2 << 23) | (0x2 << 20) 3637 | (0x2 << 17))& ~(0x1 << 14)); 3638 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3639 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3640 | (0x1 << 12) | (0x1 << 10) 3641 | (0x1 << 9) | (0x1 << 8) 3642 | (0x1 << 6) | (0x1 << 5) 3643 | (0x1 << 4) | (0x1 << 3) 3644 | (0x1 << 2)); 3645 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3646 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3647 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3648 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3649 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3650 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3651 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3652 | (0x1 << 26) | (0x7 << 24) 3653 | (0x3 << 22)); 3654 } else { 3655 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3656 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3657 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3658 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3659 | (0x1 << 26) | (0x7 << 24) 3660 | (0x3 << 22)); 3661 } 3662 3663 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3665 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3666 | (0x1 << 3) | (0x1 << 2) 3667 | (0x1 << 1)) & ~(0x1 << 0)); 3668 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3669 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3670 | (0x1 << 19) | (0x1 << 3)); 3671 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3672 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3673 } 3674 if (AR_SREV_OSPREY(ah)) { 3675 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3676 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3677 | (0x1 << 3) | (0x1 << 2) 3678 | (0x1 << 1)) & ~(0x1 << 0)); 3679 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3680 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3681 | (0x1 << 19) | (0x1 << 3)); 3682 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3683 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3684 } 3685 } 3686 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3687 /* chain one */ 3688 if ((tx_chain_mask & 0x02) == 0x02 ) { 3689 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3690 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3691 | (0x1 << 3) | (0x1 << 2) 3692 | (0x1 << 1)) & ~(0x1 << 0)); 3693 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3694 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3695 | (0x1 << 19) | (0x1 << 3)); 3696 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3697 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3698 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3699 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3700 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3701 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3702 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3703 | (0x1 << 26) | (0x7 << 24) 3704 | (0x3 << 22)); 3705 } else { 3706 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3707 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3708 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3709 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3710 | (0x1 << 26) | (0x7 << 24) 3711 | (0x3 << 22)); 3712 } 3713 3714 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3715 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3716 | (0x1 << 31) | (0x1 << 27) 3717 | (0x3 << 23) | (0x1 << 19) 3718 | (0x1 << 15) | (0x3 << 9)) 3719 & ~(0x1 << 12)); 3720 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3721 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3722 | (0x1 << 12) | (0x1 << 10) 3723 | (0x1 << 9) | (0x1 << 8) 3724 | (0x1 << 7) | (0x1 << 3) 3725 | (0x1 << 2) | (0x1 << 1)) 3726 & ~(0x1 << 11)& ~(0x1 << 0)); 3727 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3728 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3729 | (0x1 << 29) | (0x1 << 25) 3730 | (0x1 << 23) | (0x1 << 19) 3731 | (0x1 << 10) | (0x1 << 9) 3732 | (0x1 << 8) | (0x1 << 3)) 3733 & ~(0x1 << 28)& ~(0x1 << 24) 3734 & ~(0x1 << 22)& ~(0x1 << 7)); 3735 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3736 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3737 | (0x1 << 23))& ~(0x1 << 21)); 3738 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3739 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3740 | (0x3 << 3) | (0x3 << 0)); 3741 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3742 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3743 | (0x3 << 29) | (0x3 << 26) 3744 | (0x2 << 23) | (0x2 << 20) 3745 | (0x2 << 17))& ~(0x1 << 14)); 3746 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3747 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3748 | (0x1 << 12) | (0x1 << 10) 3749 | (0x1 << 9) | (0x1 << 8) 3750 | (0x1 << 6) | (0x1 << 5) 3751 | (0x1 << 4) | (0x1 << 3) 3752 | (0x1 << 2)); 3753 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3754 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3755 3756 if (AR_SREV_OSPREY(ah)) { 3757 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3758 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3759 | (0x1 << 3) | (0x1 << 2) 3760 | (0x1 << 1)) & ~(0x1 << 0)); 3761 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3762 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3763 | (0x1 << 19) | (0x1 << 3)); 3764 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3765 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3766 } 3767 } 3768 } 3769 if (AR_SREV_OSPREY(ah)) { 3770 /* chain two */ 3771 if ((tx_chain_mask & 0x04) == 0x04 ) { 3772 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3773 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3774 | (0x1 << 3) | (0x1 << 2) 3775 | (0x1 << 1)) & ~(0x1 << 0)); 3776 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3777 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3778 | (0x1 << 19) | (0x1 << 3)); 3779 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3780 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3781 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3782 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3783 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3784 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3785 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3786 | (0x1 << 26) | (0x7 << 24) 3787 | (0x3 << 22)); 3788 } else { 3789 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3790 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3791 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3792 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3793 | (0x1 << 26) | (0x7 << 24) 3794 | (0x3 << 22)); 3795 } 3796 3797 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3798 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3799 | (0x1 << 3) | (0x1 << 2) 3800 | (0x1 << 1)) & ~(0x1 << 0)); 3801 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3802 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3803 | (0x1 << 19) | (0x1 << 3)); 3804 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3805 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3806 3807 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3808 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3809 | (0x1 << 31) | (0x1 << 27) 3810 | (0x3 << 23) | (0x1 << 19) 3811 | (0x1 << 15) | (0x3 << 9)) 3812 & ~(0x1 << 12)); 3813 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3814 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3815 | (0x1 << 12) | (0x1 << 10) 3816 | (0x1 << 9) | (0x1 << 8) 3817 | (0x1 << 7) | (0x1 << 3) 3818 | (0x1 << 2) | (0x1 << 1)) 3819 & ~(0x1 << 11)& ~(0x1 << 0)); 3820 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3821 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3822 | (0x1 << 29) | (0x1 << 25) 3823 | (0x1 << 23) | (0x1 << 19) 3824 | (0x1 << 10) | (0x1 << 9) 3825 | (0x1 << 8) | (0x1 << 3)) 3826 & ~(0x1 << 28)& ~(0x1 << 24) 3827 & ~(0x1 << 22)& ~(0x1 << 7)); 3828 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3829 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3830 | (0x1 << 23))& ~(0x1 << 21)); 3831 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3832 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3833 | (0x3 << 3) | (0x3 << 0)); 3834 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3835 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3836 | (0x3 << 29) | (0x3 << 26) 3837 | (0x2 << 23) | (0x2 << 20) 3838 | (0x2 << 17))& ~(0x1 << 14)); 3839 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3840 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3841 | (0x1 << 12) | (0x1 << 10) 3842 | (0x1 << 9) | (0x1 << 8) 3843 | (0x1 << 6) | (0x1 << 5) 3844 | (0x1 << 4) | (0x1 << 3) 3845 | (0x1 << 2)); 3846 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3847 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3848 } 3849 } 3850 3851 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3852 OS_REG_WRITE(ah, 0xa288, 0x222); 3853 } 3854 } 3855 3856 void 3857 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3858 { 3859 u_int32_t val; 3860 u_int32_t qnum = (u_int32_t)data; 3861 3862 /* Disable AGC to A2 */ 3863 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3864 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3865 3866 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3867 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3868 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3869 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3870 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3871 /* 200 ok for HT20, 400 ok for HT40 */ 3872 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3873 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3874 3875 /* set QCU modes to early termination */ 3876 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3877 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3878 } 3879 3880 void 3881 ar9300_tx99_stop(struct ath_hal *ah) 3882 { 3883 /* this should follow the setting of start */ 3884 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3885 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3886 } 3887 #endif /* ATH_TX99_DIAG */ 3888 #endif /* ATH_SUPPORT_HTC */ 3889 3890 HAL_BOOL 3891 ar9300Get3StreamSignature(struct ath_hal *ah) 3892 { 3893 return AH_FALSE; 3894 } 3895 3896 HAL_BOOL 3897 ar9300ForceVCS(struct ath_hal *ah) 3898 { 3899 return AH_FALSE; 3900 } 3901 3902 HAL_BOOL 3903 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3904 { 3905 return AH_FALSE; 3906 } 3907 3908 static u_int32_t 3909 ar9300_read_loc_timer(struct ath_hal *ah) 3910 { 3911 3912 return OS_REG_READ(ah, AR_LOC_TIMER_REG); 3913 } 3914 3915 HAL_BOOL 3916 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3917 { 3918 struct ath_hal_9300 *ahp = AH9300(ah); 3919 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3920 u_int8_t *ctl_index; 3921 u_int32_t offset = 0; 3922 3923 if (!ctl_array) 3924 return AH_FALSE; 3925 3926 /* copy 2G ctl freqbin and power data */ 3927 ctl_index = p_eep_data->ctl_index_2g; 3928 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3929 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3930 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3931 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3932 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3933 3934 3935 /* copy 2G ctl freqbin and power data */ 3936 ctl_index = p_eep_data->ctl_index_5g; 3937 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3938 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3939 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3940 3941 return AH_FALSE; 3942 } 3943 3944 void 3945 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3946 { 3947 struct ath_hal_9300 *ahp = AH9300(ah); 3948 3949 /* optional txchainmask should be subset of primary txchainmask */ 3950 if ((mask & ahp->ah_tx_chainmask) != mask) { 3951 ahp->ah_tx_chainmaskopt = 0; 3952 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3953 return; 3954 } 3955 3956 ahp->ah_tx_chainmaskopt = mask; 3957 } 3958