1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 30 31 void 32 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 33 { 34 struct ath_hal_9300 *ahp = AH9300(ah); 35 *hangs = 0; 36 37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 38 *hangs |= HAL_RIFS_BB_HANG_WAR; 39 } 40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 41 *hangs |= HAL_DFS_BB_HANG_WAR; 42 } 43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 44 == HAL_OK) 45 { 46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 47 } 48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 49 *hangs |= HAL_MAC_HANG_WAR; 50 } 51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 52 == HAL_OK) 53 { 54 *hangs |= HAL_PHYRESTART_CLR_WAR; 55 } 56 57 ahp->ah_hang_wars = *hangs; 58 } 59 60 /* 61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 62 * HT20, HT40, fast-clock, turbo mode, etc. 63 */ 64 static u_int 65 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 66 { 67 #if 0 68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 69 70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 71 return (ath_hal_mac_usec(ah, clks) / 2); 72 } else { 73 return (ath_hal_mac_usec(ah, clks)); 74 } 75 #endif 76 return (ath_hal_mac_usec(ah, clks)); 77 } 78 79 u_int 80 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 81 { 82 #if 0 83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 84 85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 86 return (ath_hal_mac_clks(ah, usecs) * 2); 87 } else { 88 return (ath_hal_mac_clks(ah, usecs)); 89 } 90 #endif 91 return (ath_hal_mac_clks(ah, usecs)); 92 } 93 94 void 95 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 96 { 97 struct ath_hal_9300 *ahp = AH9300(ah); 98 99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 100 } 101 102 HAL_BOOL 103 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 104 { 105 struct ath_hal_9300 *ahp = AH9300(ah); 106 107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 108 return AH_TRUE; 109 } 110 111 void 112 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 113 { 114 struct ath_hal_9300 *ahp = AH9300(ah); 115 116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 117 } 118 119 HAL_BOOL 120 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 121 { 122 struct ath_hal_9300 *ahp = AH9300(ah); 123 124 /* save it since it must be rewritten on reset */ 125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 126 127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 129 return AH_TRUE; 130 } 131 132 /* 133 * Attempt to change the cards operating regulatory domain to the given value 134 * Returns: A_EINVAL for an unsupported regulatory domain. 135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 136 */ 137 HAL_BOOL 138 ar9300_set_regulatory_domain(struct ath_hal *ah, 139 u_int16_t reg_domain, HAL_STATUS *status) 140 { 141 HAL_STATUS ecode; 142 143 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 144 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 145 return AH_TRUE; 146 } 147 ecode = HAL_EIO; 148 149 #if 0 150 bad: 151 #endif 152 if (status) { 153 *status = ecode; 154 } 155 return AH_FALSE; 156 } 157 158 /* 159 * Return the wireless modes (a,b,g,t) supported by hardware. 160 * 161 * This value is what is actually supported by the hardware 162 * and is unaffected by regulatory/country code settings. 163 * 164 */ 165 u_int 166 ar9300_get_wireless_modes(struct ath_hal *ah) 167 { 168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 169 } 170 171 /* 172 * Set the interrupt and GPIO values so the ISR can disable RF 173 * on a switch signal. Assumes GPIO port and interrupt polarity 174 * are set prior to call. 175 */ 176 void 177 ar9300_enable_rf_kill(struct ath_hal *ah) 178 { 179 /* TODO - can this really be above the hal on the GPIO interface for 180 * TODO - the client only? 181 */ 182 struct ath_hal_9300 *ahp = AH9300(ah); 183 184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 185 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 188 AR_RFSILENT_FORCE); 189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 190 } 191 else { 192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 193 AR_RFSILENT_FORCE); 194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 195 } 196 } 197 else { 198 /* Connect rfsilent_bb_l to baseband */ 199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 201 202 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 204 AR_GPIO_INPUT_MUX2_RFSILENT); 205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 (ahp->ah_gpio_select & 0x0f) << 4); 207 208 /* 209 * Configure the desired GPIO port for input and 210 * enable baseband rf silence 211 */ 212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 214 } 215 216 /* 217 * If radio disable switch connection to GPIO bit x is enabled 218 * program GPIO interrupt. 219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 220 * verified that it is a later version of eeprom, it has a place for 221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 222 * connection is present. 223 */ 224 /* 225 * RFKill uses polling not interrupt, 226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 227 */ 228 if (ath_hal_hasrfkill_int(ah)) { 229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 230 /* switch already closed, set to interrupt upon open */ 231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 232 } else { 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 234 } 235 } 236 } 237 238 /* 239 * Change the LED blinking pattern to correspond to the connectivity 240 */ 241 void 242 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 243 { 244 static const u_int32_t ledbits[8] = { 245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 252 AR_CFG_LED_ASSOC_NONE, 253 }; 254 255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 256 } 257 258 /* 259 * Sets the Power LED on the cardbus without affecting the Network LED. 260 */ 261 void 262 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 263 { 264 u_int32_t val; 265 266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 268 } 269 270 /* 271 * Sets the Network LED on the cardbus without affecting the Power LED. 272 */ 273 void 274 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 275 { 276 u_int32_t val; 277 278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 280 } 281 282 /* 283 * Change association related fields programmed into the hardware. 284 * Writing a valid BSSID to the hardware effectively enables the hardware 285 * to synchronize its TSF to the correct beacons and receive frames coming 286 * from that BSSID. It is called by the SME JOIN operation. 287 */ 288 void 289 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 290 u_int16_t assoc_id) 291 { 292 struct ath_hal_9300 *ahp = AH9300(ah); 293 294 /* save bssid and assoc_id for restore on reset */ 295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 296 ahp->ah_assoc_id = assoc_id; 297 298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 301 } 302 303 /* 304 * Get the current hardware tsf for stamlme 305 */ 306 u_int64_t 307 ar9300_get_tsf64(struct ath_hal *ah) 308 { 309 u_int64_t tsf; 310 311 /* XXX sync multi-word read? */ 312 tsf = OS_REG_READ(ah, AR_TSF_U32); 313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 314 return tsf; 315 } 316 317 void 318 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 319 { 320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 322 } 323 324 /* 325 * Get the current hardware tsf for stamlme 326 */ 327 u_int32_t 328 ar9300_get_tsf32(struct ath_hal *ah) 329 { 330 return OS_REG_READ(ah, AR_TSF_L32); 331 } 332 333 u_int32_t 334 ar9300_get_tsf2_32(struct ath_hal *ah) 335 { 336 return OS_REG_READ(ah, AR_TSF2_L32); 337 } 338 339 /* 340 * Reset the current hardware tsf for stamlme. 341 */ 342 void 343 ar9300_reset_tsf(struct ath_hal *ah) 344 { 345 int count; 346 347 count = 0; 348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 349 count++; 350 if (count > 10) { 351 HALDEBUG(ah, HAL_DEBUG_RESET, 352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 353 break; 354 } 355 OS_DELAY(10); 356 } 357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 358 } 359 360 /* 361 * Set or clear hardware basic rate bit 362 * Set hardware basic rate set if basic rate is found 363 * and basic rate is equal or less than 2Mbps 364 */ 365 void 366 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 367 { 368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 369 u_int32_t reg; 370 u_int8_t xset; 371 int i; 372 373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 374 return; 375 } 376 xset = 0; 377 for (i = 0; i < rs->rs_count; i++) { 378 u_int8_t rset = rs->rs_rates[i]; 379 /* Basic rate defined? */ 380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 381 xset = rset; 382 } 383 } 384 /* 385 * Set the h/w bit to reflect whether or not the basic 386 * rate is found to be equal or less than 2Mbps. 387 */ 388 reg = OS_REG_READ(ah, AR_STA_ID1); 389 if (xset && xset / 2 <= 2) { 390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 391 } else { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 393 } 394 } 395 396 /* 397 * Grab a semi-random value from hardware registers - may not 398 * change often 399 */ 400 u_int32_t 401 ar9300_get_random_seed(struct ath_hal *ah) 402 { 403 u_int32_t nf; 404 405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 406 if (nf & 0x100) { 407 nf = 0 - ((nf ^ 0x1ff) + 1); 408 } 409 return (OS_REG_READ(ah, AR_TSF_U32) ^ 410 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 411 } 412 413 /* 414 * Detect if our card is present 415 */ 416 HAL_BOOL 417 ar9300_detect_card_present(struct ath_hal *ah) 418 { 419 u_int16_t mac_version, mac_rev; 420 u_int32_t v; 421 422 /* 423 * Read the Silicon Revision register and compare that 424 * to what we read at attach time. If the same, we say 425 * a card/device is present. 426 */ 427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 428 if (v == 0xFF) { 429 /* new SREV format */ 430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 431 /* 432 * Include 6-bit Chip Type (masked to 0) to differentiate 433 * from pre-Sowl versions 434 */ 435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 436 mac_rev = MS(v, AR_SREV_REVISION2); 437 } else { 438 mac_version = MS(v, AR_SREV_VERSION); 439 mac_rev = v & AR_SREV_REVISION; 440 } 441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 442 AH_PRIVATE(ah)->ah_macRev == mac_rev); 443 } 444 445 /* 446 * Update MIB Counters 447 */ 448 void 449 ar9300_update_mib_mac_stats(struct ath_hal *ah) 450 { 451 struct ath_hal_9300 *ahp = AH9300(ah); 452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 453 454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 459 } 460 461 void 462 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 463 { 464 struct ath_hal_9300 *ahp = AH9300(ah); 465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 466 467 stats->ackrcv_bad = istats->ackrcv_bad; 468 stats->rts_bad = istats->rts_bad; 469 stats->fcs_bad = istats->fcs_bad; 470 stats->rts_good = istats->rts_good; 471 stats->beacons = istats->beacons; 472 } 473 474 /* 475 * Detect if the HW supports spreading a CCK signal on channel 14 476 */ 477 HAL_BOOL 478 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 479 { 480 return AH_TRUE; 481 } 482 483 /* 484 * Get the rssi of frame curently being received. 485 */ 486 u_int32_t 487 ar9300_get_cur_rssi(struct ath_hal *ah) 488 { 489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 490 /* get combined RSSI */ 491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 492 } 493 494 #if ATH_GEN_RANDOMNESS 495 /* 496 * Get the rssi value from BB on ctl chain0. 497 */ 498 u_int32_t 499 ar9300_get_rssi_chain0(struct ath_hal *ah) 500 { 501 /* get ctl chain0 RSSI */ 502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 503 } 504 #endif 505 506 u_int 507 ar9300_get_def_antenna(struct ath_hal *ah) 508 { 509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 510 } 511 512 /* Setup coverage class */ 513 void 514 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 515 { 516 } 517 518 void 519 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 520 { 521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 522 } 523 524 HAL_BOOL 525 ar9300_set_antenna_switch(struct ath_hal *ah, 526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 528 { 529 struct ath_hal_9300 *ahp = AH9300(ah); 530 531 /* 532 * Owl does not support diversity or changing antennas. 533 * 534 * Instead this API and function are defined differently for AR9300. 535 * To support Tablet PC's, this interface allows the system 536 * to dramatically reduce the TX power on a particular chain. 537 * 538 * Based on the value of (redefined) diversity_control, the 539 * reset code will decrease power on chain 0 or chain 1/2. 540 * 541 * Based on the value of bit 0 of antenna_switch_swap, 542 * the mapping between OID call and chain is defined as: 543 * 0: map A -> 0, B -> 1; 544 * 1: map A -> 1, B -> 0; 545 * 546 * NOTE: 547 * The devices that use this OID should use a tx_chain_mask and 548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 549 * used in order to ensure an active transmit antenna. This 550 * API will allow the host to turn off the only transmitting 551 * antenna to ensure the antenna closest to the user's body is 552 * powered-down. 553 */ 554 /* 555 * Set antenna control for use during reset sequence by 556 * ar9300_decrease_chain_power() 557 */ 558 ahp->ah_diversity_control = settings; 559 560 return AH_TRUE; 561 } 562 563 HAL_BOOL 564 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 565 { 566 return AH_TRUE; 567 } 568 569 HAL_BOOL 570 ar9300_set_slot_time(struct ath_hal *ah, u_int us) 571 { 572 struct ath_hal_9300 *ahp = AH9300(ah); 573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 576 return AH_FALSE; 577 } else { 578 /* convert to system clocks */ 579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 580 ahp->ah_slot_time = us; 581 return AH_TRUE; 582 } 583 } 584 585 HAL_BOOL 586 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 587 { 588 struct ath_hal_9300 *ahp = AH9300(ah); 589 590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 593 return AH_FALSE; 594 } else { 595 /* convert to system clocks */ 596 OS_REG_RMW_FIELD(ah, 597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 598 ahp->ah_ack_timeout = us; 599 return AH_TRUE; 600 } 601 } 602 603 u_int 604 ar9300_get_ack_timeout(struct ath_hal *ah) 605 { 606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 608 } 609 610 HAL_STATUS 611 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 612 u_int32_t next_start, HAL_QUIET_FLAG flag) 613 { 614 #define TU_TO_USEC(_tu) ((_tu) << 10) 615 HAL_STATUS status = HAL_EIO; 616 u_int32_t tsf = 0, j, next_start_us = 0; 617 if (flag & HAL_QUIET_ENABLE) { 618 for (j = 0; j < 2; j++) { 619 next_start_us = TU_TO_USEC(next_start); 620 tsf = OS_REG_READ(ah, AR_TSF_L32); 621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 622 next_start_us += tsf; 623 } 624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 625 next_start_us += 626 ah->ah_config.ah_sw_beacon_response_time; 627 } 628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 634 status = HAL_OK; 635 break; 636 } 637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 639 /* TSF shouldn't count twice or reg access is taking forever */ 640 HALASSERT(j < 1); 641 } 642 } else { 643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 644 status = HAL_OK; 645 } 646 647 return status; 648 #undef TU_TO_USEC 649 } 650 #ifdef ATH_SUPPORT_DFS 651 void 652 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 653 { 654 u32 reg1, reg2; 655 656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 658 AH9300(ah)->ah_cac_quiet_enabled = enable; 659 660 if (enable) { 661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 662 reg1 | AR_PCU_FORCE_QUIET_COLL); 663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 665 } else { 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 667 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 670 } 671 } 672 #endif /* ATH_SUPPORT_DFS */ 673 674 void 675 ar9300_set_pcu_config(struct ath_hal *ah) 676 { 677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 678 } 679 680 HAL_STATUS 681 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 682 u_int32_t capability, u_int32_t *result) 683 { 684 struct ath_hal_9300 *ahp = AH9300(ah); 685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 686 struct ar9300_ani_state *ani; 687 688 switch (type) { 689 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 690 switch (capability) { 691 case HAL_CIPHER_AES_CCM: 692 case HAL_CIPHER_AES_OCB: 693 case HAL_CIPHER_TKIP: 694 case HAL_CIPHER_WEP: 695 case HAL_CIPHER_MIC: 696 case HAL_CIPHER_CLR: 697 return HAL_OK; 698 default: 699 return HAL_ENOTSUPP; 700 } 701 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 702 switch (capability) { 703 case 0: /* hardware capability */ 704 return HAL_OK; 705 case 1: 706 return (ahp->ah_sta_id1_defaults & 707 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 708 default: 709 return HAL_ENOTSUPP; 710 } 711 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 712 switch (capability) { 713 case 0: /* hardware capability */ 714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 715 case 1: /* current setting */ 716 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 717 HAL_ENXIO : HAL_OK; 718 default: 719 return HAL_ENOTSUPP; 720 } 721 case HAL_CAP_WME_TKIPMIC: 722 /* hardware can do TKIP MIC when WMM is turned on */ 723 return HAL_OK; 724 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 725 return HAL_OK; 726 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 727 switch (capability) { 728 case 0: /* hardware capability */ 729 return HAL_OK; 730 case 1: /* current setting */ 731 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 732 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 733 HAL_OK : HAL_ENXIO; 734 } 735 return HAL_EINVAL; 736 case HAL_CAP_TPC: 737 switch (capability) { 738 case 0: /* hardware capability */ 739 return HAL_OK; 740 case 1: 741 return ah->ah_config.ath_hal_desc_tpc ? 742 HAL_OK : HAL_ENXIO; 743 } 744 return HAL_OK; 745 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 746 return HAL_OK; 747 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 748 switch (capability) { 749 case 0: /* hardware capability */ 750 return HAL_OK; 751 case 1: 752 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 753 /* 754 * Owl and Merlin have problems in mcast key search. 755 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 756 * 26802 757 */ 758 return HAL_ENXIO; 759 } else { 760 return (ahp->ah_sta_id1_defaults & 761 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 762 } 763 } 764 return HAL_EINVAL; 765 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 766 switch (capability) { 767 case 0: /* hardware capability */ 768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 769 case 1: 770 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 771 HAL_OK : HAL_ENXIO; 772 } 773 return HAL_EINVAL; 774 case HAL_CAP_RFSILENT: /* rfsilent support */ 775 if (capability == 3) { /* rfkill interrupt */ 776 /* 777 * XXX: Interrupt-based notification of RF Kill state 778 * changes not working yet. Report that this feature 779 * is not supported so that polling is used instead. 780 */ 781 return (HAL_ENOTSUPP); 782 } 783 return ath_hal_getcapability(ah, type, capability, result); 784 case HAL_CAP_4ADDR_AGGR: 785 return HAL_OK; 786 case HAL_CAP_BB_RIFS_HANG: 787 return HAL_ENOTSUPP; 788 case HAL_CAP_BB_DFS_HANG: 789 return HAL_ENOTSUPP; 790 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 791 /* Track chips that are known to have BB hangs related 792 * to rx_clear stuck low. 793 */ 794 return HAL_ENOTSUPP; 795 case HAL_CAP_MAC_HANG: 796 /* Track chips that are known to have MAC hangs. 797 */ 798 return HAL_OK; 799 case HAL_CAP_RIFS_RX_ENABLED: 800 /* Is RIFS RX currently enabled */ 801 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 802 #if 0 803 case HAL_CAP_ANT_CFG_2GHZ: 804 *result = p_cap->halNumAntCfg2Ghz; 805 return HAL_OK; 806 case HAL_CAP_ANT_CFG_5GHZ: 807 *result = p_cap->halNumAntCfg5Ghz; 808 return HAL_OK; 809 case HAL_CAP_RX_STBC: 810 *result = p_cap->hal_rx_stbc_support; 811 return HAL_OK; 812 case HAL_CAP_TX_STBC: 813 *result = p_cap->hal_tx_stbc_support; 814 return HAL_OK; 815 #endif 816 case HAL_CAP_LDPC: 817 *result = p_cap->halLDPCSupport; 818 return HAL_OK; 819 case HAL_CAP_DYNAMIC_SMPS: 820 return HAL_OK; 821 case HAL_CAP_DS: 822 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 823 (p_cap->halTxChainMask & 0x3) != 0x3 || 824 (p_cap->halRxChainMask & 0x3) != 0x3) ? 825 HAL_ENOTSUPP : HAL_OK; 826 case HAL_CAP_TS: 827 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 828 (p_cap->halTxChainMask & 0x7) != 0x7 || 829 (p_cap->halRxChainMask & 0x7) != 0x7) ? 830 HAL_ENOTSUPP : HAL_OK; 831 case HAL_CAP_OL_PWRCTRL: 832 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 833 HAL_OK : HAL_ENOTSUPP; 834 case HAL_CAP_CRDC: 835 #if ATH_SUPPORT_CRDC 836 return (AR_SREV_WASP(ah) && 837 ah->ah_config.ath_hal_crdc_enable) ? 838 HAL_OK : HAL_ENOTSUPP; 839 #else 840 return HAL_ENOTSUPP; 841 #endif 842 #if 0 843 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 844 *result = (u_int32_t)(-1); 845 return HAL_OK; 846 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849 #endif 850 case HAL_CAP_BB_PANIC_WATCHDOG: 851 return HAL_OK; 852 case HAL_CAP_PHYRESTART_CLR_WAR: 853 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 854 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 855 { 856 return HAL_OK; 857 } 858 else 859 { 860 return HAL_ENOTSUPP; 861 } 862 case HAL_CAP_ENTERPRISE_MODE: 863 *result = ahp->ah_enterprise_mode >> 16; 864 /* 865 * WAR for EV 77658 - Add delimiters to first sub-frame when using 866 * RTS/CTS with aggregation and non-enterprise Osprey. 867 * 868 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 869 */ 870 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 871 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 872 AR_SREV_WASP_10(ah))) { 873 *result |= AH_ENT_RTSCTS_DELIM_WAR; 874 } 875 return HAL_OK; 876 case HAL_CAP_LDPCWAR: 877 /* WAR for RIFS+LDPC issue is required for all chips currently 878 * supported by ar9300 HAL. 879 */ 880 return HAL_OK; 881 case HAL_CAP_ENABLE_APM: 882 *result = p_cap->halApmEnable; 883 return HAL_OK; 884 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 886 case HAL_CAP_PCIE_LCR_OFFSET: 887 *result = p_cap->hal_pcie_lcr_offset; 888 return HAL_OK; 889 case HAL_CAP_SMARTANTENNA: 890 /* FIXME A request is pending with h/w team to add feature bit in 891 * caldata to detect if board has smart antenna or not, once added 892 * we need to fix his piece of code to read and return value without 893 * any compile flags 894 */ 895 #if UMAC_SUPPORT_SMARTANTENNA 896 /* enable smart antenna for Peacock, Wasp and scorpion 897 for future chips need to modify */ 898 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 899 return HAL_OK; 900 } else { 901 return HAL_ENOTSUPP; 902 } 903 #else 904 return HAL_ENOTSUPP; 905 #endif 906 907 #ifdef ATH_TRAFFIC_FAST_RECOVER 908 case HAL_CAP_TRAFFIC_FAST_RECOVER: 909 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 910 return HAL_OK; 911 } else { 912 return HAL_ENOTSUPP; 913 } 914 #endif 915 916 /* FreeBSD ANI */ 917 case HAL_CAP_INTMIT: /* interference mitigation */ 918 switch (capability) { 919 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 920 return HAL_OK; 921 case HAL_CAP_INTMIT_ENABLE: 922 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 923 HAL_OK : HAL_ENXIO; 924 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 925 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 926 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 927 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 928 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 929 ani = ar9300_ani_get_current_state(ah); 930 if (ani == AH_NULL) 931 return HAL_ENXIO; 932 switch (capability) { 933 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 934 case 2: *result = ani->ofdm_noise_immunity_level; break; 935 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 936 // case 4: *result = ani->cck_weak_sig_threshold; break; 937 case 5: *result = ani->firstep_level; break; 938 case 6: *result = ani->spur_immunity_level; break; 939 } 940 return HAL_OK; 941 } 942 return HAL_EINVAL; 943 default: 944 return ath_hal_getcapability(ah, type, capability, result); 945 } 946 } 947 948 HAL_BOOL 949 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 950 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 951 { 952 struct ath_hal_9300 *ahp = AH9300(ah); 953 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 954 u_int32_t v; 955 956 switch (type) { 957 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 958 if (! p_cap->halTkipMicTxRxKeySupport) 959 return AH_FALSE; 960 961 if (setting) 962 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 963 else 964 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 965 966 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 967 return AH_TRUE; 968 969 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 970 if (setting) { 971 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 972 } else { 973 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 974 } 975 return AH_TRUE; 976 case HAL_CAP_DIVERSITY: 977 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 978 if (setting) { 979 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 980 } else { 981 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 982 } 983 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 984 return AH_TRUE; 985 case HAL_CAP_DIAG: /* hardware diagnostic support */ 986 /* 987 * NB: could split this up into virtual capabilities, 988 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 989 * seems worth the additional complexity. 990 */ 991 #ifdef AH_DEBUG 992 AH_PRIVATE(ah)->ah_diagreg = setting; 993 #else 994 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 995 #endif 996 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 997 return AH_TRUE; 998 case HAL_CAP_TPC: 999 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1000 return AH_TRUE; 1001 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1002 if (setting) { 1003 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1004 } else { 1005 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1006 } 1007 return AH_TRUE; 1008 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1009 if (p_cap->halTsfAddSupport) { 1010 if (setting) { 1011 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1012 } else { 1013 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1014 } 1015 return AH_TRUE; 1016 } 1017 return AH_FALSE; 1018 1019 /* FreeBSD interrupt mitigation / ANI */ 1020 case HAL_CAP_INTMIT: { /* interference mitigation */ 1021 /* This maps the public ANI commands to the internal ANI commands */ 1022 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1023 static const HAL_ANI_CMD cmds[] = { 1024 HAL_ANI_PRESENT, 1025 HAL_ANI_MODE, 1026 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1027 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1028 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1029 HAL_ANI_FIRSTEP_LEVEL, 1030 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1031 }; 1032 #define N(a) (sizeof(a) / sizeof(a[0])) 1033 return capability < N(cmds) ? 1034 ar9300_ani_control(ah, cmds[capability], setting) : 1035 AH_FALSE; 1036 #undef N 1037 } 1038 1039 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1040 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1041 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1042 return AH_TRUE; 1043 1044 /* fall thru... */ 1045 default: 1046 return ath_hal_setcapability(ah, type, capability, setting, status); 1047 } 1048 } 1049 1050 #ifdef AH_DEBUG 1051 static void 1052 ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1053 { 1054 u_int32_t i = 0; 1055 1056 /* Read 0x80d0 to trigger pcie analyzer */ 1057 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1058 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1059 1060 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1061 struct ath_hal_9300 *ahp = AH9300(ah); 1062 u_int32_t tf, rf, rc, cc; 1063 1064 tf = OS_REG_READ(ah, AR_TFCNT); 1065 rf = OS_REG_READ(ah, AR_RFCNT); 1066 rc = OS_REG_READ(ah, AR_RCCNT); 1067 cc = OS_REG_READ(ah, AR_CCCNT); 1068 1069 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1070 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1071 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1072 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1073 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1074 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1075 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1076 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1077 1078 ahp->last_tf = tf; 1079 ahp->last_rf = rf; 1080 ahp->last_rc = rc; 1081 ahp->last_cc = cc; 1082 1083 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1084 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1085 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1086 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1087 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1088 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1089 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1090 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1091 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1092 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1093 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1094 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1095 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1096 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1097 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1098 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1099 } 1100 1101 if (args & HAL_DIAG_PRINT_REG_ALL) { 1102 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1103 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1104 i, OS_REG_READ(ah, i)); 1105 } 1106 1107 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1109 i, OS_REG_READ(ah, i)); 1110 } 1111 1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1113 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1114 1115 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1116 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1117 1118 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1119 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1120 i, OS_REG_READ(ah, i)); 1121 } 1122 1123 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1124 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1125 i, OS_REG_READ(ah, i)); 1126 } 1127 1128 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1130 i, OS_REG_READ(ah, i)); 1131 } 1132 1133 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1135 i, OS_REG_READ(ah, i)); 1136 } 1137 1138 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1139 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1140 i, OS_REG_READ(ah, i)); 1141 } 1142 1143 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1144 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1145 i, OS_REG_READ(ah, i)); 1146 } 1147 1148 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1149 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1150 i, OS_REG_READ(ah, i)); 1151 } 1152 1153 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1154 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1155 i, OS_REG_READ(ah, i)); 1156 } 1157 1158 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1159 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1160 i, OS_REG_READ(ah, i)); 1161 } 1162 1163 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1164 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1165 i, OS_REG_READ(ah, i)); 1166 } 1167 1168 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1169 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1170 i, OS_REG_READ(ah, i)); 1171 } 1172 } 1173 } 1174 #endif 1175 1176 HAL_BOOL 1177 ar9300_get_diag_state(struct ath_hal *ah, int request, 1178 const void *args, u_int32_t argsize, 1179 void **result, u_int32_t *resultsize) 1180 { 1181 struct ath_hal_9300 *ahp = AH9300(ah); 1182 struct ar9300_ani_state *ani; 1183 1184 (void) ahp; 1185 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1186 return AH_TRUE; 1187 } 1188 switch (request) { 1189 #ifdef AH_PRIVATE_DIAG 1190 case HAL_DIAG_EEPROM: 1191 *result = &ahp->ah_eeprom; 1192 *resultsize = sizeof(ar9300_eeprom_t); 1193 return AH_TRUE; 1194 1195 #if 0 /* XXX - TODO */ 1196 case HAL_DIAG_EEPROM_EXP_11A: 1197 case HAL_DIAG_EEPROM_EXP_11B: 1198 case HAL_DIAG_EEPROM_EXP_11G: 1199 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1200 *result = pe->p_channels; 1201 *resultsize = (*result == AH_NULL) ? 0 : 1202 roundup(sizeof(u_int16_t) * pe->num_channels, 1203 sizeof(u_int32_t)) + 1204 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1205 return AH_TRUE; 1206 #endif 1207 case HAL_DIAG_RFGAIN: 1208 *result = &ahp->ah_gain_values; 1209 *resultsize = sizeof(GAIN_VALUES); 1210 return AH_TRUE; 1211 case HAL_DIAG_RFGAIN_CURSTEP: 1212 *result = (void *) ahp->ah_gain_values.curr_step; 1213 *resultsize = (*result == AH_NULL) ? 1214 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1215 return AH_TRUE; 1216 #if 0 /* XXX - TODO */ 1217 case HAL_DIAG_PCDAC: 1218 *result = ahp->ah_pcdac_table; 1219 *resultsize = ahp->ah_pcdac_table_size; 1220 return AH_TRUE; 1221 #endif 1222 case HAL_DIAG_ANI_CURRENT: 1223 1224 ani = ar9300_ani_get_current_state(ah); 1225 if (ani == AH_NULL) 1226 return AH_FALSE; 1227 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1228 /* XXX TODO: add all of these to the HAL ANI state structure */ 1229 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1230 /* XXX should this be OFDM or CCK noise immunity level? */ 1231 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1232 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1233 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1234 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1235 /* mrc_cck_off */ 1236 /* cck_noise_immunity_level */ 1237 1238 ahp->ext_ani_state.listenTime = ani->listen_time; 1239 1240 *result = &ahp->ext_ani_state; 1241 *resultsize = sizeof(ahp->ext_ani_state); 1242 #if 0 1243 *result = ar9300_ani_get_current_state(ah); 1244 *resultsize = (*result == AH_NULL) ? 1245 0 : sizeof(struct ar9300_ani_state); 1246 #endif 1247 return AH_TRUE; 1248 case HAL_DIAG_ANI_STATS: 1249 *result = ar9300_ani_get_current_stats(ah); 1250 *resultsize = (*result == AH_NULL) ? 1251 0 : sizeof(HAL_ANI_STATS); 1252 return AH_TRUE; 1253 case HAL_DIAG_ANI_CMD: 1254 if (argsize != 2*sizeof(u_int32_t)) { 1255 return AH_FALSE; 1256 } 1257 ar9300_ani_control( 1258 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1259 return AH_TRUE; 1260 #if 0 1261 case HAL_DIAG_TXCONT: 1262 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1263 return AH_TRUE; 1264 #endif /* 0 */ 1265 #endif /* AH_PRIVATE_DIAG */ 1266 case HAL_DIAG_CHANNELS: 1267 #if 0 1268 *result = &(ahp->ah_priv.ah_channels[0]); 1269 *resultsize = 1270 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1271 #endif 1272 return AH_TRUE; 1273 #ifdef AH_DEBUG 1274 case HAL_DIAG_PRINT_REG: 1275 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1276 return AH_TRUE; 1277 #endif 1278 default: 1279 break; 1280 } 1281 1282 return AH_FALSE; 1283 } 1284 1285 void 1286 ar9300_dma_reg_dump(struct ath_hal *ah) 1287 { 1288 #ifdef AH_DEBUG 1289 #define NUM_DMA_DEBUG_REGS 8 1290 #define NUM_QUEUES 10 1291 1292 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1293 int qcu_offset = 0, dcu_offset = 0; 1294 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1295 int i, j, k; 1296 int16_t nfarray[HAL_NUM_NF_READINGS]; 1297 #ifdef ATH_NF_PER_CHAN 1298 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1299 #endif /* ATH_NF_PER_CHAN */ 1300 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1301 1302 /* selecting DMA OBS 8 */ 1303 OS_REG_WRITE(ah, AR_MACMISC, 1304 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1305 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1306 1307 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1308 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1309 if (i % 4 == 0) { 1310 ath_hal_printf(ah, "\n"); 1311 } 1312 1313 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1314 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1315 } 1316 1317 ath_hal_printf(ah, "\n\n"); 1318 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1319 1320 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1321 if (i == 8) { 1322 /* only 8 QCU entries in val[0] */ 1323 qcu_offset = 0; 1324 qcu_base++; 1325 } 1326 1327 if (i == 6) { 1328 /* only 6 DCU entries in val[4] */ 1329 dcu_offset = 0; 1330 dcu_base++; 1331 } 1332 1333 ath_hal_printf(ah, 1334 "%2d %2x %1x %2x %2x\n", 1335 i, 1336 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1337 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1338 val[2] & (0x7 << (i * 3)) >> (i * 3), 1339 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1340 } 1341 1342 ath_hal_printf(ah, "\n"); 1343 ath_hal_printf(ah, 1344 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1345 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1346 ath_hal_printf(ah, 1347 "qcu_complete state: %2x dcu_complete state: %2x\n", 1348 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1349 ath_hal_printf(ah, 1350 "dcu_arb state: %2x dcu_fp state: %2x\n", 1351 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1352 ath_hal_printf(ah, 1353 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1354 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1355 ath_hal_printf(ah, 1356 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1357 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1358 ath_hal_printf(ah, 1359 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1360 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1361 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1362 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1363 1364 ar9300_upload_noise_floor(ah, 1, nfarray); 1365 ath_hal_printf(ah, "2G:\n"); 1366 ath_hal_printf(ah, "Min CCA Out:\n"); 1367 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1368 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1369 nfarray[0], nfarray[1], nfarray[2]); 1370 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1371 nfarray[3], nfarray[4], nfarray[5]); 1372 1373 ar9300_upload_noise_floor(ah, 0, nfarray); 1374 ath_hal_printf(ah, "5G:\n"); 1375 ath_hal_printf(ah, "Min CCA Out:\n"); 1376 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1377 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1378 nfarray[0], nfarray[1], nfarray[2]); 1379 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1380 nfarray[3], nfarray[4], nfarray[5]); 1381 1382 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1383 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1384 ((i < 3) ? "Control " : "Extension "), i%3); 1385 for (j = 0, k = h->base.curr_index; 1386 j < HAL_NF_CAL_HIST_LEN_FULL; 1387 j++, k++) { 1388 ath_hal_printf(ah, "Element %d: %d\n", 1389 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1390 } 1391 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1392 } 1393 1394 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1395 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1396 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1397 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1398 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1399 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1400 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1401 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1402 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1403 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1404 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1405 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1406 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1407 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1408 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1409 reg = OS_REG_READ(ah, AR_PHY_AGC); 1410 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1411 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1412 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1413 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1414 MS(reg, AR_PHY_AGC_COARSE_LOW), 1415 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1416 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1417 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1418 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1419 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1420 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1421 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1422 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1423 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1424 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1425 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1426 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1427 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1428 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1429 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1430 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1431 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1432 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1433 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1434 1435 1436 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1437 reg = OS_REG_READ(ah, 0xa360); 1438 reg &= ~0x00800000; 1439 OS_REG_WRITE(ah, 0xa360, reg); 1440 1441 /* Step 2a: Set register 0xa364 to 0x1000 */ 1442 reg = 0x1000; 1443 OS_REG_WRITE(ah, 0xa364, reg); 1444 1445 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1446 reg = OS_REG_READ(ah, 0x9c20); 1447 reg &= 0x0003ffff; 1448 ath_hal_printf(ah, 1449 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1450 __func__, reg); 1451 1452 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1453 reg = OS_REG_READ(ah, 0xa360); 1454 reg &= ~0x00800000; 1455 OS_REG_WRITE(ah, 0xa360, reg); 1456 1457 /* Step 2b: Set register 0xa364 to 0x1400 */ 1458 reg = 0x1400; 1459 OS_REG_WRITE(ah, 0xa364, reg); 1460 1461 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1462 reg = OS_REG_READ(ah, 0x9c20); 1463 reg &= 0x0003ffff; 1464 ath_hal_printf(ah, 1465 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1466 __func__, reg); 1467 1468 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1469 reg = OS_REG_READ(ah, 0xa360); 1470 reg &= ~0x00800000; 1471 OS_REG_WRITE(ah, 0xa360, reg); 1472 1473 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1474 reg = 0x3c00; 1475 OS_REG_WRITE(ah, 0xa364, reg); 1476 1477 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1478 reg = OS_REG_READ(ah, 0x9c20); 1479 reg &= 0x0003ffff; 1480 ath_hal_printf(ah, 1481 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1482 __func__, reg); 1483 1484 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1485 reg = OS_REG_READ(ah, 0xa360); 1486 reg &= ~0x001040000; 1487 OS_REG_WRITE(ah, 0xa360, reg); 1488 1489 /* Step 2d: Set register 0xa364 to 0x5005D */ 1490 reg = 0x5005D; 1491 OS_REG_WRITE(ah, 0xa364, reg); 1492 1493 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1494 reg = OS_REG_READ(ah, 0xa368); 1495 reg &= 0x0003ffff; 1496 ath_hal_printf(ah, 1497 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1498 __func__, reg); 1499 1500 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1501 reg = OS_REG_READ(ah, 0xa360); 1502 reg &= ~0x001040000; 1503 OS_REG_WRITE(ah, 0xa360, reg); 1504 1505 /* Step 2e: Set register 0xa364 to 0x7005D */ 1506 reg = 0x7005D; 1507 OS_REG_WRITE(ah, 0xa364, reg); 1508 1509 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1510 reg = OS_REG_READ(ah, 0xa368); 1511 reg &= 0x0003ffff; 1512 ath_hal_printf(ah, 1513 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1514 __func__, reg); 1515 1516 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1517 reg = OS_REG_READ(ah, 0xa360); 1518 reg &= ~0x001000000; 1519 reg |= 0x40000; 1520 OS_REG_WRITE(ah, 0xa360, reg); 1521 1522 /* Step 2f: Set register 0xa364 to 0x3005D */ 1523 reg = 0x3005D; 1524 OS_REG_WRITE(ah, 0xa364, reg); 1525 1526 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1527 reg = OS_REG_READ(ah, 0xa368); 1528 reg &= 0x0003ffff; 1529 ath_hal_printf(ah, 1530 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1531 __func__, reg); 1532 1533 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1534 reg = OS_REG_READ(ah, 0xa360); 1535 reg &= ~0x001000000; 1536 reg |= 0x40000; 1537 OS_REG_WRITE(ah, 0xa360, reg); 1538 1539 /* Step 2g: Set register 0xa364 to 0x6005D */ 1540 reg = 0x6005D; 1541 OS_REG_WRITE(ah, 0xa364, reg); 1542 1543 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1544 reg = OS_REG_READ(ah, 0xa368); 1545 reg &= 0x0003ffff; 1546 ath_hal_printf(ah, 1547 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1548 __func__, reg); 1549 #endif /* AH_DEBUG */ 1550 } 1551 1552 /* 1553 * Return the busy for rx_frame, rx_clear, and tx_frame 1554 */ 1555 u_int32_t 1556 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1557 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1558 { 1559 struct ath_hal_9300 *ahp = AH9300(ah); 1560 u_int32_t good = 1; 1561 1562 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1563 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1564 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1565 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1566 1567 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1568 /* 1569 * Cycle counter wrap (or initial call); it's not possible 1570 * to accurately calculate a value because the registers 1571 * right shift rather than wrap--so punt and return 0. 1572 */ 1573 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1574 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1575 good = 0; 1576 } else { 1577 u_int32_t cc_d = cc - ahp->ah_cycles; 1578 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1579 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1580 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1581 1582 if (cc_d != 0) { 1583 *rxc_pcnt = rc_d * 100 / cc_d; 1584 *rxf_pcnt = rf_d * 100 / cc_d; 1585 *txf_pcnt = tf_d * 100 / cc_d; 1586 } else { 1587 good = 0; 1588 } 1589 } 1590 1591 ahp->ah_cycles = cc; 1592 ahp->ah_rx_frame = rf; 1593 ahp->ah_rx_clear = rc; 1594 ahp->ah_tx_frame = tf; 1595 1596 return good; 1597 } 1598 1599 /* 1600 * Return approximation of extension channel busy over an time interval 1601 * 0% (clear) -> 100% (busy) 1602 * -1 for invalid estimate 1603 */ 1604 uint32_t 1605 ar9300_get_11n_ext_busy(struct ath_hal *ah) 1606 { 1607 /* 1608 * Overflow condition to check before multiplying to get % 1609 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1610 */ 1611 #define OVERFLOW_LIMIT 0x28F5C28 1612 #define ERROR_CODE -1 1613 1614 struct ath_hal_9300 *ahp = AH9300(ah); 1615 u_int32_t busy = 0; /* percentage */ 1616 int8_t busyper = 0; 1617 u_int32_t cycle_count, ctl_busy, ext_busy; 1618 1619 /* cycle_count will always be the first to wrap; therefore, read it last 1620 * This sequence of reads is not atomic, and MIB counter wrap 1621 * could happen during it ? 1622 */ 1623 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1624 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1625 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1626 1627 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1628 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1629 { 1630 /* 1631 * Cycle counter wrap (or initial call); it's not possible 1632 * to accurately calculate a value because the registers 1633 * right shift rather than wrap--so punt and return 0. 1634 */ 1635 busyper = ERROR_CODE; 1636 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1637 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1638 } else { 1639 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1640 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1641 1642 /* 1643 * Compute extension channel busy percentage 1644 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1645 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1646 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1647 * and shift necessitated by large ext_busy_delta. 1648 * Due to timing difference to read the registers and counter overflow, 1649 * it may still happen that cycle_delta >> 7 = 0. 1650 * 1651 */ 1652 if (cycle_delta) { 1653 if (ext_busy_delta > OVERFLOW_LIMIT) { 1654 if (cycle_delta >> 7) { 1655 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1656 } else { 1657 busyper = ERROR_CODE; 1658 } 1659 } else { 1660 busy = (ext_busy_delta * 100) / cycle_delta; 1661 } 1662 } else { 1663 busyper = ERROR_CODE; 1664 } 1665 1666 if (busy > 100) { 1667 busy = 100; 1668 } 1669 if ( busyper != ERROR_CODE ) { 1670 busyper = busy; 1671 } 1672 } 1673 1674 ahp->ah_cycle_count = cycle_count; 1675 ahp->ah_ctl_busy = ctl_busy; 1676 ahp->ah_ext_busy = ext_busy; 1677 1678 return busyper; 1679 #undef OVERFLOW_LIMIT 1680 #undef ERROR_CODE 1681 } 1682 1683 /* BB Panic Watchdog declarations */ 1684 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1685 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1686 1687 void 1688 ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1689 { 1690 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1691 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1692 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1693 u_int32_t val, idle_count; 1694 1695 if (idle_tmo_ms != 0) { 1696 /* enable IRQ, disable chip-reset for BB panic */ 1697 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1698 AR_PHY_BB_PANIC_CNTL2_MASK; 1699 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1700 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1701 /* bound limit to 10 secs */ 1702 if (idle_tmo_ms > 10000) { 1703 idle_tmo_ms = 10000; 1704 } 1705 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1706 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1707 } else { 1708 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1709 } 1710 /* 1711 * enable panic in non-IDLE mode, 1712 * disable in IDLE mode, 1713 * set idle time-out 1714 */ 1715 1716 // EV92527 : Enable IDLE mode panic 1717 1718 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1719 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1720 AR_PHY_BB_PANIC_IDLE_ENABLE | 1721 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1722 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1723 } else { 1724 /* disable IRQ, disable chip-reset for BB panic */ 1725 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1726 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1727 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1728 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1729 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1730 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1731 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1732 } 1733 1734 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1735 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1736 #undef HAL_BB_PANIC_IDLE_TIME_OUT 1737 } 1738 1739 1740 void 1741 ar9300_handle_bb_panic(struct ath_hal *ah) 1742 { 1743 u_int32_t status; 1744 /* 1745 * we want to avoid printing in ISR context so we save 1746 * panic watchdog status to be printed later in DPC context 1747 */ 1748 AH9300(ah)->ah_bb_panic_last_status = status = 1749 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1750 /* 1751 * panic watchdog timer should reset on status read 1752 * but to make sure we write 0 to the watchdog status bit 1753 */ 1754 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1755 } 1756 1757 int 1758 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1759 { 1760 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1761 1762 /* 1763 * For signature 04000539 do not print anything. 1764 * This is a very common occurence as a compromise between 1765 * BB Panic and AH_FALSE detects (EV71009). It indicates 1766 * radar hang, which can be cleared by reprogramming 1767 * radar related register and does not requre a chip reset 1768 */ 1769 1770 /* Suppress BB Status mesg following signature */ 1771 switch (bb_panic->status) { 1772 case 0x04000539: 1773 case 0x04008009: 1774 case 0x04000b09: 1775 case 0x1300000a: 1776 return -1; 1777 } 1778 1779 bb_panic->tsf = ar9300_get_tsf32(ah); 1780 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1781 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1782 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1783 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1784 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1785 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1786 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1787 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1788 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1789 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1790 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1791 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1792 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1793 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1794 &bb_panic->rxc_pcnt, 1795 &bb_panic->rxf_pcnt, 1796 &bb_panic->txf_pcnt); 1797 1798 if (ah->ah_config.ath_hal_show_bb_panic) { 1799 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1800 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1801 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1802 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1803 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1804 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1805 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1806 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1807 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1808 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1809 bb_panic->phy_gen_ctrl); 1810 if (bb_panic->cycles) { 1811 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1812 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1813 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1814 } 1815 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1816 } 1817 1818 return 0; //The returned data will be stored for athstats to retrieve it 1819 } 1820 1821 /* set the reason for HAL reset */ 1822 void 1823 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1824 { 1825 AH9300(ah)->ah_reset_reason = resetreason; 1826 } 1827 1828 /* 1829 * Configure 20/40 operation 1830 * 1831 * 20/40 = joint rx clear (control and extension) 1832 * 20 = rx clear (control) 1833 * 1834 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1835 * when changing from 20/40 => 20 only 1836 */ 1837 void 1838 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1839 { 1840 u_int32_t macmode; 1841 1842 /* Configure MAC for 20/40 operation */ 1843 if (mode == HAL_HT_MACMODE_2040 && 1844 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1845 macmode = AR_2040_JOINED_RX_CLEAR; 1846 } else { 1847 macmode = 0; 1848 } 1849 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1850 } 1851 1852 /* 1853 * Get Rx clear (control/extension channel) 1854 * 1855 * Returns active low (busy) for ctrl/ext channel 1856 * Owl 2.0 1857 */ 1858 HAL_HT_RXCLEAR 1859 ar9300_get_11n_rx_clear(struct ath_hal *ah) 1860 { 1861 HAL_HT_RXCLEAR rxclear = 0; 1862 u_int32_t val; 1863 1864 val = OS_REG_READ(ah, AR_DIAG_SW); 1865 1866 /* control channel */ 1867 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1868 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1869 } 1870 /* extension channel */ 1871 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1872 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1873 } 1874 return rxclear; 1875 } 1876 1877 /* 1878 * Set Rx clear (control/extension channel) 1879 * 1880 * Useful for forcing the channel to appear busy for 1881 * debugging/diagnostics 1882 * Owl 2.0 1883 */ 1884 void 1885 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1886 { 1887 /* control channel */ 1888 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1889 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1890 } else { 1891 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1892 } 1893 /* extension channel */ 1894 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1895 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1896 } else { 1897 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1898 } 1899 } 1900 1901 1902 /* 1903 * HAL support code for force ppm tracking workaround. 1904 */ 1905 1906 u_int32_t 1907 ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1908 { 1909 u_int32_t retval; 1910 u_int32_t off1; 1911 u_int32_t off2; 1912 1913 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1914 off1 = 0x2000; 1915 off2 = 0x1000; 1916 } else { 1917 off1 = 0x1000; 1918 off2 = 0x2000; 1919 } 1920 1921 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1922 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1923 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1924 1925 return retval; 1926 } 1927 1928 u_int32_t 1929 ar9300_ppm_force(struct ath_hal *ah) 1930 { 1931 u_int32_t data_fine; 1932 u_int32_t data4; 1933 //u_int32_t off1; 1934 //u_int32_t off2; 1935 HAL_BOOL signed_val = AH_FALSE; 1936 1937 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1938 // off1 = 0x2000; 1939 // off2 = 0x1000; 1940 // } else { 1941 // off1 = 0x1000; 1942 // off2 = 0x2000; 1943 // } 1944 data_fine = 1945 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1946 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1947 1948 /* 1949 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1950 * So check value from bit[10:0]. 1951 * Now get the abs val of the ppm value read in bit[0:11]. 1952 * After that do bound check on abs value. 1953 * if value is off limit, CAP the value and and restore signed bit. 1954 */ 1955 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1956 { 1957 /* get the positive value */ 1958 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1959 signed_val = AH_TRUE; 1960 } 1961 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1962 { 1963 HALDEBUG(ah, HAL_DEBUG_REGIO, 1964 "%s Correcting ppm out of range %x\n", 1965 __func__, (data_fine & 0x7ff)); 1966 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 1967 } 1968 /* 1969 * Restore signed value if changed above. 1970 * Use typecast to avoid compilation errors 1971 */ 1972 if (signed_val) { 1973 data_fine = (-(int32_t)data_fine) & 1974 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1975 } 1976 1977 /* write value */ 1978 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 1979 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1980 OS_REG_WRITE(ah, AR_PHY_TIMING2, 1981 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 1982 1983 return data_fine; 1984 } 1985 1986 void 1987 ar9300_ppm_un_force(struct ath_hal *ah) 1988 { 1989 u_int32_t data4; 1990 1991 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 1992 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 1993 } 1994 1995 u_int32_t 1996 ar9300_ppm_arm_trigger(struct ath_hal *ah) 1997 { 1998 u_int32_t val; 1999 u_int32_t ret; 2000 2001 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2002 ret = OS_REG_READ(ah, AR_TSF_L32); 2003 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2004 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2005 2006 /* return low word of TSF at arm time */ 2007 return ret; 2008 } 2009 2010 int 2011 ar9300_ppm_get_trigger(struct ath_hal *ah) 2012 { 2013 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2014 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2015 { 2016 /* has not triggered yet, return AH_FALSE */ 2017 return 0; 2018 } 2019 2020 /* else triggered, return AH_TRUE */ 2021 return 1; 2022 } 2023 2024 void 2025 ar9300_mark_phy_inactive(struct ath_hal *ah) 2026 { 2027 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2028 } 2029 2030 /* DEBUG */ 2031 u_int32_t 2032 ar9300_ppm_get_force_state(struct ath_hal *ah) 2033 { 2034 return 2035 OS_REG_READ(ah, AR_PHY_TIMING2) & 2036 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2037 } 2038 2039 /* 2040 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2041 */ 2042 HAL_BOOL 2043 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2044 { 2045 /* 2046 * XXX FreeBSD todo: reimplement this 2047 */ 2048 #if 0 2049 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2050 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2051 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2052 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2053 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2054 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2055 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2056 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2057 #endif 2058 return AH_FALSE; 2059 } 2060 2061 void 2062 ar9300_clear_mib_counters(struct ath_hal *ah) 2063 { 2064 u_int32_t reg_val; 2065 2066 reg_val = OS_REG_READ(ah, AR_MIBC); 2067 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2068 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2069 } 2070 2071 2072 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2073 HAL_BOOL 2074 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2075 { 2076 struct ath_hal_9300 *ahp = AH9300(ah); 2077 HAL_CHANNEL_INTERNAL *ichan = 2078 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2079 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2080 u_int32_t tmp = 0; 2081 2082 if (enable) { 2083 if (ahp->ah_rifs_enabled == AH_TRUE) { 2084 return AH_TRUE; 2085 } 2086 2087 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2088 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2089 ahp->ah_rifs_reg[1]); 2090 2091 ahp->ah_rifs_enabled = AH_TRUE; 2092 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2093 } else { 2094 if (ahp->ah_rifs_enabled == AH_TRUE) { 2095 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2096 AR_PHY_SEARCH_START_DELAY); 2097 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2098 } 2099 /* Change rifs init delay to 0 */ 2100 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2101 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2102 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2103 if (is_chan_2g) { 2104 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2105 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2106 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2107 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2108 } 2109 } else { 2110 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2111 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2112 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2113 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2114 } 2115 } 2116 2117 ahp->ah_rifs_enabled = AH_FALSE; 2118 } 2119 return AH_TRUE; 2120 2121 } /* ar9300_set_rifs_delay () */ 2122 2123 /* Set the current RIFS Rx setting */ 2124 HAL_BOOL 2125 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2126 { 2127 /* Non-Owl 11n chips */ 2128 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2129 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2130 return ar9300_set_rifs_delay(ah, enable); 2131 } 2132 return AH_FALSE; 2133 } 2134 2135 return AH_TRUE; 2136 } /* ar9300_set_11n_rx_rifs () */ 2137 2138 static hal_mac_hangs_t 2139 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2140 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2141 { 2142 int i = 0; 2143 hal_mac_hangs_t found_hangs = 0; 2144 2145 if (hangs & dcu_chain_state) { 2146 for (i = 0; i < 6; i++) { 2147 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2148 hang_check.dcu_chain_state) 2149 { 2150 found_hangs |= dcu_chain_state; 2151 *dcu_chain = i; 2152 } 2153 } 2154 for (i = 0; i < 4; i++) { 2155 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2156 hang_check.dcu_chain_state) 2157 { 2158 found_hangs |= dcu_chain_state; 2159 *dcu_chain = i + 6; 2160 } 2161 } 2162 } 2163 2164 if (hangs & dcu_complete_state) { 2165 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2166 found_hangs |= dcu_complete_state; 2167 } 2168 } 2169 2170 return found_hangs; 2171 2172 } /* end - ar9300_compare_dbg_hang */ 2173 2174 #define NUM_STATUS_READS 50 2175 HAL_BOOL 2176 ar9300_detect_mac_hang(struct ath_hal *ah) 2177 { 2178 struct ath_hal_9300 *ahp = AH9300(ah); 2179 mac_dbg_regs_t mac_dbg; 2180 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2181 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2182 int i = 0; 2183 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2184 2185 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2186 return AH_FALSE; 2187 } 2188 2189 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2190 2191 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2192 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2193 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2194 2195 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2196 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2197 mac_dbg.dma_dbg_6); 2198 2199 if (hang_sig1 != 2200 ar9300_compare_dbg_hang(ah, mac_dbg, 2201 hang_sig1_val, hang_sig1, &dcu_chain)) 2202 { 2203 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2204 return AH_FALSE; 2205 } 2206 2207 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2208 shift_val *= 5; 2209 2210 for (i = 1; i <= NUM_STATUS_READS; i++) { 2211 if (dcu_chain < 6) { 2212 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2213 current_dcu_chain_state = 2214 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2215 } else { 2216 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2217 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2218 } 2219 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2220 2221 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2222 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2223 return AH_FALSE; 2224 } 2225 } 2226 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2227 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2228 ahp->ah_hang[MAC_HANG_SIG1]++; 2229 return AH_TRUE; 2230 2231 } /* end - ar9300_detect_mac_hang */ 2232 2233 /* Determine if the baseband is hung by reading the Observation Bus Register */ 2234 HAL_BOOL 2235 ar9300_detect_bb_hang(struct ath_hal *ah) 2236 { 2237 #define N(a) (sizeof(a) / sizeof(a[0])) 2238 struct ath_hal_9300 *ahp = AH9300(ah); 2239 u_int32_t hang_sig = 0; 2240 int i = 0; 2241 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2242 * 2243 * 4 known BB hang signatures - 2244 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2245 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2246 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2247 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2248 * Rx State (bits 20-24) is 0x7. 2249 */ 2250 hal_hw_hang_check_t hang_list [] = 2251 { 2252 /* Offset Reg Value Reg Mask Hang Offset */ 2253 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2254 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2255 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2256 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2257 }; 2258 2259 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2260 HAL_DFS_BB_HANG_WAR | 2261 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2262 return AH_FALSE; 2263 } 2264 2265 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2266 for (i = 1; i <= NUM_STATUS_READS; i++) { 2267 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2268 return AH_FALSE; 2269 } 2270 } 2271 2272 for (i = 0; i < N(hang_list); i++) { 2273 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2274 ahp->ah_hang[hang_list[i].hang_offset]++; 2275 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2276 "sig3count=%d sig4count=%d\n", __func__, 2277 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2278 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2279 return AH_TRUE; 2280 } 2281 } 2282 2283 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2284 "<0x806c>=0x%x\n", __func__, hang_sig); 2285 2286 return AH_FALSE; 2287 2288 #undef N 2289 } /* end - ar9300_detect_bb_hang () */ 2290 2291 #undef NUM_STATUS_READS 2292 2293 HAL_STATUS 2294 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2295 { 2296 struct ath_hal_9300 *ahp = AH9300(ah); 2297 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2298 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2299 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2300 u_int16_t ant_config; 2301 u_int32_t hal_num_ant_config; 2302 2303 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2304 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2305 2306 if (cfg < hal_num_ant_config) { 2307 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2308 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2309 return HAL_OK; 2310 } 2311 } 2312 2313 return HAL_EINVAL; 2314 } 2315 2316 /* 2317 * Functions to get/set DCS mode 2318 */ 2319 void 2320 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2321 { 2322 AH9300(ah)->ah_dcs_enable = mode; 2323 } 2324 2325 u_int32_t 2326 ar9300_get_dcs_mode(struct ath_hal *ah) 2327 { 2328 return AH9300(ah)->ah_dcs_enable; 2329 } 2330 2331 #if ATH_BT_COEX 2332 void 2333 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2334 { 2335 struct ath_hal_9300 *ahp = AH9300(ah); 2336 2337 ahp->ah_bt_module = btinfo->bt_module; 2338 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2339 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2340 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2341 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2342 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2343 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2344 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2345 } 2346 2347 void 2348 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2349 { 2350 struct ath_hal_9300 *ahp = AH9300(ah); 2351 HAL_BOOL rx_clear_polarity; 2352 2353 /* 2354 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2355 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2356 */ 2357 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2358 2359 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2360 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2361 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2362 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2363 SM(btconf->bt_mode, AR_BT_MODE) | 2364 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2365 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2366 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2367 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2368 2369 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2370 2371 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2372 /* Enable ACK to go out even though BT has higher priority. */ 2373 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2374 } 2375 } 2376 2377 void 2378 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2379 { 2380 struct ath_hal_9300 *ahp = AH9300(ah); 2381 2382 /* clear the old value, then set the new value */ 2383 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2384 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2385 } 2386 2387 void 2388 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2389 { 2390 struct ath_hal_9300 *ahp = AH9300(ah); 2391 2392 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2393 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2394 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2395 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2396 2397 switch (stomp_type) { 2398 case HAL_BT_COEX_STOMP_ALL: 2399 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2400 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2401 break; 2402 case HAL_BT_COEX_STOMP_LOW: 2403 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2404 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2405 break; 2406 case HAL_BT_COEX_STOMP_ALL_FORCE: 2407 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2408 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2409 break; 2410 case HAL_BT_COEX_STOMP_LOW_FORCE: 2411 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2412 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2413 break; 2414 case HAL_BT_COEX_STOMP_NONE: 2415 case HAL_BT_COEX_NO_STOMP: 2416 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2417 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2418 break; 2419 default: 2420 /* There is a force_weight from registry */ 2421 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2422 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2423 break; 2424 } 2425 } 2426 2427 void 2428 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2429 { 2430 struct ath_hal_9300 *ahp = AH9300(ah); 2431 2432 /* clear the old value, then set the new value */ 2433 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2434 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2435 } 2436 2437 static void 2438 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2439 { 2440 struct ath_hal_9300 *ahp = AH9300(ah); 2441 #if ATH_ANT_DIV_COMB 2442 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2443 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2444 #endif 2445 2446 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2447 { 2448 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2449 { 2450 /* Config antenna diversity */ 2451 #if ATH_ANT_DIV_COMB 2452 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2453 #endif 2454 } 2455 } 2456 } 2457 2458 2459 void 2460 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2461 u_int32_t value) 2462 { 2463 struct ath_hal_9300 *ahp = AH9300(ah); 2464 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2465 2466 switch (type) { 2467 case HAL_BT_COEX_SET_ACK_PWR: 2468 if (value) { 2469 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2470 } else { 2471 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2472 } 2473 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2474 ahpriv->ah_extraTxPow, 0); 2475 break; 2476 2477 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2478 if (AR_SREV_POSEIDON(ah)) { 2479 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2480 if (value) { 2481 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2482 } 2483 else { 2484 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2485 } 2486 ar9300_bt_coex_antenna_diversity(ah, value); 2487 } 2488 break; 2489 case HAL_BT_COEX_LOWER_TX_PWR: 2490 if (value) { 2491 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2492 } 2493 else { 2494 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2495 } 2496 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2497 ahpriv->ah_extraTxPow, 0); 2498 break; 2499 #if ATH_SUPPORT_MCI 2500 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2501 if ((ah->ah_config.ath_hal_mci_config & 2502 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2503 { 2504 if (value) { 2505 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2506 ahp->ah_mci_concur_tx_en = AH_TRUE; 2507 } 2508 else { 2509 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2510 ahp->ah_mci_concur_tx_en = AH_FALSE; 2511 } 2512 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2513 ahpriv->ah_extraTxPow, 0); 2514 } 2515 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2516 ahp->ah_mci_concur_tx_en); 2517 break; 2518 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2519 if (value) { 2520 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2521 } 2522 else { 2523 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2524 } 2525 break; 2526 #endif 2527 default: 2528 break; 2529 } 2530 } 2531 2532 void 2533 ar9300_bt_coex_disable(struct ath_hal *ah) 2534 { 2535 struct ath_hal_9300 *ahp = AH9300(ah); 2536 2537 /* Always drive rx_clear_external output as 0 */ 2538 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2539 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2540 2541 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2542 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2543 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2544 } 2545 2546 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2547 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2548 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2549 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2550 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2551 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2552 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2553 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2554 2555 ahp->ah_bt_coex_enabled = AH_FALSE; 2556 } 2557 2558 int 2559 ar9300_bt_coex_enable(struct ath_hal *ah) 2560 { 2561 struct ath_hal_9300 *ahp = AH9300(ah); 2562 2563 /* Program coex mode and weight registers to actually enable coex */ 2564 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2565 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2566 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2567 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2568 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2569 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2570 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2571 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2572 2573 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2574 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2575 } else { 2576 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2577 } 2578 2579 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2580 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2581 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2582 } else { 2583 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2584 } 2585 2586 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2587 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2588 ath_hal_gpioCfgOutput(ah, 2589 ahp->ah_wlan_active_gpio_select, 2590 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2591 } 2592 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2593 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2594 { 2595 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2596 ath_hal_gpioCfgOutput(ah, 2597 ahp->ah_wlan_active_gpio_select, 2598 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2599 } 2600 2601 /* 2602 * Enable a weak pull down on BT_ACTIVE. 2603 * When BT device is disabled, BT_ACTIVE might be floating. 2604 */ 2605 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2606 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2607 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2608 2609 ahp->ah_bt_coex_enabled = AH_TRUE; 2610 2611 return 0; 2612 } 2613 2614 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2615 { 2616 return 0; 2617 } 2618 2619 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2620 { 2621 return bOn; 2622 } 2623 2624 void 2625 ar9300_init_bt_coex(struct ath_hal *ah) 2626 { 2627 struct ath_hal_9300 *ahp = AH9300(ah); 2628 2629 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2630 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2631 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2632 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2633 2634 /* 2635 * Set input mux for bt_prority_async and 2636 * bt_active_async to GPIO pins 2637 */ 2638 OS_REG_RMW_FIELD(ah, 2639 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2640 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2641 ahp->ah_bt_active_gpio_select); 2642 OS_REG_RMW_FIELD(ah, 2643 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2644 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2645 ahp->ah_bt_priority_gpio_select); 2646 2647 /* Configure the desired GPIO ports for input */ 2648 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2649 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2650 2651 if (ahp->ah_bt_coex_enabled) { 2652 ar9300_bt_coex_enable(ah); 2653 } else { 2654 ar9300_bt_coex_disable(ah); 2655 } 2656 } 2657 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2658 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2659 { 2660 /* 2-wire */ 2661 if (ahp->ah_bt_coex_enabled) { 2662 /* Connect bt_active_async to baseband */ 2663 OS_REG_CLR_BIT(ah, 2664 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2665 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2666 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2667 OS_REG_SET_BIT(ah, 2668 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2669 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2670 2671 /* 2672 * Set input mux for bt_prority_async and 2673 * bt_active_async to GPIO pins 2674 */ 2675 OS_REG_RMW_FIELD(ah, 2676 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2677 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2678 ahp->ah_bt_active_gpio_select); 2679 2680 /* Configure the desired GPIO ports for input */ 2681 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2682 2683 /* Enable coexistence on initialization */ 2684 ar9300_bt_coex_enable(ah); 2685 } 2686 } 2687 #if ATH_SUPPORT_MCI 2688 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2689 if (ahp->ah_bt_coex_enabled) { 2690 ar9300_mci_bt_coex_enable(ah); 2691 } 2692 else { 2693 ar9300_mci_bt_coex_disable(ah); 2694 } 2695 } 2696 #endif /* ATH_SUPPORT_MCI */ 2697 } 2698 2699 #endif /* ATH_BT_COEX */ 2700 2701 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2702 { 2703 u_int32_t val; 2704 int wasp_mm_rev; 2705 2706 #define AR_SOC_RST_REVISION_ID 0xB8060090 2707 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2708 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2709 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2710 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2711 #undef AR_SOC_RST_REVISION_ID 2712 #undef REG_READ 2713 2714 /* 2715 * Azimuth (ProxySTA) Mode is only supported correctly by 2716 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2717 * 2718 * Enable this feature for Scorpion at this time. The silicon 2719 * still needs to be validated. 2720 */ 2721 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2722 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2723 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2724 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2725 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2726 wasp_mm_rev >= 0 /* 1 */)))) 2727 { 2728 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2729 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2730 __func__, AH_PRIVATE((ah))->ah_macVersion, 2731 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2732 return HAL_ENOTSUPP; 2733 } 2734 2735 OS_REG_WRITE(ah, 2736 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2737 2738 /* turn on mode bit[24] for proxy sta */ 2739 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2740 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2741 2742 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2743 if (enable) { 2744 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2745 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2746 AR_AZIMUTH_BA_USES_AD1; 2747 /* turn off filter pass hold (bit 9) */ 2748 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2749 } else { 2750 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2751 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2752 AR_AZIMUTH_BA_USES_AD1); 2753 } 2754 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2755 2756 /* enable promiscous mode */ 2757 OS_REG_WRITE(ah, AR_RX_FILTER, 2758 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2759 /* enable promiscous in azimuth mode */ 2760 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2761 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2762 2763 /* turn on filter pass hold (bit 9) */ 2764 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2765 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2766 2767 return HAL_OK; 2768 } 2769 2770 #if 0 2771 void ar9300_mat_enable(struct ath_hal *ah, int enable) 2772 { 2773 /* 2774 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2775 * mitigation and turn on key search always for better performance. 2776 */ 2777 struct ath_hal_9300 *ahp = AH9300(ah); 2778 struct ath_hal_private *ap = AH_PRIVATE(ah); 2779 2780 ahp->ah_intr_mitigation_rx = !enable; 2781 if (ahp->ah_intr_mitigation_rx) { 2782 /* 2783 * Enable Interrupt Mitigation for Rx. 2784 * If no build-specific limits for the rx interrupt mitigation 2785 * timer have been specified, use conservative defaults. 2786 */ 2787 #ifndef AH_RIMT_VAL_LAST 2788 #define AH_RIMT_LAST_MICROSEC 500 2789 #endif 2790 #ifndef AH_RIMT_VAL_FIRST 2791 #define AH_RIMT_FIRST_MICROSEC 2000 2792 #endif 2793 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2794 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2795 } else { 2796 OS_REG_WRITE(ah, AR_RIMT, 0); 2797 } 2798 2799 ahp->ah_enable_keysearch_always = !!enable; 2800 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2801 } 2802 #endif 2803 2804 void ar9300_enable_tpc(struct ath_hal *ah) 2805 { 2806 u_int32_t val = 0; 2807 2808 ah->ah_config.ath_hal_desc_tpc = 1; 2809 2810 /* Enable TPC */ 2811 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2812 2813 /* 2814 * Disable per chain power reduction since we are already 2815 * accounting for this in our calculations 2816 */ 2817 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2818 if (AR_SREV_WASP(ah)) { 2819 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2820 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2821 } else { 2822 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2823 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2824 } 2825 } 2826 2827 2828 /* 2829 * ar9300_force_tsf_sync 2830 * This function forces the TSF sync to the given bssid, this is implemented 2831 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2832 * mode of operation, where we sync the TSF to RootAP TSF values 2833 */ 2834 void 2835 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2836 u_int16_t assoc_id) 2837 { 2838 ar9300_set_operating_mode(ah, HAL_M_STA); 2839 ar9300_write_associd(ah, bssid, assoc_id); 2840 } 2841 2842 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2843 { 2844 struct ath_hal_9300 *ahp = AH9300(ah); 2845 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2846 u_int32_t temp_powertx_rate9_reg_val; 2847 int8_t olpc_power_offset = 0; 2848 int8_t tmp_olpc_val = 0; 2849 HAL_RSSI_TX_POWER old_greentx_status; 2850 u_int8_t target_power_val_t[ar9300_rate_size]; 2851 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2852 2853 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2854 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2855 return; 2856 } 2857 2858 old_greentx_status = AH9300(ah)->green_tx_status; 2859 if (ahp->ah_hw_green_tx_enable) { 2860 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2861 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2862 } else { 2863 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2864 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2865 } 2866 2867 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2868 && (rssi > tmp_rss1_thr1)) 2869 { 2870 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2871 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2872 } 2873 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2874 && (rssi > tmp_rss1_thr2)) 2875 { 2876 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2877 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2878 } 2879 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2880 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2881 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2882 } 2883 } 2884 2885 /* If status is not change, don't do anything */ 2886 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2887 return; 2888 } 2889 2890 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2891 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2892 && AR_SREV_POSEIDON(ah)) 2893 { 2894 if (ahp->ah_hw_green_tx_enable) { 2895 switch (AH9300(ah)->green_tx_status) { 2896 case HAL_RSSI_TX_POWER_SHORT: 2897 /* 1. TxPower Config */ 2898 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2899 sizeof(target_power_val_t)); 2900 /* 1.1 Store OLPC Delta Calibration Offset*/ 2901 olpc_power_offset = 0; 2902 /* 2. Store OB/DB */ 2903 /* 3. Store TPC settting */ 2904 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2905 SM(14, AR_TPC_CTS) | 2906 SM(14, AR_TPC_CHIRP) | 2907 SM(14, AR_TPC_RPT)); 2908 /* 4. Store BB_powertx_rate9 value */ 2909 temp_powertx_rate9_reg_val = 2910 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2911 break; 2912 case HAL_RSSI_TX_POWER_MIDDLE: 2913 /* 1. TxPower Config */ 2914 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2915 sizeof(target_power_val_t)); 2916 /* 1.1 Store OLPC Delta Calibration Offset*/ 2917 olpc_power_offset = 0; 2918 /* 2. Store OB/DB */ 2919 /* 3. Store TPC settting */ 2920 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2921 SM(18, AR_TPC_CTS) | 2922 SM(18, AR_TPC_CHIRP) | 2923 SM(18, AR_TPC_RPT)); 2924 /* 4. Store BB_powertx_rate9 value */ 2925 temp_powertx_rate9_reg_val = 2926 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2927 break; 2928 case HAL_RSSI_TX_POWER_LONG: 2929 default: 2930 /* 1. TxPower Config */ 2931 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2932 sizeof(target_power_val_t)); 2933 /* 1.1 Store OLPC Delta Calibration Offset*/ 2934 olpc_power_offset = 0; 2935 /* 2. Store OB/DB1/DB2 */ 2936 /* 3. Store TPC settting */ 2937 temp_tcp_reg_val = 2938 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2939 /* 4. Store BB_powertx_rate9 value */ 2940 temp_powertx_rate9_reg_val = 2941 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2942 break; 2943 } 2944 } else { 2945 switch (AH9300(ah)->green_tx_status) { 2946 case HAL_RSSI_TX_POWER_SHORT: 2947 /* 1. TxPower Config */ 2948 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2949 sizeof(target_power_val_t)); 2950 /* 1.1 Store OLPC Delta Calibration Offset*/ 2951 olpc_power_offset = 2952 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2953 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2954 /* 2. Store OB/DB */ 2955 temp_obdb_reg_val = 2956 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2957 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2958 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2959 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2960 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2961 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2962 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2963 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2964 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2965 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2966 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2967 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2968 /* 3. Store TPC settting */ 2969 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 2970 SM(6, AR_TPC_CTS) | 2971 SM(6, AR_TPC_CHIRP) | 2972 SM(6, AR_TPC_RPT)); 2973 /* 4. Store BB_powertx_rate9 value */ 2974 temp_powertx_rate9_reg_val = 2975 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 2976 break; 2977 case HAL_RSSI_TX_POWER_MIDDLE: 2978 /* 1. TxPower Config */ 2979 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 2980 sizeof(target_power_val_t)); 2981 /* 1.1 Store OLPC Delta Calibration Offset*/ 2982 olpc_power_offset = 2983 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 2984 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2985 /* 2. Store OB/DB */ 2986 temp_obdb_reg_val = 2987 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2988 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2989 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2990 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2991 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2992 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2993 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2994 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2995 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2996 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2997 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2998 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2999 /* 3. Store TPC settting */ 3000 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3001 SM(14, AR_TPC_CTS) | 3002 SM(14, AR_TPC_CHIRP) | 3003 SM(14, AR_TPC_RPT)); 3004 /* 4. Store BB_powertx_rate9 value */ 3005 temp_powertx_rate9_reg_val = 3006 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3007 break; 3008 case HAL_RSSI_TX_POWER_LONG: 3009 default: 3010 /* 1. TxPower Config */ 3011 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3012 sizeof(target_power_val_t)); 3013 /* 1.1 Store OLPC Delta Calibration Offset*/ 3014 olpc_power_offset = 3015 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3016 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3017 /* 2. Store OB/DB1/DB2 */ 3018 temp_obdb_reg_val = 3019 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3020 /* 3. Store TPC settting */ 3021 temp_tcp_reg_val = 3022 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3023 /* 4. Store BB_powertx_rate9 value */ 3024 temp_powertx_rate9_reg_val = 3025 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3026 break; 3027 } 3028 } 3029 /* 1.1 Do OLPC Delta Calibration Offset */ 3030 tmp_olpc_val = 3031 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3032 tmp_olpc_val += olpc_power_offset; 3033 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3034 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3035 AR_PHY_TPC_OLPC_GAIN_DELTA); 3036 3037 /* 1.2 TxPower Config */ 3038 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3039 /* 2. Config OB/DB */ 3040 if (!ahp->ah_hw_green_tx_enable) { 3041 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3042 } 3043 /* 3. config TPC settting */ 3044 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3045 /* 4. config BB_powertx_rate9 value */ 3046 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3047 } 3048 } 3049 3050 #if 0 3051 void 3052 ar9300_get_vow_stats( 3053 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3054 { 3055 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3056 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3057 } 3058 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3059 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3060 } 3061 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3062 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3063 } 3064 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3065 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3066 } 3067 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3068 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3069 } 3070 } 3071 #endif 3072 3073 /* 3074 * ar9300_is_skip_paprd_by_greentx 3075 * 3076 * This function check if we need to skip PAPRD tuning 3077 * when GreenTx in specific state. 3078 */ 3079 HAL_BOOL 3080 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3081 { 3082 if (AR_SREV_POSEIDON(ah) && 3083 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3084 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3085 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3086 { 3087 return AH_TRUE; 3088 } 3089 return AH_FALSE; 3090 } 3091 3092 void 3093 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3094 { 3095 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3096 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3097 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3098 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3099 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3100 struct ath_hal_9300 *ahp = AH9300(ah); 3101 3102 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3103 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3104 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3105 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3106 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3107 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3108 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3109 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3110 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3111 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3112 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3113 } 3114 } 3115 3116 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3117 { 3118 struct ath_hal_9300 *ahp = AH9300(ah); 3119 3120 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3121 if ((value == 0) || (value == 1)) { 3122 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3123 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3124 } 3125 } 3126 } 3127 3128 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3129 { 3130 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3131 } 3132 3133 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3134 { 3135 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3136 3137 /* RSSI format is 8.4. Ignore lowest four bits */ 3138 val = val >> 4; 3139 return val; 3140 } 3141 3142 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3143 u_int32_t rssi_threshold) 3144 { 3145 struct ath_hal_9300 *ahp = AH9300(ah); 3146 3147 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3148 3149 /* save value for restoring after chip reset */ 3150 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3151 } 3152 3153 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3154 { 3155 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3156 } 3157 3158 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3159 { 3160 if (on) { 3161 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3162 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3163 } 3164 else { 3165 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3166 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3167 } 3168 } 3169 /* 3170 * Gets the contents of the specified key cache entry. 3171 */ 3172 HAL_BOOL 3173 ar9300_print_keycache(struct ath_hal *ah) 3174 { 3175 3176 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3177 u_int32_t key0, key1, key2, key3, key4; 3178 u_int32_t mac_hi, mac_lo; 3179 u_int16_t entry = 0; 3180 u_int32_t valid = 0; 3181 u_int32_t key_type; 3182 3183 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3184 3185 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3186 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3187 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3188 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3189 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3190 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3191 3192 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3193 3194 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3195 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3196 3197 if (mac_hi & AR_KEYTABLE_VALID) { 3198 valid = 1; 3199 } else { 3200 valid = 0; 3201 } 3202 3203 if ((mac_hi != 0) && (mac_lo != 0)) { 3204 mac_hi &= ~0x8000; 3205 mac_hi <<= 1; 3206 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3207 mac_lo <<= 1; 3208 } 3209 3210 ath_hal_printf(ah, 3211 "%03d " 3212 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3213 " %02d %02d " 3214 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3215 entry, 3216 (key0 << 24) >> 24, (key0 << 16) >> 24, 3217 (key0 << 8) >> 24, key0 >> 24, 3218 (key1 << 24) >> 24, (key1 << 16) >> 24, 3219 //(key1 << 8) >> 24, key1 >> 24, 3220 (key2 << 24) >> 24, (key2 << 16) >> 24, 3221 (key2 << 8) >> 24, key2 >> 24, 3222 (key3 << 24) >> 24, (key3 << 16) >> 24, 3223 //(key3 << 8) >> 24, key3 >> 24, 3224 (key4 << 24) >> 24, (key4 << 16) >> 24, 3225 (key4 << 8) >> 24, key4 >> 24, 3226 valid, key_type, 3227 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3228 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3229 } 3230 3231 return AH_TRUE; 3232 } 3233 3234 /* enable/disable smart antenna mode */ 3235 HAL_BOOL 3236 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3237 { 3238 struct ath_hal_9300 *ahp = AH9300(ah); 3239 3240 if (enable) { 3241 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3242 } else { 3243 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3244 } 3245 3246 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3247 * and swcom2 with 0 3248 * FIXME Ideally these registers need to be made read from caldata. 3249 * Until the calibration team gets them, keep them along with board 3250 * configuration. 3251 */ 3252 if (enable && AR_SREV_SCORPION(ah) && 3253 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3254 3255 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3256 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3257 } 3258 3259 ahp->ah_smartantenna_enable = enable; 3260 return 1; 3261 } 3262 3263 #ifdef ATH_TX99_DIAG 3264 #ifndef ATH_SUPPORT_HTC 3265 void 3266 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3267 u_int32_t txpower) 3268 { 3269 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3270 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3271 int32_t i; 3272 3273 /* The max power is limited to 63 */ 3274 if (txpower <= AR9300_MAX_RATE_POWER) { 3275 for (i = 0; i < ar9300_rate_size; i++) { 3276 p_pwr_array[i] = txpower; 3277 } 3278 } else { 3279 for (i = 0; i < ar9300_rate_size; i++) { 3280 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3281 } 3282 } 3283 3284 OS_REG_WRITE(ah, 0xa458, 0); 3285 3286 /* Write the OFDM power per rate set */ 3287 /* 6 (LSB), 9, 12, 18 (MSB) */ 3288 OS_REG_WRITE(ah, 0xa3c0, 3289 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3290 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3291 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3292 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3293 ); 3294 /* 24 (LSB), 36, 48, 54 (MSB) */ 3295 OS_REG_WRITE(ah, 0xa3c4, 3296 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3297 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3298 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3299 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3300 ); 3301 3302 /* Write the CCK power per rate set */ 3303 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3304 OS_REG_WRITE(ah, 0xa3c8, 3305 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3306 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3307 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3308 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3309 ); 3310 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3311 OS_REG_WRITE(ah, 0xa3cc, 3312 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3313 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3314 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3315 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3316 ); 3317 3318 /* Write the HT20 power per rate set */ 3319 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3320 OS_REG_WRITE(ah, 0xa3d0, 3321 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3322 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3323 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3324 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3325 ); 3326 3327 /* 6 (LSB), 7, 12, 13 (MSB) */ 3328 OS_REG_WRITE(ah, 0xa3d4, 3329 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3330 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3331 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3332 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3333 ); 3334 3335 /* 14 (LSB), 15, 20, 21 */ 3336 OS_REG_WRITE(ah, 0xa3e4, 3337 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3338 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3339 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3340 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3341 ); 3342 3343 /* Mixed HT20 and HT40 rates */ 3344 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3345 OS_REG_WRITE(ah, 0xa3e8, 3346 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3347 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3348 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3349 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3350 ); 3351 3352 /* Write the HT40 power per rate set */ 3353 /* correct PAR difference between HT40 and HT20/LEGACY */ 3354 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3355 OS_REG_WRITE(ah, 0xa3d8, 3356 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3357 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3358 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3359 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3360 ); 3361 3362 /* 6 (LSB), 7, 12, 13 (MSB) */ 3363 OS_REG_WRITE(ah, 0xa3dc, 3364 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3365 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3366 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3367 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3368 ); 3369 3370 /* 14 (LSB), 15, 20, 21 */ 3371 OS_REG_WRITE(ah, 0xa3ec, 3372 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3373 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3374 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3375 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3376 ); 3377 #undef PWR_MAS 3378 } 3379 3380 void 3381 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3382 { 3383 if (tx_chainmask == 0x5) { 3384 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3385 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3386 } 3387 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3388 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3389 3390 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3391 if (tx_chainmask == 0x5) { 3392 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3393 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3394 } 3395 } 3396 3397 void 3398 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3399 int chtype) 3400 { 3401 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3402 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3403 OS_REG_WRITE(ah, 0xa350, 3404 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3405 3406 /* 11G mode */ 3407 if (!chtype) { 3408 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3409 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3410 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3411 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3412 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3413 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3414 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3415 | (0x1 << 26) | (0x7 << 24)) 3416 & ~(0x1 << 22)); 3417 } else { 3418 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3419 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3420 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3421 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3422 | (0x1 << 26) | (0x7 << 24)) 3423 & ~(0x1 << 22)); 3424 } 3425 3426 /* chain zero */ 3427 if ((tx_chain_mask & 0x01) == 0x01) { 3428 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3429 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3430 | (0x1 << 31) | (0x5 << 15) 3431 | (0x3 << 9)) & ~(0x1 << 27) 3432 & ~(0x1 << 12)); 3433 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3434 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3435 | (0x1 << 12) | (0x1 << 10) 3436 | (0x1 << 9) | (0x1 << 8) 3437 | (0x1 << 7)) & ~(0x1 << 11)); 3438 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3439 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3440 | (0x1 << 29) | (0x1 << 25) 3441 | (0x1 << 23) | (0x1 << 19) 3442 | (0x1 << 10) | (0x1 << 9) 3443 | (0x1 << 8) | (0x1 << 3)) 3444 & ~(0x1 << 28)& ~(0x1 << 24) 3445 & ~(0x1 << 22)& ~(0x1 << 7)); 3446 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3447 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3448 | (0x1 << 23))& ~(0x1 << 21)); 3449 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3450 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3451 | (0x1 << 12) | (0x1 << 10) 3452 | (0x1 << 9) | (0x1 << 8) 3453 | (0x1 << 6) | (0x1 << 5) 3454 | (0x1 << 4) | (0x1 << 3) 3455 | (0x1 << 2)); 3456 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3457 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3458 } 3459 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3460 /* chain one */ 3461 if ((tx_chain_mask & 0x02) == 0x02 ) { 3462 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3463 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3464 | (0x1 << 31) | (0x5 << 15) 3465 | (0x3 << 9)) & ~(0x1 << 27) 3466 & ~(0x1 << 12)); 3467 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3468 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3469 | (0x1 << 12) | (0x1 << 10) 3470 | (0x1 << 9) | (0x1 << 8) 3471 | (0x1 << 7)) & ~(0x1 << 11)); 3472 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3473 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3474 | (0x1 << 29) | (0x1 << 25) 3475 | (0x1 << 23) | (0x1 << 19) 3476 | (0x1 << 10) | (0x1 << 9) 3477 | (0x1 << 8) | (0x1 << 3)) 3478 & ~(0x1 << 28)& ~(0x1 << 24) 3479 & ~(0x1 << 22)& ~(0x1 << 7)); 3480 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3481 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3482 | (0x1 << 23))& ~(0x1 << 21)); 3483 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3484 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3485 | (0x1 << 12) | (0x1 << 10) 3486 | (0x1 << 9) | (0x1 << 8) 3487 | (0x1 << 6) | (0x1 << 5) 3488 | (0x1 << 4) | (0x1 << 3) 3489 | (0x1 << 2)); 3490 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3491 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3492 } 3493 } 3494 if (AR_SREV_OSPREY(ah)) { 3495 /* chain two */ 3496 if ((tx_chain_mask & 0x04) == 0x04 ) { 3497 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3498 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3499 | (0x1 << 31) | (0x5 << 15) 3500 | (0x3 << 9)) & ~(0x1 << 27) 3501 & ~(0x1 << 12)); 3502 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3503 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3504 | (0x1 << 12) | (0x1 << 10) 3505 | (0x1 << 9) | (0x1 << 8) 3506 | (0x1 << 7)) & ~(0x1 << 11)); 3507 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3508 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3509 | (0x1 << 29) | (0x1 << 25) 3510 | (0x1 << 23) | (0x1 << 19) 3511 | (0x1 << 10) | (0x1 << 9) 3512 | (0x1 << 8) | (0x1 << 3)) 3513 & ~(0x1 << 28)& ~(0x1 << 24) 3514 & ~(0x1 << 22)& ~(0x1 << 7)); 3515 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3516 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3517 | (0x1 << 23))& ~(0x1 << 21)); 3518 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3519 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3520 | (0x1 << 12) | (0x1 << 10) 3521 | (0x1 << 9) | (0x1 << 8) 3522 | (0x1 << 6) | (0x1 << 5) 3523 | (0x1 << 4) | (0x1 << 3) 3524 | (0x1 << 2)); 3525 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3526 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3527 } 3528 } 3529 3530 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3531 OS_REG_WRITE(ah, 0xa288, 0x111); 3532 } else { 3533 /* chain zero */ 3534 if ((tx_chain_mask & 0x01) == 0x01) { 3535 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3536 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3537 | (0x1 << 31) | (0x1 << 27) 3538 | (0x3 << 23) | (0x1 << 19) 3539 | (0x1 << 15) | (0x3 << 9)) 3540 & ~(0x1 << 12)); 3541 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3542 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3543 | (0x1 << 12) | (0x1 << 10) 3544 | (0x1 << 9) | (0x1 << 8) 3545 | (0x1 << 7) | (0x1 << 3) 3546 | (0x1 << 2) | (0x1 << 1)) 3547 & ~(0x1 << 11)& ~(0x1 << 0)); 3548 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3549 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3550 | (0x1 << 29) | (0x1 << 25) 3551 | (0x1 << 23) | (0x1 << 19) 3552 | (0x1 << 10) | (0x1 << 9) 3553 | (0x1 << 8) | (0x1 << 3)) 3554 & ~(0x1 << 28)& ~(0x1 << 24) 3555 & ~(0x1 << 22)& ~(0x1 << 7)); 3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3557 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3558 | (0x1 << 23))& ~(0x1 << 21)); 3559 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3560 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3561 | (0x3 << 3) | (0x3 << 0)); 3562 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3563 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3564 | (0x3 << 29) | (0x3 << 26) 3565 | (0x2 << 23) | (0x2 << 20) 3566 | (0x2 << 17))& ~(0x1 << 14)); 3567 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3568 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3569 | (0x1 << 12) | (0x1 << 10) 3570 | (0x1 << 9) | (0x1 << 8) 3571 | (0x1 << 6) | (0x1 << 5) 3572 | (0x1 << 4) | (0x1 << 3) 3573 | (0x1 << 2)); 3574 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3575 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3576 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3577 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3578 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3579 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3580 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3581 | (0x1 << 26) | (0x7 << 24) 3582 | (0x3 << 22)); 3583 } else { 3584 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3585 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3586 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3587 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3588 | (0x1 << 26) | (0x7 << 24) 3589 | (0x3 << 22)); 3590 } 3591 3592 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3593 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3594 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3595 | (0x1 << 3) | (0x1 << 2) 3596 | (0x1 << 1)) & ~(0x1 << 0)); 3597 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3598 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3599 | (0x1 << 19) | (0x1 << 3)); 3600 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3601 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3602 } 3603 if (AR_SREV_OSPREY(ah)) { 3604 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3605 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3606 | (0x1 << 3) | (0x1 << 2) 3607 | (0x1 << 1)) & ~(0x1 << 0)); 3608 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3609 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3610 | (0x1 << 19) | (0x1 << 3)); 3611 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3612 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3613 } 3614 } 3615 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3616 /* chain one */ 3617 if ((tx_chain_mask & 0x02) == 0x02 ) { 3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3619 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3620 | (0x1 << 3) | (0x1 << 2) 3621 | (0x1 << 1)) & ~(0x1 << 0)); 3622 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3623 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3624 | (0x1 << 19) | (0x1 << 3)); 3625 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3626 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3627 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3628 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3629 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3630 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3631 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3632 | (0x1 << 26) | (0x7 << 24) 3633 | (0x3 << 22)); 3634 } else { 3635 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3636 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3637 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3638 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3639 | (0x1 << 26) | (0x7 << 24) 3640 | (0x3 << 22)); 3641 } 3642 3643 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3644 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3645 | (0x1 << 31) | (0x1 << 27) 3646 | (0x3 << 23) | (0x1 << 19) 3647 | (0x1 << 15) | (0x3 << 9)) 3648 & ~(0x1 << 12)); 3649 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3650 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3651 | (0x1 << 12) | (0x1 << 10) 3652 | (0x1 << 9) | (0x1 << 8) 3653 | (0x1 << 7) | (0x1 << 3) 3654 | (0x1 << 2) | (0x1 << 1)) 3655 & ~(0x1 << 11)& ~(0x1 << 0)); 3656 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3657 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3658 | (0x1 << 29) | (0x1 << 25) 3659 | (0x1 << 23) | (0x1 << 19) 3660 | (0x1 << 10) | (0x1 << 9) 3661 | (0x1 << 8) | (0x1 << 3)) 3662 & ~(0x1 << 28)& ~(0x1 << 24) 3663 & ~(0x1 << 22)& ~(0x1 << 7)); 3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3665 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3666 | (0x1 << 23))& ~(0x1 << 21)); 3667 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3668 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3669 | (0x3 << 3) | (0x3 << 0)); 3670 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3671 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3672 | (0x3 << 29) | (0x3 << 26) 3673 | (0x2 << 23) | (0x2 << 20) 3674 | (0x2 << 17))& ~(0x1 << 14)); 3675 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3676 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3677 | (0x1 << 12) | (0x1 << 10) 3678 | (0x1 << 9) | (0x1 << 8) 3679 | (0x1 << 6) | (0x1 << 5) 3680 | (0x1 << 4) | (0x1 << 3) 3681 | (0x1 << 2)); 3682 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3683 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3684 3685 if (AR_SREV_OSPREY(ah)) { 3686 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3687 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3688 | (0x1 << 3) | (0x1 << 2) 3689 | (0x1 << 1)) & ~(0x1 << 0)); 3690 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3691 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3692 | (0x1 << 19) | (0x1 << 3)); 3693 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3694 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3695 } 3696 } 3697 } 3698 if (AR_SREV_OSPREY(ah)) { 3699 /* chain two */ 3700 if ((tx_chain_mask & 0x04) == 0x04 ) { 3701 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3702 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3703 | (0x1 << 3) | (0x1 << 2) 3704 | (0x1 << 1)) & ~(0x1 << 0)); 3705 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3706 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3707 | (0x1 << 19) | (0x1 << 3)); 3708 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3709 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3710 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3711 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3712 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3713 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3714 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3715 | (0x1 << 26) | (0x7 << 24) 3716 | (0x3 << 22)); 3717 } else { 3718 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3719 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3720 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3721 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3722 | (0x1 << 26) | (0x7 << 24) 3723 | (0x3 << 22)); 3724 } 3725 3726 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3727 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3728 | (0x1 << 3) | (0x1 << 2) 3729 | (0x1 << 1)) & ~(0x1 << 0)); 3730 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3731 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3732 | (0x1 << 19) | (0x1 << 3)); 3733 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3734 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3735 3736 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3737 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3738 | (0x1 << 31) | (0x1 << 27) 3739 | (0x3 << 23) | (0x1 << 19) 3740 | (0x1 << 15) | (0x3 << 9)) 3741 & ~(0x1 << 12)); 3742 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3743 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3744 | (0x1 << 12) | (0x1 << 10) 3745 | (0x1 << 9) | (0x1 << 8) 3746 | (0x1 << 7) | (0x1 << 3) 3747 | (0x1 << 2) | (0x1 << 1)) 3748 & ~(0x1 << 11)& ~(0x1 << 0)); 3749 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3750 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3751 | (0x1 << 29) | (0x1 << 25) 3752 | (0x1 << 23) | (0x1 << 19) 3753 | (0x1 << 10) | (0x1 << 9) 3754 | (0x1 << 8) | (0x1 << 3)) 3755 & ~(0x1 << 28)& ~(0x1 << 24) 3756 & ~(0x1 << 22)& ~(0x1 << 7)); 3757 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3758 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3759 | (0x1 << 23))& ~(0x1 << 21)); 3760 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3761 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3762 | (0x3 << 3) | (0x3 << 0)); 3763 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3764 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3765 | (0x3 << 29) | (0x3 << 26) 3766 | (0x2 << 23) | (0x2 << 20) 3767 | (0x2 << 17))& ~(0x1 << 14)); 3768 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3769 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3770 | (0x1 << 12) | (0x1 << 10) 3771 | (0x1 << 9) | (0x1 << 8) 3772 | (0x1 << 6) | (0x1 << 5) 3773 | (0x1 << 4) | (0x1 << 3) 3774 | (0x1 << 2)); 3775 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3776 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3777 } 3778 } 3779 3780 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3781 OS_REG_WRITE(ah, 0xa288, 0x222); 3782 } 3783 } 3784 3785 void 3786 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3787 { 3788 u_int32_t val; 3789 u_int32_t qnum = (u_int32_t)data; 3790 3791 /* Disable AGC to A2 */ 3792 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3793 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3794 3795 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3796 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3797 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3798 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3799 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3800 /* 200 ok for HT20, 400 ok for HT40 */ 3801 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3802 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3803 3804 /* set QCU modes to early termination */ 3805 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3806 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3807 } 3808 3809 void 3810 ar9300_tx99_stop(struct ath_hal *ah) 3811 { 3812 /* this should follow the setting of start */ 3813 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3814 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3815 } 3816 #endif /* ATH_TX99_DIAG */ 3817 #endif /* ATH_SUPPORT_HTC */ 3818 3819 HAL_BOOL 3820 ar9300Get3StreamSignature(struct ath_hal *ah) 3821 { 3822 return AH_FALSE; 3823 } 3824 3825 HAL_BOOL 3826 ar9300ForceVCS(struct ath_hal *ah) 3827 { 3828 return AH_FALSE; 3829 } 3830 3831 HAL_BOOL 3832 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3833 { 3834 return AH_FALSE; 3835 } 3836 3837 HAL_BOOL 3838 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3839 { 3840 struct ath_hal_9300 *ahp = AH9300(ah); 3841 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3842 u_int8_t *ctl_index; 3843 u_int32_t offset = 0; 3844 3845 if (!ctl_array) 3846 return AH_FALSE; 3847 3848 /* copy 2G ctl freqbin and power data */ 3849 ctl_index = p_eep_data->ctl_index_2g; 3850 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3851 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3852 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3853 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3854 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3855 3856 3857 /* copy 2G ctl freqbin and power data */ 3858 ctl_index = p_eep_data->ctl_index_5g; 3859 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3860 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3861 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3862 3863 return AH_FALSE; 3864 } 3865 3866 void 3867 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3868 { 3869 struct ath_hal_9300 *ahp = AH9300(ah); 3870 3871 /* optional txchainmask should be subset of primary txchainmask */ 3872 if ((mask & ahp->ah_tx_chainmask) != mask) { 3873 ahp->ah_tx_chainmaskopt = 0; 3874 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3875 return; 3876 } 3877 3878 ahp->ah_tx_chainmaskopt = mask; 3879 } 3880