1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 30 31 void 32 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 33 { 34 struct ath_hal_9300 *ahp = AH9300(ah); 35 *hangs = 0; 36 37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 38 *hangs |= HAL_RIFS_BB_HANG_WAR; 39 } 40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 41 *hangs |= HAL_DFS_BB_HANG_WAR; 42 } 43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 44 == HAL_OK) 45 { 46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 47 } 48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 49 *hangs |= HAL_MAC_HANG_WAR; 50 } 51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 52 == HAL_OK) 53 { 54 *hangs |= HAL_PHYRESTART_CLR_WAR; 55 } 56 57 ahp->ah_hang_wars = *hangs; 58 } 59 60 /* 61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 62 * HT20, HT40, fast-clock, turbo mode, etc. 63 */ 64 static u_int 65 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 66 { 67 #if 0 68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 69 70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 71 return (ath_hal_mac_usec(ah, clks) / 2); 72 } else { 73 return (ath_hal_mac_usec(ah, clks)); 74 } 75 #endif 76 return (ath_hal_mac_usec(ah, clks)); 77 } 78 79 u_int 80 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 81 { 82 #if 0 83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 84 85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 86 return (ath_hal_mac_clks(ah, usecs) * 2); 87 } else { 88 return (ath_hal_mac_clks(ah, usecs)); 89 } 90 #endif 91 return (ath_hal_mac_clks(ah, usecs)); 92 } 93 94 void 95 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 96 { 97 struct ath_hal_9300 *ahp = AH9300(ah); 98 99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 100 } 101 102 HAL_BOOL 103 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 104 { 105 struct ath_hal_9300 *ahp = AH9300(ah); 106 107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 108 return AH_TRUE; 109 } 110 111 void 112 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 113 { 114 struct ath_hal_9300 *ahp = AH9300(ah); 115 116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 117 } 118 119 HAL_BOOL 120 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 121 { 122 struct ath_hal_9300 *ahp = AH9300(ah); 123 124 /* save it since it must be rewritten on reset */ 125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 126 127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 129 return AH_TRUE; 130 } 131 132 /* 133 * Attempt to change the cards operating regulatory domain to the given value 134 * Returns: A_EINVAL for an unsupported regulatory domain. 135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 136 */ 137 HAL_BOOL 138 ar9300_set_regulatory_domain(struct ath_hal *ah, 139 u_int16_t reg_domain, HAL_STATUS *status) 140 { 141 HAL_STATUS ecode; 142 143 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 144 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 145 return AH_TRUE; 146 } 147 ecode = HAL_EIO; 148 149 #if 0 150 bad: 151 #endif 152 if (status) { 153 *status = ecode; 154 } 155 return AH_FALSE; 156 } 157 158 /* 159 * Return the wireless modes (a,b,g,t) supported by hardware. 160 * 161 * This value is what is actually supported by the hardware 162 * and is unaffected by regulatory/country code settings. 163 * 164 */ 165 u_int 166 ar9300_get_wireless_modes(struct ath_hal *ah) 167 { 168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 169 } 170 171 /* 172 * Set the interrupt and GPIO values so the ISR can disable RF 173 * on a switch signal. Assumes GPIO port and interrupt polarity 174 * are set prior to call. 175 */ 176 void 177 ar9300_enable_rf_kill(struct ath_hal *ah) 178 { 179 /* TODO - can this really be above the hal on the GPIO interface for 180 * TODO - the client only? 181 */ 182 struct ath_hal_9300 *ahp = AH9300(ah); 183 184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 185 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 188 AR_RFSILENT_FORCE); 189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 190 } 191 else { 192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 193 AR_RFSILENT_FORCE); 194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 195 } 196 } 197 else { 198 /* Connect rfsilent_bb_l to baseband */ 199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 201 202 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 204 AR_GPIO_INPUT_MUX2_RFSILENT); 205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 (ahp->ah_gpio_select & 0x0f) << 4); 207 208 /* 209 * Configure the desired GPIO port for input and 210 * enable baseband rf silence 211 */ 212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 214 } 215 216 /* 217 * If radio disable switch connection to GPIO bit x is enabled 218 * program GPIO interrupt. 219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 220 * verified that it is a later version of eeprom, it has a place for 221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 222 * connection is present. 223 */ 224 /* 225 * RFKill uses polling not interrupt, 226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 227 */ 228 if (ath_hal_hasrfkill_int(ah)) { 229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 230 /* switch already closed, set to interrupt upon open */ 231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 232 } else { 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 234 } 235 } 236 } 237 238 /* 239 * Change the LED blinking pattern to correspond to the connectivity 240 */ 241 void 242 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 243 { 244 static const u_int32_t ledbits[8] = { 245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 252 AR_CFG_LED_ASSOC_NONE, 253 }; 254 255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 256 } 257 258 /* 259 * Sets the Power LED on the cardbus without affecting the Network LED. 260 */ 261 void 262 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 263 { 264 u_int32_t val; 265 266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 268 } 269 270 /* 271 * Sets the Network LED on the cardbus without affecting the Power LED. 272 */ 273 void 274 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 275 { 276 u_int32_t val; 277 278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 280 } 281 282 /* 283 * Change association related fields programmed into the hardware. 284 * Writing a valid BSSID to the hardware effectively enables the hardware 285 * to synchronize its TSF to the correct beacons and receive frames coming 286 * from that BSSID. It is called by the SME JOIN operation. 287 */ 288 void 289 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 290 u_int16_t assoc_id) 291 { 292 struct ath_hal_9300 *ahp = AH9300(ah); 293 294 /* save bssid and assoc_id for restore on reset */ 295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 296 ahp->ah_assoc_id = assoc_id; 297 298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 301 } 302 303 /* 304 * Get the current hardware tsf for stamlme 305 */ 306 u_int64_t 307 ar9300_get_tsf64(struct ath_hal *ah) 308 { 309 u_int64_t tsf; 310 311 /* XXX sync multi-word read? */ 312 tsf = OS_REG_READ(ah, AR_TSF_U32); 313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 314 return tsf; 315 } 316 317 void 318 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 319 { 320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 322 } 323 324 /* 325 * Get the current hardware tsf for stamlme 326 */ 327 u_int32_t 328 ar9300_get_tsf32(struct ath_hal *ah) 329 { 330 return OS_REG_READ(ah, AR_TSF_L32); 331 } 332 333 u_int32_t 334 ar9300_get_tsf2_32(struct ath_hal *ah) 335 { 336 return OS_REG_READ(ah, AR_TSF2_L32); 337 } 338 339 /* 340 * Reset the current hardware tsf for stamlme. 341 */ 342 void 343 ar9300_reset_tsf(struct ath_hal *ah) 344 { 345 int count; 346 347 count = 0; 348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 349 count++; 350 if (count > 10) { 351 HALDEBUG(ah, HAL_DEBUG_RESET, 352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 353 break; 354 } 355 OS_DELAY(10); 356 } 357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 358 } 359 360 /* 361 * Set or clear hardware basic rate bit 362 * Set hardware basic rate set if basic rate is found 363 * and basic rate is equal or less than 2Mbps 364 */ 365 void 366 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 367 { 368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 369 u_int32_t reg; 370 u_int8_t xset; 371 int i; 372 373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 374 return; 375 } 376 xset = 0; 377 for (i = 0; i < rs->rs_count; i++) { 378 u_int8_t rset = rs->rs_rates[i]; 379 /* Basic rate defined? */ 380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 381 xset = rset; 382 } 383 } 384 /* 385 * Set the h/w bit to reflect whether or not the basic 386 * rate is found to be equal or less than 2Mbps. 387 */ 388 reg = OS_REG_READ(ah, AR_STA_ID1); 389 if (xset && xset / 2 <= 2) { 390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 391 } else { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 393 } 394 } 395 396 /* 397 * Grab a semi-random value from hardware registers - may not 398 * change often 399 */ 400 u_int32_t 401 ar9300_get_random_seed(struct ath_hal *ah) 402 { 403 u_int32_t nf; 404 405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 406 if (nf & 0x100) { 407 nf = 0 - ((nf ^ 0x1ff) + 1); 408 } 409 return (OS_REG_READ(ah, AR_TSF_U32) ^ 410 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 411 } 412 413 /* 414 * Detect if our card is present 415 */ 416 HAL_BOOL 417 ar9300_detect_card_present(struct ath_hal *ah) 418 { 419 u_int16_t mac_version, mac_rev; 420 u_int32_t v; 421 422 /* 423 * Read the Silicon Revision register and compare that 424 * to what we read at attach time. If the same, we say 425 * a card/device is present. 426 */ 427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 428 if (v == 0xFF) { 429 /* new SREV format */ 430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 431 /* 432 * Include 6-bit Chip Type (masked to 0) to differentiate 433 * from pre-Sowl versions 434 */ 435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 436 mac_rev = MS(v, AR_SREV_REVISION2); 437 } else { 438 mac_version = MS(v, AR_SREV_VERSION); 439 mac_rev = v & AR_SREV_REVISION; 440 } 441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 442 AH_PRIVATE(ah)->ah_macRev == mac_rev); 443 } 444 445 /* 446 * Update MIB Counters 447 */ 448 void 449 ar9300_update_mib_mac_stats(struct ath_hal *ah) 450 { 451 struct ath_hal_9300 *ahp = AH9300(ah); 452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 453 454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 459 } 460 461 void 462 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 463 { 464 struct ath_hal_9300 *ahp = AH9300(ah); 465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 466 467 stats->ackrcv_bad = istats->ackrcv_bad; 468 stats->rts_bad = istats->rts_bad; 469 stats->fcs_bad = istats->fcs_bad; 470 stats->rts_good = istats->rts_good; 471 stats->beacons = istats->beacons; 472 } 473 474 /* 475 * Detect if the HW supports spreading a CCK signal on channel 14 476 */ 477 HAL_BOOL 478 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 479 { 480 return AH_TRUE; 481 } 482 483 /* 484 * Get the rssi of frame curently being received. 485 */ 486 u_int32_t 487 ar9300_get_cur_rssi(struct ath_hal *ah) 488 { 489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 490 /* get combined RSSI */ 491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 492 } 493 494 #if ATH_GEN_RANDOMNESS 495 /* 496 * Get the rssi value from BB on ctl chain0. 497 */ 498 u_int32_t 499 ar9300_get_rssi_chain0(struct ath_hal *ah) 500 { 501 /* get ctl chain0 RSSI */ 502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 503 } 504 #endif 505 506 u_int 507 ar9300_get_def_antenna(struct ath_hal *ah) 508 { 509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 510 } 511 512 /* Setup coverage class */ 513 void 514 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 515 { 516 } 517 518 void 519 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 520 { 521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 522 } 523 524 HAL_BOOL 525 ar9300_set_antenna_switch(struct ath_hal *ah, 526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 528 { 529 struct ath_hal_9300 *ahp = AH9300(ah); 530 531 /* 532 * Owl does not support diversity or changing antennas. 533 * 534 * Instead this API and function are defined differently for AR9300. 535 * To support Tablet PC's, this interface allows the system 536 * to dramatically reduce the TX power on a particular chain. 537 * 538 * Based on the value of (redefined) diversity_control, the 539 * reset code will decrease power on chain 0 or chain 1/2. 540 * 541 * Based on the value of bit 0 of antenna_switch_swap, 542 * the mapping between OID call and chain is defined as: 543 * 0: map A -> 0, B -> 1; 544 * 1: map A -> 1, B -> 0; 545 * 546 * NOTE: 547 * The devices that use this OID should use a tx_chain_mask and 548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 549 * used in order to ensure an active transmit antenna. This 550 * API will allow the host to turn off the only transmitting 551 * antenna to ensure the antenna closest to the user's body is 552 * powered-down. 553 */ 554 /* 555 * Set antenna control for use during reset sequence by 556 * ar9300_decrease_chain_power() 557 */ 558 ahp->ah_diversity_control = settings; 559 560 return AH_TRUE; 561 } 562 563 HAL_BOOL 564 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 565 { 566 return AH_TRUE; 567 } 568 569 HAL_BOOL 570 ar9300_set_slot_time(struct ath_hal *ah, u_int us) 571 { 572 struct ath_hal_9300 *ahp = AH9300(ah); 573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 576 return AH_FALSE; 577 } else { 578 /* convert to system clocks */ 579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 580 ahp->ah_slot_time = us; 581 return AH_TRUE; 582 } 583 } 584 585 HAL_BOOL 586 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 587 { 588 struct ath_hal_9300 *ahp = AH9300(ah); 589 590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 593 return AH_FALSE; 594 } else { 595 /* convert to system clocks */ 596 OS_REG_RMW_FIELD(ah, 597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 598 ahp->ah_ack_timeout = us; 599 return AH_TRUE; 600 } 601 } 602 603 u_int 604 ar9300_get_ack_timeout(struct ath_hal *ah) 605 { 606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 608 } 609 610 HAL_STATUS 611 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 612 u_int32_t next_start, HAL_QUIET_FLAG flag) 613 { 614 #define TU_TO_USEC(_tu) ((_tu) << 10) 615 HAL_STATUS status = HAL_EIO; 616 u_int32_t tsf = 0, j, next_start_us = 0; 617 if (flag & HAL_QUIET_ENABLE) { 618 for (j = 0; j < 2; j++) { 619 next_start_us = TU_TO_USEC(next_start); 620 tsf = OS_REG_READ(ah, AR_TSF_L32); 621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 622 next_start_us += tsf; 623 } 624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 625 next_start_us += 626 ah->ah_config.ah_sw_beacon_response_time; 627 } 628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 634 status = HAL_OK; 635 break; 636 } 637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 639 /* TSF shouldn't count twice or reg access is taking forever */ 640 HALASSERT(j < 1); 641 } 642 } else { 643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 644 status = HAL_OK; 645 } 646 647 return status; 648 #undef TU_TO_USEC 649 } 650 #ifdef ATH_SUPPORT_DFS 651 void 652 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 653 { 654 u32 reg1, reg2; 655 656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 658 AH9300(ah)->ah_cac_quiet_enabled = enable; 659 660 if (enable) { 661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 662 reg1 | AR_PCU_FORCE_QUIET_COLL); 663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 665 } else { 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 667 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 670 } 671 } 672 #endif /* ATH_SUPPORT_DFS */ 673 674 void 675 ar9300_set_pcu_config(struct ath_hal *ah) 676 { 677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 678 } 679 680 HAL_STATUS 681 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 682 u_int32_t capability, u_int32_t *result) 683 { 684 struct ath_hal_9300 *ahp = AH9300(ah); 685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 686 struct ar9300_ani_state *ani; 687 688 switch (type) { 689 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 690 switch (capability) { 691 case HAL_CIPHER_AES_CCM: 692 case HAL_CIPHER_AES_OCB: 693 case HAL_CIPHER_TKIP: 694 case HAL_CIPHER_WEP: 695 case HAL_CIPHER_MIC: 696 case HAL_CIPHER_CLR: 697 return HAL_OK; 698 default: 699 return HAL_ENOTSUPP; 700 } 701 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 702 switch (capability) { 703 case 0: /* hardware capability */ 704 return HAL_OK; 705 case 1: 706 return (ahp->ah_sta_id1_defaults & 707 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 708 default: 709 return HAL_ENOTSUPP; 710 } 711 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 712 switch (capability) { 713 case 0: /* hardware capability */ 714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 715 case 1: /* current setting */ 716 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 717 HAL_ENXIO : HAL_OK; 718 default: 719 return HAL_ENOTSUPP; 720 } 721 case HAL_CAP_WME_TKIPMIC: 722 /* hardware can do TKIP MIC when WMM is turned on */ 723 return HAL_OK; 724 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 725 return HAL_OK; 726 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 727 switch (capability) { 728 case 0: /* hardware capability */ 729 return HAL_OK; 730 case 1: /* current setting */ 731 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 732 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 733 HAL_OK : HAL_ENXIO; 734 } 735 return HAL_EINVAL; 736 case HAL_CAP_TPC: 737 switch (capability) { 738 case 0: /* hardware capability */ 739 return HAL_OK; 740 case 1: 741 return ah->ah_config.ath_hal_desc_tpc ? 742 HAL_OK : HAL_ENXIO; 743 } 744 return HAL_OK; 745 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 746 return HAL_OK; 747 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 748 switch (capability) { 749 case 0: /* hardware capability */ 750 return HAL_OK; 751 case 1: 752 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 753 /* 754 * Owl and Merlin have problems in mcast key search. 755 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 756 * 26802 757 */ 758 return HAL_ENXIO; 759 } else { 760 return (ahp->ah_sta_id1_defaults & 761 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 762 } 763 } 764 return HAL_EINVAL; 765 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 766 switch (capability) { 767 case 0: /* hardware capability */ 768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 769 case 1: 770 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 771 HAL_OK : HAL_ENXIO; 772 } 773 return HAL_EINVAL; 774 case HAL_CAP_RFSILENT: /* rfsilent support */ 775 if (capability == 3) { /* rfkill interrupt */ 776 /* 777 * XXX: Interrupt-based notification of RF Kill state 778 * changes not working yet. Report that this feature 779 * is not supported so that polling is used instead. 780 */ 781 return (HAL_ENOTSUPP); 782 } 783 return ath_hal_getcapability(ah, type, capability, result); 784 case HAL_CAP_4ADDR_AGGR: 785 return HAL_OK; 786 case HAL_CAP_BB_RIFS_HANG: 787 return HAL_ENOTSUPP; 788 case HAL_CAP_BB_DFS_HANG: 789 return HAL_ENOTSUPP; 790 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 791 /* Track chips that are known to have BB hangs related 792 * to rx_clear stuck low. 793 */ 794 return HAL_ENOTSUPP; 795 case HAL_CAP_MAC_HANG: 796 /* Track chips that are known to have MAC hangs. 797 */ 798 return HAL_OK; 799 case HAL_CAP_RIFS_RX_ENABLED: 800 /* Is RIFS RX currently enabled */ 801 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 802 #if 0 803 case HAL_CAP_ANT_CFG_2GHZ: 804 *result = p_cap->halNumAntCfg2Ghz; 805 return HAL_OK; 806 case HAL_CAP_ANT_CFG_5GHZ: 807 *result = p_cap->halNumAntCfg5Ghz; 808 return HAL_OK; 809 case HAL_CAP_RX_STBC: 810 *result = p_cap->hal_rx_stbc_support; 811 return HAL_OK; 812 case HAL_CAP_TX_STBC: 813 *result = p_cap->hal_tx_stbc_support; 814 return HAL_OK; 815 #endif 816 case HAL_CAP_LDPC: 817 *result = p_cap->halLDPCSupport; 818 return HAL_OK; 819 case HAL_CAP_DYNAMIC_SMPS: 820 return HAL_OK; 821 case HAL_CAP_DS: 822 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 823 (p_cap->halTxChainMask & 0x3) != 0x3 || 824 (p_cap->halRxChainMask & 0x3) != 0x3) ? 825 HAL_ENOTSUPP : HAL_OK; 826 case HAL_CAP_TS: 827 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 828 (p_cap->halTxChainMask & 0x7) != 0x7 || 829 (p_cap->halRxChainMask & 0x7) != 0x7) ? 830 HAL_ENOTSUPP : HAL_OK; 831 case HAL_CAP_OL_PWRCTRL: 832 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 833 HAL_OK : HAL_ENOTSUPP; 834 case HAL_CAP_CRDC: 835 #if ATH_SUPPORT_CRDC 836 return (AR_SREV_WASP(ah) && 837 ah->ah_config.ath_hal_crdc_enable) ? 838 HAL_OK : HAL_ENOTSUPP; 839 #else 840 return HAL_ENOTSUPP; 841 #endif 842 #if 0 843 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 844 *result = (u_int32_t)(-1); 845 return HAL_OK; 846 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849 #endif 850 case HAL_CAP_BB_PANIC_WATCHDOG: 851 return HAL_OK; 852 case HAL_CAP_PHYRESTART_CLR_WAR: 853 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 854 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 855 { 856 return HAL_OK; 857 } 858 else 859 { 860 return HAL_ENOTSUPP; 861 } 862 case HAL_CAP_ENTERPRISE_MODE: 863 *result = ahp->ah_enterprise_mode >> 16; 864 /* 865 * WAR for EV 77658 - Add delimiters to first sub-frame when using 866 * RTS/CTS with aggregation and non-enterprise Osprey. 867 * 868 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 869 */ 870 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 871 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 872 AR_SREV_WASP_10(ah))) { 873 *result |= AH_ENT_RTSCTS_DELIM_WAR; 874 } 875 return HAL_OK; 876 case HAL_CAP_LDPCWAR: 877 /* WAR for RIFS+LDPC issue is required for all chips currently 878 * supported by ar9300 HAL. 879 */ 880 return HAL_OK; 881 case HAL_CAP_ENABLE_APM: 882 *result = p_cap->halApmEnable; 883 return HAL_OK; 884 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 886 case HAL_CAP_PCIE_LCR_OFFSET: 887 *result = p_cap->hal_pcie_lcr_offset; 888 return HAL_OK; 889 case HAL_CAP_SMARTANTENNA: 890 /* FIXME A request is pending with h/w team to add feature bit in 891 * caldata to detect if board has smart antenna or not, once added 892 * we need to fix his piece of code to read and return value without 893 * any compile flags 894 */ 895 #if UMAC_SUPPORT_SMARTANTENNA 896 /* enable smart antenna for Peacock, Wasp and scorpion 897 for future chips need to modify */ 898 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 899 return HAL_OK; 900 } else { 901 return HAL_ENOTSUPP; 902 } 903 #else 904 return HAL_ENOTSUPP; 905 #endif 906 907 #ifdef ATH_TRAFFIC_FAST_RECOVER 908 case HAL_CAP_TRAFFIC_FAST_RECOVER: 909 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 910 return HAL_OK; 911 } else { 912 return HAL_ENOTSUPP; 913 } 914 #endif 915 916 /* FreeBSD ANI */ 917 case HAL_CAP_INTMIT: /* interference mitigation */ 918 switch (capability) { 919 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 920 return HAL_OK; 921 case HAL_CAP_INTMIT_ENABLE: 922 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 923 HAL_OK : HAL_ENXIO; 924 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 925 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 926 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 927 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 928 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 929 ani = ar9300_ani_get_current_state(ah); 930 if (ani == AH_NULL) 931 return HAL_ENXIO; 932 switch (capability) { 933 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 934 case 2: *result = ani->ofdm_noise_immunity_level; break; 935 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 936 // case 4: *result = ani->cck_weak_sig_threshold; break; 937 case 5: *result = ani->firstep_level; break; 938 case 6: *result = ani->spur_immunity_level; break; 939 } 940 return HAL_OK; 941 } 942 return HAL_EINVAL; 943 default: 944 return ath_hal_getcapability(ah, type, capability, result); 945 } 946 } 947 948 HAL_BOOL 949 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 950 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 951 { 952 struct ath_hal_9300 *ahp = AH9300(ah); 953 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 954 u_int32_t v; 955 956 switch (type) { 957 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 958 if (! p_cap->halTkipMicTxRxKeySupport) 959 return AH_FALSE; 960 961 if (setting) 962 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 963 else 964 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 965 966 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 967 return AH_TRUE; 968 969 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 970 if (setting) { 971 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 972 } else { 973 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 974 } 975 return AH_TRUE; 976 case HAL_CAP_DIVERSITY: 977 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 978 if (setting) { 979 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 980 } else { 981 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 982 } 983 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 984 return AH_TRUE; 985 case HAL_CAP_DIAG: /* hardware diagnostic support */ 986 /* 987 * NB: could split this up into virtual capabilities, 988 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 989 * seems worth the additional complexity. 990 */ 991 #ifdef AH_DEBUG 992 AH_PRIVATE(ah)->ah_diagreg = setting; 993 #else 994 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 995 #endif 996 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 997 return AH_TRUE; 998 case HAL_CAP_TPC: 999 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1000 return AH_TRUE; 1001 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1002 if (setting) { 1003 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1004 } else { 1005 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1006 } 1007 return AH_TRUE; 1008 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1009 if (p_cap->halTsfAddSupport) { 1010 if (setting) { 1011 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1012 } else { 1013 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1014 } 1015 return AH_TRUE; 1016 } 1017 return AH_FALSE; 1018 1019 /* FreeBSD interrupt mitigation / ANI */ 1020 case HAL_CAP_INTMIT: { /* interference mitigation */ 1021 /* This maps the public ANI commands to the internal ANI commands */ 1022 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1023 static const HAL_ANI_CMD cmds[] = { 1024 HAL_ANI_PRESENT, 1025 HAL_ANI_MODE, 1026 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1027 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1028 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1029 HAL_ANI_FIRSTEP_LEVEL, 1030 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1031 }; 1032 #define N(a) (sizeof(a) / sizeof(a[0])) 1033 return capability < N(cmds) ? 1034 ar9300_ani_control(ah, cmds[capability], setting) : 1035 AH_FALSE; 1036 #undef N 1037 } 1038 1039 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1040 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1041 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1042 return AH_TRUE; 1043 1044 /* fall thru... */ 1045 default: 1046 return ath_hal_setcapability(ah, type, capability, setting, status); 1047 } 1048 } 1049 1050 #ifdef AH_DEBUG 1051 static void 1052 ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1053 { 1054 u_int32_t i = 0; 1055 1056 /* Read 0x80d0 to trigger pcie analyzer */ 1057 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1058 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1059 1060 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1061 struct ath_hal_9300 *ahp = AH9300(ah); 1062 u_int32_t tf, rf, rc, cc; 1063 1064 tf = OS_REG_READ(ah, AR_TFCNT); 1065 rf = OS_REG_READ(ah, AR_RFCNT); 1066 rc = OS_REG_READ(ah, AR_RCCNT); 1067 cc = OS_REG_READ(ah, AR_CCCNT); 1068 1069 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1070 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1071 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1072 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1073 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1074 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1075 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1076 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1077 1078 ahp->last_tf = tf; 1079 ahp->last_rf = rf; 1080 ahp->last_rc = rc; 1081 ahp->last_cc = cc; 1082 1083 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1084 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1085 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1086 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1087 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1088 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1089 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1090 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1091 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1092 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1093 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1094 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1095 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1096 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1097 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1098 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1099 } 1100 1101 if (args & HAL_DIAG_PRINT_REG_ALL) { 1102 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1103 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1104 i, OS_REG_READ(ah, i)); 1105 } 1106 1107 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1109 i, OS_REG_READ(ah, i)); 1110 } 1111 1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1113 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1114 1115 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1116 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1117 1118 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1119 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1120 i, OS_REG_READ(ah, i)); 1121 } 1122 1123 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1124 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1125 i, OS_REG_READ(ah, i)); 1126 } 1127 1128 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1130 i, OS_REG_READ(ah, i)); 1131 } 1132 1133 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1135 i, OS_REG_READ(ah, i)); 1136 } 1137 1138 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1139 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1140 i, OS_REG_READ(ah, i)); 1141 } 1142 1143 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1144 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1145 i, OS_REG_READ(ah, i)); 1146 } 1147 1148 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1149 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1150 i, OS_REG_READ(ah, i)); 1151 } 1152 1153 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1154 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1155 i, OS_REG_READ(ah, i)); 1156 } 1157 1158 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1159 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1160 i, OS_REG_READ(ah, i)); 1161 } 1162 1163 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1164 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1165 i, OS_REG_READ(ah, i)); 1166 } 1167 1168 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1169 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1170 i, OS_REG_READ(ah, i)); 1171 } 1172 } 1173 } 1174 #endif 1175 1176 HAL_BOOL 1177 ar9300_get_diag_state(struct ath_hal *ah, int request, 1178 const void *args, u_int32_t argsize, 1179 void **result, u_int32_t *resultsize) 1180 { 1181 struct ath_hal_9300 *ahp = AH9300(ah); 1182 1183 (void) ahp; 1184 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1185 return AH_TRUE; 1186 } 1187 switch (request) { 1188 #ifdef AH_PRIVATE_DIAG 1189 case HAL_DIAG_EEPROM: 1190 *result = &ahp->ah_eeprom; 1191 *resultsize = sizeof(ar9300_eeprom_t); 1192 return AH_TRUE; 1193 1194 #if 0 /* XXX - TODO */ 1195 case HAL_DIAG_EEPROM_EXP_11A: 1196 case HAL_DIAG_EEPROM_EXP_11B: 1197 case HAL_DIAG_EEPROM_EXP_11G: 1198 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1199 *result = pe->p_channels; 1200 *resultsize = (*result == AH_NULL) ? 0 : 1201 roundup(sizeof(u_int16_t) * pe->num_channels, 1202 sizeof(u_int32_t)) + 1203 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1204 return AH_TRUE; 1205 #endif 1206 case HAL_DIAG_RFGAIN: 1207 *result = &ahp->ah_gain_values; 1208 *resultsize = sizeof(GAIN_VALUES); 1209 return AH_TRUE; 1210 case HAL_DIAG_RFGAIN_CURSTEP: 1211 *result = (void *) ahp->ah_gain_values.curr_step; 1212 *resultsize = (*result == AH_NULL) ? 1213 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1214 return AH_TRUE; 1215 #if 0 /* XXX - TODO */ 1216 case HAL_DIAG_PCDAC: 1217 *result = ahp->ah_pcdac_table; 1218 *resultsize = ahp->ah_pcdac_table_size; 1219 return AH_TRUE; 1220 #endif 1221 case HAL_DIAG_ANI_CURRENT: 1222 *result = ar9300_ani_get_current_state(ah); 1223 *resultsize = (*result == AH_NULL) ? 1224 0 : sizeof(struct ar9300_ani_state); 1225 return AH_TRUE; 1226 case HAL_DIAG_ANI_STATS: 1227 *result = ar9300_ani_get_current_stats(ah); 1228 *resultsize = (*result == AH_NULL) ? 1229 0 : sizeof(struct ar9300_stats); 1230 return AH_TRUE; 1231 case HAL_DIAG_ANI_CMD: 1232 if (argsize != 2*sizeof(u_int32_t)) { 1233 return AH_FALSE; 1234 } 1235 ar9300_ani_control( 1236 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1237 return AH_TRUE; 1238 #if 0 1239 case HAL_DIAG_TXCONT: 1240 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1241 return AH_TRUE; 1242 #endif /* 0 */ 1243 #endif /* AH_PRIVATE_DIAG */ 1244 case HAL_DIAG_CHANNELS: 1245 #if 0 1246 *result = &(ahp->ah_priv.ah_channels[0]); 1247 *resultsize = 1248 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1249 #endif 1250 return AH_TRUE; 1251 #ifdef AH_DEBUG 1252 case HAL_DIAG_PRINT_REG: 1253 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1254 return AH_TRUE; 1255 #endif 1256 default: 1257 break; 1258 } 1259 1260 return AH_FALSE; 1261 } 1262 1263 void 1264 ar9300_dma_reg_dump(struct ath_hal *ah) 1265 { 1266 #ifdef AH_DEBUG 1267 #define NUM_DMA_DEBUG_REGS 8 1268 #define NUM_QUEUES 10 1269 1270 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1271 int qcu_offset = 0, dcu_offset = 0; 1272 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1273 int i, j, k; 1274 int16_t nfarray[HAL_NUM_NF_READINGS]; 1275 #ifdef ATH_NF_PER_CHAN 1276 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1277 #endif /* ATH_NF_PER_CHAN */ 1278 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1279 1280 /* selecting DMA OBS 8 */ 1281 OS_REG_WRITE(ah, AR_MACMISC, 1282 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1283 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1284 1285 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1286 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1287 if (i % 4 == 0) { 1288 ath_hal_printf(ah, "\n"); 1289 } 1290 1291 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1292 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1293 } 1294 1295 ath_hal_printf(ah, "\n\n"); 1296 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1297 1298 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1299 if (i == 8) { 1300 /* only 8 QCU entries in val[0] */ 1301 qcu_offset = 0; 1302 qcu_base++; 1303 } 1304 1305 if (i == 6) { 1306 /* only 6 DCU entries in val[4] */ 1307 dcu_offset = 0; 1308 dcu_base++; 1309 } 1310 1311 ath_hal_printf(ah, 1312 "%2d %2x %1x %2x %2x\n", 1313 i, 1314 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1315 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1316 val[2] & (0x7 << (i * 3)) >> (i * 3), 1317 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1318 } 1319 1320 ath_hal_printf(ah, "\n"); 1321 ath_hal_printf(ah, 1322 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1323 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1324 ath_hal_printf(ah, 1325 "qcu_complete state: %2x dcu_complete state: %2x\n", 1326 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1327 ath_hal_printf(ah, 1328 "dcu_arb state: %2x dcu_fp state: %2x\n", 1329 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1330 ath_hal_printf(ah, 1331 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1332 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1333 ath_hal_printf(ah, 1334 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1335 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1336 ath_hal_printf(ah, 1337 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1338 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1339 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1340 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1341 1342 ar9300_upload_noise_floor(ah, 1, nfarray); 1343 ath_hal_printf(ah, "2G:\n"); 1344 ath_hal_printf(ah, "Min CCA Out:\n"); 1345 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1346 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1347 nfarray[0], nfarray[1], nfarray[2]); 1348 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1349 nfarray[3], nfarray[4], nfarray[5]); 1350 1351 ar9300_upload_noise_floor(ah, 0, nfarray); 1352 ath_hal_printf(ah, "5G:\n"); 1353 ath_hal_printf(ah, "Min CCA Out:\n"); 1354 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1355 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1356 nfarray[0], nfarray[1], nfarray[2]); 1357 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1358 nfarray[3], nfarray[4], nfarray[5]); 1359 1360 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1361 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1362 ((i < 3) ? "Control " : "Extension "), i%3); 1363 for (j = 0, k = h->base.curr_index; 1364 j < HAL_NF_CAL_HIST_LEN_FULL; 1365 j++, k++) { 1366 ath_hal_printf(ah, "Element %d: %d\n", 1367 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1368 } 1369 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1370 } 1371 1372 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1373 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1374 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1375 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1376 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1377 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1378 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1379 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1380 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1381 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1382 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1383 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1384 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1385 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1386 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1387 reg = OS_REG_READ(ah, AR_PHY_AGC); 1388 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1389 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1390 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1391 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1392 MS(reg, AR_PHY_AGC_COARSE_LOW), 1393 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1394 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1395 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1396 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1397 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1398 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1399 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1400 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1401 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1402 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1403 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1404 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1405 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1406 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1407 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1408 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1409 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1410 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1411 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1412 1413 1414 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1415 reg = OS_REG_READ(ah, 0xa360); 1416 reg &= ~0x00800000; 1417 OS_REG_WRITE(ah, 0xa360, reg); 1418 1419 /* Step 2a: Set register 0xa364 to 0x1000 */ 1420 reg = 0x1000; 1421 OS_REG_WRITE(ah, 0xa364, reg); 1422 1423 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1424 reg = OS_REG_READ(ah, 0x9c20); 1425 reg &= 0x0003ffff; 1426 ath_hal_printf(ah, 1427 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1428 __func__, reg); 1429 1430 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1431 reg = OS_REG_READ(ah, 0xa360); 1432 reg &= ~0x00800000; 1433 OS_REG_WRITE(ah, 0xa360, reg); 1434 1435 /* Step 2b: Set register 0xa364 to 0x1400 */ 1436 reg = 0x1400; 1437 OS_REG_WRITE(ah, 0xa364, reg); 1438 1439 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1440 reg = OS_REG_READ(ah, 0x9c20); 1441 reg &= 0x0003ffff; 1442 ath_hal_printf(ah, 1443 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1444 __func__, reg); 1445 1446 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1447 reg = OS_REG_READ(ah, 0xa360); 1448 reg &= ~0x00800000; 1449 OS_REG_WRITE(ah, 0xa360, reg); 1450 1451 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1452 reg = 0x3c00; 1453 OS_REG_WRITE(ah, 0xa364, reg); 1454 1455 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1456 reg = OS_REG_READ(ah, 0x9c20); 1457 reg &= 0x0003ffff; 1458 ath_hal_printf(ah, 1459 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1460 __func__, reg); 1461 1462 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1463 reg = OS_REG_READ(ah, 0xa360); 1464 reg &= ~0x001040000; 1465 OS_REG_WRITE(ah, 0xa360, reg); 1466 1467 /* Step 2d: Set register 0xa364 to 0x5005D */ 1468 reg = 0x5005D; 1469 OS_REG_WRITE(ah, 0xa364, reg); 1470 1471 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1472 reg = OS_REG_READ(ah, 0xa368); 1473 reg &= 0x0003ffff; 1474 ath_hal_printf(ah, 1475 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1476 __func__, reg); 1477 1478 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1479 reg = OS_REG_READ(ah, 0xa360); 1480 reg &= ~0x001040000; 1481 OS_REG_WRITE(ah, 0xa360, reg); 1482 1483 /* Step 2e: Set register 0xa364 to 0x7005D */ 1484 reg = 0x7005D; 1485 OS_REG_WRITE(ah, 0xa364, reg); 1486 1487 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1488 reg = OS_REG_READ(ah, 0xa368); 1489 reg &= 0x0003ffff; 1490 ath_hal_printf(ah, 1491 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1492 __func__, reg); 1493 1494 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1495 reg = OS_REG_READ(ah, 0xa360); 1496 reg &= ~0x001000000; 1497 reg |= 0x40000; 1498 OS_REG_WRITE(ah, 0xa360, reg); 1499 1500 /* Step 2f: Set register 0xa364 to 0x3005D */ 1501 reg = 0x3005D; 1502 OS_REG_WRITE(ah, 0xa364, reg); 1503 1504 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1505 reg = OS_REG_READ(ah, 0xa368); 1506 reg &= 0x0003ffff; 1507 ath_hal_printf(ah, 1508 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1509 __func__, reg); 1510 1511 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1512 reg = OS_REG_READ(ah, 0xa360); 1513 reg &= ~0x001000000; 1514 reg |= 0x40000; 1515 OS_REG_WRITE(ah, 0xa360, reg); 1516 1517 /* Step 2g: Set register 0xa364 to 0x6005D */ 1518 reg = 0x6005D; 1519 OS_REG_WRITE(ah, 0xa364, reg); 1520 1521 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1522 reg = OS_REG_READ(ah, 0xa368); 1523 reg &= 0x0003ffff; 1524 ath_hal_printf(ah, 1525 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1526 __func__, reg); 1527 #endif /* AH_DEBUG */ 1528 } 1529 1530 /* 1531 * Return the busy for rx_frame, rx_clear, and tx_frame 1532 */ 1533 u_int32_t 1534 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1535 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1536 { 1537 struct ath_hal_9300 *ahp = AH9300(ah); 1538 u_int32_t good = 1; 1539 1540 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1541 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1542 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1543 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1544 1545 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1546 /* 1547 * Cycle counter wrap (or initial call); it's not possible 1548 * to accurately calculate a value because the registers 1549 * right shift rather than wrap--so punt and return 0. 1550 */ 1551 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1552 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1553 good = 0; 1554 } else { 1555 u_int32_t cc_d = cc - ahp->ah_cycles; 1556 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1557 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1558 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1559 1560 if (cc_d != 0) { 1561 *rxc_pcnt = rc_d * 100 / cc_d; 1562 *rxf_pcnt = rf_d * 100 / cc_d; 1563 *txf_pcnt = tf_d * 100 / cc_d; 1564 } else { 1565 good = 0; 1566 } 1567 } 1568 1569 ahp->ah_cycles = cc; 1570 ahp->ah_rx_frame = rf; 1571 ahp->ah_rx_clear = rc; 1572 ahp->ah_tx_frame = tf; 1573 1574 return good; 1575 } 1576 1577 /* 1578 * Return approximation of extension channel busy over an time interval 1579 * 0% (clear) -> 100% (busy) 1580 * -1 for invalid estimate 1581 */ 1582 uint32_t 1583 ar9300_get_11n_ext_busy(struct ath_hal *ah) 1584 { 1585 /* 1586 * Overflow condition to check before multiplying to get % 1587 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1588 */ 1589 #define OVERFLOW_LIMIT 0x28F5C28 1590 #define ERROR_CODE -1 1591 1592 struct ath_hal_9300 *ahp = AH9300(ah); 1593 u_int32_t busy = 0; /* percentage */ 1594 int8_t busyper = 0; 1595 u_int32_t cycle_count, ctl_busy, ext_busy; 1596 1597 /* cycle_count will always be the first to wrap; therefore, read it last 1598 * This sequence of reads is not atomic, and MIB counter wrap 1599 * could happen during it ? 1600 */ 1601 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1602 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1603 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1604 1605 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1606 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1607 { 1608 /* 1609 * Cycle counter wrap (or initial call); it's not possible 1610 * to accurately calculate a value because the registers 1611 * right shift rather than wrap--so punt and return 0. 1612 */ 1613 busyper = ERROR_CODE; 1614 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1615 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1616 } else { 1617 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1618 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1619 1620 /* 1621 * Compute extension channel busy percentage 1622 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1623 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1624 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1625 * and shift necessitated by large ext_busy_delta. 1626 * Due to timing difference to read the registers and counter overflow, 1627 * it may still happen that cycle_delta >> 7 = 0. 1628 * 1629 */ 1630 if (cycle_delta) { 1631 if (ext_busy_delta > OVERFLOW_LIMIT) { 1632 if (cycle_delta >> 7) { 1633 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1634 } else { 1635 busyper = ERROR_CODE; 1636 } 1637 } else { 1638 busy = (ext_busy_delta * 100) / cycle_delta; 1639 } 1640 } else { 1641 busyper = ERROR_CODE; 1642 } 1643 1644 if (busy > 100) { 1645 busy = 100; 1646 } 1647 if ( busyper != ERROR_CODE ) { 1648 busyper = busy; 1649 } 1650 } 1651 1652 ahp->ah_cycle_count = cycle_count; 1653 ahp->ah_ctl_busy = ctl_busy; 1654 ahp->ah_ext_busy = ext_busy; 1655 1656 return busyper; 1657 #undef OVERFLOW_LIMIT 1658 #undef ERROR_CODE 1659 } 1660 1661 /* BB Panic Watchdog declarations */ 1662 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1663 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1664 1665 void 1666 ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1667 { 1668 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1669 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1670 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1671 u_int32_t val, idle_count; 1672 1673 if (idle_tmo_ms != 0) { 1674 /* enable IRQ, disable chip-reset for BB panic */ 1675 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1676 AR_PHY_BB_PANIC_CNTL2_MASK; 1677 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1678 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1679 /* bound limit to 10 secs */ 1680 if (idle_tmo_ms > 10000) { 1681 idle_tmo_ms = 10000; 1682 } 1683 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1684 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1685 } else { 1686 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1687 } 1688 /* 1689 * enable panic in non-IDLE mode, 1690 * disable in IDLE mode, 1691 * set idle time-out 1692 */ 1693 1694 // EV92527 : Enable IDLE mode panic 1695 1696 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1697 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1698 AR_PHY_BB_PANIC_IDLE_ENABLE | 1699 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1700 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1701 } else { 1702 /* disable IRQ, disable chip-reset for BB panic */ 1703 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1704 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1705 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1706 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1707 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1708 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1709 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1710 } 1711 1712 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1713 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1714 #undef HAL_BB_PANIC_IDLE_TIME_OUT 1715 } 1716 1717 1718 void 1719 ar9300_handle_bb_panic(struct ath_hal *ah) 1720 { 1721 u_int32_t status; 1722 /* 1723 * we want to avoid printing in ISR context so we save 1724 * panic watchdog status to be printed later in DPC context 1725 */ 1726 AH9300(ah)->ah_bb_panic_last_status = status = 1727 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1728 /* 1729 * panic watchdog timer should reset on status read 1730 * but to make sure we write 0 to the watchdog status bit 1731 */ 1732 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1733 } 1734 1735 int 1736 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1737 { 1738 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1739 1740 /* 1741 * For signature 04000539 do not print anything. 1742 * This is a very common occurence as a compromise between 1743 * BB Panic and AH_FALSE detects (EV71009). It indicates 1744 * radar hang, which can be cleared by reprogramming 1745 * radar related register and does not requre a chip reset 1746 */ 1747 1748 /* Suppress BB Status mesg following signature */ 1749 switch (bb_panic->status) { 1750 case 0x04000539: 1751 case 0x04008009: 1752 case 0x04000b09: 1753 case 0x1300000a: 1754 return -1; 1755 } 1756 1757 bb_panic->tsf = ar9300_get_tsf32(ah); 1758 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1759 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1760 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1761 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1762 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1763 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1764 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1765 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1766 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1767 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1768 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1769 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1770 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1771 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1772 &bb_panic->rxc_pcnt, 1773 &bb_panic->rxf_pcnt, 1774 &bb_panic->txf_pcnt); 1775 1776 if (ah->ah_config.ath_hal_show_bb_panic) { 1777 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1778 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1779 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1780 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1781 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1782 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1783 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1784 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1785 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1786 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1787 bb_panic->phy_gen_ctrl); 1788 if (bb_panic->cycles) { 1789 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1790 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1791 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1792 } 1793 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1794 } 1795 1796 return 0; //The returned data will be stored for athstats to retrieve it 1797 } 1798 1799 /* set the reason for HAL reset */ 1800 void 1801 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1802 { 1803 AH9300(ah)->ah_reset_reason = resetreason; 1804 } 1805 1806 /* 1807 * Configure 20/40 operation 1808 * 1809 * 20/40 = joint rx clear (control and extension) 1810 * 20 = rx clear (control) 1811 * 1812 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1813 * when changing from 20/40 => 20 only 1814 */ 1815 void 1816 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1817 { 1818 u_int32_t macmode; 1819 1820 /* Configure MAC for 20/40 operation */ 1821 if (mode == HAL_HT_MACMODE_2040 && 1822 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1823 macmode = AR_2040_JOINED_RX_CLEAR; 1824 } else { 1825 macmode = 0; 1826 } 1827 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1828 } 1829 1830 /* 1831 * Get Rx clear (control/extension channel) 1832 * 1833 * Returns active low (busy) for ctrl/ext channel 1834 * Owl 2.0 1835 */ 1836 HAL_HT_RXCLEAR 1837 ar9300_get_11n_rx_clear(struct ath_hal *ah) 1838 { 1839 HAL_HT_RXCLEAR rxclear = 0; 1840 u_int32_t val; 1841 1842 val = OS_REG_READ(ah, AR_DIAG_SW); 1843 1844 /* control channel */ 1845 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1846 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1847 } 1848 /* extension channel */ 1849 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1850 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1851 } 1852 return rxclear; 1853 } 1854 1855 /* 1856 * Set Rx clear (control/extension channel) 1857 * 1858 * Useful for forcing the channel to appear busy for 1859 * debugging/diagnostics 1860 * Owl 2.0 1861 */ 1862 void 1863 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1864 { 1865 /* control channel */ 1866 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1867 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1868 } else { 1869 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1870 } 1871 /* extension channel */ 1872 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1873 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1874 } else { 1875 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1876 } 1877 } 1878 1879 1880 /* 1881 * HAL support code for force ppm tracking workaround. 1882 */ 1883 1884 u_int32_t 1885 ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1886 { 1887 u_int32_t retval; 1888 u_int32_t off1; 1889 u_int32_t off2; 1890 1891 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1892 off1 = 0x2000; 1893 off2 = 0x1000; 1894 } else { 1895 off1 = 0x1000; 1896 off2 = 0x2000; 1897 } 1898 1899 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1900 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1901 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1902 1903 return retval; 1904 } 1905 1906 u_int32_t 1907 ar9300_ppm_force(struct ath_hal *ah) 1908 { 1909 u_int32_t data_fine; 1910 u_int32_t data4; 1911 //u_int32_t off1; 1912 //u_int32_t off2; 1913 HAL_BOOL signed_val = AH_FALSE; 1914 1915 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1916 // off1 = 0x2000; 1917 // off2 = 0x1000; 1918 // } else { 1919 // off1 = 0x1000; 1920 // off2 = 0x2000; 1921 // } 1922 data_fine = 1923 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1924 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1925 1926 /* 1927 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1928 * So check value from bit[10:0]. 1929 * Now get the abs val of the ppm value read in bit[0:11]. 1930 * After that do bound check on abs value. 1931 * if value is off limit, CAP the value and and restore signed bit. 1932 */ 1933 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1934 { 1935 /* get the positive value */ 1936 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1937 signed_val = AH_TRUE; 1938 } 1939 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1940 { 1941 HALDEBUG(ah, HAL_DEBUG_REGIO, 1942 "%s Correcting ppm out of range %x\n", 1943 __func__, (data_fine & 0x7ff)); 1944 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 1945 } 1946 /* 1947 * Restore signed value if changed above. 1948 * Use typecast to avoid compilation errors 1949 */ 1950 if (signed_val) { 1951 data_fine = (-(int32_t)data_fine) & 1952 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1953 } 1954 1955 /* write value */ 1956 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 1957 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1958 OS_REG_WRITE(ah, AR_PHY_TIMING2, 1959 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 1960 1961 return data_fine; 1962 } 1963 1964 void 1965 ar9300_ppm_un_force(struct ath_hal *ah) 1966 { 1967 u_int32_t data4; 1968 1969 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 1970 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 1971 } 1972 1973 u_int32_t 1974 ar9300_ppm_arm_trigger(struct ath_hal *ah) 1975 { 1976 u_int32_t val; 1977 u_int32_t ret; 1978 1979 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 1980 ret = OS_REG_READ(ah, AR_TSF_L32); 1981 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 1982 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 1983 1984 /* return low word of TSF at arm time */ 1985 return ret; 1986 } 1987 1988 int 1989 ar9300_ppm_get_trigger(struct ath_hal *ah) 1990 { 1991 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 1992 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 1993 { 1994 /* has not triggered yet, return AH_FALSE */ 1995 return 0; 1996 } 1997 1998 /* else triggered, return AH_TRUE */ 1999 return 1; 2000 } 2001 2002 void 2003 ar9300_mark_phy_inactive(struct ath_hal *ah) 2004 { 2005 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2006 } 2007 2008 /* DEBUG */ 2009 u_int32_t 2010 ar9300_ppm_get_force_state(struct ath_hal *ah) 2011 { 2012 return 2013 OS_REG_READ(ah, AR_PHY_TIMING2) & 2014 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2015 } 2016 2017 /* 2018 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2019 */ 2020 HAL_BOOL 2021 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2022 { 2023 /* 2024 * XXX FreeBSD todo: reimplement this 2025 */ 2026 #if 0 2027 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2028 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2029 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2030 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2031 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2032 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2033 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2034 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2035 #endif 2036 return AH_FALSE; 2037 } 2038 2039 void 2040 ar9300_clear_mib_counters(struct ath_hal *ah) 2041 { 2042 u_int32_t reg_val; 2043 2044 reg_val = OS_REG_READ(ah, AR_MIBC); 2045 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2046 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2047 } 2048 2049 2050 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2051 HAL_BOOL 2052 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2053 { 2054 struct ath_hal_9300 *ahp = AH9300(ah); 2055 HAL_CHANNEL_INTERNAL *ichan = 2056 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2057 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2058 u_int32_t tmp = 0; 2059 2060 if (enable) { 2061 if (ahp->ah_rifs_enabled == AH_TRUE) { 2062 return AH_TRUE; 2063 } 2064 2065 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2066 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2067 ahp->ah_rifs_reg[1]); 2068 2069 ahp->ah_rifs_enabled = AH_TRUE; 2070 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2071 } else { 2072 if (ahp->ah_rifs_enabled == AH_TRUE) { 2073 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2074 AR_PHY_SEARCH_START_DELAY); 2075 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2076 } 2077 /* Change rifs init delay to 0 */ 2078 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2079 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2080 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2081 if (is_chan_2g) { 2082 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2083 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2084 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2085 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2086 } 2087 } else { 2088 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2089 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2090 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2091 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2092 } 2093 } 2094 2095 ahp->ah_rifs_enabled = AH_FALSE; 2096 } 2097 return AH_TRUE; 2098 2099 } /* ar9300_set_rifs_delay () */ 2100 2101 /* Set the current RIFS Rx setting */ 2102 HAL_BOOL 2103 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2104 { 2105 /* Non-Owl 11n chips */ 2106 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2107 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2108 return ar9300_set_rifs_delay(ah, enable); 2109 } 2110 return AH_FALSE; 2111 } 2112 2113 return AH_TRUE; 2114 } /* ar9300_set_11n_rx_rifs () */ 2115 2116 static hal_mac_hangs_t 2117 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2118 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2119 { 2120 int i = 0; 2121 hal_mac_hangs_t found_hangs = 0; 2122 2123 if (hangs & dcu_chain_state) { 2124 for (i = 0; i < 6; i++) { 2125 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2126 hang_check.dcu_chain_state) 2127 { 2128 found_hangs |= dcu_chain_state; 2129 *dcu_chain = i; 2130 } 2131 } 2132 for (i = 0; i < 4; i++) { 2133 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2134 hang_check.dcu_chain_state) 2135 { 2136 found_hangs |= dcu_chain_state; 2137 *dcu_chain = i + 6; 2138 } 2139 } 2140 } 2141 2142 if (hangs & dcu_complete_state) { 2143 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2144 found_hangs |= dcu_complete_state; 2145 } 2146 } 2147 2148 return found_hangs; 2149 2150 } /* end - ar9300_compare_dbg_hang */ 2151 2152 #define NUM_STATUS_READS 50 2153 HAL_BOOL 2154 ar9300_detect_mac_hang(struct ath_hal *ah) 2155 { 2156 struct ath_hal_9300 *ahp = AH9300(ah); 2157 mac_dbg_regs_t mac_dbg; 2158 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2159 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2160 int i = 0; 2161 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2162 2163 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2164 return AH_FALSE; 2165 } 2166 2167 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2168 2169 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2170 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2171 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2172 2173 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2174 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2175 mac_dbg.dma_dbg_6); 2176 2177 if (hang_sig1 != 2178 ar9300_compare_dbg_hang(ah, mac_dbg, 2179 hang_sig1_val, hang_sig1, &dcu_chain)) 2180 { 2181 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2182 return AH_FALSE; 2183 } 2184 2185 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2186 shift_val *= 5; 2187 2188 for (i = 1; i <= NUM_STATUS_READS; i++) { 2189 if (dcu_chain < 6) { 2190 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2191 current_dcu_chain_state = 2192 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2193 } else { 2194 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2195 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2196 } 2197 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2198 2199 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2200 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2201 return AH_FALSE; 2202 } 2203 } 2204 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2205 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2206 ahp->ah_hang[MAC_HANG_SIG1]++; 2207 return AH_TRUE; 2208 2209 } /* end - ar9300_detect_mac_hang */ 2210 2211 /* Determine if the baseband is hung by reading the Observation Bus Register */ 2212 HAL_BOOL 2213 ar9300_detect_bb_hang(struct ath_hal *ah) 2214 { 2215 #define N(a) (sizeof(a) / sizeof(a[0])) 2216 struct ath_hal_9300 *ahp = AH9300(ah); 2217 u_int32_t hang_sig = 0; 2218 int i = 0; 2219 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2220 * 2221 * 4 known BB hang signatures - 2222 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2223 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2224 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2225 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2226 * Rx State (bits 20-24) is 0x7. 2227 */ 2228 hal_hw_hang_check_t hang_list [] = 2229 { 2230 /* Offset Reg Value Reg Mask Hang Offset */ 2231 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2232 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2233 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2234 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2235 }; 2236 2237 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2238 HAL_DFS_BB_HANG_WAR | 2239 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2240 return AH_FALSE; 2241 } 2242 2243 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2244 for (i = 1; i <= NUM_STATUS_READS; i++) { 2245 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2246 return AH_FALSE; 2247 } 2248 } 2249 2250 for (i = 0; i < N(hang_list); i++) { 2251 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2252 ahp->ah_hang[hang_list[i].hang_offset]++; 2253 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2254 "sig3count=%d sig4count=%d\n", __func__, 2255 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2256 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2257 return AH_TRUE; 2258 } 2259 } 2260 2261 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2262 "<0x806c>=0x%x\n", __func__, hang_sig); 2263 2264 return AH_FALSE; 2265 2266 #undef N 2267 } /* end - ar9300_detect_bb_hang () */ 2268 2269 #undef NUM_STATUS_READS 2270 2271 HAL_STATUS 2272 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2273 { 2274 struct ath_hal_9300 *ahp = AH9300(ah); 2275 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2276 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2277 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2278 u_int16_t ant_config; 2279 u_int32_t hal_num_ant_config; 2280 2281 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2282 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2283 2284 if (cfg < hal_num_ant_config) { 2285 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2286 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2287 return HAL_OK; 2288 } 2289 } 2290 2291 return HAL_EINVAL; 2292 } 2293 2294 /* 2295 * Functions to get/set DCS mode 2296 */ 2297 void 2298 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2299 { 2300 AH9300(ah)->ah_dcs_enable = mode; 2301 } 2302 2303 u_int32_t 2304 ar9300_get_dcs_mode(struct ath_hal *ah) 2305 { 2306 return AH9300(ah)->ah_dcs_enable; 2307 } 2308 2309 #if ATH_BT_COEX 2310 void 2311 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2312 { 2313 struct ath_hal_9300 *ahp = AH9300(ah); 2314 2315 ahp->ah_bt_module = btinfo->bt_module; 2316 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2317 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2318 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2319 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2320 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2321 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2322 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2323 } 2324 2325 void 2326 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2327 { 2328 struct ath_hal_9300 *ahp = AH9300(ah); 2329 HAL_BOOL rx_clear_polarity; 2330 2331 /* 2332 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2333 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2334 */ 2335 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2336 2337 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2338 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2339 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2340 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2341 SM(btconf->bt_mode, AR_BT_MODE) | 2342 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2343 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2344 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2345 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2346 2347 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2348 2349 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2350 /* Enable ACK to go out even though BT has higher priority. */ 2351 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2352 } 2353 } 2354 2355 void 2356 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2357 { 2358 struct ath_hal_9300 *ahp = AH9300(ah); 2359 2360 /* clear the old value, then set the new value */ 2361 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2362 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2363 } 2364 2365 void 2366 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2367 { 2368 struct ath_hal_9300 *ahp = AH9300(ah); 2369 2370 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2371 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2372 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2373 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2374 2375 switch (stomp_type) { 2376 case HAL_BT_COEX_STOMP_ALL: 2377 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2378 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2379 break; 2380 case HAL_BT_COEX_STOMP_LOW: 2381 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2382 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2383 break; 2384 case HAL_BT_COEX_STOMP_ALL_FORCE: 2385 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2386 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2387 break; 2388 case HAL_BT_COEX_STOMP_LOW_FORCE: 2389 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2390 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2391 break; 2392 case HAL_BT_COEX_STOMP_NONE: 2393 case HAL_BT_COEX_NO_STOMP: 2394 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2395 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2396 break; 2397 default: 2398 /* There is a force_weight from registry */ 2399 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2400 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2401 break; 2402 } 2403 } 2404 2405 void 2406 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2407 { 2408 struct ath_hal_9300 *ahp = AH9300(ah); 2409 2410 /* clear the old value, then set the new value */ 2411 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2412 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2413 } 2414 2415 static void 2416 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2417 { 2418 struct ath_hal_9300 *ahp = AH9300(ah); 2419 #if ATH_ANT_DIV_COMB 2420 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2421 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2422 #endif 2423 2424 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2425 { 2426 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2427 { 2428 /* Config antenna diversity */ 2429 #if ATH_ANT_DIV_COMB 2430 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2431 #endif 2432 } 2433 } 2434 } 2435 2436 2437 void 2438 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2439 u_int32_t value) 2440 { 2441 struct ath_hal_9300 *ahp = AH9300(ah); 2442 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2443 2444 switch (type) { 2445 case HAL_BT_COEX_SET_ACK_PWR: 2446 if (value) { 2447 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2448 } else { 2449 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2450 } 2451 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2452 ahpriv->ah_extraTxPow, 0); 2453 break; 2454 2455 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2456 if (AR_SREV_POSEIDON(ah)) { 2457 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2458 if (value) { 2459 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2460 } 2461 else { 2462 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2463 } 2464 ar9300_bt_coex_antenna_diversity(ah, value); 2465 } 2466 break; 2467 case HAL_BT_COEX_LOWER_TX_PWR: 2468 if (value) { 2469 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2470 } 2471 else { 2472 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2473 } 2474 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2475 ahpriv->ah_extraTxPow, 0); 2476 break; 2477 #if ATH_SUPPORT_MCI 2478 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2479 if ((ah->ah_config.ath_hal_mci_config & 2480 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2481 { 2482 if (value) { 2483 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2484 ahp->ah_mci_concur_tx_en = AH_TRUE; 2485 } 2486 else { 2487 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2488 ahp->ah_mci_concur_tx_en = AH_FALSE; 2489 } 2490 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2491 ahpriv->ah_extraTxPow, 0); 2492 } 2493 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2494 ahp->ah_mci_concur_tx_en); 2495 break; 2496 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2497 if (value) { 2498 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2499 } 2500 else { 2501 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2502 } 2503 break; 2504 #endif 2505 default: 2506 break; 2507 } 2508 } 2509 2510 void 2511 ar9300_bt_coex_disable(struct ath_hal *ah) 2512 { 2513 struct ath_hal_9300 *ahp = AH9300(ah); 2514 2515 /* Always drive rx_clear_external output as 0 */ 2516 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2517 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2518 2519 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2520 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2521 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2522 } 2523 2524 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2525 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2526 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2527 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2528 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2529 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2530 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2531 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2532 2533 ahp->ah_bt_coex_enabled = AH_FALSE; 2534 } 2535 2536 int 2537 ar9300_bt_coex_enable(struct ath_hal *ah) 2538 { 2539 struct ath_hal_9300 *ahp = AH9300(ah); 2540 2541 /* Program coex mode and weight registers to actually enable coex */ 2542 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2543 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2544 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2545 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2546 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2547 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2548 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2549 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2550 2551 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2552 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2553 } else { 2554 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2555 } 2556 2557 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2558 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2559 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2560 } else { 2561 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2562 } 2563 2564 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2565 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2566 ath_hal_gpioCfgOutput(ah, 2567 ahp->ah_wlan_active_gpio_select, 2568 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2569 } 2570 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2571 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2572 { 2573 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2574 ath_hal_gpioCfgOutput(ah, 2575 ahp->ah_wlan_active_gpio_select, 2576 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2577 } 2578 2579 /* 2580 * Enable a weak pull down on BT_ACTIVE. 2581 * When BT device is disabled, BT_ACTIVE might be floating. 2582 */ 2583 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2584 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2585 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2586 2587 ahp->ah_bt_coex_enabled = AH_TRUE; 2588 2589 return 0; 2590 } 2591 2592 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2593 { 2594 return 0; 2595 } 2596 2597 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2598 { 2599 return bOn; 2600 } 2601 2602 void 2603 ar9300_init_bt_coex(struct ath_hal *ah) 2604 { 2605 struct ath_hal_9300 *ahp = AH9300(ah); 2606 2607 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2608 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2609 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2610 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2611 2612 /* 2613 * Set input mux for bt_prority_async and 2614 * bt_active_async to GPIO pins 2615 */ 2616 OS_REG_RMW_FIELD(ah, 2617 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2618 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2619 ahp->ah_bt_active_gpio_select); 2620 OS_REG_RMW_FIELD(ah, 2621 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2622 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2623 ahp->ah_bt_priority_gpio_select); 2624 2625 /* Configure the desired GPIO ports for input */ 2626 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2627 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2628 2629 if (ahp->ah_bt_coex_enabled) { 2630 ar9300_bt_coex_enable(ah); 2631 } else { 2632 ar9300_bt_coex_disable(ah); 2633 } 2634 } 2635 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2636 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2637 { 2638 /* 2-wire */ 2639 if (ahp->ah_bt_coex_enabled) { 2640 /* Connect bt_active_async to baseband */ 2641 OS_REG_CLR_BIT(ah, 2642 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2643 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2644 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2645 OS_REG_SET_BIT(ah, 2646 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2647 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2648 2649 /* 2650 * Set input mux for bt_prority_async and 2651 * bt_active_async to GPIO pins 2652 */ 2653 OS_REG_RMW_FIELD(ah, 2654 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2655 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2656 ahp->ah_bt_active_gpio_select); 2657 2658 /* Configure the desired GPIO ports for input */ 2659 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2660 2661 /* Enable coexistence on initialization */ 2662 ar9300_bt_coex_enable(ah); 2663 } 2664 } 2665 #if ATH_SUPPORT_MCI 2666 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2667 if (ahp->ah_bt_coex_enabled) { 2668 ar9300_mci_bt_coex_enable(ah); 2669 } 2670 else { 2671 ar9300_mci_bt_coex_disable(ah); 2672 } 2673 } 2674 #endif /* ATH_SUPPORT_MCI */ 2675 } 2676 2677 #endif /* ATH_BT_COEX */ 2678 2679 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2680 { 2681 u_int32_t val; 2682 int wasp_mm_rev; 2683 2684 #define AR_SOC_RST_REVISION_ID 0xB8060090 2685 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2686 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2687 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2688 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2689 #undef AR_SOC_RST_REVISION_ID 2690 #undef REG_READ 2691 2692 /* 2693 * Azimuth (ProxySTA) Mode is only supported correctly by 2694 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2695 * 2696 * Enable this feature for Scorpion at this time. The silicon 2697 * still needs to be validated. 2698 */ 2699 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2700 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2701 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2702 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2703 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2704 wasp_mm_rev >= 0 /* 1 */)))) 2705 { 2706 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2707 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2708 __func__, AH_PRIVATE((ah))->ah_macVersion, 2709 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2710 return HAL_ENOTSUPP; 2711 } 2712 2713 OS_REG_WRITE(ah, 2714 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2715 2716 /* turn on mode bit[24] for proxy sta */ 2717 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2718 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2719 2720 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2721 if (enable) { 2722 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2723 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2724 AR_AZIMUTH_BA_USES_AD1; 2725 /* turn off filter pass hold (bit 9) */ 2726 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2727 } else { 2728 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2729 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2730 AR_AZIMUTH_BA_USES_AD1); 2731 } 2732 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2733 2734 /* enable promiscous mode */ 2735 OS_REG_WRITE(ah, AR_RX_FILTER, 2736 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2737 /* enable promiscous in azimuth mode */ 2738 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2739 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2740 2741 /* turn on filter pass hold (bit 9) */ 2742 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2743 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2744 2745 return HAL_OK; 2746 } 2747 2748 #if 0 2749 void ar9300_mat_enable(struct ath_hal *ah, int enable) 2750 { 2751 /* 2752 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2753 * mitigation and turn on key search always for better performance. 2754 */ 2755 struct ath_hal_9300 *ahp = AH9300(ah); 2756 struct ath_hal_private *ap = AH_PRIVATE(ah); 2757 2758 ahp->ah_intr_mitigation_rx = !enable; 2759 if (ahp->ah_intr_mitigation_rx) { 2760 /* 2761 * Enable Interrupt Mitigation for Rx. 2762 * If no build-specific limits for the rx interrupt mitigation 2763 * timer have been specified, use conservative defaults. 2764 */ 2765 #ifndef AH_RIMT_VAL_LAST 2766 #define AH_RIMT_LAST_MICROSEC 500 2767 #endif 2768 #ifndef AH_RIMT_VAL_FIRST 2769 #define AH_RIMT_FIRST_MICROSEC 2000 2770 #endif 2771 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2772 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2773 } else { 2774 OS_REG_WRITE(ah, AR_RIMT, 0); 2775 } 2776 2777 ahp->ah_enable_keysearch_always = !!enable; 2778 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2779 } 2780 #endif 2781 2782 void ar9300_enable_tpc(struct ath_hal *ah) 2783 { 2784 u_int32_t val = 0; 2785 2786 ah->ah_config.ath_hal_desc_tpc = 1; 2787 2788 /* Enable TPC */ 2789 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2790 2791 /* 2792 * Disable per chain power reduction since we are already 2793 * accounting for this in our calculations 2794 */ 2795 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2796 if (AR_SREV_WASP(ah)) { 2797 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2798 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2799 } else { 2800 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2801 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2802 } 2803 } 2804 2805 2806 /* 2807 * ar9300_force_tsf_sync 2808 * This function forces the TSF sync to the given bssid, this is implemented 2809 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2810 * mode of operation, where we sync the TSF to RootAP TSF values 2811 */ 2812 void 2813 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2814 u_int16_t assoc_id) 2815 { 2816 ar9300_set_operating_mode(ah, HAL_M_STA); 2817 ar9300_write_associd(ah, bssid, assoc_id); 2818 } 2819 2820 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2821 { 2822 struct ath_hal_9300 *ahp = AH9300(ah); 2823 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2824 u_int32_t temp_powertx_rate9_reg_val; 2825 int8_t olpc_power_offset = 0; 2826 int8_t tmp_olpc_val = 0; 2827 HAL_RSSI_TX_POWER old_greentx_status; 2828 u_int8_t target_power_val_t[ar9300_rate_size]; 2829 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2830 2831 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2832 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2833 return; 2834 } 2835 2836 old_greentx_status = AH9300(ah)->green_tx_status; 2837 if (ahp->ah_hw_green_tx_enable) { 2838 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2839 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2840 } else { 2841 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2842 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2843 } 2844 2845 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2846 && (rssi > tmp_rss1_thr1)) 2847 { 2848 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2849 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2850 } 2851 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2852 && (rssi > tmp_rss1_thr2)) 2853 { 2854 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2855 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2856 } 2857 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2858 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2859 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2860 } 2861 } 2862 2863 /* If status is not change, don't do anything */ 2864 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2865 return; 2866 } 2867 2868 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2869 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2870 && AR_SREV_POSEIDON(ah)) 2871 { 2872 if (ahp->ah_hw_green_tx_enable) { 2873 switch (AH9300(ah)->green_tx_status) { 2874 case HAL_RSSI_TX_POWER_SHORT: 2875 /* 1. TxPower Config */ 2876 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2877 sizeof(target_power_val_t)); 2878 /* 1.1 Store OLPC Delta Calibration Offset*/ 2879 olpc_power_offset = 0; 2880 /* 2. Store OB/DB */ 2881 /* 3. Store TPC settting */ 2882 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2883 SM(14, AR_TPC_CTS) | 2884 SM(14, AR_TPC_CHIRP) | 2885 SM(14, AR_TPC_RPT)); 2886 /* 4. Store BB_powertx_rate9 value */ 2887 temp_powertx_rate9_reg_val = 2888 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2889 break; 2890 case HAL_RSSI_TX_POWER_MIDDLE: 2891 /* 1. TxPower Config */ 2892 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2893 sizeof(target_power_val_t)); 2894 /* 1.1 Store OLPC Delta Calibration Offset*/ 2895 olpc_power_offset = 0; 2896 /* 2. Store OB/DB */ 2897 /* 3. Store TPC settting */ 2898 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2899 SM(18, AR_TPC_CTS) | 2900 SM(18, AR_TPC_CHIRP) | 2901 SM(18, AR_TPC_RPT)); 2902 /* 4. Store BB_powertx_rate9 value */ 2903 temp_powertx_rate9_reg_val = 2904 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2905 break; 2906 case HAL_RSSI_TX_POWER_LONG: 2907 default: 2908 /* 1. TxPower Config */ 2909 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2910 sizeof(target_power_val_t)); 2911 /* 1.1 Store OLPC Delta Calibration Offset*/ 2912 olpc_power_offset = 0; 2913 /* 2. Store OB/DB1/DB2 */ 2914 /* 3. Store TPC settting */ 2915 temp_tcp_reg_val = 2916 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2917 /* 4. Store BB_powertx_rate9 value */ 2918 temp_powertx_rate9_reg_val = 2919 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2920 break; 2921 } 2922 } else { 2923 switch (AH9300(ah)->green_tx_status) { 2924 case HAL_RSSI_TX_POWER_SHORT: 2925 /* 1. TxPower Config */ 2926 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2927 sizeof(target_power_val_t)); 2928 /* 1.1 Store OLPC Delta Calibration Offset*/ 2929 olpc_power_offset = 2930 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2931 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2932 /* 2. Store OB/DB */ 2933 temp_obdb_reg_val = 2934 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2935 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2936 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2937 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2938 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2939 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2940 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2941 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2942 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2943 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2944 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2945 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2946 /* 3. Store TPC settting */ 2947 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 2948 SM(6, AR_TPC_CTS) | 2949 SM(6, AR_TPC_CHIRP) | 2950 SM(6, AR_TPC_RPT)); 2951 /* 4. Store BB_powertx_rate9 value */ 2952 temp_powertx_rate9_reg_val = 2953 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 2954 break; 2955 case HAL_RSSI_TX_POWER_MIDDLE: 2956 /* 1. TxPower Config */ 2957 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 2958 sizeof(target_power_val_t)); 2959 /* 1.1 Store OLPC Delta Calibration Offset*/ 2960 olpc_power_offset = 2961 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 2962 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2963 /* 2. Store OB/DB */ 2964 temp_obdb_reg_val = 2965 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2966 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2967 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2968 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2969 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2970 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2971 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2972 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2973 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2974 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2975 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2976 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2977 /* 3. Store TPC settting */ 2978 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2979 SM(14, AR_TPC_CTS) | 2980 SM(14, AR_TPC_CHIRP) | 2981 SM(14, AR_TPC_RPT)); 2982 /* 4. Store BB_powertx_rate9 value */ 2983 temp_powertx_rate9_reg_val = 2984 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 2985 break; 2986 case HAL_RSSI_TX_POWER_LONG: 2987 default: 2988 /* 1. TxPower Config */ 2989 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2990 sizeof(target_power_val_t)); 2991 /* 1.1 Store OLPC Delta Calibration Offset*/ 2992 olpc_power_offset = 2993 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 2994 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2995 /* 2. Store OB/DB1/DB2 */ 2996 temp_obdb_reg_val = 2997 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2998 /* 3. Store TPC settting */ 2999 temp_tcp_reg_val = 3000 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3001 /* 4. Store BB_powertx_rate9 value */ 3002 temp_powertx_rate9_reg_val = 3003 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3004 break; 3005 } 3006 } 3007 /* 1.1 Do OLPC Delta Calibration Offset */ 3008 tmp_olpc_val = 3009 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3010 tmp_olpc_val += olpc_power_offset; 3011 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3012 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3013 AR_PHY_TPC_OLPC_GAIN_DELTA); 3014 3015 /* 1.2 TxPower Config */ 3016 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3017 /* 2. Config OB/DB */ 3018 if (!ahp->ah_hw_green_tx_enable) { 3019 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3020 } 3021 /* 3. config TPC settting */ 3022 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3023 /* 4. config BB_powertx_rate9 value */ 3024 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3025 } 3026 } 3027 3028 #if 0 3029 void 3030 ar9300_get_vow_stats( 3031 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3032 { 3033 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3034 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3035 } 3036 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3037 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3038 } 3039 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3040 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3041 } 3042 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3043 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3044 } 3045 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3046 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3047 } 3048 } 3049 #endif 3050 3051 /* 3052 * ar9300_is_skip_paprd_by_greentx 3053 * 3054 * This function check if we need to skip PAPRD tuning 3055 * when GreenTx in specific state. 3056 */ 3057 HAL_BOOL 3058 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3059 { 3060 if (AR_SREV_POSEIDON(ah) && 3061 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3062 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3063 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3064 { 3065 return AH_TRUE; 3066 } 3067 return AH_FALSE; 3068 } 3069 3070 void 3071 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3072 { 3073 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3074 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3075 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3076 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3077 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3078 struct ath_hal_9300 *ahp = AH9300(ah); 3079 3080 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3081 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3082 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3083 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3084 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3085 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3086 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3087 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3088 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3089 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3090 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3091 } 3092 } 3093 3094 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3095 { 3096 struct ath_hal_9300 *ahp = AH9300(ah); 3097 3098 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3099 if ((value == 0) || (value == 1)) { 3100 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3101 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3102 } 3103 } 3104 } 3105 3106 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3107 { 3108 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3109 } 3110 3111 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3112 { 3113 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3114 3115 /* RSSI format is 8.4. Ignore lowest four bits */ 3116 val = val >> 4; 3117 return val; 3118 } 3119 3120 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3121 u_int32_t rssi_threshold) 3122 { 3123 struct ath_hal_9300 *ahp = AH9300(ah); 3124 3125 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3126 3127 /* save value for restoring after chip reset */ 3128 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3129 } 3130 3131 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3132 { 3133 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3134 } 3135 3136 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3137 { 3138 if (on) { 3139 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3140 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3141 } 3142 else { 3143 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3144 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3145 } 3146 } 3147 /* 3148 * Gets the contents of the specified key cache entry. 3149 */ 3150 HAL_BOOL 3151 ar9300_print_keycache(struct ath_hal *ah) 3152 { 3153 3154 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3155 u_int32_t key0, key1, key2, key3, key4; 3156 u_int32_t mac_hi, mac_lo; 3157 u_int16_t entry = 0; 3158 u_int32_t valid = 0; 3159 u_int32_t key_type; 3160 3161 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3162 3163 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3164 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3165 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3166 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3167 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3168 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3169 3170 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3171 3172 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3173 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3174 3175 if (mac_hi & AR_KEYTABLE_VALID) { 3176 valid = 1; 3177 } else { 3178 valid = 0; 3179 } 3180 3181 if ((mac_hi != 0) && (mac_lo != 0)) { 3182 mac_hi &= ~0x8000; 3183 mac_hi <<= 1; 3184 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3185 mac_lo <<= 1; 3186 } 3187 3188 ath_hal_printf(ah, 3189 "%03d " 3190 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3191 " %02d %02d " 3192 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3193 entry, 3194 (key0 << 24) >> 24, (key0 << 16) >> 24, 3195 (key0 << 8) >> 24, key0 >> 24, 3196 (key1 << 24) >> 24, (key1 << 16) >> 24, 3197 //(key1 << 8) >> 24, key1 >> 24, 3198 (key2 << 24) >> 24, (key2 << 16) >> 24, 3199 (key2 << 8) >> 24, key2 >> 24, 3200 (key3 << 24) >> 24, (key3 << 16) >> 24, 3201 //(key3 << 8) >> 24, key3 >> 24, 3202 (key4 << 24) >> 24, (key4 << 16) >> 24, 3203 (key4 << 8) >> 24, key4 >> 24, 3204 valid, key_type, 3205 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3206 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3207 } 3208 3209 return AH_TRUE; 3210 } 3211 3212 /* enable/disable smart antenna mode */ 3213 HAL_BOOL 3214 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3215 { 3216 struct ath_hal_9300 *ahp = AH9300(ah); 3217 3218 if (enable) { 3219 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3220 } else { 3221 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3222 } 3223 3224 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3225 * and swcom2 with 0 3226 * FIXME Ideally these registers need to be made read from caldata. 3227 * Until the calibration team gets them, keep them along with board 3228 * configuration. 3229 */ 3230 if (enable && AR_SREV_SCORPION(ah) && 3231 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3232 3233 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3234 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3235 } 3236 3237 ahp->ah_smartantenna_enable = enable; 3238 return 1; 3239 } 3240 3241 #ifdef ATH_TX99_DIAG 3242 #ifndef ATH_SUPPORT_HTC 3243 void 3244 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3245 u_int32_t txpower) 3246 { 3247 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3248 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3249 int32_t i; 3250 3251 /* The max power is limited to 63 */ 3252 if (txpower <= AR9300_MAX_RATE_POWER) { 3253 for (i = 0; i < ar9300_rate_size; i++) { 3254 p_pwr_array[i] = txpower; 3255 } 3256 } else { 3257 for (i = 0; i < ar9300_rate_size; i++) { 3258 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3259 } 3260 } 3261 3262 OS_REG_WRITE(ah, 0xa458, 0); 3263 3264 /* Write the OFDM power per rate set */ 3265 /* 6 (LSB), 9, 12, 18 (MSB) */ 3266 OS_REG_WRITE(ah, 0xa3c0, 3267 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3268 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3269 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3270 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3271 ); 3272 /* 24 (LSB), 36, 48, 54 (MSB) */ 3273 OS_REG_WRITE(ah, 0xa3c4, 3274 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3275 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3276 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3277 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3278 ); 3279 3280 /* Write the CCK power per rate set */ 3281 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3282 OS_REG_WRITE(ah, 0xa3c8, 3283 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3284 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3285 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3286 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3287 ); 3288 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3289 OS_REG_WRITE(ah, 0xa3cc, 3290 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3291 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3292 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3293 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3294 ); 3295 3296 /* Write the HT20 power per rate set */ 3297 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3298 OS_REG_WRITE(ah, 0xa3d0, 3299 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3300 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3301 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3302 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3303 ); 3304 3305 /* 6 (LSB), 7, 12, 13 (MSB) */ 3306 OS_REG_WRITE(ah, 0xa3d4, 3307 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3308 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3309 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3310 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3311 ); 3312 3313 /* 14 (LSB), 15, 20, 21 */ 3314 OS_REG_WRITE(ah, 0xa3e4, 3315 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3316 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3317 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3318 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3319 ); 3320 3321 /* Mixed HT20 and HT40 rates */ 3322 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3323 OS_REG_WRITE(ah, 0xa3e8, 3324 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3325 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3326 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3327 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3328 ); 3329 3330 /* Write the HT40 power per rate set */ 3331 /* correct PAR difference between HT40 and HT20/LEGACY */ 3332 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3333 OS_REG_WRITE(ah, 0xa3d8, 3334 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3335 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3336 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3337 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3338 ); 3339 3340 /* 6 (LSB), 7, 12, 13 (MSB) */ 3341 OS_REG_WRITE(ah, 0xa3dc, 3342 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3343 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3344 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3345 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3346 ); 3347 3348 /* 14 (LSB), 15, 20, 21 */ 3349 OS_REG_WRITE(ah, 0xa3ec, 3350 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3351 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3352 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3353 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3354 ); 3355 #undef PWR_MAS 3356 } 3357 3358 void 3359 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3360 { 3361 if (tx_chainmask == 0x5) { 3362 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3363 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3364 } 3365 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3366 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3367 3368 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3369 if (tx_chainmask == 0x5) { 3370 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3371 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3372 } 3373 } 3374 3375 void 3376 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3377 int chtype) 3378 { 3379 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3380 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3381 OS_REG_WRITE(ah, 0xa350, 3382 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3383 3384 /* 11G mode */ 3385 if (!chtype) { 3386 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3387 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3388 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3389 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3390 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3391 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3392 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3393 | (0x1 << 26) | (0x7 << 24)) 3394 & ~(0x1 << 22)); 3395 } else { 3396 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3397 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3398 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3399 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3400 | (0x1 << 26) | (0x7 << 24)) 3401 & ~(0x1 << 22)); 3402 } 3403 3404 /* chain zero */ 3405 if ((tx_chain_mask & 0x01) == 0x01) { 3406 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3407 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3408 | (0x1 << 31) | (0x5 << 15) 3409 | (0x3 << 9)) & ~(0x1 << 27) 3410 & ~(0x1 << 12)); 3411 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3412 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3413 | (0x1 << 12) | (0x1 << 10) 3414 | (0x1 << 9) | (0x1 << 8) 3415 | (0x1 << 7)) & ~(0x1 << 11)); 3416 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3417 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3418 | (0x1 << 29) | (0x1 << 25) 3419 | (0x1 << 23) | (0x1 << 19) 3420 | (0x1 << 10) | (0x1 << 9) 3421 | (0x1 << 8) | (0x1 << 3)) 3422 & ~(0x1 << 28)& ~(0x1 << 24) 3423 & ~(0x1 << 22)& ~(0x1 << 7)); 3424 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3425 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3426 | (0x1 << 23))& ~(0x1 << 21)); 3427 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3428 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3429 | (0x1 << 12) | (0x1 << 10) 3430 | (0x1 << 9) | (0x1 << 8) 3431 | (0x1 << 6) | (0x1 << 5) 3432 | (0x1 << 4) | (0x1 << 3) 3433 | (0x1 << 2)); 3434 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3435 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3436 } 3437 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3438 /* chain one */ 3439 if ((tx_chain_mask & 0x02) == 0x02 ) { 3440 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3441 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3442 | (0x1 << 31) | (0x5 << 15) 3443 | (0x3 << 9)) & ~(0x1 << 27) 3444 & ~(0x1 << 12)); 3445 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3446 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3447 | (0x1 << 12) | (0x1 << 10) 3448 | (0x1 << 9) | (0x1 << 8) 3449 | (0x1 << 7)) & ~(0x1 << 11)); 3450 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3451 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3452 | (0x1 << 29) | (0x1 << 25) 3453 | (0x1 << 23) | (0x1 << 19) 3454 | (0x1 << 10) | (0x1 << 9) 3455 | (0x1 << 8) | (0x1 << 3)) 3456 & ~(0x1 << 28)& ~(0x1 << 24) 3457 & ~(0x1 << 22)& ~(0x1 << 7)); 3458 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3459 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3460 | (0x1 << 23))& ~(0x1 << 21)); 3461 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3462 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3463 | (0x1 << 12) | (0x1 << 10) 3464 | (0x1 << 9) | (0x1 << 8) 3465 | (0x1 << 6) | (0x1 << 5) 3466 | (0x1 << 4) | (0x1 << 3) 3467 | (0x1 << 2)); 3468 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3469 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3470 } 3471 } 3472 if (AR_SREV_OSPREY(ah)) { 3473 /* chain two */ 3474 if ((tx_chain_mask & 0x04) == 0x04 ) { 3475 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3476 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3477 | (0x1 << 31) | (0x5 << 15) 3478 | (0x3 << 9)) & ~(0x1 << 27) 3479 & ~(0x1 << 12)); 3480 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3481 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3482 | (0x1 << 12) | (0x1 << 10) 3483 | (0x1 << 9) | (0x1 << 8) 3484 | (0x1 << 7)) & ~(0x1 << 11)); 3485 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3486 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3487 | (0x1 << 29) | (0x1 << 25) 3488 | (0x1 << 23) | (0x1 << 19) 3489 | (0x1 << 10) | (0x1 << 9) 3490 | (0x1 << 8) | (0x1 << 3)) 3491 & ~(0x1 << 28)& ~(0x1 << 24) 3492 & ~(0x1 << 22)& ~(0x1 << 7)); 3493 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3494 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3495 | (0x1 << 23))& ~(0x1 << 21)); 3496 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3497 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3498 | (0x1 << 12) | (0x1 << 10) 3499 | (0x1 << 9) | (0x1 << 8) 3500 | (0x1 << 6) | (0x1 << 5) 3501 | (0x1 << 4) | (0x1 << 3) 3502 | (0x1 << 2)); 3503 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3504 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3505 } 3506 } 3507 3508 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3509 OS_REG_WRITE(ah, 0xa288, 0x111); 3510 } else { 3511 /* chain zero */ 3512 if ((tx_chain_mask & 0x01) == 0x01) { 3513 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3514 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3515 | (0x1 << 31) | (0x1 << 27) 3516 | (0x3 << 23) | (0x1 << 19) 3517 | (0x1 << 15) | (0x3 << 9)) 3518 & ~(0x1 << 12)); 3519 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3520 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3521 | (0x1 << 12) | (0x1 << 10) 3522 | (0x1 << 9) | (0x1 << 8) 3523 | (0x1 << 7) | (0x1 << 3) 3524 | (0x1 << 2) | (0x1 << 1)) 3525 & ~(0x1 << 11)& ~(0x1 << 0)); 3526 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3527 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3528 | (0x1 << 29) | (0x1 << 25) 3529 | (0x1 << 23) | (0x1 << 19) 3530 | (0x1 << 10) | (0x1 << 9) 3531 | (0x1 << 8) | (0x1 << 3)) 3532 & ~(0x1 << 28)& ~(0x1 << 24) 3533 & ~(0x1 << 22)& ~(0x1 << 7)); 3534 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3535 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3536 | (0x1 << 23))& ~(0x1 << 21)); 3537 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3538 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3539 | (0x3 << 3) | (0x3 << 0)); 3540 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3541 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3542 | (0x3 << 29) | (0x3 << 26) 3543 | (0x2 << 23) | (0x2 << 20) 3544 | (0x2 << 17))& ~(0x1 << 14)); 3545 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3546 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3547 | (0x1 << 12) | (0x1 << 10) 3548 | (0x1 << 9) | (0x1 << 8) 3549 | (0x1 << 6) | (0x1 << 5) 3550 | (0x1 << 4) | (0x1 << 3) 3551 | (0x1 << 2)); 3552 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3553 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3554 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3555 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3556 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3557 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3558 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3559 | (0x1 << 26) | (0x7 << 24) 3560 | (0x3 << 22)); 3561 } else { 3562 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3563 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3564 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3565 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3566 | (0x1 << 26) | (0x7 << 24) 3567 | (0x3 << 22)); 3568 } 3569 3570 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3571 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3572 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3573 | (0x1 << 3) | (0x1 << 2) 3574 | (0x1 << 1)) & ~(0x1 << 0)); 3575 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3576 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3577 | (0x1 << 19) | (0x1 << 3)); 3578 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3579 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3580 } 3581 if (AR_SREV_OSPREY(ah)) { 3582 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3583 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3584 | (0x1 << 3) | (0x1 << 2) 3585 | (0x1 << 1)) & ~(0x1 << 0)); 3586 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3587 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3588 | (0x1 << 19) | (0x1 << 3)); 3589 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3590 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3591 } 3592 } 3593 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3594 /* chain one */ 3595 if ((tx_chain_mask & 0x02) == 0x02 ) { 3596 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3597 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3598 | (0x1 << 3) | (0x1 << 2) 3599 | (0x1 << 1)) & ~(0x1 << 0)); 3600 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3601 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3602 | (0x1 << 19) | (0x1 << 3)); 3603 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3604 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3605 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3606 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3607 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3608 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3609 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3610 | (0x1 << 26) | (0x7 << 24) 3611 | (0x3 << 22)); 3612 } else { 3613 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3614 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3615 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3616 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3617 | (0x1 << 26) | (0x7 << 24) 3618 | (0x3 << 22)); 3619 } 3620 3621 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3622 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3623 | (0x1 << 31) | (0x1 << 27) 3624 | (0x3 << 23) | (0x1 << 19) 3625 | (0x1 << 15) | (0x3 << 9)) 3626 & ~(0x1 << 12)); 3627 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3628 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3629 | (0x1 << 12) | (0x1 << 10) 3630 | (0x1 << 9) | (0x1 << 8) 3631 | (0x1 << 7) | (0x1 << 3) 3632 | (0x1 << 2) | (0x1 << 1)) 3633 & ~(0x1 << 11)& ~(0x1 << 0)); 3634 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3635 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3636 | (0x1 << 29) | (0x1 << 25) 3637 | (0x1 << 23) | (0x1 << 19) 3638 | (0x1 << 10) | (0x1 << 9) 3639 | (0x1 << 8) | (0x1 << 3)) 3640 & ~(0x1 << 28)& ~(0x1 << 24) 3641 & ~(0x1 << 22)& ~(0x1 << 7)); 3642 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3643 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3644 | (0x1 << 23))& ~(0x1 << 21)); 3645 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3646 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3647 | (0x3 << 3) | (0x3 << 0)); 3648 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3649 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3650 | (0x3 << 29) | (0x3 << 26) 3651 | (0x2 << 23) | (0x2 << 20) 3652 | (0x2 << 17))& ~(0x1 << 14)); 3653 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3654 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3655 | (0x1 << 12) | (0x1 << 10) 3656 | (0x1 << 9) | (0x1 << 8) 3657 | (0x1 << 6) | (0x1 << 5) 3658 | (0x1 << 4) | (0x1 << 3) 3659 | (0x1 << 2)); 3660 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3661 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3662 3663 if (AR_SREV_OSPREY(ah)) { 3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3665 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3666 | (0x1 << 3) | (0x1 << 2) 3667 | (0x1 << 1)) & ~(0x1 << 0)); 3668 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3669 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3670 | (0x1 << 19) | (0x1 << 3)); 3671 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3672 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3673 } 3674 } 3675 } 3676 if (AR_SREV_OSPREY(ah)) { 3677 /* chain two */ 3678 if ((tx_chain_mask & 0x04) == 0x04 ) { 3679 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3680 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3681 | (0x1 << 3) | (0x1 << 2) 3682 | (0x1 << 1)) & ~(0x1 << 0)); 3683 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3684 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3685 | (0x1 << 19) | (0x1 << 3)); 3686 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3687 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3688 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3689 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3690 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3691 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3692 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3693 | (0x1 << 26) | (0x7 << 24) 3694 | (0x3 << 22)); 3695 } else { 3696 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3697 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3698 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3699 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3700 | (0x1 << 26) | (0x7 << 24) 3701 | (0x3 << 22)); 3702 } 3703 3704 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3705 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3706 | (0x1 << 3) | (0x1 << 2) 3707 | (0x1 << 1)) & ~(0x1 << 0)); 3708 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3709 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3710 | (0x1 << 19) | (0x1 << 3)); 3711 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3712 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3713 3714 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3715 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3716 | (0x1 << 31) | (0x1 << 27) 3717 | (0x3 << 23) | (0x1 << 19) 3718 | (0x1 << 15) | (0x3 << 9)) 3719 & ~(0x1 << 12)); 3720 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3721 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3722 | (0x1 << 12) | (0x1 << 10) 3723 | (0x1 << 9) | (0x1 << 8) 3724 | (0x1 << 7) | (0x1 << 3) 3725 | (0x1 << 2) | (0x1 << 1)) 3726 & ~(0x1 << 11)& ~(0x1 << 0)); 3727 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3728 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3729 | (0x1 << 29) | (0x1 << 25) 3730 | (0x1 << 23) | (0x1 << 19) 3731 | (0x1 << 10) | (0x1 << 9) 3732 | (0x1 << 8) | (0x1 << 3)) 3733 & ~(0x1 << 28)& ~(0x1 << 24) 3734 & ~(0x1 << 22)& ~(0x1 << 7)); 3735 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3736 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3737 | (0x1 << 23))& ~(0x1 << 21)); 3738 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3739 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3740 | (0x3 << 3) | (0x3 << 0)); 3741 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3742 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3743 | (0x3 << 29) | (0x3 << 26) 3744 | (0x2 << 23) | (0x2 << 20) 3745 | (0x2 << 17))& ~(0x1 << 14)); 3746 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3747 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3748 | (0x1 << 12) | (0x1 << 10) 3749 | (0x1 << 9) | (0x1 << 8) 3750 | (0x1 << 6) | (0x1 << 5) 3751 | (0x1 << 4) | (0x1 << 3) 3752 | (0x1 << 2)); 3753 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3754 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3755 } 3756 } 3757 3758 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3759 OS_REG_WRITE(ah, 0xa288, 0x222); 3760 } 3761 } 3762 3763 void 3764 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3765 { 3766 u_int32_t val; 3767 u_int32_t qnum = (u_int32_t)data; 3768 3769 /* Disable AGC to A2 */ 3770 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3771 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3772 3773 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3774 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3775 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3776 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3777 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3778 /* 200 ok for HT20, 400 ok for HT40 */ 3779 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3780 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3781 3782 /* set QCU modes to early termination */ 3783 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3784 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3785 } 3786 3787 void 3788 ar9300_tx99_stop(struct ath_hal *ah) 3789 { 3790 /* this should follow the setting of start */ 3791 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3792 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3793 } 3794 #endif /* ATH_TX99_DIAG */ 3795 #endif /* ATH_SUPPORT_HTC */ 3796 3797 HAL_BOOL 3798 ar9300Get3StreamSignature(struct ath_hal *ah) 3799 { 3800 return AH_FALSE; 3801 } 3802 3803 HAL_BOOL 3804 ar9300ForceVCS(struct ath_hal *ah) 3805 { 3806 return AH_FALSE; 3807 } 3808 3809 HAL_BOOL 3810 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3811 { 3812 return AH_FALSE; 3813 } 3814 3815 HAL_BOOL 3816 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3817 { 3818 struct ath_hal_9300 *ahp = AH9300(ah); 3819 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3820 u_int8_t *ctl_index; 3821 u_int32_t offset = 0; 3822 3823 if (!ctl_array) 3824 return AH_FALSE; 3825 3826 /* copy 2G ctl freqbin and power data */ 3827 ctl_index = p_eep_data->ctl_index_2g; 3828 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3829 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3830 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3831 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3832 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3833 3834 3835 /* copy 2G ctl freqbin and power data */ 3836 ctl_index = p_eep_data->ctl_index_5g; 3837 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3838 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3839 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3840 3841 return AH_FALSE; 3842 } 3843 3844 void 3845 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3846 { 3847 struct ath_hal_9300 *ahp = AH9300(ah); 3848 3849 /* optional txchainmask should be subset of primary txchainmask */ 3850 if ((mask & ahp->ah_tx_chainmask) != mask) { 3851 ahp->ah_tx_chainmaskopt = 0; 3852 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3853 return; 3854 } 3855 3856 ahp->ah_tx_chainmaskopt = mask; 3857 } 3858