1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 #include "ar9300/ar9300desc.h" 30 31 static u_int32_t ar9300_read_loc_timer(struct ath_hal *ah); 32 33 void 34 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 35 { 36 struct ath_hal_9300 *ahp = AH9300(ah); 37 *hangs = 0; 38 39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 40 *hangs |= HAL_RIFS_BB_HANG_WAR; 41 } 42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 43 *hangs |= HAL_DFS_BB_HANG_WAR; 44 } 45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 46 == HAL_OK) 47 { 48 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 49 } 50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 51 *hangs |= HAL_MAC_HANG_WAR; 52 } 53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 54 == HAL_OK) 55 { 56 *hangs |= HAL_PHYRESTART_CLR_WAR; 57 } 58 59 ahp->ah_hang_wars = *hangs; 60 } 61 62 /* 63 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 64 * HT20, HT40, fast-clock, turbo mode, etc. 65 */ 66 static u_int 67 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 68 { 69 #if 0 70 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 71 72 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 73 return (ath_hal_mac_usec(ah, clks) / 2); 74 } else { 75 return (ath_hal_mac_usec(ah, clks)); 76 } 77 #endif 78 return (ath_hal_mac_usec(ah, clks)); 79 } 80 81 u_int 82 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 83 { 84 #if 0 85 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 86 87 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 88 return (ath_hal_mac_clks(ah, usecs) * 2); 89 } else { 90 return (ath_hal_mac_clks(ah, usecs)); 91 } 92 #endif 93 return (ath_hal_mac_clks(ah, usecs)); 94 } 95 96 void 97 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 98 { 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 101 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 102 } 103 104 HAL_BOOL 105 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 106 { 107 struct ath_hal_9300 *ahp = AH9300(ah); 108 109 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 110 return AH_TRUE; 111 } 112 113 void 114 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 115 { 116 struct ath_hal_9300 *ahp = AH9300(ah); 117 118 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 119 } 120 121 HAL_BOOL 122 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 123 { 124 struct ath_hal_9300 *ahp = AH9300(ah); 125 126 /* save it since it must be rewritten on reset */ 127 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 128 129 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 130 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 131 return AH_TRUE; 132 } 133 134 /* 135 * Attempt to change the cards operating regulatory domain to the given value 136 * Returns: A_EINVAL for an unsupported regulatory domain. 137 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 138 */ 139 HAL_BOOL 140 ar9300_set_regulatory_domain(struct ath_hal *ah, 141 u_int16_t reg_domain, HAL_STATUS *status) 142 { 143 HAL_STATUS ecode; 144 145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 146 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 147 return AH_TRUE; 148 } 149 ecode = HAL_EIO; 150 151 #if 0 152 bad: 153 #endif 154 if (status) { 155 *status = ecode; 156 } 157 return AH_FALSE; 158 } 159 160 /* 161 * Return the wireless modes (a,b,g,t) supported by hardware. 162 * 163 * This value is what is actually supported by the hardware 164 * and is unaffected by regulatory/country code settings. 165 * 166 */ 167 u_int 168 ar9300_get_wireless_modes(struct ath_hal *ah) 169 { 170 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 171 } 172 173 /* 174 * Set the interrupt and GPIO values so the ISR can disable RF 175 * on a switch signal. Assumes GPIO port and interrupt polarity 176 * are set prior to call. 177 */ 178 void 179 ar9300_enable_rf_kill(struct ath_hal *ah) 180 { 181 /* TODO - can this really be above the hal on the GPIO interface for 182 * TODO - the client only? 183 */ 184 struct ath_hal_9300 *ahp = AH9300(ah); 185 186 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 187 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 188 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 190 AR_RFSILENT_FORCE); 191 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 192 } 193 else { 194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 195 AR_RFSILENT_FORCE); 196 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 197 } 198 } 199 else { 200 /* Connect rfsilent_bb_l to baseband */ 201 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 202 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 203 204 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 AR_GPIO_INPUT_MUX2_RFSILENT); 207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 208 (ahp->ah_gpio_select & 0x0f) << 4); 209 210 /* 211 * Configure the desired GPIO port for input and 212 * enable baseband rf silence 213 */ 214 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 215 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 216 } 217 218 /* 219 * If radio disable switch connection to GPIO bit x is enabled 220 * program GPIO interrupt. 221 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 222 * verified that it is a later version of eeprom, it has a place for 223 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 224 * connection is present. 225 */ 226 /* 227 * RFKill uses polling not interrupt, 228 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 229 */ 230 if (ath_hal_hasrfkill_int(ah)) { 231 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 232 /* switch already closed, set to interrupt upon open */ 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 234 } else { 235 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 236 } 237 } 238 } 239 240 /* 241 * Change the LED blinking pattern to correspond to the connectivity 242 */ 243 void 244 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 245 { 246 static const u_int32_t ledbits[8] = { 247 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 250 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 251 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 252 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 253 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 254 AR_CFG_LED_ASSOC_NONE, 255 }; 256 257 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 258 } 259 260 /* 261 * Sets the Power LED on the cardbus without affecting the Network LED. 262 */ 263 void 264 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 265 { 266 u_int32_t val; 267 268 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 269 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 270 } 271 272 /* 273 * Sets the Network LED on the cardbus without affecting the Power LED. 274 */ 275 void 276 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 277 { 278 u_int32_t val; 279 280 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 281 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 282 } 283 284 /* 285 * Change association related fields programmed into the hardware. 286 * Writing a valid BSSID to the hardware effectively enables the hardware 287 * to synchronize its TSF to the correct beacons and receive frames coming 288 * from that BSSID. It is called by the SME JOIN operation. 289 */ 290 void 291 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 292 u_int16_t assoc_id) 293 { 294 struct ath_hal_9300 *ahp = AH9300(ah); 295 296 /* save bssid and assoc_id for restore on reset */ 297 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 298 ahp->ah_assoc_id = assoc_id; 299 300 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 301 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 302 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 303 } 304 305 /* 306 * Get the current hardware tsf for stamlme 307 */ 308 u_int64_t 309 ar9300_get_tsf64(struct ath_hal *ah) 310 { 311 u_int64_t tsf; 312 313 /* XXX sync multi-word read? */ 314 tsf = OS_REG_READ(ah, AR_TSF_U32); 315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 316 return tsf; 317 } 318 319 void 320 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 321 { 322 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 323 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 324 } 325 326 /* 327 * Get the current hardware tsf for stamlme 328 */ 329 u_int32_t 330 ar9300_get_tsf32(struct ath_hal *ah) 331 { 332 return OS_REG_READ(ah, AR_TSF_L32); 333 } 334 335 u_int32_t 336 ar9300_get_tsf2_32(struct ath_hal *ah) 337 { 338 return OS_REG_READ(ah, AR_TSF2_L32); 339 } 340 341 /* 342 * Reset the current hardware tsf for stamlme. 343 */ 344 void 345 ar9300_reset_tsf(struct ath_hal *ah) 346 { 347 int count; 348 349 count = 0; 350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 351 count++; 352 if (count > 10) { 353 HALDEBUG(ah, HAL_DEBUG_RESET, 354 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 355 break; 356 } 357 OS_DELAY(10); 358 } 359 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 360 } 361 362 /* 363 * Set or clear hardware basic rate bit 364 * Set hardware basic rate set if basic rate is found 365 * and basic rate is equal or less than 2Mbps 366 */ 367 void 368 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 369 { 370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 371 u_int32_t reg; 372 u_int8_t xset; 373 int i; 374 375 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 376 return; 377 } 378 xset = 0; 379 for (i = 0; i < rs->rs_count; i++) { 380 u_int8_t rset = rs->rs_rates[i]; 381 /* Basic rate defined? */ 382 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 383 xset = rset; 384 } 385 } 386 /* 387 * Set the h/w bit to reflect whether or not the basic 388 * rate is found to be equal or less than 2Mbps. 389 */ 390 reg = OS_REG_READ(ah, AR_STA_ID1); 391 if (xset && xset / 2 <= 2) { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 393 } else { 394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 395 } 396 } 397 398 /* 399 * Grab a semi-random value from hardware registers - may not 400 * change often 401 */ 402 u_int32_t 403 ar9300_get_random_seed(struct ath_hal *ah) 404 { 405 u_int32_t nf; 406 407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 408 if (nf & 0x100) { 409 nf = 0 - ((nf ^ 0x1ff) + 1); 410 } 411 return (OS_REG_READ(ah, AR_TSF_U32) ^ 412 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 413 } 414 415 /* 416 * Detect if our card is present 417 */ 418 HAL_BOOL 419 ar9300_detect_card_present(struct ath_hal *ah) 420 { 421 u_int16_t mac_version, mac_rev; 422 u_int32_t v; 423 424 /* 425 * Read the Silicon Revision register and compare that 426 * to what we read at attach time. If the same, we say 427 * a card/device is present. 428 */ 429 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 430 if (v == 0xFF) { 431 /* new SREV format */ 432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 433 /* 434 * Include 6-bit Chip Type (masked to 0) to differentiate 435 * from pre-Sowl versions 436 */ 437 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 438 mac_rev = MS(v, AR_SREV_REVISION2); 439 } else { 440 mac_version = MS(v, AR_SREV_VERSION); 441 mac_rev = v & AR_SREV_REVISION; 442 } 443 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 444 AH_PRIVATE(ah)->ah_macRev == mac_rev); 445 } 446 447 /* 448 * Update MIB Counters 449 */ 450 void 451 ar9300_update_mib_mac_stats(struct ath_hal *ah) 452 { 453 struct ath_hal_9300 *ahp = AH9300(ah); 454 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 455 456 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 457 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 458 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 459 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 460 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 461 } 462 463 void 464 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 465 { 466 struct ath_hal_9300 *ahp = AH9300(ah); 467 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 468 469 stats->ackrcv_bad = istats->ackrcv_bad; 470 stats->rts_bad = istats->rts_bad; 471 stats->fcs_bad = istats->fcs_bad; 472 stats->rts_good = istats->rts_good; 473 stats->beacons = istats->beacons; 474 } 475 476 /* 477 * Detect if the HW supports spreading a CCK signal on channel 14 478 */ 479 HAL_BOOL 480 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 481 { 482 return AH_TRUE; 483 } 484 485 /* 486 * Get the rssi of frame curently being received. 487 */ 488 u_int32_t 489 ar9300_get_cur_rssi(struct ath_hal *ah) 490 { 491 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 492 /* get combined RSSI */ 493 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 494 } 495 496 #if ATH_GEN_RANDOMNESS 497 /* 498 * Get the rssi value from BB on ctl chain0. 499 */ 500 u_int32_t 501 ar9300_get_rssi_chain0(struct ath_hal *ah) 502 { 503 /* get ctl chain0 RSSI */ 504 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 505 } 506 #endif 507 508 u_int 509 ar9300_get_def_antenna(struct ath_hal *ah) 510 { 511 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 512 } 513 514 /* Setup coverage class */ 515 void 516 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 517 { 518 } 519 520 void 521 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 522 { 523 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 524 } 525 526 HAL_BOOL 527 ar9300_set_antenna_switch(struct ath_hal *ah, 528 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 529 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 530 { 531 struct ath_hal_9300 *ahp = AH9300(ah); 532 533 /* 534 * Owl does not support diversity or changing antennas. 535 * 536 * Instead this API and function are defined differently for AR9300. 537 * To support Tablet PC's, this interface allows the system 538 * to dramatically reduce the TX power on a particular chain. 539 * 540 * Based on the value of (redefined) diversity_control, the 541 * reset code will decrease power on chain 0 or chain 1/2. 542 * 543 * Based on the value of bit 0 of antenna_switch_swap, 544 * the mapping between OID call and chain is defined as: 545 * 0: map A -> 0, B -> 1; 546 * 1: map A -> 1, B -> 0; 547 * 548 * NOTE: 549 * The devices that use this OID should use a tx_chain_mask and 550 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 551 * used in order to ensure an active transmit antenna. This 552 * API will allow the host to turn off the only transmitting 553 * antenna to ensure the antenna closest to the user's body is 554 * powered-down. 555 */ 556 /* 557 * Set antenna control for use during reset sequence by 558 * ar9300_decrease_chain_power() 559 */ 560 ahp->ah_diversity_control = settings; 561 562 return AH_TRUE; 563 } 564 565 HAL_BOOL 566 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 567 { 568 return AH_TRUE; 569 } 570 571 HAL_BOOL 572 ar9300_set_slot_time(struct ath_hal *ah, u_int us) 573 { 574 struct ath_hal_9300 *ahp = AH9300(ah); 575 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 576 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 577 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 578 return AH_FALSE; 579 } else { 580 /* convert to system clocks */ 581 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 582 ahp->ah_slot_time = us; 583 return AH_TRUE; 584 } 585 } 586 587 HAL_BOOL 588 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 589 { 590 struct ath_hal_9300 *ahp = AH9300(ah); 591 592 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 593 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 594 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 595 return AH_FALSE; 596 } else { 597 /* convert to system clocks */ 598 OS_REG_RMW_FIELD(ah, 599 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 600 ahp->ah_ack_timeout = us; 601 return AH_TRUE; 602 } 603 } 604 605 u_int 606 ar9300_get_ack_timeout(struct ath_hal *ah) 607 { 608 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 609 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 610 } 611 612 HAL_STATUS 613 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 614 u_int32_t next_start, HAL_QUIET_FLAG flag) 615 { 616 #define TU_TO_USEC(_tu) ((_tu) << 10) 617 HAL_STATUS status = HAL_EIO; 618 u_int32_t tsf = 0, j, next_start_us = 0; 619 if (flag & HAL_QUIET_ENABLE) { 620 for (j = 0; j < 2; j++) { 621 next_start_us = TU_TO_USEC(next_start); 622 tsf = OS_REG_READ(ah, AR_TSF_L32); 623 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 624 next_start_us += tsf; 625 } 626 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 627 next_start_us += 628 ah->ah_config.ah_sw_beacon_response_time; 629 } 630 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 631 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 632 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 633 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 634 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 635 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 636 status = HAL_OK; 637 break; 638 } 639 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 640 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 641 /* TSF shouldn't count twice or reg access is taking forever */ 642 HALASSERT(j < 1); 643 } 644 } else { 645 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 646 status = HAL_OK; 647 } 648 649 return status; 650 #undef TU_TO_USEC 651 } 652 #ifdef ATH_SUPPORT_DFS 653 void 654 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 655 { 656 u32 reg1, reg2; 657 658 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 659 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 660 AH9300(ah)->ah_cac_quiet_enabled = enable; 661 662 if (enable) { 663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 664 reg1 | AR_PCU_FORCE_QUIET_COLL); 665 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 666 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 667 } else { 668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 669 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 670 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 671 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 672 } 673 } 674 #endif /* ATH_SUPPORT_DFS */ 675 676 void 677 ar9300_set_pcu_config(struct ath_hal *ah) 678 { 679 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 680 } 681 682 HAL_STATUS 683 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 684 u_int32_t capability, u_int32_t *result) 685 { 686 struct ath_hal_9300 *ahp = AH9300(ah); 687 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 688 struct ar9300_ani_state *ani; 689 690 switch (type) { 691 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 692 switch (capability) { 693 case HAL_CIPHER_AES_CCM: 694 case HAL_CIPHER_AES_OCB: 695 case HAL_CIPHER_TKIP: 696 case HAL_CIPHER_WEP: 697 case HAL_CIPHER_MIC: 698 case HAL_CIPHER_CLR: 699 return HAL_OK; 700 default: 701 return HAL_ENOTSUPP; 702 } 703 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 704 switch (capability) { 705 case 0: /* hardware capability */ 706 return HAL_OK; 707 case 1: 708 return (ahp->ah_sta_id1_defaults & 709 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 710 default: 711 return HAL_ENOTSUPP; 712 } 713 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 714 switch (capability) { 715 case 0: /* hardware capability */ 716 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 717 case 1: /* current setting */ 718 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 719 HAL_ENXIO : HAL_OK; 720 default: 721 return HAL_ENOTSUPP; 722 } 723 case HAL_CAP_WME_TKIPMIC: 724 /* hardware can do TKIP MIC when WMM is turned on */ 725 return HAL_OK; 726 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 727 return HAL_OK; 728 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 729 switch (capability) { 730 case 0: /* hardware capability */ 731 return HAL_OK; 732 case 1: /* current setting */ 733 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 734 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 735 HAL_OK : HAL_ENXIO; 736 } 737 return HAL_EINVAL; 738 case HAL_CAP_TPC: 739 switch (capability) { 740 case 0: /* hardware capability */ 741 return HAL_OK; 742 case 1: 743 return ah->ah_config.ath_hal_desc_tpc ? 744 HAL_OK : HAL_ENXIO; 745 } 746 return HAL_OK; 747 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 748 return HAL_OK; 749 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 750 switch (capability) { 751 case 0: /* hardware capability */ 752 return HAL_OK; 753 case 1: 754 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 755 /* 756 * Owl and Merlin have problems in mcast key search. 757 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 758 * 26802 759 */ 760 return HAL_ENXIO; 761 } else { 762 return (ahp->ah_sta_id1_defaults & 763 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 764 } 765 } 766 return HAL_EINVAL; 767 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 768 switch (capability) { 769 case 0: /* hardware capability */ 770 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 771 case 1: 772 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 773 HAL_OK : HAL_ENXIO; 774 } 775 return HAL_EINVAL; 776 case HAL_CAP_RFSILENT: /* rfsilent support */ 777 if (capability == 3) { /* rfkill interrupt */ 778 /* 779 * XXX: Interrupt-based notification of RF Kill state 780 * changes not working yet. Report that this feature 781 * is not supported so that polling is used instead. 782 */ 783 return (HAL_ENOTSUPP); 784 } 785 return ath_hal_getcapability(ah, type, capability, result); 786 case HAL_CAP_4ADDR_AGGR: 787 return HAL_OK; 788 case HAL_CAP_BB_RIFS_HANG: 789 return HAL_ENOTSUPP; 790 case HAL_CAP_BB_DFS_HANG: 791 return HAL_ENOTSUPP; 792 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 793 /* Track chips that are known to have BB hangs related 794 * to rx_clear stuck low. 795 */ 796 return HAL_ENOTSUPP; 797 case HAL_CAP_MAC_HANG: 798 /* Track chips that are known to have MAC hangs. 799 */ 800 return HAL_OK; 801 case HAL_CAP_RIFS_RX_ENABLED: 802 /* Is RIFS RX currently enabled */ 803 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 804 #if 0 805 case HAL_CAP_ANT_CFG_2GHZ: 806 *result = p_cap->halNumAntCfg2Ghz; 807 return HAL_OK; 808 case HAL_CAP_ANT_CFG_5GHZ: 809 *result = p_cap->halNumAntCfg5Ghz; 810 return HAL_OK; 811 case HAL_CAP_RX_STBC: 812 *result = p_cap->hal_rx_stbc_support; 813 return HAL_OK; 814 case HAL_CAP_TX_STBC: 815 *result = p_cap->hal_tx_stbc_support; 816 return HAL_OK; 817 #endif 818 case HAL_CAP_LDPC: 819 *result = p_cap->halLDPCSupport; 820 return HAL_OK; 821 case HAL_CAP_DYNAMIC_SMPS: 822 return HAL_OK; 823 case HAL_CAP_DS: 824 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 825 (p_cap->halTxChainMask & 0x3) != 0x3 || 826 (p_cap->halRxChainMask & 0x3) != 0x3) ? 827 HAL_ENOTSUPP : HAL_OK; 828 case HAL_CAP_TS: 829 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 830 (p_cap->halTxChainMask & 0x7) != 0x7 || 831 (p_cap->halRxChainMask & 0x7) != 0x7) ? 832 HAL_ENOTSUPP : HAL_OK; 833 case HAL_CAP_OL_PWRCTRL: 834 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 835 HAL_OK : HAL_ENOTSUPP; 836 case HAL_CAP_CRDC: 837 #if ATH_SUPPORT_CRDC 838 return (AR_SREV_WASP(ah) && 839 ah->ah_config.ath_hal_crdc_enable) ? 840 HAL_OK : HAL_ENOTSUPP; 841 #else 842 return HAL_ENOTSUPP; 843 #endif 844 #if 0 845 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 846 *result = (u_int32_t)(-1); 847 return HAL_OK; 848 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 849 *result = (u_int32_t)(-1); 850 return HAL_OK; 851 #endif 852 case HAL_CAP_BB_PANIC_WATCHDOG: 853 return HAL_OK; 854 case HAL_CAP_PHYRESTART_CLR_WAR: 855 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 856 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 857 { 858 return HAL_OK; 859 } 860 else 861 { 862 return HAL_ENOTSUPP; 863 } 864 case HAL_CAP_ENTERPRISE_MODE: 865 *result = ahp->ah_enterprise_mode >> 16; 866 /* 867 * WAR for EV 77658 - Add delimiters to first sub-frame when using 868 * RTS/CTS with aggregation and non-enterprise Osprey. 869 * 870 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 871 */ 872 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 873 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 874 AR_SREV_WASP_10(ah))) { 875 *result |= AH_ENT_RTSCTS_DELIM_WAR; 876 } 877 return HAL_OK; 878 case HAL_CAP_LDPCWAR: 879 /* WAR for RIFS+LDPC issue is required for all chips currently 880 * supported by ar9300 HAL. 881 */ 882 return HAL_OK; 883 case HAL_CAP_ENABLE_APM: 884 *result = p_cap->halApmEnable; 885 return HAL_OK; 886 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 887 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 888 case HAL_CAP_PCIE_LCR_OFFSET: 889 *result = p_cap->hal_pcie_lcr_offset; 890 return HAL_OK; 891 case HAL_CAP_SMARTANTENNA: 892 /* FIXME A request is pending with h/w team to add feature bit in 893 * caldata to detect if board has smart antenna or not, once added 894 * we need to fix his piece of code to read and return value without 895 * any compile flags 896 */ 897 #if UMAC_SUPPORT_SMARTANTENNA 898 /* enable smart antenna for Peacock, Wasp and scorpion 899 for future chips need to modify */ 900 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 901 return HAL_OK; 902 } else { 903 return HAL_ENOTSUPP; 904 } 905 #else 906 return HAL_ENOTSUPP; 907 #endif 908 909 #ifdef ATH_TRAFFIC_FAST_RECOVER 910 case HAL_CAP_TRAFFIC_FAST_RECOVER: 911 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 912 return HAL_OK; 913 } else { 914 return HAL_ENOTSUPP; 915 } 916 #endif 917 918 /* FreeBSD ANI */ 919 case HAL_CAP_INTMIT: /* interference mitigation */ 920 switch (capability) { 921 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 922 return HAL_OK; 923 case HAL_CAP_INTMIT_ENABLE: 924 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 925 HAL_OK : HAL_ENXIO; 926 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 927 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 928 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 929 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 930 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 931 ani = ar9300_ani_get_current_state(ah); 932 if (ani == AH_NULL) 933 return HAL_ENXIO; 934 switch (capability) { 935 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 936 case 2: *result = ani->ofdm_noise_immunity_level; break; 937 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 938 // case 4: *result = ani->cck_weak_sig_threshold; break; 939 case 5: *result = ani->firstep_level; break; 940 case 6: *result = ani->spur_immunity_level; break; 941 } 942 return HAL_OK; 943 } 944 return HAL_EINVAL; 945 case HAL_CAP_ENFORCE_TXOP: 946 if (capability == 0) 947 return (HAL_OK); 948 if (capability != 1) 949 return (HAL_ENOTSUPP); 950 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 951 return (HAL_OK); 952 case HAL_CAP_TOA_LOCATIONING: 953 if (capability == 0) 954 return HAL_OK; 955 if (capability == 2) { 956 *result = ar9300_read_loc_timer(ah); 957 return (HAL_OK); 958 } 959 return HAL_ENOTSUPP; 960 default: 961 return ath_hal_getcapability(ah, type, capability, result); 962 } 963 } 964 965 HAL_BOOL 966 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 967 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 968 { 969 struct ath_hal_9300 *ahp = AH9300(ah); 970 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 971 u_int32_t v; 972 973 switch (type) { 974 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 975 if (! p_cap->halTkipMicTxRxKeySupport) 976 return AH_FALSE; 977 978 if (setting) 979 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 980 else 981 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 982 983 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 984 return AH_TRUE; 985 986 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 987 if (setting) { 988 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 989 } else { 990 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 991 } 992 return AH_TRUE; 993 case HAL_CAP_DIVERSITY: 994 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 995 if (setting) { 996 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 997 } else { 998 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 999 } 1000 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 1001 return AH_TRUE; 1002 case HAL_CAP_DIAG: /* hardware diagnostic support */ 1003 /* 1004 * NB: could split this up into virtual capabilities, 1005 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 1006 * seems worth the additional complexity. 1007 */ 1008 #ifdef AH_DEBUG 1009 AH_PRIVATE(ah)->ah_diagreg = setting; 1010 #else 1011 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 1012 #endif 1013 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 1014 return AH_TRUE; 1015 case HAL_CAP_TPC: 1016 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1017 return AH_TRUE; 1018 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1019 if (setting) { 1020 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1021 } else { 1022 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1023 } 1024 return AH_TRUE; 1025 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1026 if (p_cap->halTsfAddSupport) { 1027 if (setting) { 1028 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1029 } else { 1030 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1031 } 1032 return AH_TRUE; 1033 } 1034 return AH_FALSE; 1035 1036 /* FreeBSD interrupt mitigation / ANI */ 1037 case HAL_CAP_INTMIT: { /* interference mitigation */ 1038 /* This maps the public ANI commands to the internal ANI commands */ 1039 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1040 static const HAL_ANI_CMD cmds[] = { 1041 HAL_ANI_PRESENT, 1042 HAL_ANI_MODE, 1043 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1044 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1045 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1046 HAL_ANI_FIRSTEP_LEVEL, 1047 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1048 }; 1049 #define N(a) (sizeof(a) / sizeof(a[0])) 1050 return capability < N(cmds) ? 1051 ar9300_ani_control(ah, cmds[capability], setting) : 1052 AH_FALSE; 1053 #undef N 1054 } 1055 1056 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1057 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1058 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1059 return AH_TRUE; 1060 1061 case HAL_CAP_ENFORCE_TXOP: 1062 if (capability != 1) 1063 return AH_FALSE; 1064 if (setting) { 1065 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 1066 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1067 } else { 1068 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 1069 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1070 } 1071 return AH_TRUE; 1072 1073 case HAL_CAP_TOA_LOCATIONING: 1074 if (capability == 0) 1075 return AH_TRUE; 1076 if (capability == 1) { 1077 ar9300_update_loc_ctl_reg(ah, setting); 1078 return AH_TRUE; 1079 } 1080 return AH_FALSE; 1081 /* fall thru... */ 1082 default: 1083 return ath_hal_setcapability(ah, type, capability, setting, status); 1084 } 1085 } 1086 1087 #ifdef AH_DEBUG 1088 static void 1089 ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1090 { 1091 u_int32_t i = 0; 1092 1093 /* Read 0x80d0 to trigger pcie analyzer */ 1094 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1095 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1096 1097 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1098 struct ath_hal_9300 *ahp = AH9300(ah); 1099 u_int32_t tf, rf, rc, cc; 1100 1101 tf = OS_REG_READ(ah, AR_TFCNT); 1102 rf = OS_REG_READ(ah, AR_RFCNT); 1103 rc = OS_REG_READ(ah, AR_RCCNT); 1104 cc = OS_REG_READ(ah, AR_CCCNT); 1105 1106 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1107 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1109 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1110 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1111 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1113 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1114 1115 ahp->last_tf = tf; 1116 ahp->last_rf = rf; 1117 ahp->last_rc = rc; 1118 ahp->last_cc = cc; 1119 1120 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1121 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1122 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1123 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1124 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1125 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1126 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1127 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1128 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1129 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1130 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1131 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1132 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1133 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1135 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1136 } 1137 1138 if (args & HAL_DIAG_PRINT_REG_ALL) { 1139 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1140 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1141 i, OS_REG_READ(ah, i)); 1142 } 1143 1144 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1145 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1146 i, OS_REG_READ(ah, i)); 1147 } 1148 1149 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1150 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1151 1152 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1153 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1154 1155 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1156 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1157 i, OS_REG_READ(ah, i)); 1158 } 1159 1160 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1161 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1162 i, OS_REG_READ(ah, i)); 1163 } 1164 1165 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1166 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1167 i, OS_REG_READ(ah, i)); 1168 } 1169 1170 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1171 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1172 i, OS_REG_READ(ah, i)); 1173 } 1174 1175 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1176 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1177 i, OS_REG_READ(ah, i)); 1178 } 1179 1180 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1181 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1182 i, OS_REG_READ(ah, i)); 1183 } 1184 1185 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1186 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1187 i, OS_REG_READ(ah, i)); 1188 } 1189 1190 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1191 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1192 i, OS_REG_READ(ah, i)); 1193 } 1194 1195 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1196 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1197 i, OS_REG_READ(ah, i)); 1198 } 1199 1200 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1201 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1202 i, OS_REG_READ(ah, i)); 1203 } 1204 1205 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1206 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1207 i, OS_REG_READ(ah, i)); 1208 } 1209 } 1210 } 1211 #endif 1212 1213 HAL_BOOL 1214 ar9300_get_diag_state(struct ath_hal *ah, int request, 1215 const void *args, u_int32_t argsize, 1216 void **result, u_int32_t *resultsize) 1217 { 1218 struct ath_hal_9300 *ahp = AH9300(ah); 1219 struct ar9300_ani_state *ani; 1220 1221 (void) ahp; 1222 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1223 return AH_TRUE; 1224 } 1225 switch (request) { 1226 #ifdef AH_PRIVATE_DIAG 1227 case HAL_DIAG_EEPROM: 1228 *result = &ahp->ah_eeprom; 1229 *resultsize = sizeof(ar9300_eeprom_t); 1230 return AH_TRUE; 1231 1232 #if 0 /* XXX - TODO */ 1233 case HAL_DIAG_EEPROM_EXP_11A: 1234 case HAL_DIAG_EEPROM_EXP_11B: 1235 case HAL_DIAG_EEPROM_EXP_11G: 1236 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1237 *result = pe->p_channels; 1238 *resultsize = (*result == AH_NULL) ? 0 : 1239 roundup(sizeof(u_int16_t) * pe->num_channels, 1240 sizeof(u_int32_t)) + 1241 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1242 return AH_TRUE; 1243 #endif 1244 case HAL_DIAG_RFGAIN: 1245 *result = &ahp->ah_gain_values; 1246 *resultsize = sizeof(GAIN_VALUES); 1247 return AH_TRUE; 1248 case HAL_DIAG_RFGAIN_CURSTEP: 1249 *result = (void *) ahp->ah_gain_values.curr_step; 1250 *resultsize = (*result == AH_NULL) ? 1251 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1252 return AH_TRUE; 1253 #if 0 /* XXX - TODO */ 1254 case HAL_DIAG_PCDAC: 1255 *result = ahp->ah_pcdac_table; 1256 *resultsize = ahp->ah_pcdac_table_size; 1257 return AH_TRUE; 1258 #endif 1259 case HAL_DIAG_ANI_CURRENT: 1260 1261 ani = ar9300_ani_get_current_state(ah); 1262 if (ani == AH_NULL) 1263 return AH_FALSE; 1264 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1265 /* XXX TODO: add all of these to the HAL ANI state structure */ 1266 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1267 /* XXX should this be OFDM or CCK noise immunity level? */ 1268 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1269 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1270 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1271 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1272 /* mrc_cck_off */ 1273 /* cck_noise_immunity_level */ 1274 1275 ahp->ext_ani_state.listenTime = ani->listen_time; 1276 1277 *result = &ahp->ext_ani_state; 1278 *resultsize = sizeof(ahp->ext_ani_state); 1279 #if 0 1280 *result = ar9300_ani_get_current_state(ah); 1281 *resultsize = (*result == AH_NULL) ? 1282 0 : sizeof(struct ar9300_ani_state); 1283 #endif 1284 return AH_TRUE; 1285 case HAL_DIAG_ANI_STATS: 1286 *result = ar9300_ani_get_current_stats(ah); 1287 *resultsize = (*result == AH_NULL) ? 1288 0 : sizeof(HAL_ANI_STATS); 1289 return AH_TRUE; 1290 case HAL_DIAG_ANI_CMD: 1291 if (argsize != 2*sizeof(u_int32_t)) { 1292 return AH_FALSE; 1293 } 1294 ar9300_ani_control( 1295 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1296 return AH_TRUE; 1297 #if 0 1298 case HAL_DIAG_TXCONT: 1299 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1300 return AH_TRUE; 1301 #endif /* 0 */ 1302 #endif /* AH_PRIVATE_DIAG */ 1303 case HAL_DIAG_CHANNELS: 1304 #if 0 1305 *result = &(ahp->ah_priv.ah_channels[0]); 1306 *resultsize = 1307 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1308 #endif 1309 return AH_TRUE; 1310 #ifdef AH_DEBUG 1311 case HAL_DIAG_PRINT_REG: 1312 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1313 return AH_TRUE; 1314 #endif 1315 default: 1316 break; 1317 } 1318 1319 return AH_FALSE; 1320 } 1321 1322 void 1323 ar9300_dma_reg_dump(struct ath_hal *ah) 1324 { 1325 #ifdef AH_DEBUG 1326 #define NUM_DMA_DEBUG_REGS 8 1327 #define NUM_QUEUES 10 1328 1329 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1330 int qcu_offset = 0, dcu_offset = 0; 1331 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1332 int i, j, k; 1333 int16_t nfarray[HAL_NUM_NF_READINGS]; 1334 #ifdef ATH_NF_PER_CHAN 1335 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1336 #endif /* ATH_NF_PER_CHAN */ 1337 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1338 1339 /* selecting DMA OBS 8 */ 1340 OS_REG_WRITE(ah, AR_MACMISC, 1341 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1342 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1343 1344 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1345 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1346 if (i % 4 == 0) { 1347 ath_hal_printf(ah, "\n"); 1348 } 1349 1350 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1351 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1352 } 1353 1354 ath_hal_printf(ah, "\n\n"); 1355 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1356 1357 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1358 if (i == 8) { 1359 /* only 8 QCU entries in val[0] */ 1360 qcu_offset = 0; 1361 qcu_base++; 1362 } 1363 1364 if (i == 6) { 1365 /* only 6 DCU entries in val[4] */ 1366 dcu_offset = 0; 1367 dcu_base++; 1368 } 1369 1370 ath_hal_printf(ah, 1371 "%2d %2x %1x %2x %2x\n", 1372 i, 1373 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1374 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1375 val[2] & (0x7 << (i * 3)) >> (i * 3), 1376 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1377 } 1378 1379 ath_hal_printf(ah, "\n"); 1380 ath_hal_printf(ah, 1381 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1382 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1383 ath_hal_printf(ah, 1384 "qcu_complete state: %2x dcu_complete state: %2x\n", 1385 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1386 ath_hal_printf(ah, 1387 "dcu_arb state: %2x dcu_fp state: %2x\n", 1388 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1389 ath_hal_printf(ah, 1390 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1391 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1392 ath_hal_printf(ah, 1393 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1394 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1395 ath_hal_printf(ah, 1396 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1397 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1398 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1399 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1400 1401 ar9300_upload_noise_floor(ah, 1, nfarray); 1402 ath_hal_printf(ah, "2G:\n"); 1403 ath_hal_printf(ah, "Min CCA Out:\n"); 1404 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1405 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1406 nfarray[0], nfarray[1], nfarray[2]); 1407 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1408 nfarray[3], nfarray[4], nfarray[5]); 1409 1410 ar9300_upload_noise_floor(ah, 0, nfarray); 1411 ath_hal_printf(ah, "5G:\n"); 1412 ath_hal_printf(ah, "Min CCA Out:\n"); 1413 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1414 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1415 nfarray[0], nfarray[1], nfarray[2]); 1416 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1417 nfarray[3], nfarray[4], nfarray[5]); 1418 1419 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1420 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1421 ((i < 3) ? "Control " : "Extension "), i%3); 1422 for (j = 0, k = h->base.curr_index; 1423 j < HAL_NF_CAL_HIST_LEN_FULL; 1424 j++, k++) { 1425 ath_hal_printf(ah, "Element %d: %d\n", 1426 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1427 } 1428 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1429 } 1430 1431 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1432 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1433 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1434 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1435 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1436 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1437 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1438 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1439 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1440 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1441 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1442 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1443 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1444 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1445 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1446 reg = OS_REG_READ(ah, AR_PHY_AGC); 1447 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1448 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1449 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1450 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1451 MS(reg, AR_PHY_AGC_COARSE_LOW), 1452 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1453 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1454 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1455 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1456 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1457 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1458 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1459 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1460 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1461 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1462 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1463 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1464 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1465 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1466 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1467 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1468 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1469 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1470 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1471 1472 1473 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1474 reg = OS_REG_READ(ah, 0xa360); 1475 reg &= ~0x00800000; 1476 OS_REG_WRITE(ah, 0xa360, reg); 1477 1478 /* Step 2a: Set register 0xa364 to 0x1000 */ 1479 reg = 0x1000; 1480 OS_REG_WRITE(ah, 0xa364, reg); 1481 1482 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1483 reg = OS_REG_READ(ah, 0x9c20); 1484 reg &= 0x0003ffff; 1485 ath_hal_printf(ah, 1486 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1487 __func__, reg); 1488 1489 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1490 reg = OS_REG_READ(ah, 0xa360); 1491 reg &= ~0x00800000; 1492 OS_REG_WRITE(ah, 0xa360, reg); 1493 1494 /* Step 2b: Set register 0xa364 to 0x1400 */ 1495 reg = 0x1400; 1496 OS_REG_WRITE(ah, 0xa364, reg); 1497 1498 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1499 reg = OS_REG_READ(ah, 0x9c20); 1500 reg &= 0x0003ffff; 1501 ath_hal_printf(ah, 1502 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1503 __func__, reg); 1504 1505 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1506 reg = OS_REG_READ(ah, 0xa360); 1507 reg &= ~0x00800000; 1508 OS_REG_WRITE(ah, 0xa360, reg); 1509 1510 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1511 reg = 0x3c00; 1512 OS_REG_WRITE(ah, 0xa364, reg); 1513 1514 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1515 reg = OS_REG_READ(ah, 0x9c20); 1516 reg &= 0x0003ffff; 1517 ath_hal_printf(ah, 1518 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1519 __func__, reg); 1520 1521 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1522 reg = OS_REG_READ(ah, 0xa360); 1523 reg &= ~0x001040000; 1524 OS_REG_WRITE(ah, 0xa360, reg); 1525 1526 /* Step 2d: Set register 0xa364 to 0x5005D */ 1527 reg = 0x5005D; 1528 OS_REG_WRITE(ah, 0xa364, reg); 1529 1530 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1531 reg = OS_REG_READ(ah, 0xa368); 1532 reg &= 0x0003ffff; 1533 ath_hal_printf(ah, 1534 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1535 __func__, reg); 1536 1537 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1538 reg = OS_REG_READ(ah, 0xa360); 1539 reg &= ~0x001040000; 1540 OS_REG_WRITE(ah, 0xa360, reg); 1541 1542 /* Step 2e: Set register 0xa364 to 0x7005D */ 1543 reg = 0x7005D; 1544 OS_REG_WRITE(ah, 0xa364, reg); 1545 1546 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1547 reg = OS_REG_READ(ah, 0xa368); 1548 reg &= 0x0003ffff; 1549 ath_hal_printf(ah, 1550 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1551 __func__, reg); 1552 1553 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1554 reg = OS_REG_READ(ah, 0xa360); 1555 reg &= ~0x001000000; 1556 reg |= 0x40000; 1557 OS_REG_WRITE(ah, 0xa360, reg); 1558 1559 /* Step 2f: Set register 0xa364 to 0x3005D */ 1560 reg = 0x3005D; 1561 OS_REG_WRITE(ah, 0xa364, reg); 1562 1563 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1564 reg = OS_REG_READ(ah, 0xa368); 1565 reg &= 0x0003ffff; 1566 ath_hal_printf(ah, 1567 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1568 __func__, reg); 1569 1570 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1571 reg = OS_REG_READ(ah, 0xa360); 1572 reg &= ~0x001000000; 1573 reg |= 0x40000; 1574 OS_REG_WRITE(ah, 0xa360, reg); 1575 1576 /* Step 2g: Set register 0xa364 to 0x6005D */ 1577 reg = 0x6005D; 1578 OS_REG_WRITE(ah, 0xa364, reg); 1579 1580 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1581 reg = OS_REG_READ(ah, 0xa368); 1582 reg &= 0x0003ffff; 1583 ath_hal_printf(ah, 1584 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1585 __func__, reg); 1586 #endif /* AH_DEBUG */ 1587 } 1588 1589 /* 1590 * Return the busy for rx_frame, rx_clear, and tx_frame 1591 */ 1592 u_int32_t 1593 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1594 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1595 { 1596 struct ath_hal_9300 *ahp = AH9300(ah); 1597 u_int32_t good = 1; 1598 1599 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1600 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1601 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1602 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1603 1604 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1605 /* 1606 * Cycle counter wrap (or initial call); it's not possible 1607 * to accurately calculate a value because the registers 1608 * right shift rather than wrap--so punt and return 0. 1609 */ 1610 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1611 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1612 good = 0; 1613 } else { 1614 u_int32_t cc_d = cc - ahp->ah_cycles; 1615 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1616 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1617 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1618 1619 if (cc_d != 0) { 1620 *rxc_pcnt = rc_d * 100 / cc_d; 1621 *rxf_pcnt = rf_d * 100 / cc_d; 1622 *txf_pcnt = tf_d * 100 / cc_d; 1623 } else { 1624 good = 0; 1625 } 1626 } 1627 1628 ahp->ah_cycles = cc; 1629 ahp->ah_rx_frame = rf; 1630 ahp->ah_rx_clear = rc; 1631 ahp->ah_tx_frame = tf; 1632 1633 return good; 1634 } 1635 1636 /* 1637 * Return approximation of extension channel busy over an time interval 1638 * 0% (clear) -> 100% (busy) 1639 * -1 for invalid estimate 1640 */ 1641 uint32_t 1642 ar9300_get_11n_ext_busy(struct ath_hal *ah) 1643 { 1644 /* 1645 * Overflow condition to check before multiplying to get % 1646 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1647 */ 1648 #define OVERFLOW_LIMIT 0x28F5C28 1649 #define ERROR_CODE -1 1650 1651 struct ath_hal_9300 *ahp = AH9300(ah); 1652 u_int32_t busy = 0; /* percentage */ 1653 int8_t busyper = 0; 1654 u_int32_t cycle_count, ctl_busy, ext_busy; 1655 1656 /* cycle_count will always be the first to wrap; therefore, read it last 1657 * This sequence of reads is not atomic, and MIB counter wrap 1658 * could happen during it ? 1659 */ 1660 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1661 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1662 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1663 1664 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1665 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1666 { 1667 /* 1668 * Cycle counter wrap (or initial call); it's not possible 1669 * to accurately calculate a value because the registers 1670 * right shift rather than wrap--so punt and return 0. 1671 */ 1672 busyper = ERROR_CODE; 1673 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1674 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1675 } else { 1676 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1677 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1678 1679 /* 1680 * Compute extension channel busy percentage 1681 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1682 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1683 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1684 * and shift necessitated by large ext_busy_delta. 1685 * Due to timing difference to read the registers and counter overflow, 1686 * it may still happen that cycle_delta >> 7 = 0. 1687 * 1688 */ 1689 if (cycle_delta) { 1690 if (ext_busy_delta > OVERFLOW_LIMIT) { 1691 if (cycle_delta >> 7) { 1692 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1693 } else { 1694 busyper = ERROR_CODE; 1695 } 1696 } else { 1697 busy = (ext_busy_delta * 100) / cycle_delta; 1698 } 1699 } else { 1700 busyper = ERROR_CODE; 1701 } 1702 1703 if (busy > 100) { 1704 busy = 100; 1705 } 1706 if ( busyper != ERROR_CODE ) { 1707 busyper = busy; 1708 } 1709 } 1710 1711 ahp->ah_cycle_count = cycle_count; 1712 ahp->ah_ctl_busy = ctl_busy; 1713 ahp->ah_ext_busy = ext_busy; 1714 1715 return busyper; 1716 #undef OVERFLOW_LIMIT 1717 #undef ERROR_CODE 1718 } 1719 1720 /* BB Panic Watchdog declarations */ 1721 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1722 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1723 1724 void 1725 ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1726 { 1727 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1728 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1729 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1730 u_int32_t val, idle_count; 1731 1732 if (idle_tmo_ms != 0) { 1733 /* enable IRQ, disable chip-reset for BB panic */ 1734 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1735 AR_PHY_BB_PANIC_CNTL2_MASK; 1736 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1737 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1738 /* bound limit to 10 secs */ 1739 if (idle_tmo_ms > 10000) { 1740 idle_tmo_ms = 10000; 1741 } 1742 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1743 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1744 } else { 1745 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1746 } 1747 /* 1748 * enable panic in non-IDLE mode, 1749 * disable in IDLE mode, 1750 * set idle time-out 1751 */ 1752 1753 // EV92527 : Enable IDLE mode panic 1754 1755 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1756 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1757 AR_PHY_BB_PANIC_IDLE_ENABLE | 1758 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1759 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1760 } else { 1761 /* disable IRQ, disable chip-reset for BB panic */ 1762 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1763 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1764 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1765 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1766 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1767 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1768 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1769 } 1770 1771 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1772 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1773 #undef HAL_BB_PANIC_IDLE_TIME_OUT 1774 } 1775 1776 1777 void 1778 ar9300_handle_bb_panic(struct ath_hal *ah) 1779 { 1780 u_int32_t status; 1781 /* 1782 * we want to avoid printing in ISR context so we save 1783 * panic watchdog status to be printed later in DPC context 1784 */ 1785 AH9300(ah)->ah_bb_panic_last_status = status = 1786 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1787 /* 1788 * panic watchdog timer should reset on status read 1789 * but to make sure we write 0 to the watchdog status bit 1790 */ 1791 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1792 } 1793 1794 int 1795 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1796 { 1797 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1798 1799 /* 1800 * For signature 04000539 do not print anything. 1801 * This is a very common occurence as a compromise between 1802 * BB Panic and AH_FALSE detects (EV71009). It indicates 1803 * radar hang, which can be cleared by reprogramming 1804 * radar related register and does not requre a chip reset 1805 */ 1806 1807 /* Suppress BB Status mesg following signature */ 1808 switch (bb_panic->status) { 1809 case 0x04000539: 1810 case 0x04008009: 1811 case 0x04000b09: 1812 case 0x1300000a: 1813 return -1; 1814 } 1815 1816 bb_panic->tsf = ar9300_get_tsf32(ah); 1817 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1818 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1819 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1820 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1821 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1822 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1823 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1824 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1825 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1826 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1827 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1828 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1829 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1830 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1831 &bb_panic->rxc_pcnt, 1832 &bb_panic->rxf_pcnt, 1833 &bb_panic->txf_pcnt); 1834 1835 if (ah->ah_config.ath_hal_show_bb_panic) { 1836 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1837 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1838 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1839 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1840 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1841 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1842 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1843 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1844 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1845 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1846 bb_panic->phy_gen_ctrl); 1847 if (bb_panic->cycles) { 1848 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1849 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1850 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1851 } 1852 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1853 } 1854 1855 return 0; //The returned data will be stored for athstats to retrieve it 1856 } 1857 1858 /* set the reason for HAL reset */ 1859 void 1860 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1861 { 1862 AH9300(ah)->ah_reset_reason = resetreason; 1863 } 1864 1865 /* 1866 * Configure 20/40 operation 1867 * 1868 * 20/40 = joint rx clear (control and extension) 1869 * 20 = rx clear (control) 1870 * 1871 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1872 * when changing from 20/40 => 20 only 1873 */ 1874 void 1875 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1876 { 1877 u_int32_t macmode; 1878 1879 /* Configure MAC for 20/40 operation */ 1880 if (mode == HAL_HT_MACMODE_2040 && 1881 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1882 macmode = AR_2040_JOINED_RX_CLEAR; 1883 } else { 1884 macmode = 0; 1885 } 1886 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1887 } 1888 1889 /* 1890 * Get Rx clear (control/extension channel) 1891 * 1892 * Returns active low (busy) for ctrl/ext channel 1893 * Owl 2.0 1894 */ 1895 HAL_HT_RXCLEAR 1896 ar9300_get_11n_rx_clear(struct ath_hal *ah) 1897 { 1898 HAL_HT_RXCLEAR rxclear = 0; 1899 u_int32_t val; 1900 1901 val = OS_REG_READ(ah, AR_DIAG_SW); 1902 1903 /* control channel */ 1904 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1905 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1906 } 1907 /* extension channel */ 1908 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1909 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1910 } 1911 return rxclear; 1912 } 1913 1914 /* 1915 * Set Rx clear (control/extension channel) 1916 * 1917 * Useful for forcing the channel to appear busy for 1918 * debugging/diagnostics 1919 * Owl 2.0 1920 */ 1921 void 1922 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1923 { 1924 /* control channel */ 1925 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1926 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1927 } else { 1928 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1929 } 1930 /* extension channel */ 1931 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1932 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1933 } else { 1934 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1935 } 1936 } 1937 1938 1939 /* 1940 * HAL support code for force ppm tracking workaround. 1941 */ 1942 1943 u_int32_t 1944 ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1945 { 1946 u_int32_t retval; 1947 u_int32_t off1; 1948 u_int32_t off2; 1949 1950 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1951 off1 = 0x2000; 1952 off2 = 0x1000; 1953 } else { 1954 off1 = 0x1000; 1955 off2 = 0x2000; 1956 } 1957 1958 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1959 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1960 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1961 1962 return retval; 1963 } 1964 1965 u_int32_t 1966 ar9300_ppm_force(struct ath_hal *ah) 1967 { 1968 u_int32_t data_fine; 1969 u_int32_t data4; 1970 //u_int32_t off1; 1971 //u_int32_t off2; 1972 HAL_BOOL signed_val = AH_FALSE; 1973 1974 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1975 // off1 = 0x2000; 1976 // off2 = 0x1000; 1977 // } else { 1978 // off1 = 0x1000; 1979 // off2 = 0x2000; 1980 // } 1981 data_fine = 1982 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1983 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1984 1985 /* 1986 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1987 * So check value from bit[10:0]. 1988 * Now get the abs val of the ppm value read in bit[0:11]. 1989 * After that do bound check on abs value. 1990 * if value is off limit, CAP the value and and restore signed bit. 1991 */ 1992 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1993 { 1994 /* get the positive value */ 1995 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1996 signed_val = AH_TRUE; 1997 } 1998 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1999 { 2000 HALDEBUG(ah, HAL_DEBUG_REGIO, 2001 "%s Correcting ppm out of range %x\n", 2002 __func__, (data_fine & 0x7ff)); 2003 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 2004 } 2005 /* 2006 * Restore signed value if changed above. 2007 * Use typecast to avoid compilation errors 2008 */ 2009 if (signed_val) { 2010 data_fine = (-(int32_t)data_fine) & 2011 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 2012 } 2013 2014 /* write value */ 2015 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 2016 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2017 OS_REG_WRITE(ah, AR_PHY_TIMING2, 2018 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 2019 2020 return data_fine; 2021 } 2022 2023 void 2024 ar9300_ppm_un_force(struct ath_hal *ah) 2025 { 2026 u_int32_t data4; 2027 2028 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 2029 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 2030 } 2031 2032 u_int32_t 2033 ar9300_ppm_arm_trigger(struct ath_hal *ah) 2034 { 2035 u_int32_t val; 2036 u_int32_t ret; 2037 2038 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2039 ret = OS_REG_READ(ah, AR_TSF_L32); 2040 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2041 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2042 2043 /* return low word of TSF at arm time */ 2044 return ret; 2045 } 2046 2047 int 2048 ar9300_ppm_get_trigger(struct ath_hal *ah) 2049 { 2050 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2051 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2052 { 2053 /* has not triggered yet, return AH_FALSE */ 2054 return 0; 2055 } 2056 2057 /* else triggered, return AH_TRUE */ 2058 return 1; 2059 } 2060 2061 void 2062 ar9300_mark_phy_inactive(struct ath_hal *ah) 2063 { 2064 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2065 } 2066 2067 /* DEBUG */ 2068 u_int32_t 2069 ar9300_ppm_get_force_state(struct ath_hal *ah) 2070 { 2071 return 2072 OS_REG_READ(ah, AR_PHY_TIMING2) & 2073 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2074 } 2075 2076 /* 2077 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2078 */ 2079 HAL_BOOL 2080 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2081 { 2082 /* 2083 * XXX FreeBSD todo: reimplement this 2084 */ 2085 #if 0 2086 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2087 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2088 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2089 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2090 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2091 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2092 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2093 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2094 #endif 2095 return AH_FALSE; 2096 } 2097 2098 void 2099 ar9300_clear_mib_counters(struct ath_hal *ah) 2100 { 2101 u_int32_t reg_val; 2102 2103 reg_val = OS_REG_READ(ah, AR_MIBC); 2104 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2105 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2106 } 2107 2108 2109 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2110 HAL_BOOL 2111 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2112 { 2113 struct ath_hal_9300 *ahp = AH9300(ah); 2114 HAL_CHANNEL_INTERNAL *ichan = 2115 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2116 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2117 u_int32_t tmp = 0; 2118 2119 if (enable) { 2120 if (ahp->ah_rifs_enabled == AH_TRUE) { 2121 return AH_TRUE; 2122 } 2123 2124 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2125 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2126 ahp->ah_rifs_reg[1]); 2127 2128 ahp->ah_rifs_enabled = AH_TRUE; 2129 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2130 } else { 2131 if (ahp->ah_rifs_enabled == AH_TRUE) { 2132 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2133 AR_PHY_SEARCH_START_DELAY); 2134 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2135 } 2136 /* Change rifs init delay to 0 */ 2137 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2138 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2139 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2140 if (is_chan_2g) { 2141 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2142 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2143 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2144 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2145 } 2146 } else { 2147 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2148 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2149 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2150 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2151 } 2152 } 2153 2154 ahp->ah_rifs_enabled = AH_FALSE; 2155 } 2156 return AH_TRUE; 2157 2158 } /* ar9300_set_rifs_delay () */ 2159 2160 /* Set the current RIFS Rx setting */ 2161 HAL_BOOL 2162 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2163 { 2164 /* Non-Owl 11n chips */ 2165 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2166 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2167 return ar9300_set_rifs_delay(ah, enable); 2168 } 2169 return AH_FALSE; 2170 } 2171 2172 return AH_TRUE; 2173 } /* ar9300_set_11n_rx_rifs () */ 2174 2175 static hal_mac_hangs_t 2176 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2177 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2178 { 2179 int i = 0; 2180 hal_mac_hangs_t found_hangs = 0; 2181 2182 if (hangs & dcu_chain_state) { 2183 for (i = 0; i < 6; i++) { 2184 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2185 hang_check.dcu_chain_state) 2186 { 2187 found_hangs |= dcu_chain_state; 2188 *dcu_chain = i; 2189 } 2190 } 2191 for (i = 0; i < 4; i++) { 2192 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2193 hang_check.dcu_chain_state) 2194 { 2195 found_hangs |= dcu_chain_state; 2196 *dcu_chain = i + 6; 2197 } 2198 } 2199 } 2200 2201 if (hangs & dcu_complete_state) { 2202 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2203 found_hangs |= dcu_complete_state; 2204 } 2205 } 2206 2207 return found_hangs; 2208 2209 } /* end - ar9300_compare_dbg_hang */ 2210 2211 #define NUM_STATUS_READS 50 2212 HAL_BOOL 2213 ar9300_detect_mac_hang(struct ath_hal *ah) 2214 { 2215 struct ath_hal_9300 *ahp = AH9300(ah); 2216 mac_dbg_regs_t mac_dbg; 2217 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2218 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2219 int i = 0; 2220 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2221 2222 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2223 return AH_FALSE; 2224 } 2225 2226 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2227 2228 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2229 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2230 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2231 2232 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2233 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2234 mac_dbg.dma_dbg_6); 2235 2236 if (hang_sig1 != 2237 ar9300_compare_dbg_hang(ah, mac_dbg, 2238 hang_sig1_val, hang_sig1, &dcu_chain)) 2239 { 2240 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2241 return AH_FALSE; 2242 } 2243 2244 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2245 shift_val *= 5; 2246 2247 for (i = 1; i <= NUM_STATUS_READS; i++) { 2248 if (dcu_chain < 6) { 2249 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2250 current_dcu_chain_state = 2251 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2252 } else { 2253 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2254 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2255 } 2256 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2257 2258 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2259 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2260 return AH_FALSE; 2261 } 2262 } 2263 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2264 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2265 ahp->ah_hang[MAC_HANG_SIG1]++; 2266 return AH_TRUE; 2267 2268 } /* end - ar9300_detect_mac_hang */ 2269 2270 /* Determine if the baseband is hung by reading the Observation Bus Register */ 2271 HAL_BOOL 2272 ar9300_detect_bb_hang(struct ath_hal *ah) 2273 { 2274 #define N(a) (sizeof(a) / sizeof(a[0])) 2275 struct ath_hal_9300 *ahp = AH9300(ah); 2276 u_int32_t hang_sig = 0; 2277 int i = 0; 2278 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2279 * 2280 * 4 known BB hang signatures - 2281 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2282 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2283 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2284 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2285 * Rx State (bits 20-24) is 0x7. 2286 */ 2287 hal_hw_hang_check_t hang_list [] = 2288 { 2289 /* Offset Reg Value Reg Mask Hang Offset */ 2290 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2291 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2292 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2293 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2294 }; 2295 2296 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2297 HAL_DFS_BB_HANG_WAR | 2298 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2299 return AH_FALSE; 2300 } 2301 2302 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2303 for (i = 1; i <= NUM_STATUS_READS; i++) { 2304 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2305 return AH_FALSE; 2306 } 2307 } 2308 2309 for (i = 0; i < N(hang_list); i++) { 2310 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2311 ahp->ah_hang[hang_list[i].hang_offset]++; 2312 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2313 "sig3count=%d sig4count=%d\n", __func__, 2314 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2315 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2316 return AH_TRUE; 2317 } 2318 } 2319 2320 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2321 "<0x806c>=0x%x\n", __func__, hang_sig); 2322 2323 return AH_FALSE; 2324 2325 #undef N 2326 } /* end - ar9300_detect_bb_hang () */ 2327 2328 #undef NUM_STATUS_READS 2329 2330 HAL_STATUS 2331 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2332 { 2333 struct ath_hal_9300 *ahp = AH9300(ah); 2334 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2335 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2336 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2337 u_int16_t ant_config; 2338 u_int32_t hal_num_ant_config; 2339 2340 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2341 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2342 2343 if (cfg < hal_num_ant_config) { 2344 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2345 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2346 return HAL_OK; 2347 } 2348 } 2349 2350 return HAL_EINVAL; 2351 } 2352 2353 /* 2354 * Functions to get/set DCS mode 2355 */ 2356 void 2357 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2358 { 2359 AH9300(ah)->ah_dcs_enable = mode; 2360 } 2361 2362 u_int32_t 2363 ar9300_get_dcs_mode(struct ath_hal *ah) 2364 { 2365 return AH9300(ah)->ah_dcs_enable; 2366 } 2367 2368 #if ATH_BT_COEX 2369 void 2370 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2371 { 2372 struct ath_hal_9300 *ahp = AH9300(ah); 2373 2374 ahp->ah_bt_module = btinfo->bt_module; 2375 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2376 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2377 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2378 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2379 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2380 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2381 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2382 } 2383 2384 void 2385 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2386 { 2387 struct ath_hal_9300 *ahp = AH9300(ah); 2388 HAL_BOOL rx_clear_polarity; 2389 2390 /* 2391 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2392 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2393 */ 2394 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2395 2396 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2397 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2398 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2399 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2400 SM(btconf->bt_mode, AR_BT_MODE) | 2401 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2402 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2403 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2404 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2405 2406 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2407 2408 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2409 /* Enable ACK to go out even though BT has higher priority. */ 2410 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2411 } 2412 } 2413 2414 void 2415 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2416 { 2417 struct ath_hal_9300 *ahp = AH9300(ah); 2418 2419 /* clear the old value, then set the new value */ 2420 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2421 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2422 } 2423 2424 void 2425 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2426 { 2427 struct ath_hal_9300 *ahp = AH9300(ah); 2428 2429 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2430 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2431 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2432 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2433 2434 switch (stomp_type) { 2435 case HAL_BT_COEX_STOMP_ALL: 2436 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2437 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2438 break; 2439 case HAL_BT_COEX_STOMP_LOW: 2440 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2441 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2442 break; 2443 case HAL_BT_COEX_STOMP_ALL_FORCE: 2444 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2445 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2446 break; 2447 case HAL_BT_COEX_STOMP_LOW_FORCE: 2448 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2449 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2450 break; 2451 case HAL_BT_COEX_STOMP_NONE: 2452 case HAL_BT_COEX_NO_STOMP: 2453 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2454 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2455 break; 2456 default: 2457 /* There is a force_weight from registry */ 2458 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2459 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2460 break; 2461 } 2462 } 2463 2464 void 2465 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2466 { 2467 struct ath_hal_9300 *ahp = AH9300(ah); 2468 2469 /* clear the old value, then set the new value */ 2470 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2471 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2472 } 2473 2474 static void 2475 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2476 { 2477 struct ath_hal_9300 *ahp = AH9300(ah); 2478 #if ATH_ANT_DIV_COMB 2479 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2480 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2481 #endif 2482 2483 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value); 2484 2485 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2486 { 2487 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2488 { 2489 /* Config antenna diversity */ 2490 #if ATH_ANT_DIV_COMB 2491 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2492 #endif 2493 } 2494 } 2495 } 2496 2497 2498 void 2499 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2500 u_int32_t value) 2501 { 2502 struct ath_hal_9300 *ahp = AH9300(ah); 2503 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2504 2505 switch (type) { 2506 case HAL_BT_COEX_SET_ACK_PWR: 2507 if (value) { 2508 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2509 } else { 2510 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2511 } 2512 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2513 ahpriv->ah_extraTxPow, 0); 2514 break; 2515 2516 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2517 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2518 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2519 if (value) { 2520 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2521 } 2522 else { 2523 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2524 } 2525 ar9300_bt_coex_antenna_diversity(ah, value); 2526 } 2527 break; 2528 case HAL_BT_COEX_LOWER_TX_PWR: 2529 if (value) { 2530 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2531 } 2532 else { 2533 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2534 } 2535 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2536 ahpriv->ah_extraTxPow, 0); 2537 break; 2538 #if ATH_SUPPORT_MCI 2539 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2540 if ((ah->ah_config.ath_hal_mci_config & 2541 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2542 { 2543 if (value) { 2544 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2545 ahp->ah_mci_concur_tx_en = AH_TRUE; 2546 } 2547 else { 2548 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2549 ahp->ah_mci_concur_tx_en = AH_FALSE; 2550 } 2551 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2552 ahpriv->ah_extraTxPow, 0); 2553 } 2554 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2555 ahp->ah_mci_concur_tx_en); 2556 break; 2557 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2558 if (value) { 2559 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2560 } 2561 else { 2562 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2563 } 2564 break; 2565 #endif 2566 default: 2567 break; 2568 } 2569 } 2570 2571 void 2572 ar9300_bt_coex_disable(struct ath_hal *ah) 2573 { 2574 struct ath_hal_9300 *ahp = AH9300(ah); 2575 2576 /* Always drive rx_clear_external output as 0 */ 2577 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2578 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2579 2580 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2581 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2582 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2583 } 2584 2585 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2586 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2587 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2588 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2589 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2590 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2591 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2592 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2593 2594 ahp->ah_bt_coex_enabled = AH_FALSE; 2595 } 2596 2597 int 2598 ar9300_bt_coex_enable(struct ath_hal *ah) 2599 { 2600 struct ath_hal_9300 *ahp = AH9300(ah); 2601 2602 /* Program coex mode and weight registers to actually enable coex */ 2603 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2604 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2605 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2606 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2607 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2608 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2609 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2610 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2611 2612 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2613 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2614 } else { 2615 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2616 } 2617 2618 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2619 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2620 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2621 } else { 2622 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2623 } 2624 2625 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2626 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2627 ath_hal_gpioCfgOutput(ah, 2628 ahp->ah_wlan_active_gpio_select, 2629 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2630 } 2631 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2632 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2633 { 2634 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2635 ath_hal_gpioCfgOutput(ah, 2636 ahp->ah_wlan_active_gpio_select, 2637 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2638 } 2639 2640 /* 2641 * Enable a weak pull down on BT_ACTIVE. 2642 * When BT device is disabled, BT_ACTIVE might be floating. 2643 */ 2644 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2645 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2646 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2647 2648 ahp->ah_bt_coex_enabled = AH_TRUE; 2649 2650 return 0; 2651 } 2652 2653 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2654 { 2655 return 0; 2656 } 2657 2658 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2659 { 2660 return bOn; 2661 } 2662 2663 void 2664 ar9300_init_bt_coex(struct ath_hal *ah) 2665 { 2666 struct ath_hal_9300 *ahp = AH9300(ah); 2667 2668 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2669 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2670 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2671 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2672 2673 /* 2674 * Set input mux for bt_prority_async and 2675 * bt_active_async to GPIO pins 2676 */ 2677 OS_REG_RMW_FIELD(ah, 2678 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2679 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2680 ahp->ah_bt_active_gpio_select); 2681 OS_REG_RMW_FIELD(ah, 2682 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2683 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2684 ahp->ah_bt_priority_gpio_select); 2685 2686 /* Configure the desired GPIO ports for input */ 2687 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2688 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2689 2690 if (ahp->ah_bt_coex_enabled) { 2691 ar9300_bt_coex_enable(ah); 2692 } else { 2693 ar9300_bt_coex_disable(ah); 2694 } 2695 } 2696 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2697 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2698 { 2699 /* 2-wire */ 2700 if (ahp->ah_bt_coex_enabled) { 2701 /* Connect bt_active_async to baseband */ 2702 OS_REG_CLR_BIT(ah, 2703 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2704 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2705 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2706 OS_REG_SET_BIT(ah, 2707 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2708 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2709 2710 /* 2711 * Set input mux for bt_prority_async and 2712 * bt_active_async to GPIO pins 2713 */ 2714 OS_REG_RMW_FIELD(ah, 2715 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2716 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2717 ahp->ah_bt_active_gpio_select); 2718 2719 /* Configure the desired GPIO ports for input */ 2720 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2721 2722 /* Enable coexistence on initialization */ 2723 ar9300_bt_coex_enable(ah); 2724 } 2725 } 2726 #if ATH_SUPPORT_MCI 2727 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2728 if (ahp->ah_bt_coex_enabled) { 2729 ar9300_mci_bt_coex_enable(ah); 2730 } 2731 else { 2732 ar9300_mci_bt_coex_disable(ah); 2733 } 2734 } 2735 #endif /* ATH_SUPPORT_MCI */ 2736 } 2737 2738 #endif /* ATH_BT_COEX */ 2739 2740 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2741 { 2742 u_int32_t val; 2743 int wasp_mm_rev; 2744 2745 #define AR_SOC_RST_REVISION_ID 0xB8060090 2746 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2747 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2748 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2749 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2750 #undef AR_SOC_RST_REVISION_ID 2751 #undef REG_READ 2752 2753 /* 2754 * Azimuth (ProxySTA) Mode is only supported correctly by 2755 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2756 * 2757 * Enable this feature for Scorpion at this time. The silicon 2758 * still needs to be validated. 2759 */ 2760 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2761 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2762 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2763 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2764 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2765 wasp_mm_rev >= 0 /* 1 */)))) 2766 { 2767 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2768 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2769 __func__, AH_PRIVATE((ah))->ah_macVersion, 2770 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2771 return HAL_ENOTSUPP; 2772 } 2773 2774 OS_REG_WRITE(ah, 2775 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2776 2777 /* turn on mode bit[24] for proxy sta */ 2778 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2779 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2780 2781 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2782 if (enable) { 2783 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2784 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2785 AR_AZIMUTH_BA_USES_AD1; 2786 /* turn off filter pass hold (bit 9) */ 2787 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2788 } else { 2789 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2790 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2791 AR_AZIMUTH_BA_USES_AD1); 2792 } 2793 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2794 2795 /* enable promiscous mode */ 2796 OS_REG_WRITE(ah, AR_RX_FILTER, 2797 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2798 /* enable promiscous in azimuth mode */ 2799 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2800 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2801 2802 /* turn on filter pass hold (bit 9) */ 2803 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2804 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2805 2806 return HAL_OK; 2807 } 2808 2809 #if 0 2810 void ar9300_mat_enable(struct ath_hal *ah, int enable) 2811 { 2812 /* 2813 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2814 * mitigation and turn on key search always for better performance. 2815 */ 2816 struct ath_hal_9300 *ahp = AH9300(ah); 2817 struct ath_hal_private *ap = AH_PRIVATE(ah); 2818 2819 ahp->ah_intr_mitigation_rx = !enable; 2820 if (ahp->ah_intr_mitigation_rx) { 2821 /* 2822 * Enable Interrupt Mitigation for Rx. 2823 * If no build-specific limits for the rx interrupt mitigation 2824 * timer have been specified, use conservative defaults. 2825 */ 2826 #ifndef AH_RIMT_VAL_LAST 2827 #define AH_RIMT_LAST_MICROSEC 500 2828 #endif 2829 #ifndef AH_RIMT_VAL_FIRST 2830 #define AH_RIMT_FIRST_MICROSEC 2000 2831 #endif 2832 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2833 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2834 } else { 2835 OS_REG_WRITE(ah, AR_RIMT, 0); 2836 } 2837 2838 ahp->ah_enable_keysearch_always = !!enable; 2839 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2840 } 2841 #endif 2842 2843 void ar9300_enable_tpc(struct ath_hal *ah) 2844 { 2845 u_int32_t val = 0; 2846 2847 ah->ah_config.ath_hal_desc_tpc = 1; 2848 2849 /* Enable TPC */ 2850 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2851 2852 /* 2853 * Disable per chain power reduction since we are already 2854 * accounting for this in our calculations 2855 */ 2856 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2857 if (AR_SREV_WASP(ah)) { 2858 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2859 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2860 } else { 2861 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2862 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2863 } 2864 } 2865 2866 2867 /* 2868 * ar9300_force_tsf_sync 2869 * This function forces the TSF sync to the given bssid, this is implemented 2870 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2871 * mode of operation, where we sync the TSF to RootAP TSF values 2872 */ 2873 void 2874 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2875 u_int16_t assoc_id) 2876 { 2877 ar9300_set_operating_mode(ah, HAL_M_STA); 2878 ar9300_write_associd(ah, bssid, assoc_id); 2879 } 2880 2881 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2882 { 2883 struct ath_hal_9300 *ahp = AH9300(ah); 2884 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2885 u_int32_t temp_powertx_rate9_reg_val; 2886 int8_t olpc_power_offset = 0; 2887 int8_t tmp_olpc_val = 0; 2888 HAL_RSSI_TX_POWER old_greentx_status; 2889 u_int8_t target_power_val_t[ar9300_rate_size]; 2890 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2891 2892 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2893 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2894 return; 2895 } 2896 2897 old_greentx_status = AH9300(ah)->green_tx_status; 2898 if (ahp->ah_hw_green_tx_enable) { 2899 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2900 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2901 } else { 2902 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2903 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2904 } 2905 2906 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2907 && (rssi > tmp_rss1_thr1)) 2908 { 2909 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2910 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2911 } 2912 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2913 && (rssi > tmp_rss1_thr2)) 2914 { 2915 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2916 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2917 } 2918 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2919 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2920 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2921 } 2922 } 2923 2924 /* If status is not change, don't do anything */ 2925 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2926 return; 2927 } 2928 2929 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2930 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2931 && AR_SREV_POSEIDON(ah)) 2932 { 2933 if (ahp->ah_hw_green_tx_enable) { 2934 switch (AH9300(ah)->green_tx_status) { 2935 case HAL_RSSI_TX_POWER_SHORT: 2936 /* 1. TxPower Config */ 2937 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2938 sizeof(target_power_val_t)); 2939 /* 1.1 Store OLPC Delta Calibration Offset*/ 2940 olpc_power_offset = 0; 2941 /* 2. Store OB/DB */ 2942 /* 3. Store TPC settting */ 2943 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2944 SM(14, AR_TPC_CTS) | 2945 SM(14, AR_TPC_CHIRP) | 2946 SM(14, AR_TPC_RPT)); 2947 /* 4. Store BB_powertx_rate9 value */ 2948 temp_powertx_rate9_reg_val = 2949 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2950 break; 2951 case HAL_RSSI_TX_POWER_MIDDLE: 2952 /* 1. TxPower Config */ 2953 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2954 sizeof(target_power_val_t)); 2955 /* 1.1 Store OLPC Delta Calibration Offset*/ 2956 olpc_power_offset = 0; 2957 /* 2. Store OB/DB */ 2958 /* 3. Store TPC settting */ 2959 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2960 SM(18, AR_TPC_CTS) | 2961 SM(18, AR_TPC_CHIRP) | 2962 SM(18, AR_TPC_RPT)); 2963 /* 4. Store BB_powertx_rate9 value */ 2964 temp_powertx_rate9_reg_val = 2965 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2966 break; 2967 case HAL_RSSI_TX_POWER_LONG: 2968 default: 2969 /* 1. TxPower Config */ 2970 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2971 sizeof(target_power_val_t)); 2972 /* 1.1 Store OLPC Delta Calibration Offset*/ 2973 olpc_power_offset = 0; 2974 /* 2. Store OB/DB1/DB2 */ 2975 /* 3. Store TPC settting */ 2976 temp_tcp_reg_val = 2977 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2978 /* 4. Store BB_powertx_rate9 value */ 2979 temp_powertx_rate9_reg_val = 2980 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2981 break; 2982 } 2983 } else { 2984 switch (AH9300(ah)->green_tx_status) { 2985 case HAL_RSSI_TX_POWER_SHORT: 2986 /* 1. TxPower Config */ 2987 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2988 sizeof(target_power_val_t)); 2989 /* 1.1 Store OLPC Delta Calibration Offset*/ 2990 olpc_power_offset = 2991 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2992 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2993 /* 2. Store OB/DB */ 2994 temp_obdb_reg_val = 2995 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2996 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2997 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2998 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2999 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3000 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3001 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3002 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3003 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3004 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3005 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3006 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3007 /* 3. Store TPC settting */ 3008 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 3009 SM(6, AR_TPC_CTS) | 3010 SM(6, AR_TPC_CHIRP) | 3011 SM(6, AR_TPC_RPT)); 3012 /* 4. Store BB_powertx_rate9 value */ 3013 temp_powertx_rate9_reg_val = 3014 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 3015 break; 3016 case HAL_RSSI_TX_POWER_MIDDLE: 3017 /* 1. TxPower Config */ 3018 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 3019 sizeof(target_power_val_t)); 3020 /* 1.1 Store OLPC Delta Calibration Offset*/ 3021 olpc_power_offset = 3022 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 3023 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3024 /* 2. Store OB/DB */ 3025 temp_obdb_reg_val = 3026 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3027 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3028 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3029 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3030 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3031 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3032 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3033 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3034 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3035 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3036 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3037 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3038 /* 3. Store TPC settting */ 3039 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3040 SM(14, AR_TPC_CTS) | 3041 SM(14, AR_TPC_CHIRP) | 3042 SM(14, AR_TPC_RPT)); 3043 /* 4. Store BB_powertx_rate9 value */ 3044 temp_powertx_rate9_reg_val = 3045 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3046 break; 3047 case HAL_RSSI_TX_POWER_LONG: 3048 default: 3049 /* 1. TxPower Config */ 3050 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3051 sizeof(target_power_val_t)); 3052 /* 1.1 Store OLPC Delta Calibration Offset*/ 3053 olpc_power_offset = 3054 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3055 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3056 /* 2. Store OB/DB1/DB2 */ 3057 temp_obdb_reg_val = 3058 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3059 /* 3. Store TPC settting */ 3060 temp_tcp_reg_val = 3061 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3062 /* 4. Store BB_powertx_rate9 value */ 3063 temp_powertx_rate9_reg_val = 3064 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3065 break; 3066 } 3067 } 3068 /* 1.1 Do OLPC Delta Calibration Offset */ 3069 tmp_olpc_val = 3070 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3071 tmp_olpc_val += olpc_power_offset; 3072 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3073 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3074 AR_PHY_TPC_OLPC_GAIN_DELTA); 3075 3076 /* 1.2 TxPower Config */ 3077 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3078 /* 2. Config OB/DB */ 3079 if (!ahp->ah_hw_green_tx_enable) { 3080 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3081 } 3082 /* 3. config TPC settting */ 3083 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3084 /* 4. config BB_powertx_rate9 value */ 3085 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3086 } 3087 } 3088 3089 #if 0 3090 void 3091 ar9300_get_vow_stats( 3092 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3093 { 3094 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3095 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3096 } 3097 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3098 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3099 } 3100 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3101 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3102 } 3103 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3104 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3105 } 3106 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3107 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3108 } 3109 } 3110 #endif 3111 3112 /* 3113 * ar9300_is_skip_paprd_by_greentx 3114 * 3115 * This function check if we need to skip PAPRD tuning 3116 * when GreenTx in specific state. 3117 */ 3118 HAL_BOOL 3119 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3120 { 3121 if (AR_SREV_POSEIDON(ah) && 3122 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3123 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3124 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3125 { 3126 return AH_TRUE; 3127 } 3128 return AH_FALSE; 3129 } 3130 3131 void 3132 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3133 { 3134 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3135 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3136 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3137 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3138 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3139 struct ath_hal_9300 *ahp = AH9300(ah); 3140 3141 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3142 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3143 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3144 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3145 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3146 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3147 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3148 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3149 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3150 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3151 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3152 } 3153 } 3154 3155 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3156 { 3157 struct ath_hal_9300 *ahp = AH9300(ah); 3158 3159 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3160 if ((value == 0) || (value == 1)) { 3161 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3162 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3163 } 3164 } 3165 } 3166 3167 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3168 { 3169 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3170 } 3171 3172 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3173 { 3174 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3175 3176 /* RSSI format is 8.4. Ignore lowest four bits */ 3177 val = val >> 4; 3178 return val; 3179 } 3180 3181 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3182 u_int32_t rssi_threshold) 3183 { 3184 struct ath_hal_9300 *ahp = AH9300(ah); 3185 3186 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3187 3188 /* save value for restoring after chip reset */ 3189 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3190 } 3191 3192 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3193 { 3194 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3195 } 3196 3197 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3198 { 3199 if (on) { 3200 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3201 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3202 } 3203 else { 3204 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3205 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3206 } 3207 } 3208 /* 3209 * Gets the contents of the specified key cache entry. 3210 */ 3211 HAL_BOOL 3212 ar9300_print_keycache(struct ath_hal *ah) 3213 { 3214 3215 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3216 u_int32_t key0, key1, key2, key3, key4; 3217 u_int32_t mac_hi, mac_lo; 3218 u_int16_t entry = 0; 3219 u_int32_t valid = 0; 3220 u_int32_t key_type; 3221 3222 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3223 3224 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3225 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3226 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3227 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3228 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3229 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3230 3231 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3232 3233 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3234 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3235 3236 if (mac_hi & AR_KEYTABLE_VALID) { 3237 valid = 1; 3238 } else { 3239 valid = 0; 3240 } 3241 3242 if ((mac_hi != 0) && (mac_lo != 0)) { 3243 mac_hi &= ~0x8000; 3244 mac_hi <<= 1; 3245 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3246 mac_lo <<= 1; 3247 } 3248 3249 ath_hal_printf(ah, 3250 "%03d " 3251 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3252 " %02d %02d " 3253 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3254 entry, 3255 (key0 << 24) >> 24, (key0 << 16) >> 24, 3256 (key0 << 8) >> 24, key0 >> 24, 3257 (key1 << 24) >> 24, (key1 << 16) >> 24, 3258 //(key1 << 8) >> 24, key1 >> 24, 3259 (key2 << 24) >> 24, (key2 << 16) >> 24, 3260 (key2 << 8) >> 24, key2 >> 24, 3261 (key3 << 24) >> 24, (key3 << 16) >> 24, 3262 //(key3 << 8) >> 24, key3 >> 24, 3263 (key4 << 24) >> 24, (key4 << 16) >> 24, 3264 (key4 << 8) >> 24, key4 >> 24, 3265 valid, key_type, 3266 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3267 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3268 } 3269 3270 return AH_TRUE; 3271 } 3272 3273 /* enable/disable smart antenna mode */ 3274 HAL_BOOL 3275 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3276 { 3277 struct ath_hal_9300 *ahp = AH9300(ah); 3278 3279 if (enable) { 3280 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3281 } else { 3282 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3283 } 3284 3285 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3286 * and swcom2 with 0 3287 * FIXME Ideally these registers need to be made read from caldata. 3288 * Until the calibration team gets them, keep them along with board 3289 * configuration. 3290 */ 3291 if (enable && AR_SREV_SCORPION(ah) && 3292 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3293 3294 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3295 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3296 } 3297 3298 ahp->ah_smartantenna_enable = enable; 3299 return 1; 3300 } 3301 3302 #ifdef ATH_TX99_DIAG 3303 #ifndef ATH_SUPPORT_HTC 3304 void 3305 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3306 u_int32_t txpower) 3307 { 3308 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3309 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3310 int32_t i; 3311 3312 /* The max power is limited to 63 */ 3313 if (txpower <= AR9300_MAX_RATE_POWER) { 3314 for (i = 0; i < ar9300_rate_size; i++) { 3315 p_pwr_array[i] = txpower; 3316 } 3317 } else { 3318 for (i = 0; i < ar9300_rate_size; i++) { 3319 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3320 } 3321 } 3322 3323 OS_REG_WRITE(ah, 0xa458, 0); 3324 3325 /* Write the OFDM power per rate set */ 3326 /* 6 (LSB), 9, 12, 18 (MSB) */ 3327 OS_REG_WRITE(ah, 0xa3c0, 3328 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3329 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3330 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3331 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3332 ); 3333 /* 24 (LSB), 36, 48, 54 (MSB) */ 3334 OS_REG_WRITE(ah, 0xa3c4, 3335 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3336 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3337 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3338 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3339 ); 3340 3341 /* Write the CCK power per rate set */ 3342 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3343 OS_REG_WRITE(ah, 0xa3c8, 3344 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3345 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3346 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3347 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3348 ); 3349 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3350 OS_REG_WRITE(ah, 0xa3cc, 3351 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3352 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3353 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3354 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3355 ); 3356 3357 /* Write the HT20 power per rate set */ 3358 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3359 OS_REG_WRITE(ah, 0xa3d0, 3360 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3361 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3362 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3363 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3364 ); 3365 3366 /* 6 (LSB), 7, 12, 13 (MSB) */ 3367 OS_REG_WRITE(ah, 0xa3d4, 3368 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3369 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3370 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3371 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3372 ); 3373 3374 /* 14 (LSB), 15, 20, 21 */ 3375 OS_REG_WRITE(ah, 0xa3e4, 3376 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3377 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3378 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3379 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3380 ); 3381 3382 /* Mixed HT20 and HT40 rates */ 3383 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3384 OS_REG_WRITE(ah, 0xa3e8, 3385 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3386 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3387 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3388 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3389 ); 3390 3391 /* Write the HT40 power per rate set */ 3392 /* correct PAR difference between HT40 and HT20/LEGACY */ 3393 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3394 OS_REG_WRITE(ah, 0xa3d8, 3395 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3396 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3397 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3398 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3399 ); 3400 3401 /* 6 (LSB), 7, 12, 13 (MSB) */ 3402 OS_REG_WRITE(ah, 0xa3dc, 3403 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3404 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3405 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3406 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3407 ); 3408 3409 /* 14 (LSB), 15, 20, 21 */ 3410 OS_REG_WRITE(ah, 0xa3ec, 3411 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3412 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3413 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3414 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3415 ); 3416 #undef PWR_MAS 3417 } 3418 3419 void 3420 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3421 { 3422 if (tx_chainmask == 0x5) { 3423 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3424 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3425 } 3426 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3427 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3428 3429 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3430 if (tx_chainmask == 0x5) { 3431 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3432 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3433 } 3434 } 3435 3436 void 3437 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3438 int chtype) 3439 { 3440 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3441 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3442 OS_REG_WRITE(ah, 0xa350, 3443 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3444 3445 /* 11G mode */ 3446 if (!chtype) { 3447 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3448 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3449 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3450 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3451 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3452 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3453 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3454 | (0x1 << 26) | (0x7 << 24)) 3455 & ~(0x1 << 22)); 3456 } else { 3457 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3458 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3459 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3460 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3461 | (0x1 << 26) | (0x7 << 24)) 3462 & ~(0x1 << 22)); 3463 } 3464 3465 /* chain zero */ 3466 if ((tx_chain_mask & 0x01) == 0x01) { 3467 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3468 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3469 | (0x1 << 31) | (0x5 << 15) 3470 | (0x3 << 9)) & ~(0x1 << 27) 3471 & ~(0x1 << 12)); 3472 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3473 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3474 | (0x1 << 12) | (0x1 << 10) 3475 | (0x1 << 9) | (0x1 << 8) 3476 | (0x1 << 7)) & ~(0x1 << 11)); 3477 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3478 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3479 | (0x1 << 29) | (0x1 << 25) 3480 | (0x1 << 23) | (0x1 << 19) 3481 | (0x1 << 10) | (0x1 << 9) 3482 | (0x1 << 8) | (0x1 << 3)) 3483 & ~(0x1 << 28)& ~(0x1 << 24) 3484 & ~(0x1 << 22)& ~(0x1 << 7)); 3485 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3486 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3487 | (0x1 << 23))& ~(0x1 << 21)); 3488 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3489 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3490 | (0x1 << 12) | (0x1 << 10) 3491 | (0x1 << 9) | (0x1 << 8) 3492 | (0x1 << 6) | (0x1 << 5) 3493 | (0x1 << 4) | (0x1 << 3) 3494 | (0x1 << 2)); 3495 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3496 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3497 } 3498 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3499 /* chain one */ 3500 if ((tx_chain_mask & 0x02) == 0x02 ) { 3501 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3502 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3503 | (0x1 << 31) | (0x5 << 15) 3504 | (0x3 << 9)) & ~(0x1 << 27) 3505 & ~(0x1 << 12)); 3506 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3507 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3508 | (0x1 << 12) | (0x1 << 10) 3509 | (0x1 << 9) | (0x1 << 8) 3510 | (0x1 << 7)) & ~(0x1 << 11)); 3511 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3512 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3513 | (0x1 << 29) | (0x1 << 25) 3514 | (0x1 << 23) | (0x1 << 19) 3515 | (0x1 << 10) | (0x1 << 9) 3516 | (0x1 << 8) | (0x1 << 3)) 3517 & ~(0x1 << 28)& ~(0x1 << 24) 3518 & ~(0x1 << 22)& ~(0x1 << 7)); 3519 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3520 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3521 | (0x1 << 23))& ~(0x1 << 21)); 3522 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3523 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3524 | (0x1 << 12) | (0x1 << 10) 3525 | (0x1 << 9) | (0x1 << 8) 3526 | (0x1 << 6) | (0x1 << 5) 3527 | (0x1 << 4) | (0x1 << 3) 3528 | (0x1 << 2)); 3529 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3530 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3531 } 3532 } 3533 if (AR_SREV_OSPREY(ah)) { 3534 /* chain two */ 3535 if ((tx_chain_mask & 0x04) == 0x04 ) { 3536 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3537 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3538 | (0x1 << 31) | (0x5 << 15) 3539 | (0x3 << 9)) & ~(0x1 << 27) 3540 & ~(0x1 << 12)); 3541 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3542 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3543 | (0x1 << 12) | (0x1 << 10) 3544 | (0x1 << 9) | (0x1 << 8) 3545 | (0x1 << 7)) & ~(0x1 << 11)); 3546 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3547 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3548 | (0x1 << 29) | (0x1 << 25) 3549 | (0x1 << 23) | (0x1 << 19) 3550 | (0x1 << 10) | (0x1 << 9) 3551 | (0x1 << 8) | (0x1 << 3)) 3552 & ~(0x1 << 28)& ~(0x1 << 24) 3553 & ~(0x1 << 22)& ~(0x1 << 7)); 3554 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3555 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3556 | (0x1 << 23))& ~(0x1 << 21)); 3557 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3558 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3559 | (0x1 << 12) | (0x1 << 10) 3560 | (0x1 << 9) | (0x1 << 8) 3561 | (0x1 << 6) | (0x1 << 5) 3562 | (0x1 << 4) | (0x1 << 3) 3563 | (0x1 << 2)); 3564 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3565 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3566 } 3567 } 3568 3569 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3570 OS_REG_WRITE(ah, 0xa288, 0x111); 3571 } else { 3572 /* chain zero */ 3573 if ((tx_chain_mask & 0x01) == 0x01) { 3574 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3575 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3576 | (0x1 << 31) | (0x1 << 27) 3577 | (0x3 << 23) | (0x1 << 19) 3578 | (0x1 << 15) | (0x3 << 9)) 3579 & ~(0x1 << 12)); 3580 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3581 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3582 | (0x1 << 12) | (0x1 << 10) 3583 | (0x1 << 9) | (0x1 << 8) 3584 | (0x1 << 7) | (0x1 << 3) 3585 | (0x1 << 2) | (0x1 << 1)) 3586 & ~(0x1 << 11)& ~(0x1 << 0)); 3587 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3588 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3589 | (0x1 << 29) | (0x1 << 25) 3590 | (0x1 << 23) | (0x1 << 19) 3591 | (0x1 << 10) | (0x1 << 9) 3592 | (0x1 << 8) | (0x1 << 3)) 3593 & ~(0x1 << 28)& ~(0x1 << 24) 3594 & ~(0x1 << 22)& ~(0x1 << 7)); 3595 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3596 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3597 | (0x1 << 23))& ~(0x1 << 21)); 3598 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3599 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3600 | (0x3 << 3) | (0x3 << 0)); 3601 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3602 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3603 | (0x3 << 29) | (0x3 << 26) 3604 | (0x2 << 23) | (0x2 << 20) 3605 | (0x2 << 17))& ~(0x1 << 14)); 3606 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3607 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3608 | (0x1 << 12) | (0x1 << 10) 3609 | (0x1 << 9) | (0x1 << 8) 3610 | (0x1 << 6) | (0x1 << 5) 3611 | (0x1 << 4) | (0x1 << 3) 3612 | (0x1 << 2)); 3613 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3614 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3615 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3616 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3617 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3619 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3620 | (0x1 << 26) | (0x7 << 24) 3621 | (0x3 << 22)); 3622 } else { 3623 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3624 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3625 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3626 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3627 | (0x1 << 26) | (0x7 << 24) 3628 | (0x3 << 22)); 3629 } 3630 3631 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3632 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3633 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3634 | (0x1 << 3) | (0x1 << 2) 3635 | (0x1 << 1)) & ~(0x1 << 0)); 3636 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3637 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3638 | (0x1 << 19) | (0x1 << 3)); 3639 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3640 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3641 } 3642 if (AR_SREV_OSPREY(ah)) { 3643 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3644 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3645 | (0x1 << 3) | (0x1 << 2) 3646 | (0x1 << 1)) & ~(0x1 << 0)); 3647 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3648 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3649 | (0x1 << 19) | (0x1 << 3)); 3650 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3651 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3652 } 3653 } 3654 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3655 /* chain one */ 3656 if ((tx_chain_mask & 0x02) == 0x02 ) { 3657 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3658 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3659 | (0x1 << 3) | (0x1 << 2) 3660 | (0x1 << 1)) & ~(0x1 << 0)); 3661 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3662 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3663 | (0x1 << 19) | (0x1 << 3)); 3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3665 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3666 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3667 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3668 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3669 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3670 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3671 | (0x1 << 26) | (0x7 << 24) 3672 | (0x3 << 22)); 3673 } else { 3674 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3675 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3676 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3677 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3678 | (0x1 << 26) | (0x7 << 24) 3679 | (0x3 << 22)); 3680 } 3681 3682 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3683 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3684 | (0x1 << 31) | (0x1 << 27) 3685 | (0x3 << 23) | (0x1 << 19) 3686 | (0x1 << 15) | (0x3 << 9)) 3687 & ~(0x1 << 12)); 3688 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3689 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3690 | (0x1 << 12) | (0x1 << 10) 3691 | (0x1 << 9) | (0x1 << 8) 3692 | (0x1 << 7) | (0x1 << 3) 3693 | (0x1 << 2) | (0x1 << 1)) 3694 & ~(0x1 << 11)& ~(0x1 << 0)); 3695 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3696 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3697 | (0x1 << 29) | (0x1 << 25) 3698 | (0x1 << 23) | (0x1 << 19) 3699 | (0x1 << 10) | (0x1 << 9) 3700 | (0x1 << 8) | (0x1 << 3)) 3701 & ~(0x1 << 28)& ~(0x1 << 24) 3702 & ~(0x1 << 22)& ~(0x1 << 7)); 3703 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3704 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3705 | (0x1 << 23))& ~(0x1 << 21)); 3706 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3707 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3708 | (0x3 << 3) | (0x3 << 0)); 3709 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3710 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3711 | (0x3 << 29) | (0x3 << 26) 3712 | (0x2 << 23) | (0x2 << 20) 3713 | (0x2 << 17))& ~(0x1 << 14)); 3714 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3715 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3716 | (0x1 << 12) | (0x1 << 10) 3717 | (0x1 << 9) | (0x1 << 8) 3718 | (0x1 << 6) | (0x1 << 5) 3719 | (0x1 << 4) | (0x1 << 3) 3720 | (0x1 << 2)); 3721 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3722 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3723 3724 if (AR_SREV_OSPREY(ah)) { 3725 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3726 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3727 | (0x1 << 3) | (0x1 << 2) 3728 | (0x1 << 1)) & ~(0x1 << 0)); 3729 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3730 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3731 | (0x1 << 19) | (0x1 << 3)); 3732 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3733 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3734 } 3735 } 3736 } 3737 if (AR_SREV_OSPREY(ah)) { 3738 /* chain two */ 3739 if ((tx_chain_mask & 0x04) == 0x04 ) { 3740 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3741 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3742 | (0x1 << 3) | (0x1 << 2) 3743 | (0x1 << 1)) & ~(0x1 << 0)); 3744 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3745 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3746 | (0x1 << 19) | (0x1 << 3)); 3747 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3748 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3749 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3750 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3751 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3752 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3753 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3754 | (0x1 << 26) | (0x7 << 24) 3755 | (0x3 << 22)); 3756 } else { 3757 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3758 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3759 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3760 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3761 | (0x1 << 26) | (0x7 << 24) 3762 | (0x3 << 22)); 3763 } 3764 3765 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3766 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3767 | (0x1 << 3) | (0x1 << 2) 3768 | (0x1 << 1)) & ~(0x1 << 0)); 3769 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3770 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3771 | (0x1 << 19) | (0x1 << 3)); 3772 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3773 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3774 3775 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3776 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3777 | (0x1 << 31) | (0x1 << 27) 3778 | (0x3 << 23) | (0x1 << 19) 3779 | (0x1 << 15) | (0x3 << 9)) 3780 & ~(0x1 << 12)); 3781 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3782 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3783 | (0x1 << 12) | (0x1 << 10) 3784 | (0x1 << 9) | (0x1 << 8) 3785 | (0x1 << 7) | (0x1 << 3) 3786 | (0x1 << 2) | (0x1 << 1)) 3787 & ~(0x1 << 11)& ~(0x1 << 0)); 3788 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3789 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3790 | (0x1 << 29) | (0x1 << 25) 3791 | (0x1 << 23) | (0x1 << 19) 3792 | (0x1 << 10) | (0x1 << 9) 3793 | (0x1 << 8) | (0x1 << 3)) 3794 & ~(0x1 << 28)& ~(0x1 << 24) 3795 & ~(0x1 << 22)& ~(0x1 << 7)); 3796 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3797 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3798 | (0x1 << 23))& ~(0x1 << 21)); 3799 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3800 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3801 | (0x3 << 3) | (0x3 << 0)); 3802 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3803 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3804 | (0x3 << 29) | (0x3 << 26) 3805 | (0x2 << 23) | (0x2 << 20) 3806 | (0x2 << 17))& ~(0x1 << 14)); 3807 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3808 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3809 | (0x1 << 12) | (0x1 << 10) 3810 | (0x1 << 9) | (0x1 << 8) 3811 | (0x1 << 6) | (0x1 << 5) 3812 | (0x1 << 4) | (0x1 << 3) 3813 | (0x1 << 2)); 3814 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3815 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3816 } 3817 } 3818 3819 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3820 OS_REG_WRITE(ah, 0xa288, 0x222); 3821 } 3822 } 3823 3824 void 3825 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3826 { 3827 u_int32_t val; 3828 u_int32_t qnum = (u_int32_t)data; 3829 3830 /* Disable AGC to A2 */ 3831 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3832 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3833 3834 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3835 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3836 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3837 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3838 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3839 /* 200 ok for HT20, 400 ok for HT40 */ 3840 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3841 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3842 3843 /* set QCU modes to early termination */ 3844 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3845 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3846 } 3847 3848 void 3849 ar9300_tx99_stop(struct ath_hal *ah) 3850 { 3851 /* this should follow the setting of start */ 3852 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3853 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3854 } 3855 #endif /* ATH_TX99_DIAG */ 3856 #endif /* ATH_SUPPORT_HTC */ 3857 3858 HAL_BOOL 3859 ar9300Get3StreamSignature(struct ath_hal *ah) 3860 { 3861 return AH_FALSE; 3862 } 3863 3864 HAL_BOOL 3865 ar9300ForceVCS(struct ath_hal *ah) 3866 { 3867 return AH_FALSE; 3868 } 3869 3870 HAL_BOOL 3871 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3872 { 3873 return AH_FALSE; 3874 } 3875 3876 static u_int32_t 3877 ar9300_read_loc_timer(struct ath_hal *ah) 3878 { 3879 3880 return OS_REG_READ(ah, AR_LOC_TIMER_REG); 3881 } 3882 3883 HAL_BOOL 3884 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3885 { 3886 struct ath_hal_9300 *ahp = AH9300(ah); 3887 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3888 u_int8_t *ctl_index; 3889 u_int32_t offset = 0; 3890 3891 if (!ctl_array) 3892 return AH_FALSE; 3893 3894 /* copy 2G ctl freqbin and power data */ 3895 ctl_index = p_eep_data->ctl_index_2g; 3896 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3897 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3898 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3899 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3900 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3901 3902 3903 /* copy 2G ctl freqbin and power data */ 3904 ctl_index = p_eep_data->ctl_index_5g; 3905 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3906 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3907 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3908 3909 return AH_FALSE; 3910 } 3911 3912 void 3913 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3914 { 3915 struct ath_hal_9300 *ahp = AH9300(ah); 3916 3917 /* optional txchainmask should be subset of primary txchainmask */ 3918 if ((mask & ahp->ah_tx_chainmask) != mask) { 3919 ahp->ah_tx_chainmaskopt = 0; 3920 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3921 return; 3922 } 3923 3924 ahp->ah_tx_chainmaskopt = mask; 3925 } 3926