1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 #include "ar9300/ar9300desc.h" 30 31 static u_int32_t ar9300_read_loc_timer(struct ath_hal *ah); 32 33 void 34 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 35 { 36 struct ath_hal_9300 *ahp = AH9300(ah); 37 *hangs = 0; 38 39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 40 *hangs |= HAL_RIFS_BB_HANG_WAR; 41 } 42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 43 *hangs |= HAL_DFS_BB_HANG_WAR; 44 } 45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 46 == HAL_OK) 47 { 48 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 49 } 50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 51 *hangs |= HAL_MAC_HANG_WAR; 52 } 53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 54 == HAL_OK) 55 { 56 *hangs |= HAL_PHYRESTART_CLR_WAR; 57 } 58 59 ahp->ah_hang_wars = *hangs; 60 } 61 62 /* 63 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 64 * HT20, HT40, fast-clock, turbo mode, etc. 65 */ 66 static u_int 67 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 68 { 69 #if 0 70 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 71 72 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 73 return (ath_hal_mac_usec(ah, clks) / 2); 74 } else { 75 return (ath_hal_mac_usec(ah, clks)); 76 } 77 #endif 78 return (ath_hal_mac_usec(ah, clks)); 79 } 80 81 u_int 82 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 83 { 84 #if 0 85 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 86 87 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 88 return (ath_hal_mac_clks(ah, usecs) * 2); 89 } else { 90 return (ath_hal_mac_clks(ah, usecs)); 91 } 92 #endif 93 return (ath_hal_mac_clks(ah, usecs)); 94 } 95 96 void 97 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 98 { 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 101 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 102 } 103 104 HAL_BOOL 105 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 106 { 107 struct ath_hal_9300 *ahp = AH9300(ah); 108 109 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 110 return AH_TRUE; 111 } 112 113 void 114 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 115 { 116 struct ath_hal_9300 *ahp = AH9300(ah); 117 118 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 119 } 120 121 HAL_BOOL 122 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 123 { 124 struct ath_hal_9300 *ahp = AH9300(ah); 125 126 /* save it since it must be rewritten on reset */ 127 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 128 129 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 130 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 131 return AH_TRUE; 132 } 133 134 /* 135 * Attempt to change the cards operating regulatory domain to the given value 136 * Returns: A_EINVAL for an unsupported regulatory domain. 137 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 138 */ 139 HAL_BOOL 140 ar9300_set_regulatory_domain(struct ath_hal *ah, 141 u_int16_t reg_domain, HAL_STATUS *status) 142 { 143 HAL_STATUS ecode; 144 145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 146 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 147 return AH_TRUE; 148 } 149 ecode = HAL_EIO; 150 151 #if 0 152 bad: 153 #endif 154 if (status) { 155 *status = ecode; 156 } 157 return AH_FALSE; 158 } 159 160 /* 161 * Return the wireless modes (a,b,g,t) supported by hardware. 162 * 163 * This value is what is actually supported by the hardware 164 * and is unaffected by regulatory/country code settings. 165 * 166 */ 167 u_int 168 ar9300_get_wireless_modes(struct ath_hal *ah) 169 { 170 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 171 } 172 173 /* 174 * Set the interrupt and GPIO values so the ISR can disable RF 175 * on a switch signal. Assumes GPIO port and interrupt polarity 176 * are set prior to call. 177 */ 178 void 179 ar9300_enable_rf_kill(struct ath_hal *ah) 180 { 181 /* TODO - can this really be above the hal on the GPIO interface for 182 * TODO - the client only? 183 */ 184 struct ath_hal_9300 *ahp = AH9300(ah); 185 186 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 187 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 188 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 190 AR_RFSILENT_FORCE); 191 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 192 } 193 else { 194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 195 AR_RFSILENT_FORCE); 196 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 197 } 198 } 199 else { 200 /* Connect rfsilent_bb_l to baseband */ 201 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 202 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 203 204 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 AR_GPIO_INPUT_MUX2_RFSILENT); 207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 208 (ahp->ah_gpio_select & 0x0f) << 4); 209 210 /* 211 * Configure the desired GPIO port for input and 212 * enable baseband rf silence 213 */ 214 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 215 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 216 } 217 218 /* 219 * If radio disable switch connection to GPIO bit x is enabled 220 * program GPIO interrupt. 221 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 222 * verified that it is a later version of eeprom, it has a place for 223 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 224 * connection is present. 225 */ 226 /* 227 * RFKill uses polling not interrupt, 228 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 229 */ 230 if (ath_hal_hasrfkill_int(ah)) { 231 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 232 /* switch already closed, set to interrupt upon open */ 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 234 } else { 235 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 236 } 237 } 238 } 239 240 /* 241 * Change the LED blinking pattern to correspond to the connectivity 242 */ 243 void 244 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 245 { 246 static const u_int32_t ledbits[8] = { 247 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 250 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 251 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 252 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 253 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 254 AR_CFG_LED_ASSOC_NONE, 255 }; 256 257 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 258 } 259 260 /* 261 * Sets the Power LED on the cardbus without affecting the Network LED. 262 */ 263 void 264 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 265 { 266 u_int32_t val; 267 268 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 269 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 270 } 271 272 /* 273 * Sets the Network LED on the cardbus without affecting the Power LED. 274 */ 275 void 276 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 277 { 278 u_int32_t val; 279 280 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 281 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 282 } 283 284 /* 285 * Change association related fields programmed into the hardware. 286 * Writing a valid BSSID to the hardware effectively enables the hardware 287 * to synchronize its TSF to the correct beacons and receive frames coming 288 * from that BSSID. It is called by the SME JOIN operation. 289 */ 290 void 291 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 292 u_int16_t assoc_id) 293 { 294 struct ath_hal_9300 *ahp = AH9300(ah); 295 296 /* save bssid and assoc_id for restore on reset */ 297 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 298 ahp->ah_assoc_id = assoc_id; 299 300 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 301 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 302 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 303 } 304 305 /* 306 * Get the current hardware tsf for stamlme 307 */ 308 u_int64_t 309 ar9300_get_tsf64(struct ath_hal *ah) 310 { 311 u_int64_t tsf; 312 313 /* XXX sync multi-word read? */ 314 tsf = OS_REG_READ(ah, AR_TSF_U32); 315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 316 return tsf; 317 } 318 319 void 320 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 321 { 322 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 323 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 324 } 325 326 /* 327 * Get the current hardware tsf for stamlme 328 */ 329 u_int32_t 330 ar9300_get_tsf32(struct ath_hal *ah) 331 { 332 return OS_REG_READ(ah, AR_TSF_L32); 333 } 334 335 u_int32_t 336 ar9300_get_tsf2_32(struct ath_hal *ah) 337 { 338 return OS_REG_READ(ah, AR_TSF2_L32); 339 } 340 341 /* 342 * Reset the current hardware tsf for stamlme. 343 */ 344 void 345 ar9300_reset_tsf(struct ath_hal *ah) 346 { 347 int count; 348 349 count = 0; 350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 351 count++; 352 if (count > 10) { 353 HALDEBUG(ah, HAL_DEBUG_RESET, 354 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 355 break; 356 } 357 OS_DELAY(10); 358 } 359 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 360 } 361 362 /* 363 * Set or clear hardware basic rate bit 364 * Set hardware basic rate set if basic rate is found 365 * and basic rate is equal or less than 2Mbps 366 */ 367 void 368 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 369 { 370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 371 u_int32_t reg; 372 u_int8_t xset; 373 int i; 374 375 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 376 return; 377 } 378 xset = 0; 379 for (i = 0; i < rs->rs_count; i++) { 380 u_int8_t rset = rs->rs_rates[i]; 381 /* Basic rate defined? */ 382 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 383 xset = rset; 384 } 385 } 386 /* 387 * Set the h/w bit to reflect whether or not the basic 388 * rate is found to be equal or less than 2Mbps. 389 */ 390 reg = OS_REG_READ(ah, AR_STA_ID1); 391 if (xset && xset / 2 <= 2) { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 393 } else { 394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 395 } 396 } 397 398 /* 399 * Grab a semi-random value from hardware registers - may not 400 * change often 401 */ 402 u_int32_t 403 ar9300_get_random_seed(struct ath_hal *ah) 404 { 405 u_int32_t nf; 406 407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 408 if (nf & 0x100) { 409 nf = 0 - ((nf ^ 0x1ff) + 1); 410 } 411 return (OS_REG_READ(ah, AR_TSF_U32) ^ 412 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 413 } 414 415 /* 416 * Detect if our card is present 417 */ 418 HAL_BOOL 419 ar9300_detect_card_present(struct ath_hal *ah) 420 { 421 u_int16_t mac_version, mac_rev; 422 u_int32_t v; 423 424 /* 425 * Read the Silicon Revision register and compare that 426 * to what we read at attach time. If the same, we say 427 * a card/device is present. 428 */ 429 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 430 if (v == 0xFF) { 431 /* new SREV format */ 432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 433 /* 434 * Include 6-bit Chip Type (masked to 0) to differentiate 435 * from pre-Sowl versions 436 */ 437 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 438 mac_rev = MS(v, AR_SREV_REVISION2); 439 } else { 440 mac_version = MS(v, AR_SREV_VERSION); 441 mac_rev = v & AR_SREV_REVISION; 442 } 443 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 444 AH_PRIVATE(ah)->ah_macRev == mac_rev); 445 } 446 447 /* 448 * Update MIB Counters 449 */ 450 void 451 ar9300_update_mib_mac_stats(struct ath_hal *ah) 452 { 453 struct ath_hal_9300 *ahp = AH9300(ah); 454 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 455 456 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 457 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 458 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 459 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 460 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 461 } 462 463 void 464 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 465 { 466 struct ath_hal_9300 *ahp = AH9300(ah); 467 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 468 469 stats->ackrcv_bad = istats->ackrcv_bad; 470 stats->rts_bad = istats->rts_bad; 471 stats->fcs_bad = istats->fcs_bad; 472 stats->rts_good = istats->rts_good; 473 stats->beacons = istats->beacons; 474 } 475 476 /* 477 * Detect if the HW supports spreading a CCK signal on channel 14 478 */ 479 HAL_BOOL 480 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 481 { 482 return AH_TRUE; 483 } 484 485 /* 486 * Get the rssi of frame curently being received. 487 */ 488 u_int32_t 489 ar9300_get_cur_rssi(struct ath_hal *ah) 490 { 491 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 492 /* get combined RSSI */ 493 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 494 } 495 496 #if ATH_GEN_RANDOMNESS 497 /* 498 * Get the rssi value from BB on ctl chain0. 499 */ 500 u_int32_t 501 ar9300_get_rssi_chain0(struct ath_hal *ah) 502 { 503 /* get ctl chain0 RSSI */ 504 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 505 } 506 #endif 507 508 u_int 509 ar9300_get_def_antenna(struct ath_hal *ah) 510 { 511 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 512 } 513 514 /* Setup coverage class */ 515 void 516 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 517 { 518 } 519 520 void 521 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 522 { 523 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 524 } 525 526 HAL_BOOL 527 ar9300_set_antenna_switch(struct ath_hal *ah, 528 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 529 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 530 { 531 struct ath_hal_9300 *ahp = AH9300(ah); 532 533 /* 534 * Owl does not support diversity or changing antennas. 535 * 536 * Instead this API and function are defined differently for AR9300. 537 * To support Tablet PC's, this interface allows the system 538 * to dramatically reduce the TX power on a particular chain. 539 * 540 * Based on the value of (redefined) diversity_control, the 541 * reset code will decrease power on chain 0 or chain 1/2. 542 * 543 * Based on the value of bit 0 of antenna_switch_swap, 544 * the mapping between OID call and chain is defined as: 545 * 0: map A -> 0, B -> 1; 546 * 1: map A -> 1, B -> 0; 547 * 548 * NOTE: 549 * The devices that use this OID should use a tx_chain_mask and 550 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 551 * used in order to ensure an active transmit antenna. This 552 * API will allow the host to turn off the only transmitting 553 * antenna to ensure the antenna closest to the user's body is 554 * powered-down. 555 */ 556 /* 557 * Set antenna control for use during reset sequence by 558 * ar9300_decrease_chain_power() 559 */ 560 ahp->ah_diversity_control = settings; 561 562 return AH_TRUE; 563 } 564 565 HAL_BOOL 566 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 567 { 568 return AH_TRUE; 569 } 570 571 HAL_BOOL 572 ar9300_set_slot_time(struct ath_hal *ah, u_int us) 573 { 574 struct ath_hal_9300 *ahp = AH9300(ah); 575 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 576 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 577 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 578 return AH_FALSE; 579 } else { 580 /* convert to system clocks */ 581 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 582 ahp->ah_slot_time = us; 583 return AH_TRUE; 584 } 585 } 586 587 HAL_BOOL 588 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 589 { 590 struct ath_hal_9300 *ahp = AH9300(ah); 591 592 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 593 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 594 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 595 return AH_FALSE; 596 } else { 597 /* convert to system clocks */ 598 OS_REG_RMW_FIELD(ah, 599 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 600 ahp->ah_ack_timeout = us; 601 return AH_TRUE; 602 } 603 } 604 605 u_int 606 ar9300_get_ack_timeout(struct ath_hal *ah) 607 { 608 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 609 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 610 } 611 612 HAL_STATUS 613 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 614 u_int32_t next_start, HAL_QUIET_FLAG flag) 615 { 616 #define TU_TO_USEC(_tu) ((_tu) << 10) 617 HAL_STATUS status = HAL_EIO; 618 u_int32_t tsf = 0, j, next_start_us = 0; 619 if (flag & HAL_QUIET_ENABLE) { 620 for (j = 0; j < 2; j++) { 621 next_start_us = TU_TO_USEC(next_start); 622 tsf = OS_REG_READ(ah, AR_TSF_L32); 623 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 624 next_start_us += tsf; 625 } 626 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 627 next_start_us += 628 ah->ah_config.ah_sw_beacon_response_time; 629 } 630 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 631 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 632 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 633 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 634 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 635 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 636 status = HAL_OK; 637 break; 638 } 639 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 640 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 641 /* TSF shouldn't count twice or reg access is taking forever */ 642 HALASSERT(j < 1); 643 } 644 } else { 645 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 646 status = HAL_OK; 647 } 648 649 return status; 650 #undef TU_TO_USEC 651 } 652 653 //#ifdef ATH_SUPPORT_DFS 654 void 655 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 656 { 657 uint32_t reg1, reg2; 658 659 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 660 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 661 AH9300(ah)->ah_cac_quiet_enabled = enable; 662 663 if (enable) { 664 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 665 reg1 | AR_PCU_FORCE_QUIET_COLL); 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 667 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 668 } else { 669 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 670 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 671 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 672 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 673 } 674 } 675 //#endif /* ATH_SUPPORT_DFS */ 676 677 void 678 ar9300_set_pcu_config(struct ath_hal *ah) 679 { 680 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 681 } 682 683 HAL_STATUS 684 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 685 u_int32_t capability, u_int32_t *result) 686 { 687 struct ath_hal_9300 *ahp = AH9300(ah); 688 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 689 struct ar9300_ani_state *ani; 690 691 switch (type) { 692 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 693 switch (capability) { 694 case HAL_CIPHER_AES_CCM: 695 case HAL_CIPHER_AES_OCB: 696 case HAL_CIPHER_TKIP: 697 case HAL_CIPHER_WEP: 698 case HAL_CIPHER_MIC: 699 case HAL_CIPHER_CLR: 700 return HAL_OK; 701 default: 702 return HAL_ENOTSUPP; 703 } 704 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 705 switch (capability) { 706 case 0: /* hardware capability */ 707 return HAL_OK; 708 case 1: 709 return (ahp->ah_sta_id1_defaults & 710 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 711 default: 712 return HAL_ENOTSUPP; 713 } 714 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 715 switch (capability) { 716 case 0: /* hardware capability */ 717 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 718 case 1: /* current setting */ 719 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 720 HAL_ENXIO : HAL_OK; 721 default: 722 return HAL_ENOTSUPP; 723 } 724 case HAL_CAP_WME_TKIPMIC: 725 /* hardware can do TKIP MIC when WMM is turned on */ 726 return HAL_OK; 727 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 728 return HAL_OK; 729 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 730 switch (capability) { 731 case 0: /* hardware capability */ 732 return HAL_OK; 733 case 1: /* current setting */ 734 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 735 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 736 HAL_OK : HAL_ENXIO; 737 } 738 return HAL_EINVAL; 739 case HAL_CAP_TPC: 740 switch (capability) { 741 case 0: /* hardware capability */ 742 return HAL_OK; 743 case 1: 744 return ah->ah_config.ath_hal_desc_tpc ? 745 HAL_OK : HAL_ENXIO; 746 } 747 return HAL_OK; 748 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 749 return HAL_OK; 750 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 751 switch (capability) { 752 case 0: /* hardware capability */ 753 return HAL_OK; 754 case 1: 755 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 756 /* 757 * Owl and Merlin have problems in mcast key search. 758 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 759 * 26802 760 */ 761 return HAL_ENXIO; 762 } else { 763 return (ahp->ah_sta_id1_defaults & 764 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 765 } 766 } 767 return HAL_EINVAL; 768 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 769 switch (capability) { 770 case 0: /* hardware capability */ 771 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 772 case 1: 773 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 774 HAL_OK : HAL_ENXIO; 775 } 776 return HAL_EINVAL; 777 case HAL_CAP_RFSILENT: /* rfsilent support */ 778 if (capability == 3) { /* rfkill interrupt */ 779 /* 780 * XXX: Interrupt-based notification of RF Kill state 781 * changes not working yet. Report that this feature 782 * is not supported so that polling is used instead. 783 */ 784 return (HAL_ENOTSUPP); 785 } 786 return ath_hal_getcapability(ah, type, capability, result); 787 case HAL_CAP_4ADDR_AGGR: 788 return HAL_OK; 789 case HAL_CAP_BB_RIFS_HANG: 790 return HAL_ENOTSUPP; 791 case HAL_CAP_BB_DFS_HANG: 792 return HAL_ENOTSUPP; 793 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 794 /* Track chips that are known to have BB hangs related 795 * to rx_clear stuck low. 796 */ 797 return HAL_ENOTSUPP; 798 case HAL_CAP_MAC_HANG: 799 /* Track chips that are known to have MAC hangs. 800 */ 801 return HAL_OK; 802 case HAL_CAP_RIFS_RX_ENABLED: 803 /* Is RIFS RX currently enabled */ 804 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 805 #if 0 806 case HAL_CAP_ANT_CFG_2GHZ: 807 *result = p_cap->halNumAntCfg2Ghz; 808 return HAL_OK; 809 case HAL_CAP_ANT_CFG_5GHZ: 810 *result = p_cap->halNumAntCfg5Ghz; 811 return HAL_OK; 812 case HAL_CAP_RX_STBC: 813 *result = p_cap->hal_rx_stbc_support; 814 return HAL_OK; 815 case HAL_CAP_TX_STBC: 816 *result = p_cap->hal_tx_stbc_support; 817 return HAL_OK; 818 #endif 819 case HAL_CAP_LDPC: 820 *result = p_cap->halLDPCSupport; 821 return HAL_OK; 822 case HAL_CAP_DYNAMIC_SMPS: 823 return HAL_OK; 824 case HAL_CAP_DS: 825 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 826 (p_cap->halTxChainMask & 0x3) != 0x3 || 827 (p_cap->halRxChainMask & 0x3) != 0x3) ? 828 HAL_ENOTSUPP : HAL_OK; 829 case HAL_CAP_TS: 830 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 831 (p_cap->halTxChainMask & 0x7) != 0x7 || 832 (p_cap->halRxChainMask & 0x7) != 0x7) ? 833 HAL_ENOTSUPP : HAL_OK; 834 case HAL_CAP_OL_PWRCTRL: 835 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 836 HAL_OK : HAL_ENOTSUPP; 837 case HAL_CAP_CRDC: 838 #if ATH_SUPPORT_CRDC 839 return (AR_SREV_WASP(ah) && 840 ah->ah_config.ath_hal_crdc_enable) ? 841 HAL_OK : HAL_ENOTSUPP; 842 #else 843 return HAL_ENOTSUPP; 844 #endif 845 #if 0 846 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 850 *result = (u_int32_t)(-1); 851 return HAL_OK; 852 #endif 853 case HAL_CAP_BB_PANIC_WATCHDOG: 854 return HAL_OK; 855 case HAL_CAP_PHYRESTART_CLR_WAR: 856 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 857 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 858 { 859 return HAL_OK; 860 } 861 else 862 { 863 return HAL_ENOTSUPP; 864 } 865 case HAL_CAP_ENTERPRISE_MODE: 866 *result = ahp->ah_enterprise_mode >> 16; 867 /* 868 * WAR for EV 77658 - Add delimiters to first sub-frame when using 869 * RTS/CTS with aggregation and non-enterprise Osprey. 870 * 871 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 872 */ 873 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 874 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 875 AR_SREV_WASP_10(ah))) { 876 *result |= AH_ENT_RTSCTS_DELIM_WAR; 877 } 878 return HAL_OK; 879 case HAL_CAP_LDPCWAR: 880 /* WAR for RIFS+LDPC issue is required for all chips currently 881 * supported by ar9300 HAL. 882 */ 883 return HAL_OK; 884 case HAL_CAP_ENABLE_APM: 885 *result = p_cap->halApmEnable; 886 return HAL_OK; 887 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 888 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 889 case HAL_CAP_PCIE_LCR_OFFSET: 890 *result = p_cap->hal_pcie_lcr_offset; 891 return HAL_OK; 892 case HAL_CAP_SMARTANTENNA: 893 /* FIXME A request is pending with h/w team to add feature bit in 894 * caldata to detect if board has smart antenna or not, once added 895 * we need to fix his piece of code to read and return value without 896 * any compile flags 897 */ 898 #if UMAC_SUPPORT_SMARTANTENNA 899 /* enable smart antenna for Peacock, Wasp and scorpion 900 for future chips need to modify */ 901 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 902 return HAL_OK; 903 } else { 904 return HAL_ENOTSUPP; 905 } 906 #else 907 return HAL_ENOTSUPP; 908 #endif 909 910 #ifdef ATH_TRAFFIC_FAST_RECOVER 911 case HAL_CAP_TRAFFIC_FAST_RECOVER: 912 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 913 return HAL_OK; 914 } else { 915 return HAL_ENOTSUPP; 916 } 917 #endif 918 919 /* FreeBSD ANI */ 920 case HAL_CAP_INTMIT: /* interference mitigation */ 921 switch (capability) { 922 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 923 return HAL_OK; 924 case HAL_CAP_INTMIT_ENABLE: 925 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 926 HAL_OK : HAL_ENXIO; 927 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 928 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 929 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 930 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 931 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 932 ani = ar9300_ani_get_current_state(ah); 933 if (ani == AH_NULL) 934 return HAL_ENXIO; 935 switch (capability) { 936 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 937 case 2: *result = ani->ofdm_noise_immunity_level; break; 938 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 939 // case 4: *result = ani->cck_weak_sig_threshold; break; 940 case 5: *result = ani->firstep_level; break; 941 case 6: *result = ani->spur_immunity_level; break; 942 } 943 return HAL_OK; 944 } 945 return HAL_EINVAL; 946 case HAL_CAP_ENFORCE_TXOP: 947 if (capability == 0) 948 return (HAL_OK); 949 if (capability != 1) 950 return (HAL_ENOTSUPP); 951 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 952 return (HAL_OK); 953 case HAL_CAP_TOA_LOCATIONING: 954 if (capability == 0) 955 return HAL_OK; 956 if (capability == 2) { 957 *result = ar9300_read_loc_timer(ah); 958 return (HAL_OK); 959 } 960 return HAL_ENOTSUPP; 961 default: 962 return ath_hal_getcapability(ah, type, capability, result); 963 } 964 } 965 966 HAL_BOOL 967 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 968 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 969 { 970 struct ath_hal_9300 *ahp = AH9300(ah); 971 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 972 u_int32_t v; 973 974 switch (type) { 975 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 976 if (! p_cap->halTkipMicTxRxKeySupport) 977 return AH_FALSE; 978 979 if (setting) 980 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 981 else 982 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 983 984 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 985 return AH_TRUE; 986 987 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 988 if (setting) { 989 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 990 } else { 991 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 992 } 993 return AH_TRUE; 994 case HAL_CAP_DIVERSITY: 995 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 996 if (setting) { 997 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 998 } else { 999 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 1000 } 1001 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 1002 return AH_TRUE; 1003 case HAL_CAP_DIAG: /* hardware diagnostic support */ 1004 /* 1005 * NB: could split this up into virtual capabilities, 1006 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 1007 * seems worth the additional complexity. 1008 */ 1009 #ifdef AH_DEBUG 1010 AH_PRIVATE(ah)->ah_diagreg = setting; 1011 #else 1012 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 1013 #endif 1014 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 1015 return AH_TRUE; 1016 case HAL_CAP_TPC: 1017 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1018 return AH_TRUE; 1019 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1020 if (setting) { 1021 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1022 } else { 1023 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1024 } 1025 return AH_TRUE; 1026 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1027 if (p_cap->halTsfAddSupport) { 1028 if (setting) { 1029 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1030 } else { 1031 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1032 } 1033 return AH_TRUE; 1034 } 1035 return AH_FALSE; 1036 1037 /* FreeBSD interrupt mitigation / ANI */ 1038 case HAL_CAP_INTMIT: { /* interference mitigation */ 1039 /* This maps the public ANI commands to the internal ANI commands */ 1040 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1041 static const HAL_ANI_CMD cmds[] = { 1042 HAL_ANI_PRESENT, 1043 HAL_ANI_MODE, 1044 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1045 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1046 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1047 HAL_ANI_FIRSTEP_LEVEL, 1048 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1049 }; 1050 #define N(a) (sizeof(a) / sizeof(a[0])) 1051 return capability < N(cmds) ? 1052 ar9300_ani_control(ah, cmds[capability], setting) : 1053 AH_FALSE; 1054 #undef N 1055 } 1056 1057 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1058 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1059 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1060 return AH_TRUE; 1061 1062 case HAL_CAP_ENFORCE_TXOP: 1063 if (capability != 1) 1064 return AH_FALSE; 1065 if (setting) { 1066 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 1067 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1068 } else { 1069 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 1070 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1071 } 1072 return AH_TRUE; 1073 1074 case HAL_CAP_TOA_LOCATIONING: 1075 if (capability == 0) 1076 return AH_TRUE; 1077 if (capability == 1) { 1078 ar9300_update_loc_ctl_reg(ah, setting); 1079 return AH_TRUE; 1080 } 1081 return AH_FALSE; 1082 /* fall thru... */ 1083 default: 1084 return ath_hal_setcapability(ah, type, capability, setting, status); 1085 } 1086 } 1087 1088 #ifdef AH_DEBUG 1089 static void 1090 ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1091 { 1092 u_int32_t i = 0; 1093 1094 /* Read 0x80d0 to trigger pcie analyzer */ 1095 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1096 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1097 1098 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1099 struct ath_hal_9300 *ahp = AH9300(ah); 1100 u_int32_t tf, rf, rc, cc; 1101 1102 tf = OS_REG_READ(ah, AR_TFCNT); 1103 rf = OS_REG_READ(ah, AR_RFCNT); 1104 rc = OS_REG_READ(ah, AR_RCCNT); 1105 cc = OS_REG_READ(ah, AR_CCCNT); 1106 1107 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1108 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1109 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1110 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1111 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1112 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1113 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1114 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1115 1116 ahp->last_tf = tf; 1117 ahp->last_rf = rf; 1118 ahp->last_rc = rc; 1119 ahp->last_cc = cc; 1120 1121 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1122 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1123 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1124 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1125 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1126 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1127 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1128 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1130 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1131 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1132 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1133 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1134 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1135 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1136 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1137 } 1138 1139 if (args & HAL_DIAG_PRINT_REG_ALL) { 1140 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1141 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1142 i, OS_REG_READ(ah, i)); 1143 } 1144 1145 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1146 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1147 i, OS_REG_READ(ah, i)); 1148 } 1149 1150 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1151 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1152 1153 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1154 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1155 1156 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1157 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1158 i, OS_REG_READ(ah, i)); 1159 } 1160 1161 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1162 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1163 i, OS_REG_READ(ah, i)); 1164 } 1165 1166 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1167 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1168 i, OS_REG_READ(ah, i)); 1169 } 1170 1171 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1172 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1173 i, OS_REG_READ(ah, i)); 1174 } 1175 1176 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1177 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1178 i, OS_REG_READ(ah, i)); 1179 } 1180 1181 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1182 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1183 i, OS_REG_READ(ah, i)); 1184 } 1185 1186 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1187 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1188 i, OS_REG_READ(ah, i)); 1189 } 1190 1191 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1192 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1193 i, OS_REG_READ(ah, i)); 1194 } 1195 1196 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1197 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1198 i, OS_REG_READ(ah, i)); 1199 } 1200 1201 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1202 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1203 i, OS_REG_READ(ah, i)); 1204 } 1205 1206 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1207 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1208 i, OS_REG_READ(ah, i)); 1209 } 1210 } 1211 } 1212 #endif 1213 1214 HAL_BOOL 1215 ar9300_get_diag_state(struct ath_hal *ah, int request, 1216 const void *args, u_int32_t argsize, 1217 void **result, u_int32_t *resultsize) 1218 { 1219 struct ath_hal_9300 *ahp = AH9300(ah); 1220 struct ar9300_ani_state *ani; 1221 1222 (void) ahp; 1223 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1224 return AH_TRUE; 1225 } 1226 switch (request) { 1227 #ifdef AH_PRIVATE_DIAG 1228 case HAL_DIAG_EEPROM: 1229 *result = &ahp->ah_eeprom; 1230 *resultsize = sizeof(ar9300_eeprom_t); 1231 return AH_TRUE; 1232 1233 #if 0 /* XXX - TODO */ 1234 case HAL_DIAG_EEPROM_EXP_11A: 1235 case HAL_DIAG_EEPROM_EXP_11B: 1236 case HAL_DIAG_EEPROM_EXP_11G: 1237 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1238 *result = pe->p_channels; 1239 *resultsize = (*result == AH_NULL) ? 0 : 1240 roundup(sizeof(u_int16_t) * pe->num_channels, 1241 sizeof(u_int32_t)) + 1242 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1243 return AH_TRUE; 1244 #endif 1245 case HAL_DIAG_RFGAIN: 1246 *result = &ahp->ah_gain_values; 1247 *resultsize = sizeof(GAIN_VALUES); 1248 return AH_TRUE; 1249 case HAL_DIAG_RFGAIN_CURSTEP: 1250 *result = (void *) ahp->ah_gain_values.curr_step; 1251 *resultsize = (*result == AH_NULL) ? 1252 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1253 return AH_TRUE; 1254 #if 0 /* XXX - TODO */ 1255 case HAL_DIAG_PCDAC: 1256 *result = ahp->ah_pcdac_table; 1257 *resultsize = ahp->ah_pcdac_table_size; 1258 return AH_TRUE; 1259 #endif 1260 case HAL_DIAG_ANI_CURRENT: 1261 1262 ani = ar9300_ani_get_current_state(ah); 1263 if (ani == AH_NULL) 1264 return AH_FALSE; 1265 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1266 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1267 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1268 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1269 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1270 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1271 ahp->ext_ani_state.mrcCckOff = ani->mrc_cck_off; 1272 ahp->ext_ani_state.cckNoiseImmunityLevel = ani->cck_noise_immunity_level; 1273 1274 ahp->ext_ani_state.listenTime = ani->listen_time; 1275 1276 *result = &ahp->ext_ani_state; 1277 *resultsize = sizeof(ahp->ext_ani_state); 1278 #if 0 1279 *result = ar9300_ani_get_current_state(ah); 1280 *resultsize = (*result == AH_NULL) ? 1281 0 : sizeof(struct ar9300_ani_state); 1282 #endif 1283 return AH_TRUE; 1284 case HAL_DIAG_ANI_STATS: 1285 *result = ar9300_ani_get_current_stats(ah); 1286 *resultsize = (*result == AH_NULL) ? 1287 0 : sizeof(HAL_ANI_STATS); 1288 return AH_TRUE; 1289 case HAL_DIAG_ANI_CMD: 1290 if (argsize != 2*sizeof(u_int32_t)) { 1291 return AH_FALSE; 1292 } 1293 ar9300_ani_control( 1294 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1295 return AH_TRUE; 1296 #if 0 1297 case HAL_DIAG_TXCONT: 1298 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1299 return AH_TRUE; 1300 #endif /* 0 */ 1301 #endif /* AH_PRIVATE_DIAG */ 1302 case HAL_DIAG_CHANNELS: 1303 #if 0 1304 *result = &(ahp->ah_priv.ah_channels[0]); 1305 *resultsize = 1306 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1307 #endif 1308 return AH_TRUE; 1309 #ifdef AH_DEBUG 1310 case HAL_DIAG_PRINT_REG: 1311 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1312 return AH_TRUE; 1313 #endif 1314 default: 1315 break; 1316 } 1317 1318 return AH_FALSE; 1319 } 1320 1321 void 1322 ar9300_dma_reg_dump(struct ath_hal *ah) 1323 { 1324 #ifdef AH_DEBUG 1325 #define NUM_DMA_DEBUG_REGS 8 1326 #define NUM_QUEUES 10 1327 1328 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1329 int qcu_offset = 0, dcu_offset = 0; 1330 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1331 int i, j, k; 1332 int16_t nfarray[HAL_NUM_NF_READINGS]; 1333 #ifdef ATH_NF_PER_CHAN 1334 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1335 #endif /* ATH_NF_PER_CHAN */ 1336 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1337 1338 /* selecting DMA OBS 8 */ 1339 OS_REG_WRITE(ah, AR_MACMISC, 1340 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1341 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1342 1343 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1344 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1345 if (i % 4 == 0) { 1346 ath_hal_printf(ah, "\n"); 1347 } 1348 1349 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1350 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1351 } 1352 1353 ath_hal_printf(ah, "\n\n"); 1354 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1355 1356 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1357 if (i == 8) { 1358 /* only 8 QCU entries in val[0] */ 1359 qcu_offset = 0; 1360 qcu_base++; 1361 } 1362 1363 if (i == 6) { 1364 /* only 6 DCU entries in val[4] */ 1365 dcu_offset = 0; 1366 dcu_base++; 1367 } 1368 1369 ath_hal_printf(ah, 1370 "%2d %2x %1x %2x %2x\n", 1371 i, 1372 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1373 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1374 val[2] & (0x7 << (i * 3)) >> (i * 3), 1375 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1376 } 1377 1378 ath_hal_printf(ah, "\n"); 1379 ath_hal_printf(ah, 1380 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1381 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1382 ath_hal_printf(ah, 1383 "qcu_complete state: %2x dcu_complete state: %2x\n", 1384 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1385 ath_hal_printf(ah, 1386 "dcu_arb state: %2x dcu_fp state: %2x\n", 1387 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1388 ath_hal_printf(ah, 1389 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1390 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1391 ath_hal_printf(ah, 1392 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1393 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1394 ath_hal_printf(ah, 1395 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1396 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1397 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1398 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1399 1400 ar9300_upload_noise_floor(ah, 1, nfarray); 1401 ath_hal_printf(ah, "2G:\n"); 1402 ath_hal_printf(ah, "Min CCA Out:\n"); 1403 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1404 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1405 nfarray[0], nfarray[1], nfarray[2]); 1406 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1407 nfarray[3], nfarray[4], nfarray[5]); 1408 1409 ar9300_upload_noise_floor(ah, 0, nfarray); 1410 ath_hal_printf(ah, "5G:\n"); 1411 ath_hal_printf(ah, "Min CCA Out:\n"); 1412 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1413 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1414 nfarray[0], nfarray[1], nfarray[2]); 1415 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1416 nfarray[3], nfarray[4], nfarray[5]); 1417 1418 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1419 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1420 ((i < 3) ? "Control " : "Extension "), i%3); 1421 for (j = 0, k = h->base.curr_index; 1422 j < HAL_NF_CAL_HIST_LEN_FULL; 1423 j++, k++) { 1424 ath_hal_printf(ah, "Element %d: %d\n", 1425 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1426 } 1427 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1428 } 1429 1430 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1431 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1432 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1433 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1434 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1435 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1436 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1437 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1438 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1439 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1440 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1441 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1442 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1443 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1444 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1445 reg = OS_REG_READ(ah, AR_PHY_AGC); 1446 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1447 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1448 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1449 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1450 MS(reg, AR_PHY_AGC_COARSE_LOW), 1451 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1452 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1453 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1454 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1455 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1456 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1457 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1458 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1459 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1460 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1461 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1462 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1463 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1464 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1465 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1466 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1467 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1468 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1469 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1470 1471 1472 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1473 reg = OS_REG_READ(ah, 0xa360); 1474 reg &= ~0x00800000; 1475 OS_REG_WRITE(ah, 0xa360, reg); 1476 1477 /* Step 2a: Set register 0xa364 to 0x1000 */ 1478 reg = 0x1000; 1479 OS_REG_WRITE(ah, 0xa364, reg); 1480 1481 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1482 reg = OS_REG_READ(ah, 0x9c20); 1483 reg &= 0x0003ffff; 1484 ath_hal_printf(ah, 1485 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1486 __func__, reg); 1487 1488 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1489 reg = OS_REG_READ(ah, 0xa360); 1490 reg &= ~0x00800000; 1491 OS_REG_WRITE(ah, 0xa360, reg); 1492 1493 /* Step 2b: Set register 0xa364 to 0x1400 */ 1494 reg = 0x1400; 1495 OS_REG_WRITE(ah, 0xa364, reg); 1496 1497 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1498 reg = OS_REG_READ(ah, 0x9c20); 1499 reg &= 0x0003ffff; 1500 ath_hal_printf(ah, 1501 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1502 __func__, reg); 1503 1504 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1505 reg = OS_REG_READ(ah, 0xa360); 1506 reg &= ~0x00800000; 1507 OS_REG_WRITE(ah, 0xa360, reg); 1508 1509 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1510 reg = 0x3c00; 1511 OS_REG_WRITE(ah, 0xa364, reg); 1512 1513 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1514 reg = OS_REG_READ(ah, 0x9c20); 1515 reg &= 0x0003ffff; 1516 ath_hal_printf(ah, 1517 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1518 __func__, reg); 1519 1520 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1521 reg = OS_REG_READ(ah, 0xa360); 1522 reg &= ~0x001040000; 1523 OS_REG_WRITE(ah, 0xa360, reg); 1524 1525 /* Step 2d: Set register 0xa364 to 0x5005D */ 1526 reg = 0x5005D; 1527 OS_REG_WRITE(ah, 0xa364, reg); 1528 1529 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1530 reg = OS_REG_READ(ah, 0xa368); 1531 reg &= 0x0003ffff; 1532 ath_hal_printf(ah, 1533 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1534 __func__, reg); 1535 1536 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1537 reg = OS_REG_READ(ah, 0xa360); 1538 reg &= ~0x001040000; 1539 OS_REG_WRITE(ah, 0xa360, reg); 1540 1541 /* Step 2e: Set register 0xa364 to 0x7005D */ 1542 reg = 0x7005D; 1543 OS_REG_WRITE(ah, 0xa364, reg); 1544 1545 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1546 reg = OS_REG_READ(ah, 0xa368); 1547 reg &= 0x0003ffff; 1548 ath_hal_printf(ah, 1549 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1550 __func__, reg); 1551 1552 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1553 reg = OS_REG_READ(ah, 0xa360); 1554 reg &= ~0x001000000; 1555 reg |= 0x40000; 1556 OS_REG_WRITE(ah, 0xa360, reg); 1557 1558 /* Step 2f: Set register 0xa364 to 0x3005D */ 1559 reg = 0x3005D; 1560 OS_REG_WRITE(ah, 0xa364, reg); 1561 1562 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1563 reg = OS_REG_READ(ah, 0xa368); 1564 reg &= 0x0003ffff; 1565 ath_hal_printf(ah, 1566 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1567 __func__, reg); 1568 1569 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1570 reg = OS_REG_READ(ah, 0xa360); 1571 reg &= ~0x001000000; 1572 reg |= 0x40000; 1573 OS_REG_WRITE(ah, 0xa360, reg); 1574 1575 /* Step 2g: Set register 0xa364 to 0x6005D */ 1576 reg = 0x6005D; 1577 OS_REG_WRITE(ah, 0xa364, reg); 1578 1579 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1580 reg = OS_REG_READ(ah, 0xa368); 1581 reg &= 0x0003ffff; 1582 ath_hal_printf(ah, 1583 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1584 __func__, reg); 1585 #endif /* AH_DEBUG */ 1586 } 1587 1588 /* 1589 * Return the busy for rx_frame, rx_clear, and tx_frame 1590 */ 1591 u_int32_t 1592 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1593 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1594 { 1595 struct ath_hal_9300 *ahp = AH9300(ah); 1596 u_int32_t good = 1; 1597 1598 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1599 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1600 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1601 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1602 1603 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1604 /* 1605 * Cycle counter wrap (or initial call); it's not possible 1606 * to accurately calculate a value because the registers 1607 * right shift rather than wrap--so punt and return 0. 1608 */ 1609 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1610 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1611 good = 0; 1612 } else { 1613 u_int32_t cc_d = cc - ahp->ah_cycles; 1614 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1615 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1616 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1617 1618 if (cc_d != 0) { 1619 *rxc_pcnt = rc_d * 100 / cc_d; 1620 *rxf_pcnt = rf_d * 100 / cc_d; 1621 *txf_pcnt = tf_d * 100 / cc_d; 1622 } else { 1623 good = 0; 1624 } 1625 } 1626 1627 ahp->ah_cycles = cc; 1628 ahp->ah_rx_frame = rf; 1629 ahp->ah_rx_clear = rc; 1630 ahp->ah_tx_frame = tf; 1631 1632 return good; 1633 } 1634 1635 /* 1636 * Return approximation of extension channel busy over an time interval 1637 * 0% (clear) -> 100% (busy) 1638 * -1 for invalid estimate 1639 */ 1640 uint32_t 1641 ar9300_get_11n_ext_busy(struct ath_hal *ah) 1642 { 1643 /* 1644 * Overflow condition to check before multiplying to get % 1645 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1646 */ 1647 #define OVERFLOW_LIMIT 0x28F5C28 1648 #define ERROR_CODE -1 1649 1650 struct ath_hal_9300 *ahp = AH9300(ah); 1651 u_int32_t busy = 0; /* percentage */ 1652 int8_t busyper = 0; 1653 u_int32_t cycle_count, ctl_busy, ext_busy; 1654 1655 /* cycle_count will always be the first to wrap; therefore, read it last 1656 * This sequence of reads is not atomic, and MIB counter wrap 1657 * could happen during it ? 1658 */ 1659 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1660 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1661 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1662 1663 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1664 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1665 { 1666 /* 1667 * Cycle counter wrap (or initial call); it's not possible 1668 * to accurately calculate a value because the registers 1669 * right shift rather than wrap--so punt and return 0. 1670 */ 1671 busyper = ERROR_CODE; 1672 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1673 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1674 } else { 1675 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1676 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1677 1678 /* 1679 * Compute extension channel busy percentage 1680 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1681 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1682 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1683 * and shift necessitated by large ext_busy_delta. 1684 * Due to timing difference to read the registers and counter overflow, 1685 * it may still happen that cycle_delta >> 7 = 0. 1686 * 1687 */ 1688 if (cycle_delta) { 1689 if (ext_busy_delta > OVERFLOW_LIMIT) { 1690 if (cycle_delta >> 7) { 1691 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1692 } else { 1693 busyper = ERROR_CODE; 1694 } 1695 } else { 1696 busy = (ext_busy_delta * 100) / cycle_delta; 1697 } 1698 } else { 1699 busyper = ERROR_CODE; 1700 } 1701 1702 if (busy > 100) { 1703 busy = 100; 1704 } 1705 if ( busyper != ERROR_CODE ) { 1706 busyper = busy; 1707 } 1708 } 1709 1710 ahp->ah_cycle_count = cycle_count; 1711 ahp->ah_ctl_busy = ctl_busy; 1712 ahp->ah_ext_busy = ext_busy; 1713 1714 return busyper; 1715 #undef OVERFLOW_LIMIT 1716 #undef ERROR_CODE 1717 } 1718 1719 /* BB Panic Watchdog declarations */ 1720 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1721 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1722 1723 void 1724 ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1725 { 1726 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1727 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1728 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1729 u_int32_t val, idle_count; 1730 1731 if (idle_tmo_ms != 0) { 1732 /* enable IRQ, disable chip-reset for BB panic */ 1733 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1734 AR_PHY_BB_PANIC_CNTL2_MASK; 1735 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1736 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1737 /* bound limit to 10 secs */ 1738 if (idle_tmo_ms > 10000) { 1739 idle_tmo_ms = 10000; 1740 } 1741 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1742 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1743 } else { 1744 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1745 } 1746 /* 1747 * enable panic in non-IDLE mode, 1748 * disable in IDLE mode, 1749 * set idle time-out 1750 */ 1751 1752 // EV92527 : Enable IDLE mode panic 1753 1754 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1755 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1756 AR_PHY_BB_PANIC_IDLE_ENABLE | 1757 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1758 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1759 } else { 1760 /* disable IRQ, disable chip-reset for BB panic */ 1761 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1762 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1763 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1764 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1765 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1766 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1767 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1768 } 1769 1770 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1771 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1772 #undef HAL_BB_PANIC_IDLE_TIME_OUT 1773 } 1774 1775 1776 void 1777 ar9300_handle_bb_panic(struct ath_hal *ah) 1778 { 1779 u_int32_t status; 1780 /* 1781 * we want to avoid printing in ISR context so we save 1782 * panic watchdog status to be printed later in DPC context 1783 */ 1784 AH9300(ah)->ah_bb_panic_last_status = status = 1785 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1786 /* 1787 * panic watchdog timer should reset on status read 1788 * but to make sure we write 0 to the watchdog status bit 1789 */ 1790 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1791 } 1792 1793 int 1794 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1795 { 1796 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1797 1798 /* 1799 * For signature 04000539 do not print anything. 1800 * This is a very common occurence as a compromise between 1801 * BB Panic and AH_FALSE detects (EV71009). It indicates 1802 * radar hang, which can be cleared by reprogramming 1803 * radar related register and does not requre a chip reset 1804 */ 1805 1806 /* Suppress BB Status mesg following signature */ 1807 switch (bb_panic->status) { 1808 case 0x04000539: 1809 case 0x04008009: 1810 case 0x04000b09: 1811 case 0x1300000a: 1812 return -1; 1813 } 1814 1815 bb_panic->tsf = ar9300_get_tsf32(ah); 1816 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1817 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1818 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1819 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1820 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1821 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1822 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1823 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1824 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1825 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1826 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1827 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1828 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1829 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1830 &bb_panic->rxc_pcnt, 1831 &bb_panic->rxf_pcnt, 1832 &bb_panic->txf_pcnt); 1833 1834 if (ah->ah_config.ath_hal_show_bb_panic) { 1835 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1836 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1837 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1838 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1839 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1840 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1841 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1842 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1843 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1844 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1845 bb_panic->phy_gen_ctrl); 1846 if (bb_panic->cycles) { 1847 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1848 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1849 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1850 } 1851 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1852 } 1853 1854 return 0; //The returned data will be stored for athstats to retrieve it 1855 } 1856 1857 /* set the reason for HAL reset */ 1858 void 1859 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1860 { 1861 AH9300(ah)->ah_reset_reason = resetreason; 1862 } 1863 1864 /* 1865 * Configure 20/40 operation 1866 * 1867 * 20/40 = joint rx clear (control and extension) 1868 * 20 = rx clear (control) 1869 * 1870 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1871 * when changing from 20/40 => 20 only 1872 */ 1873 void 1874 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1875 { 1876 u_int32_t macmode; 1877 1878 /* Configure MAC for 20/40 operation */ 1879 if (mode == HAL_HT_MACMODE_2040 && 1880 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1881 macmode = AR_2040_JOINED_RX_CLEAR; 1882 } else { 1883 macmode = 0; 1884 } 1885 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1886 } 1887 1888 /* 1889 * Get Rx clear (control/extension channel) 1890 * 1891 * Returns active low (busy) for ctrl/ext channel 1892 * Owl 2.0 1893 */ 1894 HAL_HT_RXCLEAR 1895 ar9300_get_11n_rx_clear(struct ath_hal *ah) 1896 { 1897 HAL_HT_RXCLEAR rxclear = 0; 1898 u_int32_t val; 1899 1900 val = OS_REG_READ(ah, AR_DIAG_SW); 1901 1902 /* control channel */ 1903 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1904 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1905 } 1906 /* extension channel */ 1907 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1908 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1909 } 1910 return rxclear; 1911 } 1912 1913 /* 1914 * Set Rx clear (control/extension channel) 1915 * 1916 * Useful for forcing the channel to appear busy for 1917 * debugging/diagnostics 1918 * Owl 2.0 1919 */ 1920 void 1921 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1922 { 1923 /* control channel */ 1924 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1925 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1926 } else { 1927 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1928 } 1929 /* extension channel */ 1930 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1931 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1932 } else { 1933 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1934 } 1935 } 1936 1937 1938 /* 1939 * HAL support code for force ppm tracking workaround. 1940 */ 1941 1942 u_int32_t 1943 ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1944 { 1945 u_int32_t retval; 1946 u_int32_t off1; 1947 u_int32_t off2; 1948 1949 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1950 off1 = 0x2000; 1951 off2 = 0x1000; 1952 } else { 1953 off1 = 0x1000; 1954 off2 = 0x2000; 1955 } 1956 1957 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1958 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1959 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1960 1961 return retval; 1962 } 1963 1964 u_int32_t 1965 ar9300_ppm_force(struct ath_hal *ah) 1966 { 1967 u_int32_t data_fine; 1968 u_int32_t data4; 1969 //u_int32_t off1; 1970 //u_int32_t off2; 1971 HAL_BOOL signed_val = AH_FALSE; 1972 1973 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1974 // off1 = 0x2000; 1975 // off2 = 0x1000; 1976 // } else { 1977 // off1 = 0x1000; 1978 // off2 = 0x2000; 1979 // } 1980 data_fine = 1981 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1982 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1983 1984 /* 1985 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1986 * So check value from bit[10:0]. 1987 * Now get the abs val of the ppm value read in bit[0:11]. 1988 * After that do bound check on abs value. 1989 * if value is off limit, CAP the value and and restore signed bit. 1990 */ 1991 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1992 { 1993 /* get the positive value */ 1994 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1995 signed_val = AH_TRUE; 1996 } 1997 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1998 { 1999 HALDEBUG(ah, HAL_DEBUG_REGIO, 2000 "%s Correcting ppm out of range %x\n", 2001 __func__, (data_fine & 0x7ff)); 2002 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 2003 } 2004 /* 2005 * Restore signed value if changed above. 2006 * Use typecast to avoid compilation errors 2007 */ 2008 if (signed_val) { 2009 data_fine = (-(int32_t)data_fine) & 2010 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 2011 } 2012 2013 /* write value */ 2014 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 2015 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2016 OS_REG_WRITE(ah, AR_PHY_TIMING2, 2017 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 2018 2019 return data_fine; 2020 } 2021 2022 void 2023 ar9300_ppm_un_force(struct ath_hal *ah) 2024 { 2025 u_int32_t data4; 2026 2027 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 2028 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 2029 } 2030 2031 u_int32_t 2032 ar9300_ppm_arm_trigger(struct ath_hal *ah) 2033 { 2034 u_int32_t val; 2035 u_int32_t ret; 2036 2037 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2038 ret = OS_REG_READ(ah, AR_TSF_L32); 2039 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2040 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2041 2042 /* return low word of TSF at arm time */ 2043 return ret; 2044 } 2045 2046 int 2047 ar9300_ppm_get_trigger(struct ath_hal *ah) 2048 { 2049 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2050 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2051 { 2052 /* has not triggered yet, return AH_FALSE */ 2053 return 0; 2054 } 2055 2056 /* else triggered, return AH_TRUE */ 2057 return 1; 2058 } 2059 2060 void 2061 ar9300_mark_phy_inactive(struct ath_hal *ah) 2062 { 2063 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2064 } 2065 2066 /* DEBUG */ 2067 u_int32_t 2068 ar9300_ppm_get_force_state(struct ath_hal *ah) 2069 { 2070 return 2071 OS_REG_READ(ah, AR_PHY_TIMING2) & 2072 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2073 } 2074 2075 /* 2076 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2077 */ 2078 HAL_BOOL 2079 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2080 { 2081 /* 2082 * XXX FreeBSD todo: reimplement this 2083 */ 2084 #if 0 2085 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2086 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2087 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2088 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2089 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2090 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2091 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2092 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2093 #endif 2094 return AH_FALSE; 2095 } 2096 2097 void 2098 ar9300_clear_mib_counters(struct ath_hal *ah) 2099 { 2100 u_int32_t reg_val; 2101 2102 reg_val = OS_REG_READ(ah, AR_MIBC); 2103 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2104 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2105 } 2106 2107 2108 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2109 HAL_BOOL 2110 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2111 { 2112 struct ath_hal_9300 *ahp = AH9300(ah); 2113 HAL_CHANNEL_INTERNAL *ichan = 2114 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2115 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2116 u_int32_t tmp = 0; 2117 2118 if (enable) { 2119 if (ahp->ah_rifs_enabled == AH_TRUE) { 2120 return AH_TRUE; 2121 } 2122 2123 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2124 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2125 ahp->ah_rifs_reg[1]); 2126 2127 ahp->ah_rifs_enabled = AH_TRUE; 2128 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2129 } else { 2130 if (ahp->ah_rifs_enabled == AH_TRUE) { 2131 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2132 AR_PHY_SEARCH_START_DELAY); 2133 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2134 } 2135 /* Change rifs init delay to 0 */ 2136 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2137 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2138 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2139 if (is_chan_2g) { 2140 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2141 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2142 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2143 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2144 } 2145 } else { 2146 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2147 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2148 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2149 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2150 } 2151 } 2152 2153 ahp->ah_rifs_enabled = AH_FALSE; 2154 } 2155 return AH_TRUE; 2156 2157 } /* ar9300_set_rifs_delay () */ 2158 2159 /* Set the current RIFS Rx setting */ 2160 HAL_BOOL 2161 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2162 { 2163 /* Non-Owl 11n chips */ 2164 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2165 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2166 return ar9300_set_rifs_delay(ah, enable); 2167 } 2168 return AH_FALSE; 2169 } 2170 2171 return AH_TRUE; 2172 } /* ar9300_set_11n_rx_rifs () */ 2173 2174 static hal_mac_hangs_t 2175 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2176 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2177 { 2178 int i = 0; 2179 hal_mac_hangs_t found_hangs = 0; 2180 2181 if (hangs & dcu_chain_state) { 2182 for (i = 0; i < 6; i++) { 2183 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2184 hang_check.dcu_chain_state) 2185 { 2186 found_hangs |= dcu_chain_state; 2187 *dcu_chain = i; 2188 } 2189 } 2190 for (i = 0; i < 4; i++) { 2191 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2192 hang_check.dcu_chain_state) 2193 { 2194 found_hangs |= dcu_chain_state; 2195 *dcu_chain = i + 6; 2196 } 2197 } 2198 } 2199 2200 if (hangs & dcu_complete_state) { 2201 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2202 found_hangs |= dcu_complete_state; 2203 } 2204 } 2205 2206 return found_hangs; 2207 2208 } /* end - ar9300_compare_dbg_hang */ 2209 2210 #define NUM_STATUS_READS 50 2211 HAL_BOOL 2212 ar9300_detect_mac_hang(struct ath_hal *ah) 2213 { 2214 struct ath_hal_9300 *ahp = AH9300(ah); 2215 mac_dbg_regs_t mac_dbg; 2216 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2217 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2218 int i = 0; 2219 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2220 2221 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2222 return AH_FALSE; 2223 } 2224 2225 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2226 2227 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2228 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2229 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2230 2231 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2232 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2233 mac_dbg.dma_dbg_6); 2234 2235 if (hang_sig1 != 2236 ar9300_compare_dbg_hang(ah, mac_dbg, 2237 hang_sig1_val, hang_sig1, &dcu_chain)) 2238 { 2239 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2240 return AH_FALSE; 2241 } 2242 2243 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2244 shift_val *= 5; 2245 2246 for (i = 1; i <= NUM_STATUS_READS; i++) { 2247 if (dcu_chain < 6) { 2248 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2249 current_dcu_chain_state = 2250 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2251 } else { 2252 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2253 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2254 } 2255 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2256 2257 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2258 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2259 return AH_FALSE; 2260 } 2261 } 2262 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2263 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2264 ahp->ah_hang[MAC_HANG_SIG1]++; 2265 return AH_TRUE; 2266 2267 } /* end - ar9300_detect_mac_hang */ 2268 2269 /* Determine if the baseband is hung by reading the Observation Bus Register */ 2270 HAL_BOOL 2271 ar9300_detect_bb_hang(struct ath_hal *ah) 2272 { 2273 #define N(a) (sizeof(a) / sizeof(a[0])) 2274 struct ath_hal_9300 *ahp = AH9300(ah); 2275 u_int32_t hang_sig = 0; 2276 int i = 0; 2277 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2278 * 2279 * 4 known BB hang signatures - 2280 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2281 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2282 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2283 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2284 * Rx State (bits 20-24) is 0x7. 2285 */ 2286 hal_hw_hang_check_t hang_list [] = 2287 { 2288 /* Offset Reg Value Reg Mask Hang Offset */ 2289 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2290 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2291 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2292 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2293 }; 2294 2295 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2296 HAL_DFS_BB_HANG_WAR | 2297 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2298 return AH_FALSE; 2299 } 2300 2301 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2302 for (i = 1; i <= NUM_STATUS_READS; i++) { 2303 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2304 return AH_FALSE; 2305 } 2306 } 2307 2308 for (i = 0; i < N(hang_list); i++) { 2309 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2310 ahp->ah_hang[hang_list[i].hang_offset]++; 2311 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2312 "sig3count=%d sig4count=%d\n", __func__, 2313 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2314 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2315 return AH_TRUE; 2316 } 2317 } 2318 2319 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2320 "<0x806c>=0x%x\n", __func__, hang_sig); 2321 2322 return AH_FALSE; 2323 2324 #undef N 2325 } /* end - ar9300_detect_bb_hang () */ 2326 2327 #undef NUM_STATUS_READS 2328 2329 HAL_STATUS 2330 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2331 { 2332 struct ath_hal_9300 *ahp = AH9300(ah); 2333 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2334 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2335 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2336 u_int16_t ant_config; 2337 u_int32_t hal_num_ant_config; 2338 2339 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2340 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2341 2342 if (cfg < hal_num_ant_config) { 2343 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2344 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2345 return HAL_OK; 2346 } 2347 } 2348 2349 return HAL_EINVAL; 2350 } 2351 2352 /* 2353 * Functions to get/set DCS mode 2354 */ 2355 void 2356 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2357 { 2358 AH9300(ah)->ah_dcs_enable = mode; 2359 } 2360 2361 u_int32_t 2362 ar9300_get_dcs_mode(struct ath_hal *ah) 2363 { 2364 return AH9300(ah)->ah_dcs_enable; 2365 } 2366 2367 #if ATH_BT_COEX 2368 void 2369 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2370 { 2371 struct ath_hal_9300 *ahp = AH9300(ah); 2372 2373 ahp->ah_bt_module = btinfo->bt_module; 2374 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2375 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2376 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2377 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2378 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2379 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2380 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2381 } 2382 2383 void 2384 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2385 { 2386 struct ath_hal_9300 *ahp = AH9300(ah); 2387 HAL_BOOL rx_clear_polarity; 2388 2389 /* 2390 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2391 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2392 */ 2393 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2394 2395 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2396 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2397 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2398 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2399 SM(btconf->bt_mode, AR_BT_MODE) | 2400 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2401 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2402 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2403 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2404 2405 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2406 2407 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2408 /* Enable ACK to go out even though BT has higher priority. */ 2409 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2410 } 2411 } 2412 2413 void 2414 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2415 { 2416 struct ath_hal_9300 *ahp = AH9300(ah); 2417 2418 /* clear the old value, then set the new value */ 2419 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2420 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2421 } 2422 2423 void 2424 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2425 { 2426 struct ath_hal_9300 *ahp = AH9300(ah); 2427 2428 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2429 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2430 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2431 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2432 2433 switch (stomp_type) { 2434 case HAL_BT_COEX_STOMP_ALL: 2435 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2436 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2437 break; 2438 case HAL_BT_COEX_STOMP_LOW: 2439 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2440 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2441 break; 2442 case HAL_BT_COEX_STOMP_ALL_FORCE: 2443 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2444 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2445 break; 2446 case HAL_BT_COEX_STOMP_LOW_FORCE: 2447 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2448 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2449 break; 2450 case HAL_BT_COEX_STOMP_NONE: 2451 case HAL_BT_COEX_NO_STOMP: 2452 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2453 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2454 break; 2455 default: 2456 /* There is a force_weight from registry */ 2457 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2458 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2459 break; 2460 } 2461 } 2462 2463 void 2464 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2465 { 2466 struct ath_hal_9300 *ahp = AH9300(ah); 2467 2468 /* clear the old value, then set the new value */ 2469 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2470 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2471 } 2472 2473 static void 2474 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2475 { 2476 struct ath_hal_9300 *ahp = AH9300(ah); 2477 #if ATH_ANT_DIV_COMB 2478 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2479 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2480 #endif 2481 2482 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value); 2483 2484 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2485 { 2486 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2487 { 2488 /* Config antenna diversity */ 2489 #if ATH_ANT_DIV_COMB 2490 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2491 #endif 2492 } 2493 } 2494 } 2495 2496 2497 void 2498 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2499 u_int32_t value) 2500 { 2501 struct ath_hal_9300 *ahp = AH9300(ah); 2502 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2503 2504 switch (type) { 2505 case HAL_BT_COEX_SET_ACK_PWR: 2506 if (value) { 2507 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2508 } else { 2509 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2510 } 2511 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2512 ahpriv->ah_extraTxPow, 0); 2513 break; 2514 2515 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2516 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2517 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2518 if (value) { 2519 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2520 } 2521 else { 2522 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2523 } 2524 ar9300_bt_coex_antenna_diversity(ah, value); 2525 } 2526 break; 2527 case HAL_BT_COEX_LOWER_TX_PWR: 2528 if (value) { 2529 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2530 } 2531 else { 2532 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2533 } 2534 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2535 ahpriv->ah_extraTxPow, 0); 2536 break; 2537 #if ATH_SUPPORT_MCI 2538 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2539 if ((ah->ah_config.ath_hal_mci_config & 2540 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2541 { 2542 if (value) { 2543 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2544 ahp->ah_mci_concur_tx_en = AH_TRUE; 2545 } 2546 else { 2547 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2548 ahp->ah_mci_concur_tx_en = AH_FALSE; 2549 } 2550 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2551 ahpriv->ah_extraTxPow, 0); 2552 } 2553 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2554 ahp->ah_mci_concur_tx_en); 2555 break; 2556 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2557 if (value) { 2558 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2559 } 2560 else { 2561 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2562 } 2563 break; 2564 #endif 2565 default: 2566 break; 2567 } 2568 } 2569 2570 void 2571 ar9300_bt_coex_disable(struct ath_hal *ah) 2572 { 2573 struct ath_hal_9300 *ahp = AH9300(ah); 2574 2575 /* Always drive rx_clear_external output as 0 */ 2576 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2577 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2578 2579 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2580 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2581 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2582 } 2583 2584 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2585 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2586 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2587 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2588 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2589 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2590 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2591 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2592 2593 ahp->ah_bt_coex_enabled = AH_FALSE; 2594 } 2595 2596 int 2597 ar9300_bt_coex_enable(struct ath_hal *ah) 2598 { 2599 struct ath_hal_9300 *ahp = AH9300(ah); 2600 2601 /* Program coex mode and weight registers to actually enable coex */ 2602 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2603 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2604 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2605 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2606 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2607 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2608 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2609 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2610 2611 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2612 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2613 } else { 2614 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2615 } 2616 2617 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2618 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2619 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2620 } else { 2621 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2622 } 2623 2624 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2625 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2626 ath_hal_gpioCfgOutput(ah, 2627 ahp->ah_wlan_active_gpio_select, 2628 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2629 } 2630 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2631 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2632 { 2633 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2634 ath_hal_gpioCfgOutput(ah, 2635 ahp->ah_wlan_active_gpio_select, 2636 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2637 } 2638 2639 /* 2640 * Enable a weak pull down on BT_ACTIVE. 2641 * When BT device is disabled, BT_ACTIVE might be floating. 2642 */ 2643 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2644 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2645 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2646 2647 ahp->ah_bt_coex_enabled = AH_TRUE; 2648 2649 return 0; 2650 } 2651 2652 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2653 { 2654 return 0; 2655 } 2656 2657 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2658 { 2659 return bOn; 2660 } 2661 2662 void 2663 ar9300_init_bt_coex(struct ath_hal *ah) 2664 { 2665 struct ath_hal_9300 *ahp = AH9300(ah); 2666 2667 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2668 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2669 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2670 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2671 2672 /* 2673 * Set input mux for bt_prority_async and 2674 * bt_active_async to GPIO pins 2675 */ 2676 OS_REG_RMW_FIELD(ah, 2677 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2678 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2679 ahp->ah_bt_active_gpio_select); 2680 OS_REG_RMW_FIELD(ah, 2681 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2682 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2683 ahp->ah_bt_priority_gpio_select); 2684 2685 /* Configure the desired GPIO ports for input */ 2686 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2687 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2688 2689 if (ahp->ah_bt_coex_enabled) { 2690 ar9300_bt_coex_enable(ah); 2691 } else { 2692 ar9300_bt_coex_disable(ah); 2693 } 2694 } 2695 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2696 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2697 { 2698 /* 2-wire */ 2699 if (ahp->ah_bt_coex_enabled) { 2700 /* Connect bt_active_async to baseband */ 2701 OS_REG_CLR_BIT(ah, 2702 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2703 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2704 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2705 OS_REG_SET_BIT(ah, 2706 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2707 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2708 2709 /* 2710 * Set input mux for bt_prority_async and 2711 * bt_active_async to GPIO pins 2712 */ 2713 OS_REG_RMW_FIELD(ah, 2714 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2715 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2716 ahp->ah_bt_active_gpio_select); 2717 2718 /* Configure the desired GPIO ports for input */ 2719 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2720 2721 /* Enable coexistence on initialization */ 2722 ar9300_bt_coex_enable(ah); 2723 } 2724 } 2725 #if ATH_SUPPORT_MCI 2726 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2727 if (ahp->ah_bt_coex_enabled) { 2728 ar9300_mci_bt_coex_enable(ah); 2729 } 2730 else { 2731 ar9300_mci_bt_coex_disable(ah); 2732 } 2733 } 2734 #endif /* ATH_SUPPORT_MCI */ 2735 } 2736 2737 #endif /* ATH_BT_COEX */ 2738 2739 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2740 { 2741 u_int32_t val; 2742 int wasp_mm_rev; 2743 2744 #define AR_SOC_RST_REVISION_ID 0xB8060090 2745 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2746 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2747 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2748 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2749 #undef AR_SOC_RST_REVISION_ID 2750 #undef REG_READ 2751 2752 /* 2753 * Azimuth (ProxySTA) Mode is only supported correctly by 2754 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2755 * 2756 * Enable this feature for Scorpion at this time. The silicon 2757 * still needs to be validated. 2758 */ 2759 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2760 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2761 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2762 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2763 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2764 wasp_mm_rev >= 0 /* 1 */)))) 2765 { 2766 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2767 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2768 __func__, AH_PRIVATE((ah))->ah_macVersion, 2769 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2770 return HAL_ENOTSUPP; 2771 } 2772 2773 OS_REG_WRITE(ah, 2774 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2775 2776 /* turn on mode bit[24] for proxy sta */ 2777 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2778 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2779 2780 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2781 if (enable) { 2782 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2783 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2784 AR_AZIMUTH_BA_USES_AD1; 2785 /* turn off filter pass hold (bit 9) */ 2786 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2787 } else { 2788 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2789 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2790 AR_AZIMUTH_BA_USES_AD1); 2791 } 2792 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2793 2794 /* enable promiscous mode */ 2795 OS_REG_WRITE(ah, AR_RX_FILTER, 2796 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2797 /* enable promiscous in azimuth mode */ 2798 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2799 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2800 2801 /* turn on filter pass hold (bit 9) */ 2802 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2803 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2804 2805 return HAL_OK; 2806 } 2807 2808 #if 0 2809 void ar9300_mat_enable(struct ath_hal *ah, int enable) 2810 { 2811 /* 2812 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2813 * mitigation and turn on key search always for better performance. 2814 */ 2815 struct ath_hal_9300 *ahp = AH9300(ah); 2816 struct ath_hal_private *ap = AH_PRIVATE(ah); 2817 2818 ahp->ah_intr_mitigation_rx = !enable; 2819 if (ahp->ah_intr_mitigation_rx) { 2820 /* 2821 * Enable Interrupt Mitigation for Rx. 2822 * If no build-specific limits for the rx interrupt mitigation 2823 * timer have been specified, use conservative defaults. 2824 */ 2825 #ifndef AH_RIMT_VAL_LAST 2826 #define AH_RIMT_LAST_MICROSEC 500 2827 #endif 2828 #ifndef AH_RIMT_VAL_FIRST 2829 #define AH_RIMT_FIRST_MICROSEC 2000 2830 #endif 2831 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2832 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2833 } else { 2834 OS_REG_WRITE(ah, AR_RIMT, 0); 2835 } 2836 2837 ahp->ah_enable_keysearch_always = !!enable; 2838 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2839 } 2840 #endif 2841 2842 void ar9300_enable_tpc(struct ath_hal *ah) 2843 { 2844 u_int32_t val = 0; 2845 2846 ah->ah_config.ath_hal_desc_tpc = 1; 2847 2848 /* Enable TPC */ 2849 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2850 2851 /* 2852 * Disable per chain power reduction since we are already 2853 * accounting for this in our calculations 2854 */ 2855 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2856 if (AR_SREV_WASP(ah)) { 2857 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2858 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2859 } else { 2860 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2861 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2862 } 2863 } 2864 2865 2866 /* 2867 * ar9300_force_tsf_sync 2868 * This function forces the TSF sync to the given bssid, this is implemented 2869 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2870 * mode of operation, where we sync the TSF to RootAP TSF values 2871 */ 2872 void 2873 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2874 u_int16_t assoc_id) 2875 { 2876 ar9300_set_operating_mode(ah, HAL_M_STA); 2877 ar9300_write_associd(ah, bssid, assoc_id); 2878 } 2879 2880 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2881 { 2882 struct ath_hal_9300 *ahp = AH9300(ah); 2883 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2884 u_int32_t temp_powertx_rate9_reg_val; 2885 int8_t olpc_power_offset = 0; 2886 int8_t tmp_olpc_val = 0; 2887 HAL_RSSI_TX_POWER old_greentx_status; 2888 u_int8_t target_power_val_t[ar9300_rate_size]; 2889 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2890 2891 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2892 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2893 return; 2894 } 2895 2896 old_greentx_status = AH9300(ah)->green_tx_status; 2897 if (ahp->ah_hw_green_tx_enable) { 2898 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2899 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2900 } else { 2901 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2902 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2903 } 2904 2905 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2906 && (rssi > tmp_rss1_thr1)) 2907 { 2908 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2909 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2910 } 2911 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2912 && (rssi > tmp_rss1_thr2)) 2913 { 2914 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2915 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2916 } 2917 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2918 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2919 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2920 } 2921 } 2922 2923 /* If status is not change, don't do anything */ 2924 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2925 return; 2926 } 2927 2928 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2929 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2930 && AR_SREV_POSEIDON(ah)) 2931 { 2932 if (ahp->ah_hw_green_tx_enable) { 2933 switch (AH9300(ah)->green_tx_status) { 2934 case HAL_RSSI_TX_POWER_SHORT: 2935 /* 1. TxPower Config */ 2936 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2937 sizeof(target_power_val_t)); 2938 /* 1.1 Store OLPC Delta Calibration Offset*/ 2939 olpc_power_offset = 0; 2940 /* 2. Store OB/DB */ 2941 /* 3. Store TPC settting */ 2942 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2943 SM(14, AR_TPC_CTS) | 2944 SM(14, AR_TPC_CHIRP) | 2945 SM(14, AR_TPC_RPT)); 2946 /* 4. Store BB_powertx_rate9 value */ 2947 temp_powertx_rate9_reg_val = 2948 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2949 break; 2950 case HAL_RSSI_TX_POWER_MIDDLE: 2951 /* 1. TxPower Config */ 2952 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2953 sizeof(target_power_val_t)); 2954 /* 1.1 Store OLPC Delta Calibration Offset*/ 2955 olpc_power_offset = 0; 2956 /* 2. Store OB/DB */ 2957 /* 3. Store TPC settting */ 2958 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2959 SM(18, AR_TPC_CTS) | 2960 SM(18, AR_TPC_CHIRP) | 2961 SM(18, AR_TPC_RPT)); 2962 /* 4. Store BB_powertx_rate9 value */ 2963 temp_powertx_rate9_reg_val = 2964 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2965 break; 2966 case HAL_RSSI_TX_POWER_LONG: 2967 default: 2968 /* 1. TxPower Config */ 2969 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2970 sizeof(target_power_val_t)); 2971 /* 1.1 Store OLPC Delta Calibration Offset*/ 2972 olpc_power_offset = 0; 2973 /* 2. Store OB/DB1/DB2 */ 2974 /* 3. Store TPC settting */ 2975 temp_tcp_reg_val = 2976 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2977 /* 4. Store BB_powertx_rate9 value */ 2978 temp_powertx_rate9_reg_val = 2979 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2980 break; 2981 } 2982 } else { 2983 switch (AH9300(ah)->green_tx_status) { 2984 case HAL_RSSI_TX_POWER_SHORT: 2985 /* 1. TxPower Config */ 2986 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2987 sizeof(target_power_val_t)); 2988 /* 1.1 Store OLPC Delta Calibration Offset*/ 2989 olpc_power_offset = 2990 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2991 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2992 /* 2. Store OB/DB */ 2993 temp_obdb_reg_val = 2994 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2995 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2996 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2997 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2998 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2999 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3000 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3001 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3002 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3003 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3004 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3005 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3006 /* 3. Store TPC settting */ 3007 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 3008 SM(6, AR_TPC_CTS) | 3009 SM(6, AR_TPC_CHIRP) | 3010 SM(6, AR_TPC_RPT)); 3011 /* 4. Store BB_powertx_rate9 value */ 3012 temp_powertx_rate9_reg_val = 3013 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 3014 break; 3015 case HAL_RSSI_TX_POWER_MIDDLE: 3016 /* 1. TxPower Config */ 3017 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 3018 sizeof(target_power_val_t)); 3019 /* 1.1 Store OLPC Delta Calibration Offset*/ 3020 olpc_power_offset = 3021 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 3022 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3023 /* 2. Store OB/DB */ 3024 temp_obdb_reg_val = 3025 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3026 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3027 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3028 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3029 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3030 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3031 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3032 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3033 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3034 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3035 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3036 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3037 /* 3. Store TPC settting */ 3038 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3039 SM(14, AR_TPC_CTS) | 3040 SM(14, AR_TPC_CHIRP) | 3041 SM(14, AR_TPC_RPT)); 3042 /* 4. Store BB_powertx_rate9 value */ 3043 temp_powertx_rate9_reg_val = 3044 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3045 break; 3046 case HAL_RSSI_TX_POWER_LONG: 3047 default: 3048 /* 1. TxPower Config */ 3049 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3050 sizeof(target_power_val_t)); 3051 /* 1.1 Store OLPC Delta Calibration Offset*/ 3052 olpc_power_offset = 3053 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3054 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3055 /* 2. Store OB/DB1/DB2 */ 3056 temp_obdb_reg_val = 3057 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3058 /* 3. Store TPC settting */ 3059 temp_tcp_reg_val = 3060 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3061 /* 4. Store BB_powertx_rate9 value */ 3062 temp_powertx_rate9_reg_val = 3063 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3064 break; 3065 } 3066 } 3067 /* 1.1 Do OLPC Delta Calibration Offset */ 3068 tmp_olpc_val = 3069 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3070 tmp_olpc_val += olpc_power_offset; 3071 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3072 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3073 AR_PHY_TPC_OLPC_GAIN_DELTA); 3074 3075 /* 1.2 TxPower Config */ 3076 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3077 /* 2. Config OB/DB */ 3078 if (!ahp->ah_hw_green_tx_enable) { 3079 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3080 } 3081 /* 3. config TPC settting */ 3082 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3083 /* 4. config BB_powertx_rate9 value */ 3084 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3085 } 3086 } 3087 3088 #if 0 3089 void 3090 ar9300_get_vow_stats( 3091 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3092 { 3093 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3094 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3095 } 3096 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3097 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3098 } 3099 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3100 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3101 } 3102 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3103 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3104 } 3105 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3106 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3107 } 3108 } 3109 #endif 3110 3111 /* 3112 * ar9300_is_skip_paprd_by_greentx 3113 * 3114 * This function check if we need to skip PAPRD tuning 3115 * when GreenTx in specific state. 3116 */ 3117 HAL_BOOL 3118 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3119 { 3120 if (AR_SREV_POSEIDON(ah) && 3121 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3122 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3123 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3124 { 3125 return AH_TRUE; 3126 } 3127 return AH_FALSE; 3128 } 3129 3130 void 3131 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3132 { 3133 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3134 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3135 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3136 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3137 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3138 struct ath_hal_9300 *ahp = AH9300(ah); 3139 3140 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3141 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3142 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3143 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3144 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3145 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3146 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3147 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3148 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3149 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3150 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3151 } 3152 } 3153 3154 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3155 { 3156 struct ath_hal_9300 *ahp = AH9300(ah); 3157 3158 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3159 if ((value == 0) || (value == 1)) { 3160 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3161 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3162 } 3163 } 3164 } 3165 3166 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3167 { 3168 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3169 } 3170 3171 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3172 { 3173 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3174 3175 /* RSSI format is 8.4. Ignore lowest four bits */ 3176 val = val >> 4; 3177 return val; 3178 } 3179 3180 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3181 u_int32_t rssi_threshold) 3182 { 3183 struct ath_hal_9300 *ahp = AH9300(ah); 3184 3185 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3186 3187 /* save value for restoring after chip reset */ 3188 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3189 } 3190 3191 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3192 { 3193 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3194 } 3195 3196 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3197 { 3198 if (on) { 3199 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3200 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3201 } 3202 else { 3203 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3204 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3205 } 3206 } 3207 /* 3208 * Gets the contents of the specified key cache entry. 3209 */ 3210 HAL_BOOL 3211 ar9300_print_keycache(struct ath_hal *ah) 3212 { 3213 3214 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3215 u_int32_t key0, key1, key2, key3, key4; 3216 u_int32_t mac_hi, mac_lo; 3217 u_int16_t entry = 0; 3218 u_int32_t valid = 0; 3219 u_int32_t key_type; 3220 3221 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3222 3223 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3224 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3225 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3226 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3227 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3228 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3229 3230 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3231 3232 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3233 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3234 3235 if (mac_hi & AR_KEYTABLE_VALID) { 3236 valid = 1; 3237 } else { 3238 valid = 0; 3239 } 3240 3241 if ((mac_hi != 0) && (mac_lo != 0)) { 3242 mac_hi &= ~0x8000; 3243 mac_hi <<= 1; 3244 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3245 mac_lo <<= 1; 3246 } 3247 3248 ath_hal_printf(ah, 3249 "%03d " 3250 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3251 " %02d %02d " 3252 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3253 entry, 3254 (key0 << 24) >> 24, (key0 << 16) >> 24, 3255 (key0 << 8) >> 24, key0 >> 24, 3256 (key1 << 24) >> 24, (key1 << 16) >> 24, 3257 //(key1 << 8) >> 24, key1 >> 24, 3258 (key2 << 24) >> 24, (key2 << 16) >> 24, 3259 (key2 << 8) >> 24, key2 >> 24, 3260 (key3 << 24) >> 24, (key3 << 16) >> 24, 3261 //(key3 << 8) >> 24, key3 >> 24, 3262 (key4 << 24) >> 24, (key4 << 16) >> 24, 3263 (key4 << 8) >> 24, key4 >> 24, 3264 valid, key_type, 3265 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3266 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3267 } 3268 3269 return AH_TRUE; 3270 } 3271 3272 /* enable/disable smart antenna mode */ 3273 HAL_BOOL 3274 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3275 { 3276 struct ath_hal_9300 *ahp = AH9300(ah); 3277 3278 if (enable) { 3279 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3280 } else { 3281 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3282 } 3283 3284 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3285 * and swcom2 with 0 3286 * FIXME Ideally these registers need to be made read from caldata. 3287 * Until the calibration team gets them, keep them along with board 3288 * configuration. 3289 */ 3290 if (enable && AR_SREV_SCORPION(ah) && 3291 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3292 3293 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3294 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3295 } 3296 3297 ahp->ah_smartantenna_enable = enable; 3298 return 1; 3299 } 3300 3301 #ifdef ATH_TX99_DIAG 3302 #ifndef ATH_SUPPORT_HTC 3303 void 3304 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3305 u_int32_t txpower) 3306 { 3307 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3308 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3309 int32_t i; 3310 3311 /* The max power is limited to 63 */ 3312 if (txpower <= AR9300_MAX_RATE_POWER) { 3313 for (i = 0; i < ar9300_rate_size; i++) { 3314 p_pwr_array[i] = txpower; 3315 } 3316 } else { 3317 for (i = 0; i < ar9300_rate_size; i++) { 3318 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3319 } 3320 } 3321 3322 OS_REG_WRITE(ah, 0xa458, 0); 3323 3324 /* Write the OFDM power per rate set */ 3325 /* 6 (LSB), 9, 12, 18 (MSB) */ 3326 OS_REG_WRITE(ah, 0xa3c0, 3327 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3328 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3329 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3330 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3331 ); 3332 /* 24 (LSB), 36, 48, 54 (MSB) */ 3333 OS_REG_WRITE(ah, 0xa3c4, 3334 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3335 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3336 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3337 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3338 ); 3339 3340 /* Write the CCK power per rate set */ 3341 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3342 OS_REG_WRITE(ah, 0xa3c8, 3343 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3344 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3345 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3346 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3347 ); 3348 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3349 OS_REG_WRITE(ah, 0xa3cc, 3350 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3351 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3352 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3353 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3354 ); 3355 3356 /* Write the HT20 power per rate set */ 3357 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3358 OS_REG_WRITE(ah, 0xa3d0, 3359 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3360 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3361 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3362 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3363 ); 3364 3365 /* 6 (LSB), 7, 12, 13 (MSB) */ 3366 OS_REG_WRITE(ah, 0xa3d4, 3367 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3368 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3369 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3370 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3371 ); 3372 3373 /* 14 (LSB), 15, 20, 21 */ 3374 OS_REG_WRITE(ah, 0xa3e4, 3375 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3376 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3377 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3378 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3379 ); 3380 3381 /* Mixed HT20 and HT40 rates */ 3382 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3383 OS_REG_WRITE(ah, 0xa3e8, 3384 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3385 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3386 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3387 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3388 ); 3389 3390 /* Write the HT40 power per rate set */ 3391 /* correct PAR difference between HT40 and HT20/LEGACY */ 3392 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3393 OS_REG_WRITE(ah, 0xa3d8, 3394 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3395 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3396 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3397 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3398 ); 3399 3400 /* 6 (LSB), 7, 12, 13 (MSB) */ 3401 OS_REG_WRITE(ah, 0xa3dc, 3402 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3403 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3404 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3405 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3406 ); 3407 3408 /* 14 (LSB), 15, 20, 21 */ 3409 OS_REG_WRITE(ah, 0xa3ec, 3410 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3411 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3412 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3413 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3414 ); 3415 #undef PWR_MAS 3416 } 3417 3418 void 3419 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3420 { 3421 if (tx_chainmask == 0x5) { 3422 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3423 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3424 } 3425 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3426 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3427 3428 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3429 if (tx_chainmask == 0x5) { 3430 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3431 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3432 } 3433 } 3434 3435 void 3436 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3437 int chtype) 3438 { 3439 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3440 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3441 OS_REG_WRITE(ah, 0xa350, 3442 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3443 3444 /* 11G mode */ 3445 if (!chtype) { 3446 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3447 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3448 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3449 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3450 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3451 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3452 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3453 | (0x1 << 26) | (0x7 << 24)) 3454 & ~(0x1 << 22)); 3455 } else { 3456 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3457 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3458 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3459 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3460 | (0x1 << 26) | (0x7 << 24)) 3461 & ~(0x1 << 22)); 3462 } 3463 3464 /* chain zero */ 3465 if ((tx_chain_mask & 0x01) == 0x01) { 3466 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3467 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3468 | (0x1 << 31) | (0x5 << 15) 3469 | (0x3 << 9)) & ~(0x1 << 27) 3470 & ~(0x1 << 12)); 3471 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3472 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3473 | (0x1 << 12) | (0x1 << 10) 3474 | (0x1 << 9) | (0x1 << 8) 3475 | (0x1 << 7)) & ~(0x1 << 11)); 3476 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3477 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3478 | (0x1 << 29) | (0x1 << 25) 3479 | (0x1 << 23) | (0x1 << 19) 3480 | (0x1 << 10) | (0x1 << 9) 3481 | (0x1 << 8) | (0x1 << 3)) 3482 & ~(0x1 << 28)& ~(0x1 << 24) 3483 & ~(0x1 << 22)& ~(0x1 << 7)); 3484 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3485 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3486 | (0x1 << 23))& ~(0x1 << 21)); 3487 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3488 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3489 | (0x1 << 12) | (0x1 << 10) 3490 | (0x1 << 9) | (0x1 << 8) 3491 | (0x1 << 6) | (0x1 << 5) 3492 | (0x1 << 4) | (0x1 << 3) 3493 | (0x1 << 2)); 3494 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3495 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3496 } 3497 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3498 /* chain one */ 3499 if ((tx_chain_mask & 0x02) == 0x02 ) { 3500 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3501 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3502 | (0x1 << 31) | (0x5 << 15) 3503 | (0x3 << 9)) & ~(0x1 << 27) 3504 & ~(0x1 << 12)); 3505 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3506 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3507 | (0x1 << 12) | (0x1 << 10) 3508 | (0x1 << 9) | (0x1 << 8) 3509 | (0x1 << 7)) & ~(0x1 << 11)); 3510 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3511 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3512 | (0x1 << 29) | (0x1 << 25) 3513 | (0x1 << 23) | (0x1 << 19) 3514 | (0x1 << 10) | (0x1 << 9) 3515 | (0x1 << 8) | (0x1 << 3)) 3516 & ~(0x1 << 28)& ~(0x1 << 24) 3517 & ~(0x1 << 22)& ~(0x1 << 7)); 3518 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3519 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3520 | (0x1 << 23))& ~(0x1 << 21)); 3521 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3522 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3523 | (0x1 << 12) | (0x1 << 10) 3524 | (0x1 << 9) | (0x1 << 8) 3525 | (0x1 << 6) | (0x1 << 5) 3526 | (0x1 << 4) | (0x1 << 3) 3527 | (0x1 << 2)); 3528 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3529 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3530 } 3531 } 3532 if (AR_SREV_OSPREY(ah)) { 3533 /* chain two */ 3534 if ((tx_chain_mask & 0x04) == 0x04 ) { 3535 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3536 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3537 | (0x1 << 31) | (0x5 << 15) 3538 | (0x3 << 9)) & ~(0x1 << 27) 3539 & ~(0x1 << 12)); 3540 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3541 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3542 | (0x1 << 12) | (0x1 << 10) 3543 | (0x1 << 9) | (0x1 << 8) 3544 | (0x1 << 7)) & ~(0x1 << 11)); 3545 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3546 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3547 | (0x1 << 29) | (0x1 << 25) 3548 | (0x1 << 23) | (0x1 << 19) 3549 | (0x1 << 10) | (0x1 << 9) 3550 | (0x1 << 8) | (0x1 << 3)) 3551 & ~(0x1 << 28)& ~(0x1 << 24) 3552 & ~(0x1 << 22)& ~(0x1 << 7)); 3553 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3554 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3555 | (0x1 << 23))& ~(0x1 << 21)); 3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3557 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3558 | (0x1 << 12) | (0x1 << 10) 3559 | (0x1 << 9) | (0x1 << 8) 3560 | (0x1 << 6) | (0x1 << 5) 3561 | (0x1 << 4) | (0x1 << 3) 3562 | (0x1 << 2)); 3563 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3564 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3565 } 3566 } 3567 3568 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3569 OS_REG_WRITE(ah, 0xa288, 0x111); 3570 } else { 3571 /* chain zero */ 3572 if ((tx_chain_mask & 0x01) == 0x01) { 3573 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3574 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3575 | (0x1 << 31) | (0x1 << 27) 3576 | (0x3 << 23) | (0x1 << 19) 3577 | (0x1 << 15) | (0x3 << 9)) 3578 & ~(0x1 << 12)); 3579 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3580 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3581 | (0x1 << 12) | (0x1 << 10) 3582 | (0x1 << 9) | (0x1 << 8) 3583 | (0x1 << 7) | (0x1 << 3) 3584 | (0x1 << 2) | (0x1 << 1)) 3585 & ~(0x1 << 11)& ~(0x1 << 0)); 3586 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3587 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3588 | (0x1 << 29) | (0x1 << 25) 3589 | (0x1 << 23) | (0x1 << 19) 3590 | (0x1 << 10) | (0x1 << 9) 3591 | (0x1 << 8) | (0x1 << 3)) 3592 & ~(0x1 << 28)& ~(0x1 << 24) 3593 & ~(0x1 << 22)& ~(0x1 << 7)); 3594 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3595 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3596 | (0x1 << 23))& ~(0x1 << 21)); 3597 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3598 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3599 | (0x3 << 3) | (0x3 << 0)); 3600 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3601 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3602 | (0x3 << 29) | (0x3 << 26) 3603 | (0x2 << 23) | (0x2 << 20) 3604 | (0x2 << 17))& ~(0x1 << 14)); 3605 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3606 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3607 | (0x1 << 12) | (0x1 << 10) 3608 | (0x1 << 9) | (0x1 << 8) 3609 | (0x1 << 6) | (0x1 << 5) 3610 | (0x1 << 4) | (0x1 << 3) 3611 | (0x1 << 2)); 3612 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3613 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3614 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3615 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3616 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3617 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3618 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3619 | (0x1 << 26) | (0x7 << 24) 3620 | (0x3 << 22)); 3621 } else { 3622 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3623 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3624 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3625 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3626 | (0x1 << 26) | (0x7 << 24) 3627 | (0x3 << 22)); 3628 } 3629 3630 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3631 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3632 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3633 | (0x1 << 3) | (0x1 << 2) 3634 | (0x1 << 1)) & ~(0x1 << 0)); 3635 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3636 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3637 | (0x1 << 19) | (0x1 << 3)); 3638 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3639 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3640 } 3641 if (AR_SREV_OSPREY(ah)) { 3642 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3643 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3644 | (0x1 << 3) | (0x1 << 2) 3645 | (0x1 << 1)) & ~(0x1 << 0)); 3646 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3647 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3648 | (0x1 << 19) | (0x1 << 3)); 3649 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3650 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3651 } 3652 } 3653 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3654 /* chain one */ 3655 if ((tx_chain_mask & 0x02) == 0x02 ) { 3656 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3657 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3658 | (0x1 << 3) | (0x1 << 2) 3659 | (0x1 << 1)) & ~(0x1 << 0)); 3660 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3661 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3662 | (0x1 << 19) | (0x1 << 3)); 3663 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3664 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3665 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3666 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3667 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3668 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3669 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3670 | (0x1 << 26) | (0x7 << 24) 3671 | (0x3 << 22)); 3672 } else { 3673 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3674 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3675 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3676 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3677 | (0x1 << 26) | (0x7 << 24) 3678 | (0x3 << 22)); 3679 } 3680 3681 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3682 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3683 | (0x1 << 31) | (0x1 << 27) 3684 | (0x3 << 23) | (0x1 << 19) 3685 | (0x1 << 15) | (0x3 << 9)) 3686 & ~(0x1 << 12)); 3687 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3688 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3689 | (0x1 << 12) | (0x1 << 10) 3690 | (0x1 << 9) | (0x1 << 8) 3691 | (0x1 << 7) | (0x1 << 3) 3692 | (0x1 << 2) | (0x1 << 1)) 3693 & ~(0x1 << 11)& ~(0x1 << 0)); 3694 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3695 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3696 | (0x1 << 29) | (0x1 << 25) 3697 | (0x1 << 23) | (0x1 << 19) 3698 | (0x1 << 10) | (0x1 << 9) 3699 | (0x1 << 8) | (0x1 << 3)) 3700 & ~(0x1 << 28)& ~(0x1 << 24) 3701 & ~(0x1 << 22)& ~(0x1 << 7)); 3702 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3703 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3704 | (0x1 << 23))& ~(0x1 << 21)); 3705 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3706 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3707 | (0x3 << 3) | (0x3 << 0)); 3708 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3709 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3710 | (0x3 << 29) | (0x3 << 26) 3711 | (0x2 << 23) | (0x2 << 20) 3712 | (0x2 << 17))& ~(0x1 << 14)); 3713 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3714 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3715 | (0x1 << 12) | (0x1 << 10) 3716 | (0x1 << 9) | (0x1 << 8) 3717 | (0x1 << 6) | (0x1 << 5) 3718 | (0x1 << 4) | (0x1 << 3) 3719 | (0x1 << 2)); 3720 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3721 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3722 3723 if (AR_SREV_OSPREY(ah)) { 3724 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3725 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3726 | (0x1 << 3) | (0x1 << 2) 3727 | (0x1 << 1)) & ~(0x1 << 0)); 3728 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3729 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3730 | (0x1 << 19) | (0x1 << 3)); 3731 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3732 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3733 } 3734 } 3735 } 3736 if (AR_SREV_OSPREY(ah)) { 3737 /* chain two */ 3738 if ((tx_chain_mask & 0x04) == 0x04 ) { 3739 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3740 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3741 | (0x1 << 3) | (0x1 << 2) 3742 | (0x1 << 1)) & ~(0x1 << 0)); 3743 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3744 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3745 | (0x1 << 19) | (0x1 << 3)); 3746 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3747 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3748 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3749 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3750 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3751 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3752 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3753 | (0x1 << 26) | (0x7 << 24) 3754 | (0x3 << 22)); 3755 } else { 3756 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3757 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3758 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3759 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3760 | (0x1 << 26) | (0x7 << 24) 3761 | (0x3 << 22)); 3762 } 3763 3764 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3765 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3766 | (0x1 << 3) | (0x1 << 2) 3767 | (0x1 << 1)) & ~(0x1 << 0)); 3768 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3769 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3770 | (0x1 << 19) | (0x1 << 3)); 3771 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3772 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3773 3774 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3775 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3776 | (0x1 << 31) | (0x1 << 27) 3777 | (0x3 << 23) | (0x1 << 19) 3778 | (0x1 << 15) | (0x3 << 9)) 3779 & ~(0x1 << 12)); 3780 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3781 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3782 | (0x1 << 12) | (0x1 << 10) 3783 | (0x1 << 9) | (0x1 << 8) 3784 | (0x1 << 7) | (0x1 << 3) 3785 | (0x1 << 2) | (0x1 << 1)) 3786 & ~(0x1 << 11)& ~(0x1 << 0)); 3787 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3788 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3789 | (0x1 << 29) | (0x1 << 25) 3790 | (0x1 << 23) | (0x1 << 19) 3791 | (0x1 << 10) | (0x1 << 9) 3792 | (0x1 << 8) | (0x1 << 3)) 3793 & ~(0x1 << 28)& ~(0x1 << 24) 3794 & ~(0x1 << 22)& ~(0x1 << 7)); 3795 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3796 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3797 | (0x1 << 23))& ~(0x1 << 21)); 3798 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3799 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3800 | (0x3 << 3) | (0x3 << 0)); 3801 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3802 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3803 | (0x3 << 29) | (0x3 << 26) 3804 | (0x2 << 23) | (0x2 << 20) 3805 | (0x2 << 17))& ~(0x1 << 14)); 3806 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3807 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3808 | (0x1 << 12) | (0x1 << 10) 3809 | (0x1 << 9) | (0x1 << 8) 3810 | (0x1 << 6) | (0x1 << 5) 3811 | (0x1 << 4) | (0x1 << 3) 3812 | (0x1 << 2)); 3813 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3814 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3815 } 3816 } 3817 3818 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3819 OS_REG_WRITE(ah, 0xa288, 0x222); 3820 } 3821 } 3822 3823 void 3824 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3825 { 3826 u_int32_t val; 3827 u_int32_t qnum = (u_int32_t)data; 3828 3829 /* Disable AGC to A2 */ 3830 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3831 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3832 3833 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3834 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3835 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3836 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3837 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3838 /* 200 ok for HT20, 400 ok for HT40 */ 3839 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3840 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3841 3842 /* set QCU modes to early termination */ 3843 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3844 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3845 } 3846 3847 void 3848 ar9300_tx99_stop(struct ath_hal *ah) 3849 { 3850 /* this should follow the setting of start */ 3851 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3852 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3853 } 3854 #endif /* ATH_TX99_DIAG */ 3855 #endif /* ATH_SUPPORT_HTC */ 3856 3857 HAL_BOOL 3858 ar9300Get3StreamSignature(struct ath_hal *ah) 3859 { 3860 return AH_FALSE; 3861 } 3862 3863 HAL_BOOL 3864 ar9300ForceVCS(struct ath_hal *ah) 3865 { 3866 return AH_FALSE; 3867 } 3868 3869 HAL_BOOL 3870 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3871 { 3872 return AH_FALSE; 3873 } 3874 3875 static u_int32_t 3876 ar9300_read_loc_timer(struct ath_hal *ah) 3877 { 3878 3879 return OS_REG_READ(ah, AR_LOC_TIMER_REG); 3880 } 3881 3882 HAL_BOOL 3883 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3884 { 3885 struct ath_hal_9300 *ahp = AH9300(ah); 3886 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3887 u_int8_t *ctl_index; 3888 u_int32_t offset = 0; 3889 3890 if (!ctl_array) 3891 return AH_FALSE; 3892 3893 /* copy 2G ctl freqbin and power data */ 3894 ctl_index = p_eep_data->ctl_index_2g; 3895 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3896 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3897 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3898 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3899 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3900 3901 3902 /* copy 2G ctl freqbin and power data */ 3903 ctl_index = p_eep_data->ctl_index_5g; 3904 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3905 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3906 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3907 3908 return AH_FALSE; 3909 } 3910 3911 void 3912 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3913 { 3914 struct ath_hal_9300 *ahp = AH9300(ah); 3915 3916 /* optional txchainmask should be subset of primary txchainmask */ 3917 if ((mask & ahp->ah_tx_chainmask) != mask) { 3918 ahp->ah_tx_chainmaskopt = 0; 3919 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3920 return; 3921 } 3922 3923 ahp->ah_tx_chainmaskopt = mask; 3924 } 3925