1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _ATH_AR9300_H_ 18 #define _ATH_AR9300_H_ 19 20 #include "ar9300_freebsd_inc.h" 21 22 #define AH_BIG_ENDIAN 4321 23 #define AH_LITTLE_ENDIAN 1234 24 25 #if _BYTE_ORDER == _BIG_ENDIAN 26 #define AH_BYTE_ORDER AH_BIG_ENDIAN 27 #else 28 #define AH_BYTE_ORDER AH_LITTLE_ENDIAN 29 #endif 30 31 /* XXX doesn't belong here */ 32 #define AR_EEPROM_MODAL_SPURS 5 33 34 /* 35 * (a) this should be N(a), 36 * (b) FreeBSD does define nitems, 37 * (c) it doesn't have an AH_ prefix, sigh. 38 */ 39 #define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) 40 41 #include "ah_internal.h" 42 #include "ah_eeprom.h" 43 #include "ah_devid.h" 44 #include "ar9300eep.h" /* For Eeprom definitions */ 45 46 47 #define AR9300_MAGIC 0x19741014 48 49 50 /* MAC register values */ 51 52 #define INIT_CONFIG_STATUS 0x00000000 53 #define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 54 #define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ 55 56 /* 57 * Various fifo fill before Tx start, in 64-byte units 58 * i.e. put the frame in the air while still DMAing 59 */ 60 #define MIN_TX_FIFO_THRESHOLD 0x1 61 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) 62 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 63 64 #define CHANSEL_DIV 15 65 #define FCLK 40 66 67 #define COEFF ((FCLK * 5) / 2) 68 #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 69 #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 70 #define CHANSEL_5G_DOT5MHZ 2188 71 72 /* 73 * Receive Queue Fifo depth. 74 */ 75 enum RX_FIFO_DEPTH { 76 HAL_HP_RXFIFO_DEPTH = 16, 77 HAL_LP_RXFIFO_DEPTH = 128, 78 }; 79 80 /* 81 * Gain support. 82 */ 83 #define NUM_CORNER_FIX_BITS_2133 7 84 #define CCK_OFDM_GAIN_DELTA 15 85 86 enum GAIN_PARAMS { 87 GP_TXCLIP, 88 GP_PD90, 89 GP_PD84, 90 GP_GSEL 91 }; 92 93 enum GAIN_PARAMS_2133 { 94 GP_MIXGAIN_OVR, 95 GP_PWD_138, 96 GP_PWD_137, 97 GP_PWD_136, 98 GP_PWD_132, 99 GP_PWD_131, 100 GP_PWD_130, 101 }; 102 103 enum { 104 HAL_RESET_POWER_ON, 105 HAL_RESET_WARM, 106 HAL_RESET_COLD, 107 }; 108 109 typedef struct _gain_opt_step { 110 int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; 111 int32_t stepGain; 112 int8_t stepName[16]; 113 } GAIN_OPTIMIZATION_STEP; 114 115 typedef struct { 116 u_int32_t numStepsInLadder; 117 u_int32_t defaultStepNum; 118 GAIN_OPTIMIZATION_STEP optStep[10]; 119 } GAIN_OPTIMIZATION_LADDER; 120 121 typedef struct { 122 u_int32_t currStepNum; 123 u_int32_t currGain; 124 u_int32_t targetGain; 125 u_int32_t loTrig; 126 u_int32_t hiTrig; 127 u_int32_t gainFCorrection; 128 u_int32_t active; 129 GAIN_OPTIMIZATION_STEP *curr_step; 130 } GAIN_VALUES; 131 132 typedef struct { 133 u_int16_t synth_center; 134 u_int16_t ctl_center; 135 u_int16_t ext_center; 136 } CHAN_CENTERS; 137 138 /* RF HAL structures */ 139 typedef struct rf_hal_funcs { 140 HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); 141 HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, 142 struct ieee80211_channel *chan); 143 } RF_HAL_FUNCS; 144 145 struct ar9300_ani_default { 146 u_int16_t m1_thresh_low; 147 u_int16_t m2_thresh_low; 148 u_int16_t m1_thresh; 149 u_int16_t m2_thresh; 150 u_int16_t m2_count_thr; 151 u_int16_t m2_count_thr_low; 152 u_int16_t m1_thresh_low_ext; 153 u_int16_t m2_thresh_low_ext; 154 u_int16_t m1_thresh_ext; 155 u_int16_t m2_thresh_ext; 156 u_int16_t firstep; 157 u_int16_t firstep_low; 158 u_int16_t cycpwr_thr1; 159 u_int16_t cycpwr_thr1_ext; 160 }; 161 162 /* 163 * Per-channel ANI state private to the driver. 164 */ 165 struct ar9300_ani_state { 166 struct ieee80211_channel c; /* XXX ew? */ 167 HAL_BOOL must_restore; 168 HAL_BOOL ofdms_turn; 169 u_int8_t ofdm_noise_immunity_level; 170 u_int8_t cck_noise_immunity_level; 171 u_int8_t spur_immunity_level; 172 u_int8_t firstep_level; 173 u_int8_t ofdm_weak_sig_detect_off; 174 u_int8_t mrc_cck_off; 175 176 /* Thresholds */ 177 u_int32_t listen_time; 178 u_int32_t ofdm_trig_high; 179 u_int32_t ofdm_trig_low; 180 int32_t cck_trig_high; 181 int32_t cck_trig_low; 182 int32_t rssi_thr_low; 183 int32_t rssi_thr_high; 184 185 int32_t rssi; /* The current RSSI */ 186 u_int32_t tx_frame_count; /* Last tx_frame_count */ 187 u_int32_t rx_frame_count; /* Last rx Frame count */ 188 u_int32_t rx_busy_count; /* Last rx busy count */ 189 u_int32_t rx_ext_busy_count; /* Last rx busy count; extension channel */ 190 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ 191 u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ 192 u_int32_t cck_phy_err_count; /* CCK err count since last reset */ 193 194 struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ 195 HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ 196 }; 197 198 #define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ 199 200 #define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ 201 202 #define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ 203 #define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ 204 #define HAL_AR_EN 0x40000000 /* AR detect is capable */ 205 206 #define DO_ANI(ah) \ 207 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) 208 209 #if 0 210 struct ar9300_stats { 211 u_int32_t ast_ani_niup; /* ANI increased noise immunity */ 212 u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ 213 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ 214 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 215 u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 216 u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 217 u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 218 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 219 u_int32_t ast_ani_stepup; /* ANI increased first step level */ 220 u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ 221 u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 222 u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 223 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 224 u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ 225 u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 226 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 227 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 228 }; 229 #endif 230 231 struct ar9300_rad_reader { 232 u_int16_t rd_index; 233 u_int16_t rd_expSeq; 234 u_int32_t rd_resetVal; 235 u_int8_t rd_start; 236 }; 237 238 struct ar9300_rad_writer { 239 u_int16_t wr_index; 240 u_int16_t wr_seq; 241 }; 242 243 struct ar9300_radar_event { 244 u_int32_t re_ts; /* 32 bit time stamp */ 245 u_int8_t re_rssi; /* rssi of radar event */ 246 u_int8_t re_dur; /* duration of radar pulse */ 247 u_int8_t re_chanIndex; /* Channel of event */ 248 }; 249 250 struct ar9300_radar_q_elem { 251 u_int32_t rq_seqNum; 252 u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ 253 struct ar9300_radar_event rq_event; /* Radar event */ 254 }; 255 256 struct ar9300_radar_q_info { 257 u_int16_t ri_qsize; /* q size */ 258 u_int16_t ri_seqSize; /* Size of sequence ring */ 259 struct ar9300_rad_reader ri_reader; /* State for the q reader */ 260 struct ar9300_rad_writer ri_writer; /* state for the q writer */ 261 }; 262 263 #define HAL_MAX_ACK_RADAR_DUR 511 264 #define HAL_MAX_NUM_PEAKS 3 265 #define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ 266 #define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ 267 #define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ 268 #define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ 269 #define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ 270 271 struct ar9300_ar_state { 272 u_int16_t ar_prev_time_stamp; 273 u_int32_t ar_prev_width; 274 u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; 275 u_int32_t ar_ack_sum; 276 u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; 277 u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ 278 u_int32_t ar_par_threshold; /* Thresh to determine peak */ 279 u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ 280 }; 281 282 struct ar9300_radar_state { 283 struct ieee80211_channel *rs_chan; /* Channel info */ 284 u_int8_t rs_chan_index; /* Channel index in radar structure */ 285 u_int32_t rs_num_radar_events; /* Number of radar events */ 286 int32_t rs_firpwr; /* Thresh to check radar sig is gone */ 287 u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ 288 u_int32_t rs_height; /* Thresh for pulse height (dB)*/ 289 u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ 290 u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ 291 }; 292 typedef struct { 293 u_int8_t uc_receiver_errors; 294 u_int8_t uc_bad_tlp_errors; 295 u_int8_t uc_bad_dllp_errors; 296 u_int8_t uc_replay_timeout_errors; 297 u_int8_t uc_replay_number_rollover_errors; 298 } ar_pcie_error_moniter_counters; 299 300 #define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ 301 #define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ 302 #define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ 303 #define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ 304 #define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ 305 #define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ 306 307 /* 308 * For Kite and later chipsets, the following bits are not being programmed in EEPROM 309 * and so need to be enabled always. 310 * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 311 * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 312 */ 313 #define AR9300_RDEXT_DEFAULT 0x1F 314 315 #define AR9300_MAX_CHAINS 3 316 #define AR9300_NUM_CHAINS(chainmask) \ 317 (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) 318 #define AR9300_CHAIN0_MASK 0x1 319 #define AR9300_CHAIN1_MASK 0x2 320 #define AR9300_CHAIN2_MASK 0x4 321 322 /* Support for multiple INIs */ 323 struct ar9300_ini_array { 324 const u_int32_t *ia_array; 325 u_int32_t ia_rows; 326 u_int32_t ia_columns; 327 }; 328 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 329 (iniarray)->ia_array = (const u_int32_t *)(array); \ 330 (iniarray)->ia_rows = (rows); \ 331 (iniarray)->ia_columns = (columns); \ 332 } while (0) 333 #define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 334 335 #define INIT_CAL(_perCal) \ 336 (_perCal)->cal_state = CAL_WAITING; \ 337 (_perCal)->cal_next = AH_NULL; 338 339 #define INSERT_CAL(_ahp, _perCal) \ 340 do { \ 341 if ((_ahp)->ah_cal_list_last == AH_NULL) { \ 342 (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ 343 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 344 } else { \ 345 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 346 (_ahp)->ah_cal_list_last = (_perCal); \ 347 (_perCal)->cal_next = (_ahp)->ah_cal_list; \ 348 } \ 349 } while (0) 350 351 typedef enum cal_types { 352 IQ_MISMATCH_CAL = 0x1, 353 TEMP_COMP_CAL = 0x2, 354 } HAL_CAL_TYPES; 355 356 typedef enum cal_state { 357 CAL_INACTIVE, 358 CAL_WAITING, 359 CAL_RUNNING, 360 CAL_DONE 361 } HAL_CAL_STATE; /* Calibrate state */ 362 363 #define MIN_CAL_SAMPLES 1 364 #define MAX_CAL_SAMPLES 64 365 #define INIT_LOG_COUNT 5 366 #define PER_MIN_LOG_COUNT 2 367 #define PER_MAX_LOG_COUNT 10 368 369 #define AR9300_NUM_BT_WEIGHTS 4 370 #define AR9300_NUM_WLAN_WEIGHTS 4 371 372 /* Per Calibration data structure */ 373 typedef struct per_cal_data { 374 HAL_CAL_TYPES cal_type; // Type of calibration 375 u_int32_t cal_num_samples; // Number of SW samples to collect 376 u_int32_t cal_count_max; // Number of HW samples to collect 377 void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func 378 void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func 379 } HAL_PERCAL_DATA; 380 381 /* List structure for calibration data */ 382 typedef struct cal_list { 383 const HAL_PERCAL_DATA *cal_data; 384 HAL_CAL_STATE cal_state; 385 struct cal_list *cal_next; 386 } HAL_CAL_LIST; 387 388 #define AR9300_NUM_CAL_TYPES 2 389 #define AR9300_PAPRD_TABLE_SZ 24 390 #define AR9300_PAPRD_GAIN_TABLE_SZ 32 391 #define AR9382_MAX_GPIO_PIN_NUM (16) 392 #define AR9382_GPIO_PIN_8_RESERVED (8) 393 #define AR9382_GPIO_9_INPUT_ONLY (9) 394 #define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) 395 #define AR9382_GPIO_PIN_11_RESERVED (11) 396 #define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) 397 398 /* Paprd tx power adjust data structure */ 399 struct ar9300_paprd_pwr_adjust { 400 u_int32_t target_rate; // rate index 401 u_int32_t reg_addr; // register offset 402 u_int32_t reg_mask; // mask of register 403 u_int32_t reg_mask_offset; // mask offset of register 404 u_int32_t sub_db; // offset value unit of dB 405 }; 406 407 struct ar9300NfLimits { 408 int16_t max; 409 int16_t min; 410 int16_t nominal; 411 }; 412 413 #define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ 414 struct ath_hal_9300 { 415 struct ath_hal_private ah_priv; /* base class */ 416 417 /* 418 * Information retrieved from EEPROM. 419 */ 420 ar9300_eeprom_t ah_eeprom; 421 422 GAIN_VALUES ah_gain_values; 423 424 u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; 425 u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 426 u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; 427 u_int16_t ah_assoc_id; 428 429 /* 430 * Runtime state. 431 */ 432 u_int32_t ah_mask_reg; /* copy of AR_IMR */ 433 u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ 434 u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ 435 os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ 436 HAL_ANI_STATS ah_stats; /* various statistics */ 437 RF_HAL_FUNCS ah_rf_hal; 438 u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ 439 u_int32_t ah_tx_ok_interrupt_mask; 440 u_int32_t ah_tx_err_interrupt_mask; 441 u_int32_t ah_tx_desc_interrupt_mask; 442 u_int32_t ah_tx_eol_interrupt_mask; 443 u_int32_t ah_tx_urn_interrupt_mask; 444 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 445 HAL_SMPS_MODE ah_sm_power_mode; 446 HAL_BOOL ah_chip_full_sleep; 447 u_int32_t ah_atim_window; 448 HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ 449 u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ 450 u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ 451 u_int8_t ah_rx_chainmask_cfg; 452 u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ 453 /* Calibration related fields */ 454 HAL_CAL_TYPES ah_supp_cals; 455 HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ 456 HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ 457 HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ 458 HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ 459 HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ 460 // IQ Cal aliases 461 #define ah_total_power_meas_i ah_meas0.unsign 462 #define ah_total_power_meas_q ah_meas1.unsign 463 #define ah_total_iq_corr_meas ah_meas2.sign 464 union { 465 u_int32_t unsign[AR9300_MAX_CHAINS]; 466 int32_t sign[AR9300_MAX_CHAINS]; 467 } ah_meas0; 468 union { 469 u_int32_t unsign[AR9300_MAX_CHAINS]; 470 int32_t sign[AR9300_MAX_CHAINS]; 471 } ah_meas1; 472 union { 473 u_int32_t unsign[AR9300_MAX_CHAINS]; 474 int32_t sign[AR9300_MAX_CHAINS]; 475 } ah_meas2; 476 union { 477 u_int32_t unsign[AR9300_MAX_CHAINS]; 478 int32_t sign[AR9300_MAX_CHAINS]; 479 } ah_meas3; 480 u_int16_t ah_cal_samples; 481 /* end - Calibration related fields */ 482 u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ 483 u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ 484 u_int32_t ah_misc_mode; /* MISC_MODE settings */ 485 HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ 486 enum { 487 AUTO_32KHZ, /* use it if 32kHz crystal present */ 488 USE_32KHZ, /* do it regardless */ 489 DONT_USE_32KHZ, /* don't use it regardless */ 490 } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ 491 492 u_int32_t ah_ofdm_tx_power; 493 int16_t ah_tx_power_index_offset; 494 495 u_int ah_slot_time; /* user-specified slot time */ 496 u_int ah_ack_timeout; /* user-specified ack timeout */ 497 /* 498 * XXX 499 * 11g-specific stuff; belongs in the driver. 500 */ 501 u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ 502 u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ 503 u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ 504 /* 505 * RF Silent handling; setup according to the EEPROM. 506 */ 507 u_int32_t ah_gpio_select; /* GPIO pin to use */ 508 u_int32_t ah_polarity; /* polarity to disable RF */ 509 u_int32_t ah_gpio_bit; /* after init, prev value */ 510 HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ 511 512 #ifdef ATH_BT_COEX 513 /* 514 * Bluetooth coexistence static setup according to the registry 515 */ 516 HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ 517 u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ 518 u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ 519 u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ 520 u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ 521 u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ 522 HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ 523 u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ 524 /* 525 * Bluetooth coexistence runtime settings 526 */ 527 HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ 528 u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 529 u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 530 u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 531 u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 532 u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ 533 #endif 534 535 /* 536 * Generic timer support 537 */ 538 u_int32_t ah_avail_gen_timers; /* mask of available timers */ 539 u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ 540 u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ 541 HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ 542 543 /* 544 * ANI & Radar support. 545 */ 546 u_int32_t ah_proc_phy_err; /* Process Phy errs */ 547 u_int32_t ah_ani_period; /* ani update list period */ 548 struct ar9300_ani_state *ah_curani; /* cached last reference */ 549 struct ar9300_ani_state ah_ani[255]; /* per-channel state */ 550 struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ 551 struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ 552 struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ 553 struct ar9300_ar_state ah_ar; /* AR detector state */ 554 struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ 555 struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ 556 557 /* 558 * Transmit power state. Note these are maintained 559 * here so they can be retrieved by diagnostic tools. 560 */ 561 u_int16_t ah_rates_array[16]; 562 563 /* 564 * Tx queue interrupt state. 565 */ 566 u_int32_t ah_intr_txqs; 567 568 HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ 569 HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ 570 571 /* 572 * Extension Channel Rx Clear State 573 */ 574 u_int32_t ah_cycle_count; 575 u_int32_t ah_ctl_busy; 576 u_int32_t ah_ext_busy; 577 578 /* HT CWM state */ 579 HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; 580 u_int8_t ah_tx_chainmask; /* tx chain mask */ 581 u_int8_t ah_rx_chainmask; /* rx chain mask */ 582 583 /* optional tx chainmask */ 584 u_int8_t ah_tx_chainmaskopt; 585 586 u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ 587 u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ 588 589 int ah_hwp; 590 void *ah_cal_mem; 591 HAL_BOOL ah_emu_eeprom; 592 593 HAL_ANI_CMD ah_ani_function; 594 HAL_BOOL ah_rifs_enabled; 595 u_int32_t ah_rifs_reg[11]; 596 u_int32_t ah_rifs_sec_cnt; 597 598 /* open-loop power control */ 599 u_int32_t original_gain[22]; 600 int32_t init_pdadc; 601 int32_t pdadc_delta; 602 603 /* cycle counts for beacon stuck diagnostics */ 604 u_int32_t ah_cycles; 605 u_int32_t ah_rx_clear; 606 u_int32_t ah_rx_frame; 607 u_int32_t ah_tx_frame; 608 609 #define BB_HANG_SIG1 0 610 #define BB_HANG_SIG2 1 611 #define BB_HANG_SIG3 2 612 #define BB_HANG_SIG4 3 613 #define MAC_HANG_SIG1 4 614 #define MAC_HANG_SIG2 5 615 /* bb hang detection */ 616 int ah_hang[6]; 617 hal_hw_hangs_t ah_hang_wars; 618 619 /* 620 * Keytable type table 621 */ 622 #define AR_KEYTABLE_SIZE 128 /* XXX! */ 623 uint8_t ah_keytype[AR_KEYTABLE_SIZE]; 624 #undef AR_KEYTABLE_SIZE 625 /* 626 * Support for ar9300 multiple INIs 627 */ 628 struct ar9300_ini_array ah_ini_pcie_serdes; 629 struct ar9300_ini_array ah_ini_pcie_serdes_low_power; 630 struct ar9300_ini_array ah_ini_modes_additional; 631 struct ar9300_ini_array ah_ini_modes_additional_40mhz; 632 struct ar9300_ini_array ah_ini_modes_rxgain; 633 struct ar9300_ini_array ah_ini_modes_rxgain_bounds; 634 struct ar9300_ini_array ah_ini_modes_txgain; 635 struct ar9300_ini_array ah_ini_japan2484; 636 struct ar9300_ini_array ah_ini_radio_post_sys2ant; 637 struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; 638 /* 639 * New INI format starting with Osprey 2.0 INI. 640 * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) 641 */ 642 #define ATH_INI_PRE 0 643 #define ATH_INI_CORE 1 644 #define ATH_INI_POST 2 645 #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) 646 struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ 647 struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ 648 struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ 649 struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ 650 651 /* 652 * Added to support DFS postamble array in INI that we need to apply 653 * in DFS channels 654 */ 655 656 struct ar9300_ini_array ah_ini_dfs; 657 658 #if ATH_WOW 659 struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ 660 #endif 661 662 /* To indicate EEPROM mapping used */ 663 u_int32_t ah_immunity_vals[6]; 664 HAL_BOOL ah_immunity_on; 665 /* 666 * snap shot of counter register for debug purposes 667 */ 668 #ifdef AH_DEBUG 669 u_int32_t last_tf; 670 u_int32_t last_rf; 671 u_int32_t last_rc; 672 u_int32_t last_cc; 673 #endif 674 HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ 675 u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ 676 677 u_int32_t reg_dmn; /* Regulatory Domain */ 678 int16_t twice_antenna_gain; /* Antenna Gain */ 679 u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ 680 681 /* 682 * Upper limit after factoring in the regulatory max, antenna gain and 683 * multichain factor. No TxBF, CDD or STBC gain factored 684 */ 685 int16_t upper_limit[AR9300_MAX_CHAINS]; 686 687 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ 688 int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 689 690 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ 691 int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 692 693 /* Transmit Status ring support */ 694 struct ar9300_txs *ts_ring; 695 u_int16_t ts_tail; 696 u_int16_t ts_size; 697 u_int32_t ts_paddr_start; 698 u_int32_t ts_paddr_end; 699 700 /* Receive Buffer size */ 701 #define HAL_RXBUFSIZE_DEFAULT 0xfff 702 u_int16_t rx_buf_size; 703 704 u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). 705 706 /* Indicate the PLL source clock rate is 25Mhz or not. 707 * clk_25mhz = 0 by default. 708 */ 709 u_int8_t clk_25mhz; 710 /* For PAPRD uses */ 711 u_int16_t small_signal_gain[AH_MAX_CHAINS]; 712 u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; 713 u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; 714 u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; 715 u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ 716 u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ 717 u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ 718 u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ 719 u_int32_t paprd_training_power; 720 /* For GreenTx use to store the default tx power */ 721 u_int8_t ah_default_tx_power[ar9300_rate_size]; 722 HAL_BOOL ah_paprd_broken; 723 724 /* To store offsets of host interface registers */ 725 struct { 726 u_int32_t AR_RC; 727 u_int32_t AR_WA; 728 u_int32_t AR_PM_STATE; 729 u_int32_t AR_H_INFOL; 730 u_int32_t AR_H_INFOH; 731 u_int32_t AR_PCIE_PM_CTRL; 732 u_int32_t AR_HOST_TIMEOUT; 733 u_int32_t AR_EEPROM; 734 u_int32_t AR_SREV; 735 u_int32_t AR_INTR_SYNC_CAUSE; 736 u_int32_t AR_INTR_SYNC_CAUSE_CLR; 737 u_int32_t AR_INTR_SYNC_ENABLE; 738 u_int32_t AR_INTR_ASYNC_MASK; 739 u_int32_t AR_INTR_SYNC_MASK; 740 u_int32_t AR_INTR_ASYNC_CAUSE_CLR; 741 u_int32_t AR_INTR_ASYNC_CAUSE; 742 u_int32_t AR_INTR_ASYNC_ENABLE; 743 u_int32_t AR_PCIE_SERDES; 744 u_int32_t AR_PCIE_SERDES2; 745 u_int32_t AR_GPIO_OUT; 746 u_int32_t AR_GPIO_IN; 747 u_int32_t AR_GPIO_OE_OUT; 748 u_int32_t AR_GPIO_OE1_OUT; 749 u_int32_t AR_GPIO_INTR_POL; 750 u_int32_t AR_GPIO_INPUT_EN_VAL; 751 u_int32_t AR_GPIO_INPUT_MUX1; 752 u_int32_t AR_GPIO_INPUT_MUX2; 753 u_int32_t AR_GPIO_OUTPUT_MUX1; 754 u_int32_t AR_GPIO_OUTPUT_MUX2; 755 u_int32_t AR_GPIO_OUTPUT_MUX3; 756 u_int32_t AR_INPUT_STATE; 757 u_int32_t AR_SPARE; 758 u_int32_t AR_PCIE_CORE_RESET_EN; 759 u_int32_t AR_CLKRUN; 760 u_int32_t AR_EEPROM_STATUS_DATA; 761 u_int32_t AR_OBS; 762 u_int32_t AR_RFSILENT; 763 u_int32_t AR_GPIO_PDPU; 764 u_int32_t AR_GPIO_DS; 765 u_int32_t AR_MISC; 766 u_int32_t AR_PCIE_MSI; 767 u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; 768 u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; 769 u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; 770 u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; 771 u_int32_t AR_TDMA_CCA_CNTL; 772 u_int32_t AR_TXAPSYNC; 773 u_int32_t AR_TXSYNC_INIT_SYNC_TMR; 774 u_int32_t AR_INTR_PRIO_SYNC_CAUSE; 775 u_int32_t AR_INTR_PRIO_SYNC_ENABLE; 776 u_int32_t AR_INTR_PRIO_ASYNC_MASK; 777 u_int32_t AR_INTR_PRIO_SYNC_MASK; 778 u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; 779 u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; 780 } ah_hostifregs; 781 782 u_int32_t ah_enterprise_mode; 783 u_int32_t ah_radar1; 784 u_int32_t ah_dc_offset; 785 HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ 786 HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ 787 u_int32_t ah_disable_cck; 788 HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ 789 790 791 /* 792 * Different types of memory where the calibration data might be stored. 793 * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. 794 * To disable searching a type, set its parameter to 0. 795 */ 796 int try_dram; 797 int try_flash; 798 int try_eeprom; 799 int try_otp; 800 #ifdef ATH_CAL_NAND_FLASH 801 int try_nand; 802 #endif 803 /* 804 * This is where we found the calibration data. 805 */ 806 int calibration_data_source; 807 int calibration_data_source_address; 808 /* 809 * This is where we look for the calibration data. must be set before ath_attach() is called 810 */ 811 int calibration_data_try; 812 int calibration_data_try_address; 813 u_int8_t 814 tx_iq_cal_enable : 1, 815 tx_iq_cal_during_agc_cal : 1, 816 tx_cl_cal_enable : 1; 817 818 #if ATH_SUPPORT_MCI 819 /* For MCI */ 820 HAL_BOOL ah_mci_ready; 821 u_int32_t ah_mci_int_raw; 822 u_int32_t ah_mci_int_rx_msg; 823 u_int32_t ah_mci_rx_status; 824 u_int32_t ah_mci_cont_status; 825 u_int8_t ah_mci_bt_state; 826 u_int32_t ah_mci_gpm_addr; 827 u_int8_t *ah_mci_gpm_buf; 828 u_int32_t ah_mci_gpm_len; 829 u_int32_t ah_mci_gpm_idx; 830 u_int32_t ah_mci_sched_addr; 831 u_int8_t *ah_mci_sched_buf; 832 u_int8_t ah_mci_coex_major_version_wlan; 833 u_int8_t ah_mci_coex_minor_version_wlan; 834 u_int8_t ah_mci_coex_major_version_bt; 835 u_int8_t ah_mci_coex_minor_version_bt; 836 HAL_BOOL ah_mci_coex_bt_version_known; 837 HAL_BOOL ah_mci_coex_wlan_channels_update; 838 u_int32_t ah_mci_coex_wlan_channels[4]; 839 HAL_BOOL ah_mci_coex_2g5g_update; 840 HAL_BOOL ah_mci_coex_is_2g; 841 HAL_BOOL ah_mci_query_bt; 842 HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ 843 HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ 844 HAL_BOOL ah_mci_need_flush_btinfo; 845 HAL_BOOL ah_mci_concur_tx_en; 846 u_int8_t ah_mci_stomp_low_tx_pri; 847 u_int8_t ah_mci_stomp_all_tx_pri; 848 u_int8_t ah_mci_stomp_none_tx_pri; 849 u_int32_t ah_mci_wlan_cal_seq; 850 u_int32_t ah_mci_wlan_cal_done; 851 #if ATH_SUPPORT_AIC 852 HAL_BOOL ah_aic_enabled; 853 u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; 854 #endif 855 856 #endif /* ATH_SUPPORT_MCI */ 857 u_int8_t ah_cac_quiet_enabled; 858 #if ATH_WOW_OFFLOAD 859 u_int32_t ah_mcast_filter_l32_set; 860 u_int32_t ah_mcast_filter_u32_set; 861 #endif 862 HAL_BOOL ah_reduced_self_gen_mask; 863 HAL_BOOL ah_chip_reset_done; 864 HAL_BOOL ah_abort_txdma_norx; 865 /* store previous passive RX Cal info */ 866 HAL_BOOL ah_skip_rx_iq_cal; 867 HAL_BOOL ah_rx_cal_complete; /* previous rx cal completed or not */ 868 u_int32_t ah_rx_cal_chan; /* chan on which rx cal is done */ 869 u_int32_t ah_rx_cal_chan_flag; 870 u_int32_t ah_rx_cal_corr[AR9300_MAX_CHAINS]; 871 872 /* Local additions for FreeBSD */ 873 /* 874 * These fields are in the top level HAL in the atheros 875 * codebase; here we place them in the AR9300 HAL and 876 * access them via accessor methods if the driver requires them. 877 */ 878 u_int32_t ah_ob_db1[3]; 879 u_int32_t ah_db2[3]; 880 u_int32_t ah_bb_panic_timeout_ms; 881 u_int32_t ah_bb_panic_last_status; 882 u_int32_t ah_tx_trig_level; 883 u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; 884 int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ 885 int ah_phyrestart_disabled; 886 HAL_RSSI_TX_POWER green_tx_status; 887 int green_ap_ps_on; 888 int ah_enable_keysearch_always; 889 int ah_fccaifs; 890 int ah_reset_reason; 891 int ah_dcs_enable; 892 HAL_ANI_STATE ext_ani_state; /* FreeBSD; external facing ANI state */ 893 894 struct ar9300NfLimits nf_2GHz; 895 struct ar9300NfLimits nf_5GHz; 896 struct ar9300NfLimits *nfp; 897 }; 898 899 #define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) 900 901 #define IS_9300_EMU(ah) \ 902 (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) 903 904 #define ar9300_eep_data_in_flash(_ah) \ 905 (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) 906 907 #ifdef notyet 908 // Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. 909 && \ 910 ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ 911 (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) 912 #endif 913 914 /* 915 * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows 916 * other cards' DMA reads to complete in the middle of our reset. 917 */ 918 #define WAR_6773(x) do { \ 919 if ((++(x) % 64) == 0) \ 920 OS_DELAY(1); \ 921 } while (0) 922 923 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 924 int r; \ 925 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 926 OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ 927 WAR_6773(regWr); \ 928 } \ 929 } while (0) 930 931 #define UPPER_5G_SUB_BANDSTART 5700 932 #define MID_5G_SUB_BANDSTART 5400 933 #define TRAINPOWER_DB_OFFSET 6 934 935 #define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ 936 } else { \ 937 if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ 938 else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ 939 { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ 940 else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) 941 942 #ifdef AH_ASSERT 943 #define ar9300FeatureNotSupported(feature, ah, func) \ 944 ath_hal_printf(ah, # feature \ 945 " not supported but called from %s\n", (func)), \ 946 hal_assert(0) 947 #else 948 #define ar9300FeatureNotSupported(feature, ah, func) \ 949 ath_hal_printf(ah, # feature \ 950 " not supported but called from %s\n", (func)) 951 #endif /* AH_ASSERT */ 952 953 /* 954 * Green Tx, Based on different RSSI of Received Beacon thresholds, 955 * using different tx power by modified register tx power related values. 956 * The thresholds are decided by system team. 957 */ 958 #define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ 959 #define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ 960 #define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta 961 Calibration Offset */ 962 #define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value 963 in short distance*/ 964 #define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value 965 in middle distance */ 966 #define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value 967 in long distance */ 968 #define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx 969 BB_powertx_rate9 reg 970 value in short 971 distance */ 972 #define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx 973 BB_powertx_rate9 reg 974 value in middle 975 distance */ 976 977 978 /* Tx power for short distacnce in SwGreenTx.*/ 979 static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 980 6, /*ALL_TARGET_LEGACY_6_24*/ 981 6, /*ALL_TARGET_LEGACY_36*/ 982 6, /*ALL_TARGET_LEGACY_48*/ 983 4, /*ALL_TARGET_LEGACY_54*/ 984 6, /*ALL_TARGET_LEGACY_1L_5L*/ 985 6, /*ALL_TARGET_LEGACY_5S*/ 986 6, /*ALL_TARGET_LEGACY_11L*/ 987 6, /*ALL_TARGET_LEGACY_11S*/ 988 6, /*ALL_TARGET_HT20_0_8_16*/ 989 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 990 4, /*ALL_TARGET_HT20_4*/ 991 4, /*ALL_TARGET_HT20_5*/ 992 4, /*ALL_TARGET_HT20_6*/ 993 2, /*ALL_TARGET_HT20_7*/ 994 0, /*ALL_TARGET_HT20_12*/ 995 0, /*ALL_TARGET_HT20_13*/ 996 0, /*ALL_TARGET_HT20_14*/ 997 0, /*ALL_TARGET_HT20_15*/ 998 0, /*ALL_TARGET_HT20_20*/ 999 0, /*ALL_TARGET_HT20_21*/ 1000 0, /*ALL_TARGET_HT20_22*/ 1001 0, /*ALL_TARGET_HT20_23*/ 1002 6, /*ALL_TARGET_HT40_0_8_16*/ 1003 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1004 4, /*ALL_TARGET_HT40_4*/ 1005 4, /*ALL_TARGET_HT40_5*/ 1006 4, /*ALL_TARGET_HT40_6*/ 1007 2, /*ALL_TARGET_HT40_7*/ 1008 0, /*ALL_TARGET_HT40_12*/ 1009 0, /*ALL_TARGET_HT40_13*/ 1010 0, /*ALL_TARGET_HT40_14*/ 1011 0, /*ALL_TARGET_HT40_15*/ 1012 0, /*ALL_TARGET_HT40_20*/ 1013 0, /*ALL_TARGET_HT40_21*/ 1014 0, /*ALL_TARGET_HT40_22*/ 1015 0 /*ALL_TARGET_HT40_23*/ 1016 }; 1017 1018 /* Tx power for middle distacnce in SwGreenTx.*/ 1019 static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 1020 14, /*ALL_TARGET_LEGACY_6_24*/ 1021 14, /*ALL_TARGET_LEGACY_36*/ 1022 14, /*ALL_TARGET_LEGACY_48*/ 1023 12, /*ALL_TARGET_LEGACY_54*/ 1024 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1025 14, /*ALL_TARGET_LEGACY_5S*/ 1026 14, /*ALL_TARGET_LEGACY_11L*/ 1027 14, /*ALL_TARGET_LEGACY_11S*/ 1028 14, /*ALL_TARGET_HT20_0_8_16*/ 1029 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1030 14, /*ALL_TARGET_HT20_4*/ 1031 14, /*ALL_TARGET_HT20_5*/ 1032 12, /*ALL_TARGET_HT20_6*/ 1033 10, /*ALL_TARGET_HT20_7*/ 1034 0, /*ALL_TARGET_HT20_12*/ 1035 0, /*ALL_TARGET_HT20_13*/ 1036 0, /*ALL_TARGET_HT20_14*/ 1037 0, /*ALL_TARGET_HT20_15*/ 1038 0, /*ALL_TARGET_HT20_20*/ 1039 0, /*ALL_TARGET_HT20_21*/ 1040 0, /*ALL_TARGET_HT20_22*/ 1041 0, /*ALL_TARGET_HT20_23*/ 1042 14, /*ALL_TARGET_HT40_0_8_16*/ 1043 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1044 14, /*ALL_TARGET_HT40_4*/ 1045 14, /*ALL_TARGET_HT40_5*/ 1046 12, /*ALL_TARGET_HT40_6*/ 1047 10, /*ALL_TARGET_HT40_7*/ 1048 0, /*ALL_TARGET_HT40_12*/ 1049 0, /*ALL_TARGET_HT40_13*/ 1050 0, /*ALL_TARGET_HT40_14*/ 1051 0, /*ALL_TARGET_HT40_15*/ 1052 0, /*ALL_TARGET_HT40_20*/ 1053 0, /*ALL_TARGET_HT40_21*/ 1054 0, /*ALL_TARGET_HT40_22*/ 1055 0 /*ALL_TARGET_HT40_23*/ 1056 }; 1057 1058 /* OLPC DeltaCalibration Offset unit in half dB.*/ 1059 static const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 1060 0, /* OB0*/ 1061 16, /* OB1*/ 1062 9, /* OB2*/ 1063 5, /* OB3*/ 1064 2, /* OB4*/ 1065 0, /* OB5*/ 1066 }; 1067 1068 /* 1069 * Definitions for HwGreenTx 1070 */ 1071 #define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ 1072 #define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ 1073 #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx 1074 BB_powertx_rate9 reg 1075 value in short 1076 distance */ 1077 #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx 1078 BB_powertx_rate9 reg 1079 value in middle 1080 distance */ 1081 1082 /* Tx power for short distacnce in HwGreenTx.*/ 1083 static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 1084 14, /*ALL_TARGET_LEGACY_6_24*/ 1085 14, /*ALL_TARGET_LEGACY_36*/ 1086 8, /*ALL_TARGET_LEGACY_48*/ 1087 2, /*ALL_TARGET_LEGACY_54*/ 1088 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1089 14, /*ALL_TARGET_LEGACY_5S*/ 1090 14, /*ALL_TARGET_LEGACY_11L*/ 1091 14, /*ALL_TARGET_LEGACY_11S*/ 1092 12, /*ALL_TARGET_HT20_0_8_16*/ 1093 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1094 12, /*ALL_TARGET_HT20_4*/ 1095 12, /*ALL_TARGET_HT20_5*/ 1096 8, /*ALL_TARGET_HT20_6*/ 1097 2, /*ALL_TARGET_HT20_7*/ 1098 0, /*ALL_TARGET_HT20_12*/ 1099 0, /*ALL_TARGET_HT20_13*/ 1100 0, /*ALL_TARGET_HT20_14*/ 1101 0, /*ALL_TARGET_HT20_15*/ 1102 0, /*ALL_TARGET_HT20_20*/ 1103 0, /*ALL_TARGET_HT20_21*/ 1104 0, /*ALL_TARGET_HT20_22*/ 1105 0, /*ALL_TARGET_HT20_23*/ 1106 10, /*ALL_TARGET_HT40_0_8_16*/ 1107 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1108 10, /*ALL_TARGET_HT40_4*/ 1109 10, /*ALL_TARGET_HT40_5*/ 1110 6, /*ALL_TARGET_HT40_6*/ 1111 2, /*ALL_TARGET_HT40_7*/ 1112 0, /*ALL_TARGET_HT40_12*/ 1113 0, /*ALL_TARGET_HT40_13*/ 1114 0, /*ALL_TARGET_HT40_14*/ 1115 0, /*ALL_TARGET_HT40_15*/ 1116 0, /*ALL_TARGET_HT40_20*/ 1117 0, /*ALL_TARGET_HT40_21*/ 1118 0, /*ALL_TARGET_HT40_22*/ 1119 0 /*ALL_TARGET_HT40_23*/ 1120 }; 1121 1122 /* Tx power for middle distacnce in HwGreenTx.*/ 1123 static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 1124 18, /*ALL_TARGET_LEGACY_6_24*/ 1125 18, /*ALL_TARGET_LEGACY_36*/ 1126 14, /*ALL_TARGET_LEGACY_48*/ 1127 12, /*ALL_TARGET_LEGACY_54*/ 1128 18, /*ALL_TARGET_LEGACY_1L_5L*/ 1129 18, /*ALL_TARGET_LEGACY_5S*/ 1130 18, /*ALL_TARGET_LEGACY_11L*/ 1131 18, /*ALL_TARGET_LEGACY_11S*/ 1132 16, /*ALL_TARGET_HT20_0_8_16*/ 1133 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1134 16, /*ALL_TARGET_HT20_4*/ 1135 16, /*ALL_TARGET_HT20_5*/ 1136 14, /*ALL_TARGET_HT20_6*/ 1137 12, /*ALL_TARGET_HT20_7*/ 1138 0, /*ALL_TARGET_HT20_12*/ 1139 0, /*ALL_TARGET_HT20_13*/ 1140 0, /*ALL_TARGET_HT20_14*/ 1141 0, /*ALL_TARGET_HT20_15*/ 1142 0, /*ALL_TARGET_HT20_20*/ 1143 0, /*ALL_TARGET_HT20_21*/ 1144 0, /*ALL_TARGET_HT20_22*/ 1145 0, /*ALL_TARGET_HT20_23*/ 1146 14, /*ALL_TARGET_HT40_0_8_16*/ 1147 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1148 14, /*ALL_TARGET_HT40_4*/ 1149 14, /*ALL_TARGET_HT40_5*/ 1150 14, /*ALL_TARGET_HT40_6*/ 1151 12, /*ALL_TARGET_HT40_7*/ 1152 0, /*ALL_TARGET_HT40_12*/ 1153 0, /*ALL_TARGET_HT40_13*/ 1154 0, /*ALL_TARGET_HT40_14*/ 1155 0, /*ALL_TARGET_HT40_15*/ 1156 0, /*ALL_TARGET_HT40_20*/ 1157 0, /*ALL_TARGET_HT40_21*/ 1158 0, /*ALL_TARGET_HT40_22*/ 1159 0 /*ALL_TARGET_HT40_23*/ 1160 }; 1161 1162 /* MIMO Modes used in TPC calculations */ 1163 typedef enum { 1164 AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ 1165 AR9300_TXBF_MODE, 1166 AR9300_STBC_MODE 1167 } AR9300_TXMODES; 1168 typedef enum { 1169 POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ 1170 POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1171 POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in 1172 * BB_powertx_rate9 reg 1173 */ 1174 POSEIDON_STORED_REG_SZ /* Can not add anymore */ 1175 } POSEIDON_STORED_REGS; 1176 1177 typedef enum { 1178 POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ 1179 POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ 1180 } POSEIDON_STORED_REGS_G2; 1181 1182 #if AH_NEED_TX_DATA_SWAP 1183 #if AH_NEED_RX_DATA_SWAP 1184 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) 1185 #else 1186 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) 1187 #endif 1188 #elif AH_NEED_RX_DATA_SWAP 1189 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) 1190 #else 1191 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) 1192 #endif 1193 1194 extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); 1195 1196 struct ath_hal; 1197 1198 extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, 1199 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1200 HAL_OPS_CONFIG *ah_config, 1201 HAL_STATUS *status); 1202 extern struct ath_hal * ar9300_attach(u_int16_t devid, 1203 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1204 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status); 1205 extern void ar9300_detach(struct ath_hal *ah); 1206 extern void ar9300_read_revisions(struct ath_hal *ah); 1207 extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); 1208 extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, 1209 u_int16_t flags, u_int16_t *low, u_int16_t *high); 1210 extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); 1211 1212 extern void ar9300_beacon_init(struct ath_hal *ah, 1213 u_int32_t next_beacon, u_int32_t beacon_period, 1214 u_int32_t beacon_period_fraction, HAL_OPMODE opmode); 1215 extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, 1216 const HAL_BEACON_STATE *); 1217 1218 extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); 1219 extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); 1220 extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); 1221 extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); 1222 extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, 1223 HAL_INT_MITIGATION reg, u_int32_t value); 1224 extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, 1225 HAL_INT_MITIGATION reg); 1226 extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); 1227 extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); 1228 extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); 1229 extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, 1230 const struct ieee80211_channel *chan); 1231 1232 extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, 1233 u_int16_t entry, const u_int8_t *mac); 1234 extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1235 const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); 1236 extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); 1237 #if ATH_SUPPORT_KEYPLUMB_WAR 1238 extern HAL_BOOL ar9300_check_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1239 const HAL_KEYVAL *k, int xorKey); 1240 #endif 1241 1242 extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); 1243 extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); 1244 extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); 1245 extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); 1246 extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); 1247 #if 0 1248 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 1249 #endif 1250 extern HAL_BOOL ar9300_ant_swcom_sel(struct ath_hal *ah, u_int8_t ops, 1251 u_int32_t *common_tbl1, u_int32_t *common_tbl2); 1252 extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, 1253 u_int16_t reg_domain, HAL_STATUS *stats); 1254 extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); 1255 extern void ar9300_enable_rf_kill(struct ath_hal *); 1256 extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1257 extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1258 extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); 1259 extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); 1260 extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); 1261 extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); 1262 extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); 1263 extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); 1264 extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); 1265 extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); 1266 extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); 1267 extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); 1268 extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); 1269 extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); 1270 extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 1271 u_int16_t assoc_id); 1272 extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); 1273 extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); 1274 extern int ar9300_ppm_get_trigger(struct ath_hal *); 1275 extern u_int32_t ar9300_ppm_force(struct ath_hal *); 1276 extern void ar9300_ppm_un_force(struct ath_hal *); 1277 extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1278 extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); 1279 extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); 1280 extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); 1281 extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); 1282 extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); 1283 extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); 1284 extern void ar9300_reset_tsf(struct ath_hal *ah); 1285 extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); 1286 extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); 1287 extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); 1288 extern void ar9300_update_mib_mac_stats(struct ath_hal *ah); 1289 extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); 1290 extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); 1291 extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); 1292 extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); 1293 extern u_int ar9300_get_def_antenna(struct ath_hal *ah); 1294 extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); 1295 extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, 1296 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 1297 u_int8_t *, u_int8_t *, u_int8_t *); 1298 extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); 1299 extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); 1300 extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); 1301 extern u_int ar9300_get_ack_timeout(struct ath_hal *); 1302 extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 1303 u_int32_t next_start, HAL_QUIET_FLAG flag); 1304 extern void ar9300_set_pcu_config(struct ath_hal *); 1305 extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1306 u_int32_t, u_int32_t *); 1307 extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1308 u_int32_t, u_int32_t, HAL_STATUS *); 1309 extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, 1310 const void *args, u_int32_t argsize, 1311 void **result, u_int32_t *resultsize); 1312 extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 1313 extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); 1314 extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 1315 extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); 1316 extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 1317 extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, 1318 int set_chip); 1319 extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); 1320 extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); 1321 extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); 1322 1323 extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); 1324 1325 extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 1326 u_int16_t assoc_id); 1327 1328 1329 #if ATH_WOW 1330 extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, 1331 u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); 1332 //extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); 1333 extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); 1334 extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, 1335 HAL_BOOL offloadEnable); 1336 #if ATH_WOW_OFFLOAD 1337 /* ARP offload */ 1338 #define WOW_OFFLOAD_ARP_INFO_MAX 2 1339 1340 struct hal_wow_offload_arp_info { 1341 u_int32_t valid; 1342 u_int32_t id; 1343 1344 u_int32_t Flags; 1345 union { 1346 u_int8_t u8[4]; 1347 u_int32_t u32; 1348 } RemoteIPv4Address; 1349 union { 1350 u_int8_t u8[4]; 1351 u_int32_t u32; 1352 } HostIPv4Address; 1353 union { 1354 u_int8_t u8[6]; 1355 u_int32_t u32[2]; 1356 } MacAddress; 1357 }; 1358 1359 /* NS offload */ 1360 #define WOW_OFFLOAD_NS_INFO_MAX 2 1361 1362 struct hal_wow_offload_ns_info { 1363 u_int32_t valid; 1364 u_int32_t id; 1365 1366 u_int32_t Flags; 1367 union { 1368 u_int8_t u8[16]; 1369 u_int32_t u32[4]; 1370 } RemoteIPv6Address; 1371 union { 1372 u_int8_t u8[16]; 1373 u_int32_t u32[4]; 1374 } SolicitedNodeIPv6Address; 1375 union { 1376 u_int8_t u8[6]; 1377 u_int32_t u32[2]; 1378 } MacAddress; 1379 union { 1380 u_int8_t u8[16]; 1381 u_int32_t u32[4]; 1382 } TargetIPv6Addresses[2]; 1383 }; 1384 1385 extern void ar9300_wowoffload_prep(struct ath_hal *ah); 1386 extern void ar9300_wowoffload_post(struct ath_hal *ah); 1387 extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); 1388 extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); 1389 extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); 1390 extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); 1391 extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1392 extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1393 #endif /* ATH_WOW_OFFLOAD */ 1394 #endif 1395 1396 extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, 1397 struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, 1398 u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, 1399 HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); 1400 extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, 1401 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); 1402 extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); 1403 extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); 1404 extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); 1405 extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); 1406 extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); 1407 extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); 1408 extern HAL_BOOL ar9300_disable(struct ath_hal *ah); 1409 extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *); 1410 extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1411 u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); 1412 extern void ar9300_reset_cal_valid(struct ath_hal *ah, 1413 const struct ieee80211_channel *chan, 1414 HAL_BOOL *isIQdone, u_int32_t cal_type); 1415 extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); 1416 extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); 1417 extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); 1418 extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); 1419 extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); 1420 extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); 1421 1422 extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, 1423 u_int16_t extra_txpow, u_int16_t tpc_in_db); 1424 extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, 1425 struct ieee80211_channel *chan, int is_scan); 1426 extern int16_t ar9300_get_nf_from_reg(struct ath_hal *ah, struct ieee80211_channel *chan, int wait_time); 1427 extern int ar9300_get_rx_nf_offset(struct ath_hal *ah, struct ieee80211_channel *chan, int8_t *nf_pwr, int8_t *nf_cal); 1428 extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); 1429 1430 extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); 1431 extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); 1432 extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, 1433 u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); 1434 extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, 1435 const struct ieee80211_channel *chan, 1436 u_int8_t powerPerRate[], 1437 u_int8_t chainmask); 1438 extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, 1439 u_int8_t powerPerRate[]); 1440 extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, 1441 u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); 1442 1443 extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); 1444 extern void ar9300_enable_mib_counters(struct ath_hal *); 1445 extern void ar9300_disable_mib_counters(struct ath_hal *); 1446 extern void ar9300_ani_attach(struct ath_hal *); 1447 extern void ar9300_ani_detach(struct ath_hal *); 1448 extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); 1449 extern HAL_ANI_STATS *ar9300_ani_get_current_stats(struct ath_hal *); 1450 extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); 1451 struct ath_rx_status; 1452 1453 extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); 1454 extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, 1455 const struct ieee80211_channel *, HAL_ANISTATS *); 1456 extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); 1457 extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); 1458 extern void ar9300_enable_tpc(struct ath_hal *); 1459 1460 extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); 1461 extern void ar9300_rx_gain_table_apply(struct ath_hal *ah); 1462 extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); 1463 extern void ar9300_mat_enable(struct ath_hal *ah, int enable); 1464 extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); 1465 extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); 1466 1467 /* BB Panic Watchdog declarations */ 1468 #define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ 1469 #define HAL_BB_PANIC_WD_TMO_HORNET 85 1470 extern void ar9300_config_bb_panic_watchdog(struct ath_hal *); 1471 extern void ar9300_handle_bb_panic(struct ath_hal *); 1472 extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); 1473 extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); 1474 extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); 1475 1476 /* DFS declarations */ 1477 extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); 1478 extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, 1479 u_int64_t nolTime); 1480 extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1481 extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1482 extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); 1483 extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, 1484 u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, 1485 int *numb5radars, HAL_PHYERR_PARAM *pe); 1486 extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); 1487 extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); 1488 extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); 1489 extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); 1490 1491 extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); 1492 extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); 1493 1494 1495 extern void ar9300_mark_phy_inactive(struct ath_hal *ah); 1496 1497 /* Spectral scan declarations */ 1498 extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1499 extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); 1500 extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1501 extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); 1502 extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); 1503 extern void ar9300_start_spectral_scan(struct ath_hal *ah); 1504 extern void ar9300_stop_spectral_scan(struct ath_hal *ah); 1505 extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); 1506 extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); 1507 int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); 1508 int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); 1509 /* End spectral scan declarations */ 1510 1511 /* Raw ADC capture functions */ 1512 extern void ar9300_enable_test_addac_mode(struct ath_hal *ah); 1513 extern void ar9300_disable_test_addac_mode(struct ath_hal *ah); 1514 extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); 1515 extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); 1516 extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); 1517 extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); 1518 1519 extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, 1520 struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); 1521 extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); 1522 1523 extern void ar9300_get_channel_centers(struct ath_hal *ah, 1524 const struct ieee80211_channel *chan, 1525 CHAN_CENTERS *centers); 1526 extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, 1527 const struct ieee80211_channel *chan); 1528 extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, 1529 const struct ieee80211_channel *chan); 1530 extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); 1531 1532 extern void ar9300_dma_reg_dump(struct ath_hal *); 1533 extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); 1534 extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); 1535 extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); 1536 extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); 1537 extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); 1538 1539 #ifdef ATH_BT_COEX 1540 extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); 1541 extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); 1542 extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); 1543 extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1544 extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); 1545 extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); 1546 extern void ar9300_bt_coex_disable(struct ath_hal *ah); 1547 extern int ar9300_bt_coex_enable(struct ath_hal *ah); 1548 extern void ar9300_init_bt_coex(struct ath_hal *ah); 1549 extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1550 extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); 1551 #endif 1552 extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); 1553 extern void ar9300_free_generic_timer(struct ath_hal *ah, int index); 1554 extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, 1555 u_int32_t timer_period); 1556 extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); 1557 extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, 1558 u_int32_t *thresh); 1559 extern void ar9300_start_tsf2(struct ath_hal *ah); 1560 1561 extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); 1562 extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); 1563 extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); 1564 extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); 1565 extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); 1566 extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); 1567 extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); 1568 extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 1569 u_int32_t rssi_threshold); 1570 extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); 1571 extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); 1572 extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, 1573 u_int8_t); 1574 1575 extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); 1576 extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); 1577 extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); 1578 extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); 1579 extern void ar9300_clear_mib_counters(struct ath_hal *ah); 1580 1581 /* EEPROM interface functions */ 1582 /* Common Interface functions */ 1583 extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); 1584 extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); 1585 1586 extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, 1587 ar9300_eeprom_t *p_eep_data, 1588 u_int32_t reg, 1589 u_int32_t val); 1590 1591 extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, 1592 ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, 1593 u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, 1594 u_int16_t twice_max_regulatory_power, u_int16_t power_limit); 1595 extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); 1596 extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); 1597 extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); 1598 extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); 1599 extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 1600 extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); 1601 1602 extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); 1603 extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); 1604 extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); 1605 extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); 1606 extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, 1607 u_int8_t index, u_int16_t *config); 1608 extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); 1609 extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); 1610 extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); 1611 extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); 1612 extern void ar9300_disp_tpc_tables(struct ath_hal *ah); 1613 extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); 1614 extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); 1615 extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); 1616 1617 /* Common EEPROM Help function */ 1618 extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); 1619 extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); 1620 1621 extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); 1622 1623 /* tx_bf interface */ 1624 #define ar9300_init_txbf(ah) 1625 #define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) 1626 #define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 1627 #define ar9300_txbf_save_cv_from_compress( \ 1628 ah, key_idx, mimo_control, compress_rpt) \ 1629 false 1630 #define ar9300_txbf_save_cv_from_non_compress( \ 1631 ah, key_idx, mimo_control, non_compress_rpt) \ 1632 false 1633 #define ar9300_txbf_rc_update( \ 1634 ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ 1635 false 1636 #define ar9300_fill_csi_frame( \ 1637 ah, rx_status, bandwidth, local_h, csi_frame_body) \ 1638 0 1639 #define ar9300_fill_txbf_capabilities(ah) 1640 #define ar9300_get_txbf_capabilities(ah) NULL 1641 #define ar9300_txbf_set_key( \ 1642 ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) 1643 #define ar9300_read_key_cache_mac(ah, entry, mac) false 1644 #define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) 1645 #define ar9300_set_selfgenrate_limit(ah, ts_ratecode) 1646 #define ar9300_reset_lowest_txrate(ah) 1647 #define ar9300_txbf_set_basic_set(ah) 1648 1649 extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); 1650 extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); 1651 1652 1653 1654 #if ATH_SUPPORT_MCI 1655 extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1656 extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); 1657 extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); 1658 extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, 1659 void *gpm_buf, u_int16_t len, 1660 u_int32_t sched_addr); 1661 extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); 1662 extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); 1663 extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); 1664 extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, 1665 u_int32_t flag, u_int32_t *payload, u_int8_t len, 1666 HAL_BOOL wait_done, HAL_BOOL check_bt); 1667 extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, 1668 u_int32_t *mci_int, 1669 u_int32_t *mci_int_rx_msg); 1670 extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); 1671 extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); 1672 extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); 1673 extern void ar9300_mci_mute_bt(struct ath_hal *ah); 1674 extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); 1675 extern void ar9300_mci_enable_interrupt(struct ath_hal *ah); 1676 extern void ar9300_mci_disable_interrupt(struct ath_hal *ah); 1677 extern void ar9300_mci_detach (struct ath_hal *ah); 1678 extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); 1679 extern void ar9300_mci_sync_bt_state (struct ath_hal *ah); 1680 extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); 1681 extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); 1682 #if ATH_SUPPORT_AIC 1683 extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); 1684 extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); 1685 #endif 1686 #endif 1687 1688 extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); 1689 1690 extern HAL_BOOL ar9300_regulatory_domain_override( 1691 struct ath_hal *ah, u_int16_t regdmn); 1692 #if ATH_ANT_DIV_COMB 1693 extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1694 extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1695 #endif /* ATH_ANT_DIV_COMB */ 1696 extern void ar9300_disable_phy_restart(struct ath_hal *ah, 1697 int disable_phy_restart); 1698 extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); 1699 extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); 1700 extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); 1701 extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); 1702 1703 #ifdef ATH_TX99_DIAG 1704 #ifndef ATH_SUPPORT_HTC 1705 extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); 1706 extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); 1707 extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); 1708 extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); 1709 extern void ar9300_tx99_stop(struct ath_hal *ah); 1710 #endif /* ATH_SUPPORT_HTC */ 1711 #endif /* ATH_TX99_DIAG */ 1712 extern HAL_BOOL ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array); 1713 extern void ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask); 1714 1715 enum { 1716 AR9300_COEFF_TX_TYPE = 0, 1717 AR9300_COEFF_RX_TYPE 1718 }; 1719 1720 #endif /* _ATH_AR9300_H_ */ 1721