1 /****************************************************************************** 2 * 3 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2020, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #ifndef __ACTBL2_H__ 153 #define __ACTBL2_H__ 154 155 156 /******************************************************************************* 157 * 158 * Additional ACPI Tables (2) 159 * 160 * These tables are not consumed directly by the ACPICA subsystem, but are 161 * included here to support device drivers and the AML disassembler. 162 * 163 ******************************************************************************/ 164 165 166 /* 167 * Values for description table header signatures for tables defined in this 168 * file. Useful because they make it more difficult to inadvertently type in 169 * the wrong signature. 170 */ 171 #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ 172 #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ 173 #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ 174 #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ 175 #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ 176 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ 177 #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */ 178 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ 179 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ 180 #define ACPI_SIG_MTMR "MTMR" /* MID Timer table */ 181 #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ 182 #define ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */ 183 #define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */ 184 #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */ 185 #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ 186 #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ 187 #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ 188 #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ 189 #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ 190 #define ACPI_SIG_NHLT "NHLT" /* Non-HDAudio Link Table */ 191 192 193 /* 194 * All tables must be byte-packed to match the ACPI specification, since 195 * the tables are provided by the system BIOS. 196 */ 197 #pragma pack(1) 198 199 /* 200 * Note: C bitfields are not used for this reason: 201 * 202 * "Bitfields are great and easy to read, but unfortunately the C language 203 * does not specify the layout of bitfields in memory, which means they are 204 * essentially useless for dealing with packed data in on-disk formats or 205 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, 206 * this decision was a design error in C. Ritchie could have picked an order 207 * and stuck with it." Norman Ramsey. 208 * See http://stackoverflow.com/a/1053662/41661 209 */ 210 211 212 /******************************************************************************* 213 * 214 * IORT - IO Remapping Table 215 * 216 * Conforms to "IO Remapping Table System Software on ARM Platforms", 217 * Document number: ARM DEN 0049D, March 2018 218 * 219 ******************************************************************************/ 220 221 typedef struct acpi_table_iort 222 { 223 ACPI_TABLE_HEADER Header; 224 UINT32 NodeCount; 225 UINT32 NodeOffset; 226 UINT32 Reserved; 227 228 } ACPI_TABLE_IORT; 229 230 231 /* 232 * IORT subtables 233 */ 234 typedef struct acpi_iort_node 235 { 236 UINT8 Type; 237 UINT16 Length; 238 UINT8 Revision; 239 UINT32 Reserved; 240 UINT32 MappingCount; 241 UINT32 MappingOffset; 242 char NodeData[1]; 243 244 } ACPI_IORT_NODE; 245 246 /* Values for subtable Type above */ 247 248 enum AcpiIortNodeType 249 { 250 ACPI_IORT_NODE_ITS_GROUP = 0x00, 251 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01, 252 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02, 253 ACPI_IORT_NODE_SMMU = 0x03, 254 ACPI_IORT_NODE_SMMU_V3 = 0x04, 255 ACPI_IORT_NODE_PMCG = 0x05 256 }; 257 258 259 typedef struct acpi_iort_id_mapping 260 { 261 UINT32 InputBase; /* Lowest value in input range */ 262 UINT32 IdCount; /* Number of IDs */ 263 UINT32 OutputBase; /* Lowest value in output range */ 264 UINT32 OutputReference; /* A reference to the output node */ 265 UINT32 Flags; 266 267 } ACPI_IORT_ID_MAPPING; 268 269 /* Masks for Flags field above for IORT subtable */ 270 271 #define ACPI_IORT_ID_SINGLE_MAPPING (1) 272 273 274 typedef struct acpi_iort_memory_access 275 { 276 UINT32 CacheCoherency; 277 UINT8 Hints; 278 UINT16 Reserved; 279 UINT8 MemoryFlags; 280 281 } ACPI_IORT_MEMORY_ACCESS; 282 283 /* Values for CacheCoherency field above */ 284 285 #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */ 286 #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */ 287 288 /* Masks for Hints field above */ 289 290 #define ACPI_IORT_HT_TRANSIENT (1) 291 #define ACPI_IORT_HT_WRITE (1<<1) 292 #define ACPI_IORT_HT_READ (1<<2) 293 #define ACPI_IORT_HT_OVERRIDE (1<<3) 294 295 /* Masks for MemoryFlags field above */ 296 297 #define ACPI_IORT_MF_COHERENCY (1) 298 #define ACPI_IORT_MF_ATTRIBUTES (1<<1) 299 300 301 /* 302 * IORT node specific subtables 303 */ 304 typedef struct acpi_iort_its_group 305 { 306 UINT32 ItsCount; 307 UINT32 Identifiers[1]; /* GIC ITS identifier array */ 308 309 } ACPI_IORT_ITS_GROUP; 310 311 312 typedef struct acpi_iort_named_component 313 { 314 UINT32 NodeFlags; 315 UINT64 MemoryProperties; /* Memory access properties */ 316 UINT8 MemoryAddressLimit; /* Memory address size limit */ 317 char DeviceName[1]; /* Path of namespace object */ 318 319 } ACPI_IORT_NAMED_COMPONENT; 320 321 /* Masks for Flags field above */ 322 323 #define ACPI_IORT_NC_STALL_SUPPORTED (1) 324 #define ACPI_IORT_NC_PASID_BITS (31<<1) 325 326 typedef struct acpi_iort_root_complex 327 { 328 UINT64 MemoryProperties; /* Memory access properties */ 329 UINT32 AtsAttribute; 330 UINT32 PciSegmentNumber; 331 UINT8 MemoryAddressLimit; /* Memory address size limit */ 332 UINT8 Reserved[3]; /* Reserved, must be zero */ 333 334 } ACPI_IORT_ROOT_COMPLEX; 335 336 /* Values for AtsAttribute field above */ 337 338 #define ACPI_IORT_ATS_SUPPORTED 0x00000001 /* The root complex supports ATS */ 339 #define ACPI_IORT_ATS_UNSUPPORTED 0x00000000 /* The root complex doesn't support ATS */ 340 341 342 typedef struct acpi_iort_smmu 343 { 344 UINT64 BaseAddress; /* SMMU base address */ 345 UINT64 Span; /* Length of memory range */ 346 UINT32 Model; 347 UINT32 Flags; 348 UINT32 GlobalInterruptOffset; 349 UINT32 ContextInterruptCount; 350 UINT32 ContextInterruptOffset; 351 UINT32 PmuInterruptCount; 352 UINT32 PmuInterruptOffset; 353 UINT64 Interrupts[1]; /* Interrupt array */ 354 355 } ACPI_IORT_SMMU; 356 357 /* Values for Model field above */ 358 359 #define ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */ 360 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ 361 #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ 362 #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ 363 #define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ 364 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */ 365 366 /* Masks for Flags field above */ 367 368 #define ACPI_IORT_SMMU_DVM_SUPPORTED (1) 369 #define ACPI_IORT_SMMU_COHERENT_WALK (1<<1) 370 371 /* Global interrupt format */ 372 373 typedef struct acpi_iort_smmu_gsi 374 { 375 UINT32 NSgIrpt; 376 UINT32 NSgIrptFlags; 377 UINT32 NSgCfgIrpt; 378 UINT32 NSgCfgIrptFlags; 379 380 } ACPI_IORT_SMMU_GSI; 381 382 383 typedef struct acpi_iort_smmu_v3 384 { 385 UINT64 BaseAddress; /* SMMUv3 base address */ 386 UINT32 Flags; 387 UINT32 Reserved; 388 UINT64 VatosAddress; 389 UINT32 Model; 390 UINT32 EventGsiv; 391 UINT32 PriGsiv; 392 UINT32 GerrGsiv; 393 UINT32 SyncGsiv; 394 UINT32 Pxm; 395 UINT32 IdMappingIndex; 396 397 } ACPI_IORT_SMMU_V3; 398 399 /* Values for Model field above */ 400 401 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */ 402 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */ 403 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ 404 405 /* Masks for Flags field above */ 406 407 #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) 408 #define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1) 409 #define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3) 410 411 typedef struct acpi_iort_pmcg 412 { 413 UINT64 Page0BaseAddress; 414 UINT32 OverflowGsiv; 415 UINT32 NodeReference; 416 UINT64 Page1BaseAddress; 417 418 } ACPI_IORT_PMCG; 419 420 421 /******************************************************************************* 422 * 423 * IVRS - I/O Virtualization Reporting Structure 424 * Version 1 425 * 426 * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification", 427 * Revision 1.26, February 2009. 428 * 429 ******************************************************************************/ 430 431 typedef struct acpi_table_ivrs 432 { 433 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 434 UINT32 Info; /* Common virtualization info */ 435 UINT64 Reserved; 436 437 } ACPI_TABLE_IVRS; 438 439 /* Values for Info field above */ 440 441 #define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ 442 #define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ 443 #define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ 444 445 446 /* IVRS subtable header */ 447 448 typedef struct acpi_ivrs_header 449 { 450 UINT8 Type; /* Subtable type */ 451 UINT8 Flags; 452 UINT16 Length; /* Subtable length */ 453 UINT16 DeviceId; /* ID of IOMMU */ 454 455 } ACPI_IVRS_HEADER; 456 457 /* Values for subtable Type above */ 458 459 enum AcpiIvrsType 460 { 461 ACPI_IVRS_TYPE_HARDWARE1 = 0x10, 462 ACPI_IVRS_TYPE_HARDWARE2 = 0x11, 463 ACPI_IVRS_TYPE_MEMORY1 = 0x20, 464 ACPI_IVRS_TYPE_MEMORY2 = 0x21, 465 ACPI_IVRS_TYPE_MEMORY3 = 0x22 466 }; 467 468 /* Masks for Flags field above for IVHD subtable */ 469 470 #define ACPI_IVHD_TT_ENABLE (1) 471 #define ACPI_IVHD_PASS_PW (1<<1) 472 #define ACPI_IVHD_RES_PASS_PW (1<<2) 473 #define ACPI_IVHD_ISOC (1<<3) 474 #define ACPI_IVHD_IOTLB (1<<4) 475 476 /* Masks for Flags field above for IVMD subtable */ 477 478 #define ACPI_IVMD_UNITY (1) 479 #define ACPI_IVMD_READ (1<<1) 480 #define ACPI_IVMD_WRITE (1<<2) 481 #define ACPI_IVMD_EXCLUSION_RANGE (1<<3) 482 483 484 /* 485 * IVRS subtables, correspond to Type in ACPI_IVRS_HEADER 486 */ 487 488 /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ 489 490 typedef struct acpi_ivrs_hardware_10 491 { 492 ACPI_IVRS_HEADER Header; 493 UINT16 CapabilityOffset; /* Offset for IOMMU control fields */ 494 UINT64 BaseAddress; /* IOMMU control registers */ 495 UINT16 PciSegmentGroup; 496 UINT16 Info; /* MSI number and unit ID */ 497 UINT32 FeatureReporting; 498 499 } ACPI_IVRS_HARDWARE1; 500 501 /* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */ 502 503 typedef struct acpi_ivrs_hardware_11 504 { 505 ACPI_IVRS_HEADER Header; 506 UINT16 CapabilityOffset; /* Offset for IOMMU control fields */ 507 UINT64 BaseAddress; /* IOMMU control registers */ 508 UINT16 PciSegmentGroup; 509 UINT16 Info; /* MSI number and unit ID */ 510 UINT32 Attributes; 511 UINT64 EfrRegisterImage; 512 UINT64 Reserved; 513 } ACPI_IVRS_HARDWARE2; 514 515 /* Masks for Info field above */ 516 517 #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ 518 #define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */ 519 520 521 /* 522 * Device Entries for IVHD subtable, appear after ACPI_IVRS_HARDWARE structure. 523 * Upper two bits of the Type field are the (encoded) length of the structure. 524 * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries 525 * are reserved for future use but not defined. 526 */ 527 typedef struct acpi_ivrs_de_header 528 { 529 UINT8 Type; 530 UINT16 Id; 531 UINT8 DataSetting; 532 533 } ACPI_IVRS_DE_HEADER; 534 535 /* Length of device entry is in the top two bits of Type field above */ 536 537 #define ACPI_IVHD_ENTRY_LENGTH 0xC0 538 539 /* Values for device entry Type field above */ 540 541 enum AcpiIvrsDeviceEntryType 542 { 543 /* 4-byte device entries, all use ACPI_IVRS_DEVICE4 */ 544 545 ACPI_IVRS_TYPE_PAD4 = 0, 546 ACPI_IVRS_TYPE_ALL = 1, 547 ACPI_IVRS_TYPE_SELECT = 2, 548 ACPI_IVRS_TYPE_START = 3, 549 ACPI_IVRS_TYPE_END = 4, 550 551 /* 8-byte device entries */ 552 553 ACPI_IVRS_TYPE_PAD8 = 64, 554 ACPI_IVRS_TYPE_NOT_USED = 65, 555 ACPI_IVRS_TYPE_ALIAS_SELECT = 66, /* Uses ACPI_IVRS_DEVICE8A */ 556 ACPI_IVRS_TYPE_ALIAS_START = 67, /* Uses ACPI_IVRS_DEVICE8A */ 557 ACPI_IVRS_TYPE_EXT_SELECT = 70, /* Uses ACPI_IVRS_DEVICE8B */ 558 ACPI_IVRS_TYPE_EXT_START = 71, /* Uses ACPI_IVRS_DEVICE8B */ 559 ACPI_IVRS_TYPE_SPECIAL = 72 /* Uses ACPI_IVRS_DEVICE8C */ 560 }; 561 562 /* Values for Data field above */ 563 564 #define ACPI_IVHD_INIT_PASS (1) 565 #define ACPI_IVHD_EINT_PASS (1<<1) 566 #define ACPI_IVHD_NMI_PASS (1<<2) 567 #define ACPI_IVHD_SYSTEM_MGMT (3<<4) 568 #define ACPI_IVHD_LINT0_PASS (1<<6) 569 #define ACPI_IVHD_LINT1_PASS (1<<7) 570 571 572 /* Types 0-4: 4-byte device entry */ 573 574 typedef struct acpi_ivrs_device4 575 { 576 ACPI_IVRS_DE_HEADER Header; 577 578 } ACPI_IVRS_DEVICE4; 579 580 /* Types 66-67: 8-byte device entry */ 581 582 typedef struct acpi_ivrs_device8a 583 { 584 ACPI_IVRS_DE_HEADER Header; 585 UINT8 Reserved1; 586 UINT16 UsedId; 587 UINT8 Reserved2; 588 589 } ACPI_IVRS_DEVICE8A; 590 591 /* Types 70-71: 8-byte device entry */ 592 593 typedef struct acpi_ivrs_device8b 594 { 595 ACPI_IVRS_DE_HEADER Header; 596 UINT32 ExtendedData; 597 598 } ACPI_IVRS_DEVICE8B; 599 600 /* Values for ExtendedData above */ 601 602 #define ACPI_IVHD_ATS_DISABLED (1<<31) 603 604 /* Type 72: 8-byte device entry */ 605 606 typedef struct acpi_ivrs_device8c 607 { 608 ACPI_IVRS_DE_HEADER Header; 609 UINT8 Handle; 610 UINT16 UsedId; 611 UINT8 Variety; 612 613 } ACPI_IVRS_DEVICE8C; 614 615 /* Values for Variety field above */ 616 617 #define ACPI_IVHD_IOAPIC 1 618 #define ACPI_IVHD_HPET 2 619 620 621 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */ 622 623 typedef struct acpi_ivrs_memory 624 { 625 ACPI_IVRS_HEADER Header; 626 UINT16 AuxData; 627 UINT64 Reserved; 628 UINT64 StartAddress; 629 UINT64 MemoryLength; 630 631 } ACPI_IVRS_MEMORY; 632 633 634 /******************************************************************************* 635 * 636 * LPIT - Low Power Idle Table 637 * 638 * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014. 639 * 640 ******************************************************************************/ 641 642 typedef struct acpi_table_lpit 643 { 644 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 645 646 } ACPI_TABLE_LPIT; 647 648 649 /* LPIT subtable header */ 650 651 typedef struct acpi_lpit_header 652 { 653 UINT32 Type; /* Subtable type */ 654 UINT32 Length; /* Subtable length */ 655 UINT16 UniqueId; 656 UINT16 Reserved; 657 UINT32 Flags; 658 659 } ACPI_LPIT_HEADER; 660 661 /* Values for subtable Type above */ 662 663 enum AcpiLpitType 664 { 665 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00, 666 ACPI_LPIT_TYPE_RESERVED = 0x01 /* 1 and above are reserved */ 667 }; 668 669 /* Masks for Flags field above */ 670 671 #define ACPI_LPIT_STATE_DISABLED (1) 672 #define ACPI_LPIT_NO_COUNTER (1<<1) 673 674 /* 675 * LPIT subtables, correspond to Type in ACPI_LPIT_HEADER 676 */ 677 678 /* 0x00: Native C-state instruction based LPI structure */ 679 680 typedef struct acpi_lpit_native 681 { 682 ACPI_LPIT_HEADER Header; 683 ACPI_GENERIC_ADDRESS EntryTrigger; 684 UINT32 Residency; 685 UINT32 Latency; 686 ACPI_GENERIC_ADDRESS ResidencyCounter; 687 UINT64 CounterFrequency; 688 689 } ACPI_LPIT_NATIVE; 690 691 692 /******************************************************************************* 693 * 694 * MADT - Multiple APIC Description Table 695 * Version 3 696 * 697 ******************************************************************************/ 698 699 typedef struct acpi_table_madt 700 { 701 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 702 UINT32 Address; /* Physical address of local APIC */ 703 UINT32 Flags; 704 705 } ACPI_TABLE_MADT; 706 707 /* Masks for Flags field above */ 708 709 #define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ 710 711 /* Values for PCATCompat flag */ 712 713 #define ACPI_MADT_DUAL_PIC 1 714 #define ACPI_MADT_MULTIPLE_APIC 0 715 716 717 /* Values for MADT subtable type in ACPI_SUBTABLE_HEADER */ 718 719 enum AcpiMadtType 720 { 721 ACPI_MADT_TYPE_LOCAL_APIC = 0, 722 ACPI_MADT_TYPE_IO_APIC = 1, 723 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2, 724 ACPI_MADT_TYPE_NMI_SOURCE = 3, 725 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4, 726 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5, 727 ACPI_MADT_TYPE_IO_SAPIC = 6, 728 ACPI_MADT_TYPE_LOCAL_SAPIC = 7, 729 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8, 730 ACPI_MADT_TYPE_LOCAL_X2APIC = 9, 731 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10, 732 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11, 733 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12, 734 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13, 735 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14, 736 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15, 737 ACPI_MADT_TYPE_RESERVED = 16 /* 16 and greater are reserved */ 738 }; 739 740 741 /* 742 * MADT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER 743 */ 744 745 /* 0: Processor Local APIC */ 746 747 typedef struct acpi_madt_local_apic 748 { 749 ACPI_SUBTABLE_HEADER Header; 750 UINT8 ProcessorId; /* ACPI processor id */ 751 UINT8 Id; /* Processor's local APIC id */ 752 UINT32 LapicFlags; 753 754 } ACPI_MADT_LOCAL_APIC; 755 756 757 /* 1: IO APIC */ 758 759 typedef struct acpi_madt_io_apic 760 { 761 ACPI_SUBTABLE_HEADER Header; 762 UINT8 Id; /* I/O APIC ID */ 763 UINT8 Reserved; /* Reserved - must be zero */ 764 UINT32 Address; /* APIC physical address */ 765 UINT32 GlobalIrqBase; /* Global system interrupt where INTI lines start */ 766 767 } ACPI_MADT_IO_APIC; 768 769 770 /* 2: Interrupt Override */ 771 772 typedef struct acpi_madt_interrupt_override 773 { 774 ACPI_SUBTABLE_HEADER Header; 775 UINT8 Bus; /* 0 - ISA */ 776 UINT8 SourceIrq; /* Interrupt source (IRQ) */ 777 UINT32 GlobalIrq; /* Global system interrupt */ 778 UINT16 IntiFlags; 779 780 } ACPI_MADT_INTERRUPT_OVERRIDE; 781 782 783 /* 3: NMI Source */ 784 785 typedef struct acpi_madt_nmi_source 786 { 787 ACPI_SUBTABLE_HEADER Header; 788 UINT16 IntiFlags; 789 UINT32 GlobalIrq; /* Global system interrupt */ 790 791 } ACPI_MADT_NMI_SOURCE; 792 793 794 /* 4: Local APIC NMI */ 795 796 typedef struct acpi_madt_local_apic_nmi 797 { 798 ACPI_SUBTABLE_HEADER Header; 799 UINT8 ProcessorId; /* ACPI processor id */ 800 UINT16 IntiFlags; 801 UINT8 Lint; /* LINTn to which NMI is connected */ 802 803 } ACPI_MADT_LOCAL_APIC_NMI; 804 805 806 /* 5: Address Override */ 807 808 typedef struct acpi_madt_local_apic_override 809 { 810 ACPI_SUBTABLE_HEADER Header; 811 UINT16 Reserved; /* Reserved, must be zero */ 812 UINT64 Address; /* APIC physical address */ 813 814 } ACPI_MADT_LOCAL_APIC_OVERRIDE; 815 816 817 /* 6: I/O Sapic */ 818 819 typedef struct acpi_madt_io_sapic 820 { 821 ACPI_SUBTABLE_HEADER Header; 822 UINT8 Id; /* I/O SAPIC ID */ 823 UINT8 Reserved; /* Reserved, must be zero */ 824 UINT32 GlobalIrqBase; /* Global interrupt for SAPIC start */ 825 UINT64 Address; /* SAPIC physical address */ 826 827 } ACPI_MADT_IO_SAPIC; 828 829 830 /* 7: Local Sapic */ 831 832 typedef struct acpi_madt_local_sapic 833 { 834 ACPI_SUBTABLE_HEADER Header; 835 UINT8 ProcessorId; /* ACPI processor id */ 836 UINT8 Id; /* SAPIC ID */ 837 UINT8 Eid; /* SAPIC EID */ 838 UINT8 Reserved[3]; /* Reserved, must be zero */ 839 UINT32 LapicFlags; 840 UINT32 Uid; /* Numeric UID - ACPI 3.0 */ 841 char UidString[1]; /* String UID - ACPI 3.0 */ 842 843 } ACPI_MADT_LOCAL_SAPIC; 844 845 846 /* 8: Platform Interrupt Source */ 847 848 typedef struct acpi_madt_interrupt_source 849 { 850 ACPI_SUBTABLE_HEADER Header; 851 UINT16 IntiFlags; 852 UINT8 Type; /* 1=PMI, 2=INIT, 3=corrected */ 853 UINT8 Id; /* Processor ID */ 854 UINT8 Eid; /* Processor EID */ 855 UINT8 IoSapicVector; /* Vector value for PMI interrupts */ 856 UINT32 GlobalIrq; /* Global system interrupt */ 857 UINT32 Flags; /* Interrupt Source Flags */ 858 859 } ACPI_MADT_INTERRUPT_SOURCE; 860 861 /* Masks for Flags field above */ 862 863 #define ACPI_MADT_CPEI_OVERRIDE (1) 864 865 866 /* 9: Processor Local X2APIC (ACPI 4.0) */ 867 868 typedef struct acpi_madt_local_x2apic 869 { 870 ACPI_SUBTABLE_HEADER Header; 871 UINT16 Reserved; /* Reserved - must be zero */ 872 UINT32 LocalApicId; /* Processor x2APIC ID */ 873 UINT32 LapicFlags; 874 UINT32 Uid; /* ACPI processor UID */ 875 876 } ACPI_MADT_LOCAL_X2APIC; 877 878 879 /* 10: Local X2APIC NMI (ACPI 4.0) */ 880 881 typedef struct acpi_madt_local_x2apic_nmi 882 { 883 ACPI_SUBTABLE_HEADER Header; 884 UINT16 IntiFlags; 885 UINT32 Uid; /* ACPI processor UID */ 886 UINT8 Lint; /* LINTn to which NMI is connected */ 887 UINT8 Reserved[3]; /* Reserved - must be zero */ 888 889 } ACPI_MADT_LOCAL_X2APIC_NMI; 890 891 892 /* 11: Generic Interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 changes) */ 893 894 typedef struct acpi_madt_generic_interrupt 895 { 896 ACPI_SUBTABLE_HEADER Header; 897 UINT16 Reserved; /* Reserved - must be zero */ 898 UINT32 CpuInterfaceNumber; 899 UINT32 Uid; 900 UINT32 Flags; 901 UINT32 ParkingVersion; 902 UINT32 PerformanceInterrupt; 903 UINT64 ParkedAddress; 904 UINT64 BaseAddress; 905 UINT64 GicvBaseAddress; 906 UINT64 GichBaseAddress; 907 UINT32 VgicInterrupt; 908 UINT64 GicrBaseAddress; 909 UINT64 ArmMpidr; 910 UINT8 EfficiencyClass; 911 UINT8 Reserved2[1]; 912 UINT16 SpeInterrupt; /* ACPI 6.3 */ 913 914 } ACPI_MADT_GENERIC_INTERRUPT; 915 916 /* Masks for Flags field above */ 917 918 /* ACPI_MADT_ENABLED (1) Processor is usable if set */ 919 #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ 920 #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ 921 922 923 /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */ 924 925 typedef struct acpi_madt_generic_distributor 926 { 927 ACPI_SUBTABLE_HEADER Header; 928 UINT16 Reserved; /* Reserved - must be zero */ 929 UINT32 GicId; 930 UINT64 BaseAddress; 931 UINT32 GlobalIrqBase; 932 UINT8 Version; 933 UINT8 Reserved2[3]; /* Reserved - must be zero */ 934 935 } ACPI_MADT_GENERIC_DISTRIBUTOR; 936 937 /* Values for Version field above */ 938 939 enum AcpiMadtGicVersion 940 { 941 ACPI_MADT_GIC_VERSION_NONE = 0, 942 ACPI_MADT_GIC_VERSION_V1 = 1, 943 ACPI_MADT_GIC_VERSION_V2 = 2, 944 ACPI_MADT_GIC_VERSION_V3 = 3, 945 ACPI_MADT_GIC_VERSION_V4 = 4, 946 ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */ 947 }; 948 949 950 /* 13: Generic MSI Frame (ACPI 5.1) */ 951 952 typedef struct acpi_madt_generic_msi_frame 953 { 954 ACPI_SUBTABLE_HEADER Header; 955 UINT16 Reserved; /* Reserved - must be zero */ 956 UINT32 MsiFrameId; 957 UINT64 BaseAddress; 958 UINT32 Flags; 959 UINT16 SpiCount; 960 UINT16 SpiBase; 961 962 } ACPI_MADT_GENERIC_MSI_FRAME; 963 964 /* Masks for Flags field above */ 965 966 #define ACPI_MADT_OVERRIDE_SPI_VALUES (1) 967 968 969 /* 14: Generic Redistributor (ACPI 5.1) */ 970 971 typedef struct acpi_madt_generic_redistributor 972 { 973 ACPI_SUBTABLE_HEADER Header; 974 UINT16 Reserved; /* reserved - must be zero */ 975 UINT64 BaseAddress; 976 UINT32 Length; 977 978 } ACPI_MADT_GENERIC_REDISTRIBUTOR; 979 980 981 /* 15: Generic Translator (ACPI 6.0) */ 982 983 typedef struct acpi_madt_generic_translator 984 { 985 ACPI_SUBTABLE_HEADER Header; 986 UINT16 Reserved; /* reserved - must be zero */ 987 UINT32 TranslationId; 988 UINT64 BaseAddress; 989 UINT32 Reserved2; 990 991 } ACPI_MADT_GENERIC_TRANSLATOR; 992 993 994 /* 995 * Common flags fields for MADT subtables 996 */ 997 998 /* MADT Local APIC flags */ 999 1000 #define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */ 1001 1002 /* MADT MPS INTI flags (IntiFlags) */ 1003 1004 #define ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */ 1005 #define ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */ 1006 1007 /* Values for MPS INTI flags */ 1008 1009 #define ACPI_MADT_POLARITY_CONFORMS 0 1010 #define ACPI_MADT_POLARITY_ACTIVE_HIGH 1 1011 #define ACPI_MADT_POLARITY_RESERVED 2 1012 #define ACPI_MADT_POLARITY_ACTIVE_LOW 3 1013 1014 #define ACPI_MADT_TRIGGER_CONFORMS (0) 1015 #define ACPI_MADT_TRIGGER_EDGE (1<<2) 1016 #define ACPI_MADT_TRIGGER_RESERVED (2<<2) 1017 #define ACPI_MADT_TRIGGER_LEVEL (3<<2) 1018 1019 1020 /******************************************************************************* 1021 * 1022 * MCFG - PCI Memory Mapped Configuration table and subtable 1023 * Version 1 1024 * 1025 * Conforms to "PCI Firmware Specification", Revision 3.0, June 20, 2005 1026 * 1027 ******************************************************************************/ 1028 1029 typedef struct acpi_table_mcfg 1030 { 1031 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1032 UINT8 Reserved[8]; 1033 1034 } ACPI_TABLE_MCFG; 1035 1036 1037 /* Subtable */ 1038 1039 typedef struct acpi_mcfg_allocation 1040 { 1041 UINT64 Address; /* Base address, processor-relative */ 1042 UINT16 PciSegment; /* PCI segment group number */ 1043 UINT8 StartBusNumber; /* Starting PCI Bus number */ 1044 UINT8 EndBusNumber; /* Final PCI Bus number */ 1045 UINT32 Reserved; 1046 1047 } ACPI_MCFG_ALLOCATION; 1048 1049 1050 /******************************************************************************* 1051 * 1052 * MCHI - Management Controller Host Interface Table 1053 * Version 1 1054 * 1055 * Conforms to "Management Component Transport Protocol (MCTP) Host 1056 * Interface Specification", Revision 1.0.0a, October 13, 2009 1057 * 1058 ******************************************************************************/ 1059 1060 typedef struct acpi_table_mchi 1061 { 1062 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1063 UINT8 InterfaceType; 1064 UINT8 Protocol; 1065 UINT64 ProtocolData; 1066 UINT8 InterruptType; 1067 UINT8 Gpe; 1068 UINT8 PciDeviceFlag; 1069 UINT32 GlobalInterrupt; 1070 ACPI_GENERIC_ADDRESS ControlRegister; 1071 UINT8 PciSegment; 1072 UINT8 PciBus; 1073 UINT8 PciDevice; 1074 UINT8 PciFunction; 1075 1076 } ACPI_TABLE_MCHI; 1077 1078 1079 /******************************************************************************* 1080 * 1081 * MPST - Memory Power State Table (ACPI 5.0) 1082 * Version 1 1083 * 1084 ******************************************************************************/ 1085 1086 #define ACPI_MPST_CHANNEL_INFO \ 1087 UINT8 ChannelId; \ 1088 UINT8 Reserved1[3]; \ 1089 UINT16 PowerNodeCount; \ 1090 UINT16 Reserved2; 1091 1092 /* Main table */ 1093 1094 typedef struct acpi_table_mpst 1095 { 1096 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1097 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */ 1098 1099 } ACPI_TABLE_MPST; 1100 1101 1102 /* Memory Platform Communication Channel Info */ 1103 1104 typedef struct acpi_mpst_channel 1105 { 1106 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */ 1107 1108 } ACPI_MPST_CHANNEL; 1109 1110 1111 /* Memory Power Node Structure */ 1112 1113 typedef struct acpi_mpst_power_node 1114 { 1115 UINT8 Flags; 1116 UINT8 Reserved1; 1117 UINT16 NodeId; 1118 UINT32 Length; 1119 UINT64 RangeAddress; 1120 UINT64 RangeLength; 1121 UINT32 NumPowerStates; 1122 UINT32 NumPhysicalComponents; 1123 1124 } ACPI_MPST_POWER_NODE; 1125 1126 /* Values for Flags field above */ 1127 1128 #define ACPI_MPST_ENABLED 1 1129 #define ACPI_MPST_POWER_MANAGED 2 1130 #define ACPI_MPST_HOT_PLUG_CAPABLE 4 1131 1132 1133 /* Memory Power State Structure (follows POWER_NODE above) */ 1134 1135 typedef struct acpi_mpst_power_state 1136 { 1137 UINT8 PowerState; 1138 UINT8 InfoIndex; 1139 1140 } ACPI_MPST_POWER_STATE; 1141 1142 1143 /* Physical Component ID Structure (follows POWER_STATE above) */ 1144 1145 typedef struct acpi_mpst_component 1146 { 1147 UINT16 ComponentId; 1148 1149 } ACPI_MPST_COMPONENT; 1150 1151 1152 /* Memory Power State Characteristics Structure (follows all POWER_NODEs) */ 1153 1154 typedef struct acpi_mpst_data_hdr 1155 { 1156 UINT16 CharacteristicsCount; 1157 UINT16 Reserved; 1158 1159 } ACPI_MPST_DATA_HDR; 1160 1161 typedef struct acpi_mpst_power_data 1162 { 1163 UINT8 StructureId; 1164 UINT8 Flags; 1165 UINT16 Reserved1; 1166 UINT32 AveragePower; 1167 UINT32 PowerSaving; 1168 UINT64 ExitLatency; 1169 UINT64 Reserved2; 1170 1171 } ACPI_MPST_POWER_DATA; 1172 1173 /* Values for Flags field above */ 1174 1175 #define ACPI_MPST_PRESERVE 1 1176 #define ACPI_MPST_AUTOENTRY 2 1177 #define ACPI_MPST_AUTOEXIT 4 1178 1179 1180 /* Shared Memory Region (not part of an ACPI table) */ 1181 1182 typedef struct acpi_mpst_shared 1183 { 1184 UINT32 Signature; 1185 UINT16 PccCommand; 1186 UINT16 PccStatus; 1187 UINT32 CommandRegister; 1188 UINT32 StatusRegister; 1189 UINT32 PowerStateId; 1190 UINT32 PowerNodeId; 1191 UINT64 EnergyConsumed; 1192 UINT64 AveragePower; 1193 1194 } ACPI_MPST_SHARED; 1195 1196 1197 /******************************************************************************* 1198 * 1199 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1200 * Version 1 1201 * 1202 ******************************************************************************/ 1203 1204 typedef struct acpi_table_msct 1205 { 1206 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1207 UINT32 ProximityOffset; /* Location of proximity info struct(s) */ 1208 UINT32 MaxProximityDomains;/* Max number of proximity domains */ 1209 UINT32 MaxClockDomains; /* Max number of clock domains */ 1210 UINT64 MaxAddress; /* Max physical address in system */ 1211 1212 } ACPI_TABLE_MSCT; 1213 1214 1215 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1216 1217 typedef struct acpi_msct_proximity 1218 { 1219 UINT8 Revision; 1220 UINT8 Length; 1221 UINT32 RangeStart; /* Start of domain range */ 1222 UINT32 RangeEnd; /* End of domain range */ 1223 UINT32 ProcessorCapacity; 1224 UINT64 MemoryCapacity; /* In bytes */ 1225 1226 } ACPI_MSCT_PROXIMITY; 1227 1228 1229 /******************************************************************************* 1230 * 1231 * MSDM - Microsoft Data Management table 1232 * 1233 * Conforms to "Microsoft Software Licensing Tables (SLIC and MSDM)", 1234 * November 29, 2011. Copyright 2011 Microsoft 1235 * 1236 ******************************************************************************/ 1237 1238 /* Basic MSDM table is only the common ACPI header */ 1239 1240 typedef struct acpi_table_msdm 1241 { 1242 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1243 1244 } ACPI_TABLE_MSDM; 1245 1246 1247 /******************************************************************************* 1248 * 1249 * MTMR - MID Timer Table 1250 * Version 1 1251 * 1252 * Conforms to "Simple Firmware Interface Specification", 1253 * Draft 0.8.2, Oct 19, 2010 1254 * NOTE: The ACPI MTMR is equivalent to the SFI MTMR table. 1255 * 1256 ******************************************************************************/ 1257 1258 typedef struct acpi_table_mtmr 1259 { 1260 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1261 1262 } ACPI_TABLE_MTMR; 1263 1264 /* MTMR entry */ 1265 1266 typedef struct acpi_mtmr_entry 1267 { 1268 ACPI_GENERIC_ADDRESS PhysicalAddress; 1269 UINT32 Frequency; 1270 UINT32 Irq; 1271 1272 } ACPI_MTMR_ENTRY; 1273 1274 1275 /******************************************************************************* 1276 * 1277 * NFIT - NVDIMM Interface Table (ACPI 6.0+) 1278 * Version 1 1279 * 1280 ******************************************************************************/ 1281 1282 typedef struct acpi_table_nfit 1283 { 1284 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1285 UINT32 Reserved; /* Reserved, must be zero */ 1286 1287 } ACPI_TABLE_NFIT; 1288 1289 /* Subtable header for NFIT */ 1290 1291 typedef struct acpi_nfit_header 1292 { 1293 UINT16 Type; 1294 UINT16 Length; 1295 1296 } ACPI_NFIT_HEADER; 1297 1298 1299 /* Values for subtable type in ACPI_NFIT_HEADER */ 1300 1301 enum AcpiNfitType 1302 { 1303 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0, 1304 ACPI_NFIT_TYPE_MEMORY_MAP = 1, 1305 ACPI_NFIT_TYPE_INTERLEAVE = 2, 1306 ACPI_NFIT_TYPE_SMBIOS = 3, 1307 ACPI_NFIT_TYPE_CONTROL_REGION = 4, 1308 ACPI_NFIT_TYPE_DATA_REGION = 5, 1309 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6, 1310 ACPI_NFIT_TYPE_CAPABILITIES = 7, 1311 ACPI_NFIT_TYPE_RESERVED = 8 /* 8 and greater are reserved */ 1312 }; 1313 1314 /* 1315 * NFIT Subtables 1316 */ 1317 1318 /* 0: System Physical Address Range Structure */ 1319 1320 typedef struct acpi_nfit_system_address 1321 { 1322 ACPI_NFIT_HEADER Header; 1323 UINT16 RangeIndex; 1324 UINT16 Flags; 1325 UINT32 Reserved; /* Reserved, must be zero */ 1326 UINT32 ProximityDomain; 1327 UINT8 RangeGuid[16]; 1328 UINT64 Address; 1329 UINT64 Length; 1330 UINT64 MemoryMapping; 1331 1332 } ACPI_NFIT_SYSTEM_ADDRESS; 1333 1334 /* Flags */ 1335 1336 #define ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */ 1337 #define ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */ 1338 1339 /* Range Type GUIDs appear in the include/acuuid.h file */ 1340 1341 1342 /* 1: Memory Device to System Address Range Map Structure */ 1343 1344 typedef struct acpi_nfit_memory_map 1345 { 1346 ACPI_NFIT_HEADER Header; 1347 UINT32 DeviceHandle; 1348 UINT16 PhysicalId; 1349 UINT16 RegionId; 1350 UINT16 RangeIndex; 1351 UINT16 RegionIndex; 1352 UINT64 RegionSize; 1353 UINT64 RegionOffset; 1354 UINT64 Address; 1355 UINT16 InterleaveIndex; 1356 UINT16 InterleaveWays; 1357 UINT16 Flags; 1358 UINT16 Reserved; /* Reserved, must be zero */ 1359 1360 } ACPI_NFIT_MEMORY_MAP; 1361 1362 /* Flags */ 1363 1364 #define ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */ 1365 #define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */ 1366 #define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */ 1367 #define ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */ 1368 #define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */ 1369 #define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */ 1370 #define ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */ 1371 1372 1373 /* 2: Interleave Structure */ 1374 1375 typedef struct acpi_nfit_interleave 1376 { 1377 ACPI_NFIT_HEADER Header; 1378 UINT16 InterleaveIndex; 1379 UINT16 Reserved; /* Reserved, must be zero */ 1380 UINT32 LineCount; 1381 UINT32 LineSize; 1382 UINT32 LineOffset[1]; /* Variable length */ 1383 1384 } ACPI_NFIT_INTERLEAVE; 1385 1386 1387 /* 3: SMBIOS Management Information Structure */ 1388 1389 typedef struct acpi_nfit_smbios 1390 { 1391 ACPI_NFIT_HEADER Header; 1392 UINT32 Reserved; /* Reserved, must be zero */ 1393 UINT8 Data[1]; /* Variable length */ 1394 1395 } ACPI_NFIT_SMBIOS; 1396 1397 1398 /* 4: NVDIMM Control Region Structure */ 1399 1400 typedef struct acpi_nfit_control_region 1401 { 1402 ACPI_NFIT_HEADER Header; 1403 UINT16 RegionIndex; 1404 UINT16 VendorId; 1405 UINT16 DeviceId; 1406 UINT16 RevisionId; 1407 UINT16 SubsystemVendorId; 1408 UINT16 SubsystemDeviceId; 1409 UINT16 SubsystemRevisionId; 1410 UINT8 ValidFields; 1411 UINT8 ManufacturingLocation; 1412 UINT16 ManufacturingDate; 1413 UINT8 Reserved[2]; /* Reserved, must be zero */ 1414 UINT32 SerialNumber; 1415 UINT16 Code; 1416 UINT16 Windows; 1417 UINT64 WindowSize; 1418 UINT64 CommandOffset; 1419 UINT64 CommandSize; 1420 UINT64 StatusOffset; 1421 UINT64 StatusSize; 1422 UINT16 Flags; 1423 UINT8 Reserved1[6]; /* Reserved, must be zero */ 1424 1425 } ACPI_NFIT_CONTROL_REGION; 1426 1427 /* Flags */ 1428 1429 #define ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */ 1430 1431 /* ValidFields bits */ 1432 1433 #define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */ 1434 1435 1436 /* 5: NVDIMM Block Data Window Region Structure */ 1437 1438 typedef struct acpi_nfit_data_region 1439 { 1440 ACPI_NFIT_HEADER Header; 1441 UINT16 RegionIndex; 1442 UINT16 Windows; 1443 UINT64 Offset; 1444 UINT64 Size; 1445 UINT64 Capacity; 1446 UINT64 StartAddress; 1447 1448 } ACPI_NFIT_DATA_REGION; 1449 1450 1451 /* 6: Flush Hint Address Structure */ 1452 1453 typedef struct acpi_nfit_flush_address 1454 { 1455 ACPI_NFIT_HEADER Header; 1456 UINT32 DeviceHandle; 1457 UINT16 HintCount; 1458 UINT8 Reserved[6]; /* Reserved, must be zero */ 1459 UINT64 HintAddress[1]; /* Variable length */ 1460 1461 } ACPI_NFIT_FLUSH_ADDRESS; 1462 1463 1464 /* 7: Platform Capabilities Structure */ 1465 1466 typedef struct acpi_nfit_capabilities 1467 { 1468 ACPI_NFIT_HEADER Header; 1469 UINT8 HighestCapability; 1470 UINT8 Reserved[3]; /* Reserved, must be zero */ 1471 UINT32 Capabilities; 1472 UINT32 Reserved2; 1473 1474 } ACPI_NFIT_CAPABILITIES; 1475 1476 /* Capabilities Flags */ 1477 1478 #define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */ 1479 #define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */ 1480 #define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */ 1481 1482 1483 /* 1484 * NFIT/DVDIMM device handle support - used as the _ADR for each NVDIMM 1485 */ 1486 typedef struct nfit_device_handle 1487 { 1488 UINT32 Handle; 1489 1490 } NFIT_DEVICE_HANDLE; 1491 1492 /* Device handle construction and extraction macros */ 1493 1494 #define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F 1495 #define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0 1496 #define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00 1497 #define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000 1498 #define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000 1499 1500 #define ACPI_NFIT_DIMM_NUMBER_OFFSET 0 1501 #define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4 1502 #define ACPI_NFIT_MEMORY_ID_OFFSET 8 1503 #define ACPI_NFIT_SOCKET_ID_OFFSET 12 1504 #define ACPI_NFIT_NODE_ID_OFFSET 16 1505 1506 /* Macro to construct a NFIT/NVDIMM device handle */ 1507 1508 #define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \ 1509 ((dimm) | \ 1510 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \ 1511 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \ 1512 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \ 1513 ((node) << ACPI_NFIT_NODE_ID_OFFSET)) 1514 1515 /* Macros to extract individual fields from a NFIT/NVDIMM device handle */ 1516 1517 #define ACPI_NFIT_GET_DIMM_NUMBER(handle) \ 1518 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK) 1519 1520 #define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \ 1521 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET) 1522 1523 #define ACPI_NFIT_GET_MEMORY_ID(handle) \ 1524 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET) 1525 1526 #define ACPI_NFIT_GET_SOCKET_ID(handle) \ 1527 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET) 1528 1529 #define ACPI_NFIT_GET_NODE_ID(handle) \ 1530 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET) 1531 1532 1533 /******************************************************************************* 1534 * 1535 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1536 * Version 2 (ACPI 6.2) 1537 * 1538 ******************************************************************************/ 1539 1540 typedef struct acpi_table_pcct 1541 { 1542 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1543 UINT32 Flags; 1544 UINT64 Reserved; 1545 1546 } ACPI_TABLE_PCCT; 1547 1548 /* Values for Flags field above */ 1549 1550 #define ACPI_PCCT_DOORBELL 1 1551 1552 /* Values for subtable type in ACPI_SUBTABLE_HEADER */ 1553 1554 enum AcpiPcctType 1555 { 1556 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0, 1557 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1, 1558 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2, /* ACPI 6.1 */ 1559 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3, /* ACPI 6.2 */ 1560 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4, /* ACPI 6.2 */ 1561 ACPI_PCCT_TYPE_RESERVED = 5 /* 5 and greater are reserved */ 1562 }; 1563 1564 /* 1565 * PCCT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER 1566 */ 1567 1568 /* 0: Generic Communications Subspace */ 1569 1570 typedef struct acpi_pcct_subspace 1571 { 1572 ACPI_SUBTABLE_HEADER Header; 1573 UINT8 Reserved[6]; 1574 UINT64 BaseAddress; 1575 UINT64 Length; 1576 ACPI_GENERIC_ADDRESS DoorbellRegister; 1577 UINT64 PreserveMask; 1578 UINT64 WriteMask; 1579 UINT32 Latency; 1580 UINT32 MaxAccessRate; 1581 UINT16 MinTurnaroundTime; 1582 1583 } ACPI_PCCT_SUBSPACE; 1584 1585 1586 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1587 1588 typedef struct acpi_pcct_hw_reduced 1589 { 1590 ACPI_SUBTABLE_HEADER Header; 1591 UINT32 PlatformInterrupt; 1592 UINT8 Flags; 1593 UINT8 Reserved; 1594 UINT64 BaseAddress; 1595 UINT64 Length; 1596 ACPI_GENERIC_ADDRESS DoorbellRegister; 1597 UINT64 PreserveMask; 1598 UINT64 WriteMask; 1599 UINT32 Latency; 1600 UINT32 MaxAccessRate; 1601 UINT16 MinTurnaroundTime; 1602 1603 } ACPI_PCCT_HW_REDUCED; 1604 1605 1606 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1607 1608 typedef struct acpi_pcct_hw_reduced_type2 1609 { 1610 ACPI_SUBTABLE_HEADER Header; 1611 UINT32 PlatformInterrupt; 1612 UINT8 Flags; 1613 UINT8 Reserved; 1614 UINT64 BaseAddress; 1615 UINT64 Length; 1616 ACPI_GENERIC_ADDRESS DoorbellRegister; 1617 UINT64 PreserveMask; 1618 UINT64 WriteMask; 1619 UINT32 Latency; 1620 UINT32 MaxAccessRate; 1621 UINT16 MinTurnaroundTime; 1622 ACPI_GENERIC_ADDRESS PlatformAckRegister; 1623 UINT64 AckPreserveMask; 1624 UINT64 AckWriteMask; 1625 1626 } ACPI_PCCT_HW_REDUCED_TYPE2; 1627 1628 1629 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1630 1631 typedef struct acpi_pcct_ext_pcc_master 1632 { 1633 ACPI_SUBTABLE_HEADER Header; 1634 UINT32 PlatformInterrupt; 1635 UINT8 Flags; 1636 UINT8 Reserved1; 1637 UINT64 BaseAddress; 1638 UINT32 Length; 1639 ACPI_GENERIC_ADDRESS DoorbellRegister; 1640 UINT64 PreserveMask; 1641 UINT64 WriteMask; 1642 UINT32 Latency; 1643 UINT32 MaxAccessRate; 1644 UINT32 MinTurnaroundTime; 1645 ACPI_GENERIC_ADDRESS PlatformAckRegister; 1646 UINT64 AckPreserveMask; 1647 UINT64 AckSetMask; 1648 UINT64 Reserved2; 1649 ACPI_GENERIC_ADDRESS CmdCompleteRegister; 1650 UINT64 CmdCompleteMask; 1651 ACPI_GENERIC_ADDRESS CmdUpdateRegister; 1652 UINT64 CmdUpdatePreserveMask; 1653 UINT64 CmdUpdateSetMask; 1654 ACPI_GENERIC_ADDRESS ErrorStatusRegister; 1655 UINT64 ErrorStatusMask; 1656 1657 } ACPI_PCCT_EXT_PCC_MASTER; 1658 1659 1660 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1661 1662 typedef struct acpi_pcct_ext_pcc_slave 1663 { 1664 ACPI_SUBTABLE_HEADER Header; 1665 UINT32 PlatformInterrupt; 1666 UINT8 Flags; 1667 UINT8 Reserved1; 1668 UINT64 BaseAddress; 1669 UINT32 Length; 1670 ACPI_GENERIC_ADDRESS DoorbellRegister; 1671 UINT64 PreserveMask; 1672 UINT64 WriteMask; 1673 UINT32 Latency; 1674 UINT32 MaxAccessRate; 1675 UINT32 MinTurnaroundTime; 1676 ACPI_GENERIC_ADDRESS PlatformAckRegister; 1677 UINT64 AckPreserveMask; 1678 UINT64 AckSetMask; 1679 UINT64 Reserved2; 1680 ACPI_GENERIC_ADDRESS CmdCompleteRegister; 1681 UINT64 CmdCompleteMask; 1682 ACPI_GENERIC_ADDRESS CmdUpdateRegister; 1683 UINT64 CmdUpdatePreserveMask; 1684 UINT64 CmdUpdateSetMask; 1685 ACPI_GENERIC_ADDRESS ErrorStatusRegister; 1686 UINT64 ErrorStatusMask; 1687 1688 } ACPI_PCCT_EXT_PCC_SLAVE; 1689 1690 1691 /* Values for doorbell flags above */ 1692 1693 #define ACPI_PCCT_INTERRUPT_POLARITY (1) 1694 #define ACPI_PCCT_INTERRUPT_MODE (1<<1) 1695 1696 1697 /* 1698 * PCC memory structures (not part of the ACPI table) 1699 */ 1700 1701 /* Shared Memory Region */ 1702 1703 typedef struct acpi_pcct_shared_memory 1704 { 1705 UINT32 Signature; 1706 UINT16 Command; 1707 UINT16 Status; 1708 1709 } ACPI_PCCT_SHARED_MEMORY; 1710 1711 1712 /* Extended PCC Subspace Shared Memory Region (ACPI 6.2) */ 1713 1714 typedef struct acpi_pcct_ext_pcc_shared_memory 1715 { 1716 UINT32 Signature; 1717 UINT32 Flags; 1718 UINT32 Length; 1719 UINT32 Command; 1720 1721 } ACPI_PCCT_EXT_PCC_SHARED_MEMORY; 1722 1723 1724 /******************************************************************************* 1725 * 1726 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1727 * Version 0 1728 * 1729 ******************************************************************************/ 1730 1731 typedef struct acpi_table_pdtt 1732 { 1733 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1734 UINT8 TriggerCount; 1735 UINT8 Reserved[3]; 1736 UINT32 ArrayOffset; 1737 1738 } ACPI_TABLE_PDTT; 1739 1740 1741 /* 1742 * PDTT Communication Channel Identifier Structure. 1743 * The number of these structures is defined by TriggerCount above, 1744 * starting at ArrayOffset. 1745 */ 1746 typedef struct acpi_pdtt_channel 1747 { 1748 UINT8 SubchannelId; 1749 UINT8 Flags; 1750 1751 } ACPI_PDTT_CHANNEL; 1752 1753 /* Flags for above */ 1754 1755 #define ACPI_PDTT_RUNTIME_TRIGGER (1) 1756 #define ACPI_PDTT_WAIT_COMPLETION (1<<1) 1757 #define ACPI_PDTT_TRIGGER_ORDER (1<<2) 1758 1759 1760 /******************************************************************************* 1761 * 1762 * PMTT - Platform Memory Topology Table (ACPI 5.0) 1763 * Version 1 1764 * 1765 ******************************************************************************/ 1766 1767 typedef struct acpi_table_pmtt 1768 { 1769 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1770 UINT32 Reserved; 1771 1772 } ACPI_TABLE_PMTT; 1773 1774 1775 /* Common header for PMTT subtables that follow main table */ 1776 1777 typedef struct acpi_pmtt_header 1778 { 1779 UINT8 Type; 1780 UINT8 Reserved1; 1781 UINT16 Length; 1782 UINT16 Flags; 1783 UINT16 Reserved2; 1784 1785 } ACPI_PMTT_HEADER; 1786 1787 /* Values for Type field above */ 1788 1789 #define ACPI_PMTT_TYPE_SOCKET 0 1790 #define ACPI_PMTT_TYPE_CONTROLLER 1 1791 #define ACPI_PMTT_TYPE_DIMM 2 1792 #define ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFF are reserved */ 1793 1794 /* Values for Flags field above */ 1795 1796 #define ACPI_PMTT_TOP_LEVEL 0x0001 1797 #define ACPI_PMTT_PHYSICAL 0x0002 1798 #define ACPI_PMTT_MEMORY_TYPE 0x000C 1799 1800 1801 /* 1802 * PMTT subtables, correspond to Type in acpi_pmtt_header 1803 */ 1804 1805 1806 /* 0: Socket Structure */ 1807 1808 typedef struct acpi_pmtt_socket 1809 { 1810 ACPI_PMTT_HEADER Header; 1811 UINT16 SocketId; 1812 UINT16 Reserved; 1813 1814 } ACPI_PMTT_SOCKET; 1815 1816 1817 /* 1: Memory Controller subtable */ 1818 1819 typedef struct acpi_pmtt_controller 1820 { 1821 ACPI_PMTT_HEADER Header; 1822 UINT32 ReadLatency; 1823 UINT32 WriteLatency; 1824 UINT32 ReadBandwidth; 1825 UINT32 WriteBandwidth; 1826 UINT16 AccessWidth; 1827 UINT16 Alignment; 1828 UINT16 Reserved; 1829 UINT16 DomainCount; 1830 1831 } ACPI_PMTT_CONTROLLER; 1832 1833 /* 1a: Proximity Domain substructure */ 1834 1835 typedef struct acpi_pmtt_domain 1836 { 1837 UINT32 ProximityDomain; 1838 1839 } ACPI_PMTT_DOMAIN; 1840 1841 1842 /* 2: Physical Component Identifier (DIMM) */ 1843 1844 typedef struct acpi_pmtt_physical_component 1845 { 1846 ACPI_PMTT_HEADER Header; 1847 UINT16 ComponentId; 1848 UINT16 Reserved; 1849 UINT32 MemorySize; 1850 UINT32 BiosHandle; 1851 1852 } ACPI_PMTT_PHYSICAL_COMPONENT; 1853 1854 1855 /******************************************************************************* 1856 * 1857 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1858 * Version 1 1859 * 1860 ******************************************************************************/ 1861 1862 typedef struct acpi_table_pptt 1863 { 1864 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1865 1866 } ACPI_TABLE_PPTT; 1867 1868 /* Values for Type field above */ 1869 1870 enum AcpiPpttType 1871 { 1872 ACPI_PPTT_TYPE_PROCESSOR = 0, 1873 ACPI_PPTT_TYPE_CACHE = 1, 1874 ACPI_PPTT_TYPE_ID = 2, 1875 ACPI_PPTT_TYPE_RESERVED = 3 1876 }; 1877 1878 1879 /* 0: Processor Hierarchy Node Structure */ 1880 1881 typedef struct acpi_pptt_processor 1882 { 1883 ACPI_SUBTABLE_HEADER Header; 1884 UINT16 Reserved; 1885 UINT32 Flags; 1886 UINT32 Parent; 1887 UINT32 AcpiProcessorId; 1888 UINT32 NumberOfPrivResources; 1889 1890 } ACPI_PPTT_PROCESSOR; 1891 1892 /* Flags */ 1893 1894 #define ACPI_PPTT_PHYSICAL_PACKAGE (1) 1895 #define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1) 1896 #define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */ 1897 #define ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */ 1898 #define ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */ 1899 1900 1901 /* 1: Cache Type Structure */ 1902 1903 typedef struct acpi_pptt_cache 1904 { 1905 ACPI_SUBTABLE_HEADER Header; 1906 UINT16 Reserved; 1907 UINT32 Flags; 1908 UINT32 NextLevelOfCache; 1909 UINT32 Size; 1910 UINT32 NumberOfSets; 1911 UINT8 Associativity; 1912 UINT8 Attributes; 1913 UINT16 LineSize; 1914 1915 } ACPI_PPTT_CACHE; 1916 1917 /* Flags */ 1918 1919 #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ 1920 #define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */ 1921 #define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */ 1922 #define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */ 1923 #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ 1924 #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ 1925 #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ 1926 1927 /* Masks for Attributes */ 1928 1929 #define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */ 1930 #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ 1931 #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ 1932 1933 /* Attributes describing cache */ 1934 #define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ 1935 #define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ 1936 #define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */ 1937 #define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ 1938 1939 #define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ 1940 #define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ 1941 #define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ 1942 #define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ 1943 1944 #define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ 1945 #define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ 1946 1947 /* 2: ID Structure */ 1948 1949 typedef struct acpi_pptt_id 1950 { 1951 ACPI_SUBTABLE_HEADER Header; 1952 UINT16 Reserved; 1953 UINT32 VendorId; 1954 UINT64 Level1Id; 1955 UINT64 Level2Id; 1956 UINT16 MajorRev; 1957 UINT16 MinorRev; 1958 UINT16 SpinRev; 1959 1960 } ACPI_PPTT_ID; 1961 1962 1963 /******************************************************************************* 1964 * 1965 * RASF - RAS Feature Table (ACPI 5.0) 1966 * Version 1 1967 * 1968 ******************************************************************************/ 1969 1970 typedef struct acpi_table_rasf 1971 { 1972 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1973 UINT8 ChannelId[12]; 1974 1975 } ACPI_TABLE_RASF; 1976 1977 /* RASF Platform Communication Channel Shared Memory Region */ 1978 1979 typedef struct acpi_rasf_shared_memory 1980 { 1981 UINT32 Signature; 1982 UINT16 Command; 1983 UINT16 Status; 1984 UINT16 Version; 1985 UINT8 Capabilities[16]; 1986 UINT8 SetCapabilities[16]; 1987 UINT16 NumParameterBlocks; 1988 UINT32 SetCapabilitiesStatus; 1989 1990 } ACPI_RASF_SHARED_MEMORY; 1991 1992 /* RASF Parameter Block Structure Header */ 1993 1994 typedef struct acpi_rasf_parameter_block 1995 { 1996 UINT16 Type; 1997 UINT16 Version; 1998 UINT16 Length; 1999 2000 } ACPI_RASF_PARAMETER_BLOCK; 2001 2002 /* RASF Parameter Block Structure for PATROL_SCRUB */ 2003 2004 typedef struct acpi_rasf_patrol_scrub_parameter 2005 { 2006 ACPI_RASF_PARAMETER_BLOCK Header; 2007 UINT16 PatrolScrubCommand; 2008 UINT64 RequestedAddressRange[2]; 2009 UINT64 ActualAddressRange[2]; 2010 UINT16 Flags; 2011 UINT8 RequestedSpeed; 2012 2013 } ACPI_RASF_PATROL_SCRUB_PARAMETER; 2014 2015 /* Masks for Flags and Speed fields above */ 2016 2017 #define ACPI_RASF_SCRUBBER_RUNNING 1 2018 #define ACPI_RASF_SPEED (7<<1) 2019 #define ACPI_RASF_SPEED_SLOW (0<<1) 2020 #define ACPI_RASF_SPEED_MEDIUM (4<<1) 2021 #define ACPI_RASF_SPEED_FAST (7<<1) 2022 2023 /* Channel Commands */ 2024 2025 enum AcpiRasfCommands 2026 { 2027 ACPI_RASF_EXECUTE_RASF_COMMAND = 1 2028 }; 2029 2030 /* Platform RAS Capabilities */ 2031 2032 enum AcpiRasfCapabiliities 2033 { 2034 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0, 2035 ACPI_SW_PATROL_SCRUB_EXPOSED = 1 2036 }; 2037 2038 /* Patrol Scrub Commands */ 2039 2040 enum AcpiRasfPatrolScrubCommands 2041 { 2042 ACPI_RASF_GET_PATROL_PARAMETERS = 1, 2043 ACPI_RASF_START_PATROL_SCRUBBER = 2, 2044 ACPI_RASF_STOP_PATROL_SCRUBBER = 3 2045 }; 2046 2047 /* Channel Command flags */ 2048 2049 #define ACPI_RASF_GENERATE_SCI (1<<15) 2050 2051 /* Status values */ 2052 2053 enum AcpiRasfStatus 2054 { 2055 ACPI_RASF_SUCCESS = 0, 2056 ACPI_RASF_NOT_VALID = 1, 2057 ACPI_RASF_NOT_SUPPORTED = 2, 2058 ACPI_RASF_BUSY = 3, 2059 ACPI_RASF_FAILED = 4, 2060 ACPI_RASF_ABORTED = 5, 2061 ACPI_RASF_INVALID_DATA = 6 2062 }; 2063 2064 /* Status flags */ 2065 2066 #define ACPI_RASF_COMMAND_COMPLETE (1) 2067 #define ACPI_RASF_SCI_DOORBELL (1<<1) 2068 #define ACPI_RASF_ERROR (1<<2) 2069 #define ACPI_RASF_STATUS (0x1F<<3) 2070 2071 2072 /******************************************************************************* 2073 * 2074 * SBST - Smart Battery Specification Table 2075 * Version 1 2076 * 2077 ******************************************************************************/ 2078 2079 typedef struct acpi_table_sbst 2080 { 2081 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2082 UINT32 WarningLevel; 2083 UINT32 LowLevel; 2084 UINT32 CriticalLevel; 2085 2086 } ACPI_TABLE_SBST; 2087 2088 2089 /******************************************************************************* 2090 * 2091 * SDEI - Software Delegated Exception Interface Descriptor Table 2092 * 2093 * Conforms to "Software Delegated Exception Interface (SDEI)" ARM DEN0054A, 2094 * May 8th, 2017. Copyright 2017 ARM Ltd. 2095 * 2096 ******************************************************************************/ 2097 2098 typedef struct acpi_table_sdei 2099 { 2100 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2101 2102 } ACPI_TABLE_SDEI; 2103 2104 2105 /******************************************************************************* 2106 * 2107 * SDEV - Secure Devices Table (ACPI 6.2) 2108 * Version 1 2109 * 2110 ******************************************************************************/ 2111 2112 typedef struct acpi_table_sdev 2113 { 2114 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2115 2116 } ACPI_TABLE_SDEV; 2117 2118 2119 typedef struct acpi_sdev_header 2120 { 2121 UINT8 Type; 2122 UINT8 Flags; 2123 UINT16 Length; 2124 2125 } ACPI_SDEV_HEADER; 2126 2127 2128 /* Values for subtable type above */ 2129 2130 enum AcpiSdevType 2131 { 2132 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0, 2133 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1, 2134 ACPI_SDEV_TYPE_RESERVED = 2 /* 2 and greater are reserved */ 2135 }; 2136 2137 /* Values for flags above */ 2138 2139 #define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1) 2140 2141 /* 2142 * SDEV subtables 2143 */ 2144 2145 /* 0: Namespace Device Based Secure Device Structure */ 2146 2147 typedef struct acpi_sdev_namespace 2148 { 2149 ACPI_SDEV_HEADER Header; 2150 UINT16 DeviceIdOffset; 2151 UINT16 DeviceIdLength; 2152 UINT16 VendorDataOffset; 2153 UINT16 VendorDataLength; 2154 2155 } ACPI_SDEV_NAMESPACE; 2156 2157 /* 1: PCIe Endpoint Device Based Device Structure */ 2158 2159 typedef struct acpi_sdev_pcie 2160 { 2161 ACPI_SDEV_HEADER Header; 2162 UINT16 Segment; 2163 UINT16 StartBus; 2164 UINT16 PathOffset; 2165 UINT16 PathLength; 2166 UINT16 VendorDataOffset; 2167 UINT16 VendorDataLength; 2168 2169 } ACPI_SDEV_PCIE; 2170 2171 /* 1a: PCIe Endpoint path entry */ 2172 2173 typedef struct acpi_sdev_pcie_path 2174 { 2175 UINT8 Device; 2176 UINT8 Function; 2177 2178 } ACPI_SDEV_PCIE_PATH; 2179 2180 2181 /* Reset to default packing */ 2182 2183 #pragma pack() 2184 2185 #endif /* __ACTBL2_H__ */ 2186