1 /******************************************************************************* 2 * 3 * Module Name: hwregs - Read/write access functions for the various ACPI 4 * control and status registers. 5 * 6 ******************************************************************************/ 7 8 /****************************************************************************** 9 * 10 * 1. Copyright Notice 11 * 12 * Some or all of this work - Copyright (c) 1999 - 2017, Intel Corp. 13 * All rights reserved. 14 * 15 * 2. License 16 * 17 * 2.1. This is your license from Intel Corp. under its intellectual property 18 * rights. You may have additional license terms from the party that provided 19 * you this software, covering your right to use that party's intellectual 20 * property rights. 21 * 22 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 23 * copy of the source code appearing in this file ("Covered Code") an 24 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 25 * base code distributed originally by Intel ("Original Intel Code") to copy, 26 * make derivatives, distribute, use and display any portion of the Covered 27 * Code in any form, with the right to sublicense such rights; and 28 * 29 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 30 * license (with the right to sublicense), under only those claims of Intel 31 * patents that are infringed by the Original Intel Code, to make, use, sell, 32 * offer to sell, and import the Covered Code and derivative works thereof 33 * solely to the minimum extent necessary to exercise the above copyright 34 * license, and in no event shall the patent license extend to any additions 35 * to or modifications of the Original Intel Code. No other license or right 36 * is granted directly or by implication, estoppel or otherwise; 37 * 38 * The above copyright and patent license is granted only if the following 39 * conditions are met: 40 * 41 * 3. Conditions 42 * 43 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 44 * Redistribution of source code of any substantial portion of the Covered 45 * Code or modification with rights to further distribute source must include 46 * the above Copyright Notice, the above License, this list of Conditions, 47 * and the following Disclaimer and Export Compliance provision. In addition, 48 * Licensee must cause all Covered Code to which Licensee contributes to 49 * contain a file documenting the changes Licensee made to create that Covered 50 * Code and the date of any change. Licensee must include in that file the 51 * documentation of any changes made by any predecessor Licensee. Licensee 52 * must include a prominent statement that the modification is derived, 53 * directly or indirectly, from Original Intel Code. 54 * 55 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 56 * Redistribution of source code of any substantial portion of the Covered 57 * Code or modification without rights to further distribute source must 58 * include the following Disclaimer and Export Compliance provision in the 59 * documentation and/or other materials provided with distribution. In 60 * addition, Licensee may not authorize further sublicense of source of any 61 * portion of the Covered Code, and must include terms to the effect that the 62 * license from Licensee to its licensee is limited to the intellectual 63 * property embodied in the software Licensee provides to its licensee, and 64 * not to intellectual property embodied in modifications its licensee may 65 * make. 66 * 67 * 3.3. Redistribution of Executable. Redistribution in executable form of any 68 * substantial portion of the Covered Code or modification must reproduce the 69 * above Copyright Notice, and the following Disclaimer and Export Compliance 70 * provision in the documentation and/or other materials provided with the 71 * distribution. 72 * 73 * 3.4. Intel retains all right, title, and interest in and to the Original 74 * Intel Code. 75 * 76 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 77 * Intel shall be used in advertising or otherwise to promote the sale, use or 78 * other dealings in products derived from or relating to the Covered Code 79 * without prior written authorization from Intel. 80 * 81 * 4. Disclaimer and Export Compliance 82 * 83 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 84 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 85 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 86 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 87 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 88 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 89 * PARTICULAR PURPOSE. 90 * 91 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 92 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 93 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 94 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 95 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 96 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 97 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 98 * LIMITED REMEDY. 99 * 100 * 4.3. Licensee shall not export, either directly or indirectly, any of this 101 * software or system incorporating such software without first obtaining any 102 * required license or other approval from the U. S. Department of Commerce or 103 * any other agency or department of the United States Government. In the 104 * event Licensee exports any such software from the United States or 105 * re-exports any such software from a foreign destination, Licensee shall 106 * ensure that the distribution and export/re-export of the software is in 107 * compliance with all laws, regulations, orders, or other restrictions of the 108 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 109 * any of its subsidiaries will export/re-export any technical data, process, 110 * software, or service, directly or indirectly, to any country for which the 111 * United States government or any agency thereof requires an export license, 112 * other governmental approval, or letter of assurance, without first obtaining 113 * such license, approval or letter. 114 * 115 ***************************************************************************** 116 * 117 * Alternatively, you may choose to be licensed under the terms of the 118 * following license: 119 * 120 * Redistribution and use in source and binary forms, with or without 121 * modification, are permitted provided that the following conditions 122 * are met: 123 * 1. Redistributions of source code must retain the above copyright 124 * notice, this list of conditions, and the following disclaimer, 125 * without modification. 126 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 127 * substantially similar to the "NO WARRANTY" disclaimer below 128 * ("Disclaimer") and any redistribution must be conditioned upon 129 * including a substantially similar Disclaimer requirement for further 130 * binary redistribution. 131 * 3. Neither the names of the above-listed copyright holders nor the names 132 * of any contributors may be used to endorse or promote products derived 133 * from this software without specific prior written permission. 134 * 135 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 136 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 137 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 138 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 139 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 140 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 141 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 142 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 143 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 144 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 145 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 146 * 147 * Alternatively, you may choose to be licensed under the terms of the 148 * GNU General Public License ("GPL") version 2 as published by the Free 149 * Software Foundation. 150 * 151 *****************************************************************************/ 152 153 #include <contrib/dev/acpica/include/acpi.h> 154 #include <contrib/dev/acpica/include/accommon.h> 155 #include <contrib/dev/acpica/include/acevents.h> 156 157 #define _COMPONENT ACPI_HARDWARE 158 ACPI_MODULE_NAME ("hwregs") 159 160 161 #if (!ACPI_REDUCED_HARDWARE) 162 163 /* Local Prototypes */ 164 165 static UINT8 166 AcpiHwGetAccessBitWidth ( 167 UINT64 Address, 168 ACPI_GENERIC_ADDRESS *Reg, 169 UINT8 MaxBitWidth); 170 171 static ACPI_STATUS 172 AcpiHwReadMultiple ( 173 UINT32 *Value, 174 ACPI_GENERIC_ADDRESS *RegisterA, 175 ACPI_GENERIC_ADDRESS *RegisterB); 176 177 static ACPI_STATUS 178 AcpiHwWriteMultiple ( 179 UINT32 Value, 180 ACPI_GENERIC_ADDRESS *RegisterA, 181 ACPI_GENERIC_ADDRESS *RegisterB); 182 183 #endif /* !ACPI_REDUCED_HARDWARE */ 184 185 186 /****************************************************************************** 187 * 188 * FUNCTION: AcpiHwGetAccessBitWidth 189 * 190 * PARAMETERS: Address - GAS register address 191 * Reg - GAS register structure 192 * MaxBitWidth - Max BitWidth supported (32 or 64) 193 * 194 * RETURN: Status 195 * 196 * DESCRIPTION: Obtain optimal access bit width 197 * 198 ******************************************************************************/ 199 200 static UINT8 201 AcpiHwGetAccessBitWidth ( 202 UINT64 Address, 203 ACPI_GENERIC_ADDRESS *Reg, 204 UINT8 MaxBitWidth) 205 { 206 UINT8 AccessBitWidth; 207 208 209 /* 210 * GAS format "register", used by FADT: 211 * 1. Detected if BitOffset is 0 and BitWidth is 8/16/32/64; 212 * 2. AccessSize field is ignored and BitWidth field is used for 213 * determining the boundary of the IO accesses. 214 * GAS format "region", used by APEI registers: 215 * 1. Detected if BitOffset is not 0 or BitWidth is not 8/16/32/64; 216 * 2. AccessSize field is used for determining the boundary of the 217 * IO accesses; 218 * 3. BitOffset/BitWidth fields are used to describe the "region". 219 * 220 * Note: This algorithm assumes that the "Address" fields should always 221 * contain aligned values. 222 */ 223 if (!Reg->BitOffset && Reg->BitWidth && 224 ACPI_IS_POWER_OF_TWO (Reg->BitWidth) && 225 ACPI_IS_ALIGNED (Reg->BitWidth, 8)) 226 { 227 AccessBitWidth = Reg->BitWidth; 228 } 229 else if (Reg->AccessWidth) 230 { 231 AccessBitWidth = (1 << (Reg->AccessWidth + 2)); 232 } 233 else 234 { 235 AccessBitWidth = ACPI_ROUND_UP_POWER_OF_TWO_8 ( 236 Reg->BitOffset + Reg->BitWidth); 237 if (AccessBitWidth <= 8) 238 { 239 AccessBitWidth = 8; 240 } 241 else 242 { 243 while (!ACPI_IS_ALIGNED (Address, AccessBitWidth >> 3)) 244 { 245 AccessBitWidth >>= 1; 246 } 247 } 248 } 249 250 /* Maximum IO port access bit width is 32 */ 251 252 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_IO) 253 { 254 MaxBitWidth = 32; 255 } 256 257 /* 258 * Return access width according to the requested maximum access bit width, 259 * as the caller should know the format of the register and may enforce 260 * a 32-bit accesses. 261 */ 262 if (AccessBitWidth < MaxBitWidth) 263 { 264 return (AccessBitWidth); 265 } 266 return (MaxBitWidth); 267 } 268 269 270 /****************************************************************************** 271 * 272 * FUNCTION: AcpiHwValidateRegister 273 * 274 * PARAMETERS: Reg - GAS register structure 275 * MaxBitWidth - Max BitWidth supported (32 or 64) 276 * Address - Pointer to where the gas->address 277 * is returned 278 * 279 * RETURN: Status 280 * 281 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS 282 * pointer, Address, SpaceId, BitWidth, and BitOffset. 283 * 284 ******************************************************************************/ 285 286 ACPI_STATUS 287 AcpiHwValidateRegister ( 288 ACPI_GENERIC_ADDRESS *Reg, 289 UINT8 MaxBitWidth, 290 UINT64 *Address) 291 { 292 UINT8 BitWidth; 293 UINT8 AccessWidth; 294 295 296 /* Must have a valid pointer to a GAS structure */ 297 298 if (!Reg) 299 { 300 return (AE_BAD_PARAMETER); 301 } 302 303 /* 304 * Copy the target address. This handles possible alignment issues. 305 * Address must not be null. A null address also indicates an optional 306 * ACPI register that is not supported, so no error message. 307 */ 308 ACPI_MOVE_64_TO_64 (Address, &Reg->Address); 309 if (!(*Address)) 310 { 311 return (AE_BAD_ADDRESS); 312 } 313 314 /* Validate the SpaceID */ 315 316 if ((Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) && 317 (Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO)) 318 { 319 ACPI_ERROR ((AE_INFO, 320 "Unsupported address space: 0x%X", Reg->SpaceId)); 321 return (AE_SUPPORT); 322 } 323 324 /* Validate the AccessWidth */ 325 326 if (Reg->AccessWidth > 4) 327 { 328 ACPI_ERROR ((AE_INFO, 329 "Unsupported register access width: 0x%X", Reg->AccessWidth)); 330 return (AE_SUPPORT); 331 } 332 333 /* Validate the BitWidth, convert AccessWidth into number of bits */ 334 335 AccessWidth = AcpiHwGetAccessBitWidth (*Address, Reg, MaxBitWidth); 336 BitWidth = ACPI_ROUND_UP (Reg->BitOffset + Reg->BitWidth, AccessWidth); 337 if (MaxBitWidth < BitWidth) 338 { 339 ACPI_WARNING ((AE_INFO, 340 "Requested bit width 0x%X is smaller than register bit width 0x%X", 341 MaxBitWidth, BitWidth)); 342 return (AE_SUPPORT); 343 } 344 345 return (AE_OK); 346 } 347 348 349 /****************************************************************************** 350 * 351 * FUNCTION: AcpiHwRead 352 * 353 * PARAMETERS: Value - Where the value is returned 354 * Reg - GAS register structure 355 * 356 * RETURN: Status 357 * 358 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max 359 * version of AcpiRead, used internally since the overhead of 360 * 64-bit values is not needed. 361 * 362 * LIMITATIONS: <These limitations also apply to AcpiHwWrite> 363 * SpaceID must be SystemMemory or SystemIO. 364 * 365 ******************************************************************************/ 366 367 ACPI_STATUS 368 AcpiHwRead ( 369 UINT32 *Value, 370 ACPI_GENERIC_ADDRESS *Reg) 371 { 372 UINT64 Address; 373 UINT8 AccessWidth; 374 UINT32 BitWidth; 375 UINT8 BitOffset; 376 UINT64 Value64; 377 UINT32 Value32; 378 UINT8 Index; 379 ACPI_STATUS Status; 380 381 382 ACPI_FUNCTION_NAME (HwRead); 383 384 385 /* Validate contents of the GAS register */ 386 387 Status = AcpiHwValidateRegister (Reg, 32, &Address); 388 if (ACPI_FAILURE (Status)) 389 { 390 return (Status); 391 } 392 393 /* 394 * Initialize entire 32-bit return value to zero, convert AccessWidth 395 * into number of bits based 396 */ 397 *Value = 0; 398 AccessWidth = AcpiHwGetAccessBitWidth (Address, Reg, 32); 399 BitWidth = Reg->BitOffset + Reg->BitWidth; 400 BitOffset = Reg->BitOffset; 401 402 /* 403 * Two address spaces supported: Memory or IO. PCI_Config is 404 * not supported here because the GAS structure is insufficient 405 */ 406 Index = 0; 407 while (BitWidth) 408 { 409 if (BitOffset >= AccessWidth) 410 { 411 Value32 = 0; 412 BitOffset -= AccessWidth; 413 } 414 else 415 { 416 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) 417 { 418 Status = AcpiOsReadMemory ((ACPI_PHYSICAL_ADDRESS) 419 Address + Index * ACPI_DIV_8 (AccessWidth), 420 &Value64, AccessWidth); 421 Value32 = (UINT32) Value64; 422 } 423 else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 424 { 425 Status = AcpiHwReadPort ((ACPI_IO_ADDRESS) 426 Address + Index * ACPI_DIV_8 (AccessWidth), 427 &Value32, AccessWidth); 428 } 429 } 430 431 /* 432 * Use offset style bit writes because "Index * AccessWidth" is 433 * ensured to be less than 32-bits by AcpiHwValidateRegister(). 434 */ 435 ACPI_SET_BITS (Value, Index * AccessWidth, 436 ACPI_MASK_BITS_ABOVE_32 (AccessWidth), Value32); 437 438 BitWidth -= BitWidth > AccessWidth ? AccessWidth : BitWidth; 439 Index++; 440 } 441 442 ACPI_DEBUG_PRINT ((ACPI_DB_IO, 443 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", 444 *Value, AccessWidth, ACPI_FORMAT_UINT64 (Address), 445 AcpiUtGetRegionName (Reg->SpaceId))); 446 447 return (Status); 448 } 449 450 451 /****************************************************************************** 452 * 453 * FUNCTION: AcpiHwWrite 454 * 455 * PARAMETERS: Value - Value to be written 456 * Reg - GAS register structure 457 * 458 * RETURN: Status 459 * 460 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max 461 * version of AcpiWrite, used internally since the overhead of 462 * 64-bit values is not needed. 463 * 464 ******************************************************************************/ 465 466 ACPI_STATUS 467 AcpiHwWrite ( 468 UINT32 Value, 469 ACPI_GENERIC_ADDRESS *Reg) 470 { 471 UINT64 Address; 472 UINT8 AccessWidth; 473 UINT32 BitWidth; 474 UINT8 BitOffset; 475 UINT64 Value64; 476 UINT32 Value32; 477 UINT8 Index; 478 ACPI_STATUS Status; 479 480 481 ACPI_FUNCTION_NAME (HwWrite); 482 483 484 /* Validate contents of the GAS register */ 485 486 Status = AcpiHwValidateRegister (Reg, 32, &Address); 487 if (ACPI_FAILURE (Status)) 488 { 489 return (Status); 490 } 491 492 /* Convert AccessWidth into number of bits based */ 493 494 AccessWidth = AcpiHwGetAccessBitWidth (Address, Reg, 32); 495 BitWidth = Reg->BitOffset + Reg->BitWidth; 496 BitOffset = Reg->BitOffset; 497 498 /* 499 * Two address spaces supported: Memory or IO. PCI_Config is 500 * not supported here because the GAS structure is insufficient 501 */ 502 Index = 0; 503 while (BitWidth) 504 { 505 /* 506 * Use offset style bit reads because "Index * AccessWidth" is 507 * ensured to be less than 32-bits by AcpiHwValidateRegister(). 508 */ 509 Value32 = ACPI_GET_BITS (&Value, Index * AccessWidth, 510 ACPI_MASK_BITS_ABOVE_32 (AccessWidth)); 511 512 if (BitOffset >= AccessWidth) 513 { 514 BitOffset -= AccessWidth; 515 } 516 else 517 { 518 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) 519 { 520 Value64 = (UINT64) Value32; 521 Status = AcpiOsWriteMemory ((ACPI_PHYSICAL_ADDRESS) 522 Address + Index * ACPI_DIV_8 (AccessWidth), 523 Value64, AccessWidth); 524 } 525 else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 526 { 527 Status = AcpiHwWritePort ((ACPI_IO_ADDRESS) 528 Address + Index * ACPI_DIV_8 (AccessWidth), 529 Value32, AccessWidth); 530 } 531 } 532 533 /* 534 * Index * AccessWidth is ensured to be less than 32-bits by 535 * AcpiHwValidateRegister(). 536 */ 537 BitWidth -= BitWidth > AccessWidth ? AccessWidth : BitWidth; 538 Index++; 539 } 540 541 ACPI_DEBUG_PRINT ((ACPI_DB_IO, 542 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", 543 Value, AccessWidth, ACPI_FORMAT_UINT64 (Address), 544 AcpiUtGetRegionName (Reg->SpaceId))); 545 546 return (Status); 547 } 548 549 550 #if (!ACPI_REDUCED_HARDWARE) 551 /******************************************************************************* 552 * 553 * FUNCTION: AcpiHwClearAcpiStatus 554 * 555 * PARAMETERS: None 556 * 557 * RETURN: Status 558 * 559 * DESCRIPTION: Clears all fixed and general purpose status bits 560 * 561 ******************************************************************************/ 562 563 ACPI_STATUS 564 AcpiHwClearAcpiStatus ( 565 void) 566 { 567 ACPI_STATUS Status; 568 ACPI_CPU_FLAGS LockFlags = 0; 569 570 571 ACPI_FUNCTION_TRACE (HwClearAcpiStatus); 572 573 574 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n", 575 ACPI_BITMASK_ALL_FIXED_STATUS, 576 ACPI_FORMAT_UINT64 (AcpiGbl_XPm1aStatus.Address))); 577 578 LockFlags = AcpiOsAcquireLock (AcpiGbl_HardwareLock); 579 580 /* Clear the fixed events in PM1 A/B */ 581 582 Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_STATUS, 583 ACPI_BITMASK_ALL_FIXED_STATUS); 584 585 AcpiOsReleaseLock (AcpiGbl_HardwareLock, LockFlags); 586 587 if (ACPI_FAILURE (Status)) 588 { 589 goto Exit; 590 } 591 592 /* Clear the GPE Bits in all GPE registers in all GPE blocks */ 593 594 Status = AcpiEvWalkGpeList (AcpiHwClearGpeBlock, NULL); 595 596 Exit: 597 return_ACPI_STATUS (Status); 598 } 599 600 601 /******************************************************************************* 602 * 603 * FUNCTION: AcpiHwGetBitRegisterInfo 604 * 605 * PARAMETERS: RegisterId - Index of ACPI Register to access 606 * 607 * RETURN: The bitmask to be used when accessing the register 608 * 609 * DESCRIPTION: Map RegisterId into a register bitmask. 610 * 611 ******************************************************************************/ 612 613 ACPI_BIT_REGISTER_INFO * 614 AcpiHwGetBitRegisterInfo ( 615 UINT32 RegisterId) 616 { 617 ACPI_FUNCTION_ENTRY (); 618 619 620 if (RegisterId > ACPI_BITREG_MAX) 621 { 622 ACPI_ERROR ((AE_INFO, "Invalid BitRegister ID: 0x%X", RegisterId)); 623 return (NULL); 624 } 625 626 return (&AcpiGbl_BitRegisterInfo[RegisterId]); 627 } 628 629 630 /****************************************************************************** 631 * 632 * FUNCTION: AcpiHwWritePm1Control 633 * 634 * PARAMETERS: Pm1aControl - Value to be written to PM1A control 635 * Pm1bControl - Value to be written to PM1B control 636 * 637 * RETURN: Status 638 * 639 * DESCRIPTION: Write the PM1 A/B control registers. These registers are 640 * different than than the PM1 A/B status and enable registers 641 * in that different values can be written to the A/B registers. 642 * Most notably, the SLP_TYP bits can be different, as per the 643 * values returned from the _Sx predefined methods. 644 * 645 ******************************************************************************/ 646 647 ACPI_STATUS 648 AcpiHwWritePm1Control ( 649 UINT32 Pm1aControl, 650 UINT32 Pm1bControl) 651 { 652 ACPI_STATUS Status; 653 654 655 ACPI_FUNCTION_TRACE (HwWritePm1Control); 656 657 658 Status = AcpiHwWrite (Pm1aControl, &AcpiGbl_FADT.XPm1aControlBlock); 659 if (ACPI_FAILURE (Status)) 660 { 661 return_ACPI_STATUS (Status); 662 } 663 664 if (AcpiGbl_FADT.XPm1bControlBlock.Address) 665 { 666 Status = AcpiHwWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock); 667 } 668 return_ACPI_STATUS (Status); 669 } 670 671 672 /****************************************************************************** 673 * 674 * FUNCTION: AcpiHwRegisterRead 675 * 676 * PARAMETERS: RegisterId - ACPI Register ID 677 * ReturnValue - Where the register value is returned 678 * 679 * RETURN: Status and the value read. 680 * 681 * DESCRIPTION: Read from the specified ACPI register 682 * 683 ******************************************************************************/ 684 685 ACPI_STATUS 686 AcpiHwRegisterRead ( 687 UINT32 RegisterId, 688 UINT32 *ReturnValue) 689 { 690 UINT32 Value = 0; 691 ACPI_STATUS Status; 692 693 694 ACPI_FUNCTION_TRACE (HwRegisterRead); 695 696 697 switch (RegisterId) 698 { 699 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 700 701 Status = AcpiHwReadMultiple (&Value, 702 &AcpiGbl_XPm1aStatus, 703 &AcpiGbl_XPm1bStatus); 704 break; 705 706 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 707 708 Status = AcpiHwReadMultiple (&Value, 709 &AcpiGbl_XPm1aEnable, 710 &AcpiGbl_XPm1bEnable); 711 break; 712 713 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 714 715 Status = AcpiHwReadMultiple (&Value, 716 &AcpiGbl_FADT.XPm1aControlBlock, 717 &AcpiGbl_FADT.XPm1bControlBlock); 718 719 /* 720 * Zero the write-only bits. From the ACPI specification, "Hardware 721 * Write-Only Bits": "Upon reads to registers with write-only bits, 722 * software masks out all write-only bits." 723 */ 724 Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS; 725 break; 726 727 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 728 729 Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPm2ControlBlock); 730 break; 731 732 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 733 734 Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPmTimerBlock); 735 break; 736 737 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 738 739 Status = AcpiHwReadPort (AcpiGbl_FADT.SmiCommand, &Value, 8); 740 break; 741 742 default: 743 744 ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", 745 RegisterId)); 746 Status = AE_BAD_PARAMETER; 747 break; 748 } 749 750 if (ACPI_SUCCESS (Status)) 751 { 752 *ReturnValue = Value; 753 } 754 755 return_ACPI_STATUS (Status); 756 } 757 758 759 /****************************************************************************** 760 * 761 * FUNCTION: AcpiHwRegisterWrite 762 * 763 * PARAMETERS: RegisterId - ACPI Register ID 764 * Value - The value to write 765 * 766 * RETURN: Status 767 * 768 * DESCRIPTION: Write to the specified ACPI register 769 * 770 * NOTE: In accordance with the ACPI specification, this function automatically 771 * preserves the value of the following bits, meaning that these bits cannot be 772 * changed via this interface: 773 * 774 * PM1_CONTROL[0] = SCI_EN 775 * PM1_CONTROL[9] 776 * PM1_STATUS[11] 777 * 778 * ACPI References: 779 * 1) Hardware Ignored Bits: When software writes to a register with ignored 780 * bit fields, it preserves the ignored bit fields 781 * 2) SCI_EN: OSPM always preserves this bit position 782 * 783 ******************************************************************************/ 784 785 ACPI_STATUS 786 AcpiHwRegisterWrite ( 787 UINT32 RegisterId, 788 UINT32 Value) 789 { 790 ACPI_STATUS Status; 791 UINT32 ReadValue; 792 793 794 ACPI_FUNCTION_TRACE (HwRegisterWrite); 795 796 797 switch (RegisterId) 798 { 799 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 800 /* 801 * Handle the "ignored" bit in PM1 Status. According to the ACPI 802 * specification, ignored bits are to be preserved when writing. 803 * Normally, this would mean a read/modify/write sequence. However, 804 * preserving a bit in the status register is different. Writing a 805 * one clears the status, and writing a zero preserves the status. 806 * Therefore, we must always write zero to the ignored bit. 807 * 808 * This behavior is clarified in the ACPI 4.0 specification. 809 */ 810 Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; 811 812 Status = AcpiHwWriteMultiple (Value, 813 &AcpiGbl_XPm1aStatus, 814 &AcpiGbl_XPm1bStatus); 815 break; 816 817 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 818 819 Status = AcpiHwWriteMultiple (Value, 820 &AcpiGbl_XPm1aEnable, 821 &AcpiGbl_XPm1bEnable); 822 break; 823 824 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 825 /* 826 * Perform a read first to preserve certain bits (per ACPI spec) 827 * Note: This includes SCI_EN, we never want to change this bit 828 */ 829 Status = AcpiHwReadMultiple (&ReadValue, 830 &AcpiGbl_FADT.XPm1aControlBlock, 831 &AcpiGbl_FADT.XPm1bControlBlock); 832 if (ACPI_FAILURE (Status)) 833 { 834 goto Exit; 835 } 836 837 /* Insert the bits to be preserved */ 838 839 ACPI_INSERT_BITS (Value, ACPI_PM1_CONTROL_PRESERVED_BITS, ReadValue); 840 841 /* Now we can write the data */ 842 843 Status = AcpiHwWriteMultiple (Value, 844 &AcpiGbl_FADT.XPm1aControlBlock, 845 &AcpiGbl_FADT.XPm1bControlBlock); 846 break; 847 848 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 849 /* 850 * For control registers, all reserved bits must be preserved, 851 * as per the ACPI spec. 852 */ 853 Status = AcpiHwRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock); 854 if (ACPI_FAILURE (Status)) 855 { 856 goto Exit; 857 } 858 859 /* Insert the bits to be preserved */ 860 861 ACPI_INSERT_BITS (Value, ACPI_PM2_CONTROL_PRESERVED_BITS, ReadValue); 862 863 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock); 864 break; 865 866 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 867 868 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPmTimerBlock); 869 break; 870 871 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 872 873 /* SMI_CMD is currently always in IO space */ 874 875 Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand, Value, 8); 876 break; 877 878 default: 879 880 ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", 881 RegisterId)); 882 Status = AE_BAD_PARAMETER; 883 break; 884 } 885 886 Exit: 887 return_ACPI_STATUS (Status); 888 } 889 890 891 /****************************************************************************** 892 * 893 * FUNCTION: AcpiHwReadMultiple 894 * 895 * PARAMETERS: Value - Where the register value is returned 896 * RegisterA - First ACPI register (required) 897 * RegisterB - Second ACPI register (optional) 898 * 899 * RETURN: Status 900 * 901 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) 902 * 903 ******************************************************************************/ 904 905 static ACPI_STATUS 906 AcpiHwReadMultiple ( 907 UINT32 *Value, 908 ACPI_GENERIC_ADDRESS *RegisterA, 909 ACPI_GENERIC_ADDRESS *RegisterB) 910 { 911 UINT32 ValueA = 0; 912 UINT32 ValueB = 0; 913 ACPI_STATUS Status; 914 915 916 /* The first register is always required */ 917 918 Status = AcpiHwRead (&ValueA, RegisterA); 919 if (ACPI_FAILURE (Status)) 920 { 921 return (Status); 922 } 923 924 /* Second register is optional */ 925 926 if (RegisterB->Address) 927 { 928 Status = AcpiHwRead (&ValueB, RegisterB); 929 if (ACPI_FAILURE (Status)) 930 { 931 return (Status); 932 } 933 } 934 935 /* 936 * OR the two return values together. No shifting or masking is necessary, 937 * because of how the PM1 registers are defined in the ACPI specification: 938 * 939 * "Although the bits can be split between the two register blocks (each 940 * register block has a unique pointer within the FADT), the bit positions 941 * are maintained. The register block with unimplemented bits (that is, 942 * those implemented in the other register block) always returns zeros, 943 * and writes have no side effects" 944 */ 945 *Value = (ValueA | ValueB); 946 return (AE_OK); 947 } 948 949 950 /****************************************************************************** 951 * 952 * FUNCTION: AcpiHwWriteMultiple 953 * 954 * PARAMETERS: Value - The value to write 955 * RegisterA - First ACPI register (required) 956 * RegisterB - Second ACPI register (optional) 957 * 958 * RETURN: Status 959 * 960 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) 961 * 962 ******************************************************************************/ 963 964 static ACPI_STATUS 965 AcpiHwWriteMultiple ( 966 UINT32 Value, 967 ACPI_GENERIC_ADDRESS *RegisterA, 968 ACPI_GENERIC_ADDRESS *RegisterB) 969 { 970 ACPI_STATUS Status; 971 972 973 /* The first register is always required */ 974 975 Status = AcpiHwWrite (Value, RegisterA); 976 if (ACPI_FAILURE (Status)) 977 { 978 return (Status); 979 } 980 981 /* 982 * Second register is optional 983 * 984 * No bit shifting or clearing is necessary, because of how the PM1 985 * registers are defined in the ACPI specification: 986 * 987 * "Although the bits can be split between the two register blocks (each 988 * register block has a unique pointer within the FADT), the bit positions 989 * are maintained. The register block with unimplemented bits (that is, 990 * those implemented in the other register block) always returns zeros, 991 * and writes have no side effects" 992 */ 993 if (RegisterB->Address) 994 { 995 Status = AcpiHwWrite (Value, RegisterB); 996 } 997 998 return (Status); 999 } 1000 1001 #endif /* !ACPI_REDUCED_HARDWARE */ 1002