1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2022, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include <contrib/dev/acpica/include/acpi.h> 153 #include <contrib/dev/acpica/include/accommon.h> 154 #include <contrib/dev/acpica/include/acdisasm.h> 155 #include <contrib/dev/acpica/include/actbinfo.h> 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo1") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 194 /******************************************************************************* 195 * 196 * AEST - ARM Error Source table. Conforms to: 197 * ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document Sep 2020 198 * 199 ******************************************************************************/ 200 201 /* Common Subtable header (one per Subtable) */ 202 203 ACPI_DMTABLE_INFO AcpiDmTableInfoAestHdr[] = 204 { 205 {ACPI_DMT_AEST, ACPI_AESTH_OFFSET (Type), "Subtable Type", 0}, 206 {ACPI_DMT_UINT16, ACPI_AESTH_OFFSET (Length), "Length", DT_LENGTH}, 207 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0}, 208 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeSpecificOffset), "Node Specific Offset", 0}, 209 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterfaceOffset), "Node Interface Offset", 0}, 210 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptOffset), "Node Interrupt Array Offset", 0}, 211 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptCount), "Node Interrupt Array Count", 0}, 212 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (TimestampRate), "Timestamp Rate", 0}, 213 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0}, 214 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (ErrorInjectionRate), "Error Injection Rate", 0}, 215 ACPI_DMT_TERMINATOR 216 }; 217 218 /* 219 * AEST subtables (nodes) 220 */ 221 222 /* 0: Processor Error */ 223 224 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProcError[] = 225 { 226 {ACPI_DMT_UINT32, ACPI_AEST0_OFFSET (ProcessorId), "Processor ID", 0}, 227 {ACPI_DMT_AEST_RES, ACPI_AEST0_OFFSET (ResourceType), "Resource Type", 0}, 228 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0}, 229 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Flags), "Flags (decoded Below)", 0}, 230 {ACPI_DMT_FLAG0, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Global", 0}, 231 {ACPI_DMT_FLAG1, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Shared", 0}, 232 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Revision), "Revision", 0}, 233 {ACPI_DMT_UINT64, ACPI_AEST0_OFFSET (ProcessorAffinity), "Processor Affinity Structure", 0}, 234 ACPI_DMT_TERMINATOR 235 }; 236 237 /* 0RT: Processor Cache Resource */ 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoAestCacheRsrc[] = 240 { 241 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (CacheReference), "Cache Reference", 0}, 242 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0}, 243 ACPI_DMT_TERMINATOR 244 }; 245 246 /* 1RT: ProcessorTLB Resource */ 247 248 ACPI_DMTABLE_INFO AcpiDmTableInfoAestTlbRsrc[] = 249 { 250 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (TlbLevel), "TLB Level", 0}, 251 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}, 252 ACPI_DMT_TERMINATOR 253 }; 254 255 /* 2RT: Processor Generic Resource */ 256 257 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGenRsrc[] = 258 { 259 {ACPI_DMT_RAW_BUFFER, 0, "Resource", 0}, 260 ACPI_DMT_TERMINATOR 261 }; 262 263 /* 1: Memory Error */ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoAestMemError[] = 266 { 267 {ACPI_DMT_UINT32, ACPI_AEST1_OFFSET (SratProximityDomain), "Srat Proximity Domain", 0}, 268 ACPI_DMT_TERMINATOR 269 }; 270 271 /* 2: Smmu Error */ 272 273 ACPI_DMTABLE_INFO AcpiDmTableInfoAestSmmuError[] = 274 { 275 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 276 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (SubcomponentReference), "Subcomponent Reference", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* 3: Vendor Defined */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = 283 { 284 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiHid), "ACPI HID", 0}, 285 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiUid), "ACPI UID", 0}, 286 {ACPI_DMT_BUF16, ACPI_AEST3_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 287 ACPI_DMT_TERMINATOR 288 }; 289 290 /* 4: Gic Error */ 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = 293 { 294 {ACPI_DMT_AEST_GIC, ACPI_AEST4_OFFSET (InterfaceType), "GIC Interface Type", 0}, 295 {ACPI_DMT_UINT32, ACPI_AEST4_OFFSET (InstanceId), "Instance ID", 0}, 296 ACPI_DMT_TERMINATOR 297 }; 298 299 /* AestXface: Node Interface Structure */ 300 301 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = 302 { 303 {ACPI_DMT_AEST_XFACE, ACPI_AEST0D_OFFSET (Type), "Interface Type", 0}, 304 {ACPI_DMT_UINT24, ACPI_AEST0D_OFFSET (Reserved[0]), "Reserved", 0}, 305 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (Flags), "Flags (decoded below)", 0}, 306 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 307 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 308 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (Address), "Address", 0}, 309 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 310 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 311 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 312 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 313 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (AddressingMode), "Addressing Mode", 0}, 314 ACPI_DMT_TERMINATOR 315 }; 316 317 /* AestXrupt: Node Interrupt Structure */ 318 319 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = 320 { 321 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0E_OFFSET (Type), "Interrupt Type", 0}, 322 {ACPI_DMT_UINT16, ACPI_AEST0E_OFFSET (Reserved), "Reserved", 0}, 323 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (Flags), "Flags (decoded below)", 0}, 324 {ACPI_DMT_FLAG0, ACPI_AEST0E_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 325 {ACPI_DMT_UINT32, ACPI_AEST0E_OFFSET (Gsiv), "Gsiv", 0}, 326 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (IortId), "IortId", 0}, 327 {ACPI_DMT_UINT24, ACPI_AEST0E_OFFSET (Reserved1[0]), "Reserved", 0}, 328 ACPI_DMT_TERMINATOR 329 }; 330 331 332 /******************************************************************************* 333 * 334 * ASF - Alert Standard Format table (Signature "ASF!") 335 * 336 ******************************************************************************/ 337 338 /* Common Subtable header (one per Subtable) */ 339 340 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 341 { 342 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 343 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 344 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 345 ACPI_DMT_TERMINATOR 346 }; 347 348 /* 0: ASF Information */ 349 350 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 351 { 352 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 353 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 354 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 355 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 356 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 357 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 358 ACPI_DMT_TERMINATOR 359 }; 360 361 /* 1: ASF Alerts */ 362 363 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 364 { 365 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 366 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 367 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 368 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 369 ACPI_DMT_TERMINATOR 370 }; 371 372 /* 1a: ASF Alert data */ 373 374 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 375 { 376 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 377 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 378 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 379 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 380 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 381 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 382 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 383 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 384 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 385 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 386 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 387 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 388 ACPI_DMT_TERMINATOR 389 }; 390 391 /* 2: ASF Remote Control */ 392 393 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 394 { 395 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 396 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 397 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 398 ACPI_DMT_TERMINATOR 399 }; 400 401 /* 2a: ASF Control data */ 402 403 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 404 { 405 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 406 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 407 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 408 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 409 ACPI_DMT_TERMINATOR 410 }; 411 412 /* 3: ASF RMCP Boot Options */ 413 414 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 415 { 416 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 417 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 418 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 419 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 420 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 421 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 422 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 423 ACPI_DMT_TERMINATOR 424 }; 425 426 /* 4: ASF Address */ 427 428 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 429 { 430 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 431 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 432 ACPI_DMT_TERMINATOR 433 }; 434 435 436 /******************************************************************************* 437 * 438 * BDAT - BIOS Data ACPI Table 439 * 440 ******************************************************************************/ 441 442 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 443 { 444 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 445 ACPI_DMT_TERMINATOR 446 }; 447 448 449 /******************************************************************************* 450 * 451 * BERT - Boot Error Record table 452 * 453 ******************************************************************************/ 454 455 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 456 { 457 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 458 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 459 ACPI_DMT_TERMINATOR 460 }; 461 462 463 /******************************************************************************* 464 * 465 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 466 * 467 ******************************************************************************/ 468 469 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 470 { 471 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 472 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 473 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 474 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 475 476 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 477 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 478 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 479 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 480 ACPI_DMT_TERMINATOR 481 }; 482 483 484 /******************************************************************************* 485 * 486 * BOOT - Simple Boot Flag Table 487 * 488 ******************************************************************************/ 489 490 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 491 { 492 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 493 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 494 ACPI_DMT_TERMINATOR 495 }; 496 497 498 /******************************************************************************* 499 * 500 * CEDT - CXL Early Discovery Table 501 * 502 ******************************************************************************/ 503 504 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 505 { 506 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 507 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 508 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 509 ACPI_DMT_TERMINATOR 510 }; 511 512 /* 0: CXL Host Bridge Structure */ 513 514 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 515 { 516 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 517 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 518 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 519 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 520 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 521 ACPI_DMT_TERMINATOR 522 }; 523 524 /* 1: CXL Fixed Memory Window Structure */ 525 526 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1[] = 527 { 528 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Reserved1), "Reserved", 0}, 529 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (BaseHpa), "Window base address", 0}, 530 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (WindowSize), "Window size", 0}, 531 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members (2^n)", 0}, 532 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveArithmetic), "Interleave Arithmetic", 0}, 533 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Reserved2), "Reserved", 0}, 534 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Granularity), "Granularity", 0}, 535 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Restrictions), "Restrictions", 0}, 536 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (QtgId), "QtgId", 0}, 537 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (InterleaveTargets), "First Target", 0}, 538 ACPI_DMT_TERMINATOR 539 }; 540 541 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1_te[] = 542 { 543 {ACPI_DMT_UINT32, ACPI_CEDT1_TE_OFFSET (InterleaveTarget), "Next Target", 0}, 544 ACPI_DMT_TERMINATOR 545 }; 546 547 /******************************************************************************* 548 * 549 * CPEP - Corrected Platform Error Polling table 550 * 551 ******************************************************************************/ 552 553 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 554 { 555 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 556 ACPI_DMT_TERMINATOR 557 }; 558 559 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 560 { 561 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 562 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 563 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 564 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 565 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 566 ACPI_DMT_TERMINATOR 567 }; 568 569 570 /******************************************************************************* 571 * 572 * CSRT - Core System Resource Table 573 * 574 ******************************************************************************/ 575 576 /* Main table consists only of the standard ACPI table header */ 577 578 /* Resource Group subtable */ 579 580 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 581 { 582 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 583 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 584 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 585 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 586 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 587 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 588 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 589 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 590 ACPI_DMT_TERMINATOR 591 }; 592 593 /* Shared Info subtable */ 594 595 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 596 { 597 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 598 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 599 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 600 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 601 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 602 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 603 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 604 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 605 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 606 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 607 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 608 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 609 ACPI_DMT_TERMINATOR 610 }; 611 612 /* Resource Descriptor subtable */ 613 614 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 615 { 616 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 617 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 618 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 619 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 620 ACPI_DMT_TERMINATOR 621 }; 622 623 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 624 { 625 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 626 ACPI_DMT_TERMINATOR 627 }; 628 629 630 /******************************************************************************* 631 * 632 * DBG2 - Debug Port Table 2 633 * 634 ******************************************************************************/ 635 636 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 637 { 638 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 639 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 640 ACPI_DMT_TERMINATOR 641 }; 642 643 /* Debug Device Information Subtable */ 644 645 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 646 { 647 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 648 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 649 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 650 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 651 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 652 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 653 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 654 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 655 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 656 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 657 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 658 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 659 ACPI_DMT_TERMINATOR 660 }; 661 662 /* Variable-length data for the subtable */ 663 664 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 665 { 666 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 667 ACPI_DMT_TERMINATOR 668 }; 669 670 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 671 { 672 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 673 ACPI_DMT_TERMINATOR 674 }; 675 676 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 677 { 678 {ACPI_DMT_STRING, 0, "Namepath", 0}, 679 ACPI_DMT_TERMINATOR 680 }; 681 682 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 683 { 684 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 685 ACPI_DMT_TERMINATOR 686 }; 687 688 689 /******************************************************************************* 690 * 691 * DBGP - Debug Port 692 * 693 ******************************************************************************/ 694 695 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 696 { 697 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 698 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 699 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 700 ACPI_DMT_TERMINATOR 701 }; 702 703 704 /******************************************************************************* 705 * 706 * DMAR - DMA Remapping table 707 * 708 ******************************************************************************/ 709 710 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 711 { 712 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 713 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 714 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 715 ACPI_DMT_TERMINATOR 716 }; 717 718 /* Common Subtable header (one per Subtable) */ 719 720 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 721 { 722 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 723 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 724 ACPI_DMT_TERMINATOR 725 }; 726 727 /* Common device scope entry */ 728 729 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 730 { 731 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 732 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 733 {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 734 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 735 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 736 ACPI_DMT_TERMINATOR 737 }; 738 739 /* DMAR Subtables */ 740 741 /* 0: Hardware Unit Definition */ 742 743 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 744 { 745 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 746 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, 747 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 748 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 749 ACPI_DMT_TERMINATOR 750 }; 751 752 /* 1: Reserved Memory Definition */ 753 754 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 755 { 756 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 757 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 758 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 759 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 760 ACPI_DMT_TERMINATOR 761 }; 762 763 /* 2: Root Port ATS Capability Definition */ 764 765 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 766 { 767 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 768 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 769 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 770 ACPI_DMT_TERMINATOR 771 }; 772 773 /* 3: Remapping Hardware Static Affinity Structure */ 774 775 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 776 { 777 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 778 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 779 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 780 ACPI_DMT_TERMINATOR 781 }; 782 783 /* 4: ACPI Namespace Device Declaration Structure */ 784 785 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 786 { 787 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 788 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 789 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 790 ACPI_DMT_TERMINATOR 791 }; 792 793 /* 5: Hardware Unit Definition */ 794 795 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = 796 { 797 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Flags), "Flags", 0}, 798 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Reserved), "Reserved", 0}, 799 {ACPI_DMT_UINT16, ACPI_DMAR5_OFFSET (Segment), "PCI Segment Number", 0}, 800 ACPI_DMT_TERMINATOR 801 }; 802 803 /******************************************************************************* 804 * 805 * DRTM - Dynamic Root of Trust for Measurement table 806 * 807 ******************************************************************************/ 808 809 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 810 { 811 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 812 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 813 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 814 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 815 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 816 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 817 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 818 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 819 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 820 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 821 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 822 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 823 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 824 ACPI_DMT_TERMINATOR 825 }; 826 827 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 828 { 829 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 830 ACPI_DMT_TERMINATOR 831 }; 832 833 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 834 { 835 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 836 ACPI_DMT_TERMINATOR 837 }; 838 839 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 840 { 841 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 842 ACPI_DMT_TERMINATOR 843 }; 844 845 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 846 { 847 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 848 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 849 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 850 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 851 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 852 ACPI_DMT_TERMINATOR 853 }; 854 855 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 856 { 857 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 858 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 859 ACPI_DMT_TERMINATOR 860 }; 861 862 863 /******************************************************************************* 864 * 865 * ECDT - Embedded Controller Boot Resources Table 866 * 867 ******************************************************************************/ 868 869 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 870 { 871 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 872 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 873 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 874 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 875 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 876 ACPI_DMT_TERMINATOR 877 }; 878 879 880 /******************************************************************************* 881 * 882 * EINJ - Error Injection table 883 * 884 ******************************************************************************/ 885 886 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 887 { 888 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 889 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 890 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 891 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 892 ACPI_DMT_TERMINATOR 893 }; 894 895 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 896 { 897 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 898 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 899 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 900 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 901 902 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 903 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 904 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 905 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 906 ACPI_DMT_TERMINATOR 907 }; 908 909 910 /******************************************************************************* 911 * 912 * ERST - Error Record Serialization table 913 * 914 ******************************************************************************/ 915 916 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 917 { 918 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 919 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 920 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 921 ACPI_DMT_TERMINATOR 922 }; 923 924 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 925 { 926 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 927 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 928 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 929 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 930 931 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 932 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 933 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 934 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 935 ACPI_DMT_TERMINATOR 936 }; 937 938 939 /******************************************************************************* 940 * 941 * FPDT - Firmware Performance Data Table (ACPI 5.0) 942 * 943 ******************************************************************************/ 944 945 /* Main table consists of only the standard ACPI header - subtables follow */ 946 947 /* FPDT subtable header */ 948 949 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 950 { 951 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 952 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 953 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 954 ACPI_DMT_TERMINATOR 955 }; 956 957 /* 0: Firmware Basic Boot Performance Record */ 958 959 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 960 { 961 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 962 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 963 ACPI_DMT_TERMINATOR 964 }; 965 966 /* 1: S3 Performance Table Pointer Record */ 967 968 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 969 { 970 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 971 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 972 ACPI_DMT_TERMINATOR 973 }; 974 975 #if 0 976 /* Boot Performance Record, not supported at this time. */ 977 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 978 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 979 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 980 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 981 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 982 #endif 983 984 985 /******************************************************************************* 986 * 987 * GTDT - Generic Timer Description Table 988 * 989 ******************************************************************************/ 990 991 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 992 { 993 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 994 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 995 ACPI_DMT_NEW_LINE, 996 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 997 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 998 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 999 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 1000 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 1001 ACPI_DMT_NEW_LINE, 1002 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 1003 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 1004 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 1005 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 1006 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 1007 ACPI_DMT_NEW_LINE, 1008 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1009 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 1010 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 1011 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 1012 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 1013 ACPI_DMT_NEW_LINE, 1014 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 1015 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 1016 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 1017 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 1018 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 1019 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 1020 ACPI_DMT_NEW_LINE, 1021 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 1022 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 1023 ACPI_DMT_TERMINATOR 1024 }; 1025 1026 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 1027 1028 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 1029 { 1030 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 1031 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 1032 ACPI_DMT_TERMINATOR 1033 }; 1034 1035 /* GTDT Subtable header (one per Subtable) */ 1036 1037 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1038 { 1039 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1040 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1041 ACPI_DMT_TERMINATOR 1042 }; 1043 1044 /* GTDT Subtables */ 1045 1046 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1047 { 1048 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1049 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1050 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1051 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1052 ACPI_DMT_TERMINATOR 1053 }; 1054 1055 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1056 { 1057 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1058 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1059 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1060 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1061 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1062 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1063 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1064 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1065 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1066 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1067 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1068 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1069 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1070 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1071 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1072 ACPI_DMT_TERMINATOR 1073 }; 1074 1075 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1076 { 1077 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1078 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1079 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1080 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1081 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1082 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1083 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1084 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1085 ACPI_DMT_TERMINATOR 1086 }; 1087 1088 1089 /******************************************************************************* 1090 * 1091 * HEST - Hardware Error Source table 1092 * 1093 ******************************************************************************/ 1094 1095 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1096 { 1097 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1098 ACPI_DMT_TERMINATOR 1099 }; 1100 1101 /* Common HEST structures for subtables */ 1102 1103 #define ACPI_DM_HEST_HEADER \ 1104 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1105 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1106 1107 #define ACPI_DM_HEST_AER \ 1108 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1109 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1110 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1111 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1112 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1113 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1114 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1115 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1116 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1117 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1118 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1119 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1120 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1121 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1122 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1123 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1124 1125 1126 /* HEST Subtables */ 1127 1128 /* 0: IA32 Machine Check Exception */ 1129 1130 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1131 { 1132 ACPI_DM_HEST_HEADER, 1133 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1134 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1135 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1136 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1137 1138 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1139 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1140 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1141 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1142 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1143 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1144 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1145 ACPI_DMT_TERMINATOR 1146 }; 1147 1148 /* 1: IA32 Corrected Machine Check */ 1149 1150 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1151 { 1152 ACPI_DM_HEST_HEADER, 1153 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1154 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1155 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1156 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1157 1158 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1159 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1160 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1161 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1162 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1163 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1164 ACPI_DMT_TERMINATOR 1165 }; 1166 1167 /* 2: IA32 Non-Maskable Interrupt */ 1168 1169 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1170 { 1171 ACPI_DM_HEST_HEADER, 1172 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1173 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1174 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1175 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1176 ACPI_DMT_TERMINATOR 1177 }; 1178 1179 /* 6: PCI Express Root Port AER */ 1180 1181 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1182 { 1183 ACPI_DM_HEST_HEADER, 1184 ACPI_DM_HEST_AER, 1185 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1186 ACPI_DMT_TERMINATOR 1187 }; 1188 1189 /* 7: PCI Express AER (AER Endpoint) */ 1190 1191 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1192 { 1193 ACPI_DM_HEST_HEADER, 1194 ACPI_DM_HEST_AER, 1195 ACPI_DMT_TERMINATOR 1196 }; 1197 1198 /* 8: PCI Express/PCI-X Bridge AER */ 1199 1200 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1201 { 1202 ACPI_DM_HEST_HEADER, 1203 ACPI_DM_HEST_AER, 1204 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1205 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1206 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1207 ACPI_DMT_TERMINATOR 1208 }; 1209 1210 /* 9: Generic Hardware Error Source */ 1211 1212 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1213 { 1214 ACPI_DM_HEST_HEADER, 1215 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1216 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1217 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1218 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1219 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1220 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1221 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1222 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1223 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1224 ACPI_DMT_TERMINATOR 1225 }; 1226 1227 /* 10: Generic Hardware Error Source - Version 2 */ 1228 1229 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1230 { 1231 ACPI_DM_HEST_HEADER, 1232 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1233 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1234 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1235 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1236 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1237 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1238 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1239 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1240 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1241 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1242 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1243 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1244 ACPI_DMT_TERMINATOR 1245 }; 1246 1247 /* 11: IA32 Deferred Machine Check */ 1248 1249 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1250 { 1251 ACPI_DM_HEST_HEADER, 1252 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1253 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1254 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1255 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1256 1257 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1258 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1259 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1260 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1261 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1262 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1263 ACPI_DMT_TERMINATOR 1264 }; 1265 1266 /* Notification Structure */ 1267 1268 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1269 { 1270 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1271 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1272 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1273 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1274 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1275 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1276 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1277 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1278 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1279 ACPI_DMT_TERMINATOR 1280 }; 1281 1282 1283 /* 1284 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1285 * ACPI_HEST_IA_CORRECTED structures. 1286 */ 1287 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1288 { 1289 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1290 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1291 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1292 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1293 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1294 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1295 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1296 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1297 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1298 ACPI_DMT_TERMINATOR 1299 }; 1300 1301 1302 /******************************************************************************* 1303 * 1304 * HMAT - Heterogeneous Memory Attributes Table 1305 * 1306 ******************************************************************************/ 1307 1308 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1309 { 1310 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1311 ACPI_DMT_TERMINATOR 1312 }; 1313 1314 /* Common HMAT structure header (one per Subtable) */ 1315 1316 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1317 { 1318 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1319 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1320 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1321 ACPI_DMT_TERMINATOR 1322 }; 1323 1324 /* HMAT subtables */ 1325 1326 /* 0x00: Memory proximity domain attributes */ 1327 1328 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1329 { 1330 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1331 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1332 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1333 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1334 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1335 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1336 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1337 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1338 ACPI_DMT_TERMINATOR 1339 }; 1340 1341 /* 0x01: System Locality Latency and Bandwidth Information */ 1342 1343 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1344 { 1345 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1346 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1347 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1348 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1349 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1350 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1351 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1352 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1353 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1354 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1355 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1356 ACPI_DMT_TERMINATOR 1357 }; 1358 1359 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1360 { 1361 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1362 ACPI_DMT_TERMINATOR 1363 }; 1364 1365 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1366 { 1367 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1368 ACPI_DMT_TERMINATOR 1369 }; 1370 1371 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1372 { 1373 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1374 ACPI_DMT_TERMINATOR 1375 }; 1376 1377 /* 0x02: Memory Side Cache Information */ 1378 1379 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1380 { 1381 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1382 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1383 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1384 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1385 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1386 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1387 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1388 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1389 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1390 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, 1391 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1392 ACPI_DMT_TERMINATOR 1393 }; 1394 1395 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1396 { 1397 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1398 ACPI_DMT_TERMINATOR 1399 }; 1400 1401 1402 /******************************************************************************* 1403 * 1404 * HPET - High Precision Event Timer table 1405 * 1406 ******************************************************************************/ 1407 1408 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1409 { 1410 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1411 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1412 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1413 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1414 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1415 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1416 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1417 ACPI_DMT_TERMINATOR 1418 }; 1419 /*! [End] no source code translation !*/ 1420