1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include <contrib/dev/acpica/include/acpi.h> 153 #include <contrib/dev/acpica/include/accommon.h> 154 #include <contrib/dev/acpica/include/acdisasm.h> 155 #include <contrib/dev/acpica/include/actbinfo.h> 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 /******************************************************************************* 194 * 195 * Common ACPI table header 196 * 197 ******************************************************************************/ 198 199 ACPI_DMTABLE_INFO AcpiDmTableInfoHeader[] = 200 { 201 {ACPI_DMT_SIG, ACPI_HDR_OFFSET (Signature[0]), "Signature", 0}, 202 {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (Length), "Table Length", DT_LENGTH}, 203 {ACPI_DMT_UINT8, ACPI_HDR_OFFSET (Revision), "Revision", 0}, 204 {ACPI_DMT_CHKSUM, ACPI_HDR_OFFSET (Checksum), "Checksum", 0}, 205 {ACPI_DMT_NAME6, ACPI_HDR_OFFSET (OemId[0]), "Oem ID", 0}, 206 {ACPI_DMT_NAME8, ACPI_HDR_OFFSET (OemTableId[0]), "Oem Table ID", 0}, 207 {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (OemRevision), "Oem Revision", 0}, 208 {ACPI_DMT_NAME4, ACPI_HDR_OFFSET (AslCompilerId[0]), "Asl Compiler ID", 0}, 209 {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (AslCompilerRevision), "Asl Compiler Revision", 0}, 210 ACPI_DMT_TERMINATOR 211 }; 212 213 214 /******************************************************************************* 215 * 216 * GAS - Generic Address Structure 217 * 218 ******************************************************************************/ 219 220 ACPI_DMTABLE_INFO AcpiDmTableInfoGas[] = 221 { 222 {ACPI_DMT_SPACEID, ACPI_GAS_OFFSET (SpaceId), "Space ID", 0}, 223 {ACPI_DMT_UINT8, ACPI_GAS_OFFSET (BitWidth), "Bit Width", 0}, 224 {ACPI_DMT_UINT8, ACPI_GAS_OFFSET (BitOffset), "Bit Offset", 0}, 225 {ACPI_DMT_ACCWIDTH, ACPI_GAS_OFFSET (AccessWidth), "Encoded Access Width", 0}, 226 {ACPI_DMT_UINT64, ACPI_GAS_OFFSET (Address), "Address", 0}, 227 ACPI_DMT_TERMINATOR 228 }; 229 230 231 /******************************************************************************* 232 * 233 * RSDP - Root System Description Pointer (Signature is "RSD PTR ") 234 * 235 ******************************************************************************/ 236 237 ACPI_DMTABLE_INFO AcpiDmTableInfoRsdp1[] = 238 { 239 {ACPI_DMT_NAME8, ACPI_RSDP_OFFSET (Signature[0]), "Signature", 0}, 240 {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (Checksum), "Checksum", 0}, 241 {ACPI_DMT_NAME6, ACPI_RSDP_OFFSET (OemId[0]), "Oem ID", 0}, 242 {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (Revision), "Revision", 0}, 243 {ACPI_DMT_UINT32, ACPI_RSDP_OFFSET (RsdtPhysicalAddress), "RSDT Address", 0}, 244 ACPI_DMT_TERMINATOR 245 }; 246 247 /* ACPI 2.0+ Extensions */ 248 249 ACPI_DMTABLE_INFO AcpiDmTableInfoRsdp2[] = 250 { 251 {ACPI_DMT_UINT32, ACPI_RSDP_OFFSET (Length), "Length", DT_LENGTH}, 252 {ACPI_DMT_UINT64, ACPI_RSDP_OFFSET (XsdtPhysicalAddress), "XSDT Address", 0}, 253 {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (ExtendedChecksum), "Extended Checksum", 0}, 254 {ACPI_DMT_UINT24, ACPI_RSDP_OFFSET (Reserved[0]), "Reserved", 0}, 255 ACPI_DMT_TERMINATOR 256 }; 257 258 259 /******************************************************************************* 260 * 261 * FACS - Firmware ACPI Control Structure 262 * 263 ******************************************************************************/ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoFacs[] = 266 { 267 {ACPI_DMT_NAME4, ACPI_FACS_OFFSET (Signature[0]), "Signature", 0}, 268 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (Length), "Length", DT_LENGTH}, 269 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (HardwareSignature), "Hardware Signature", 0}, 270 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (FirmwareWakingVector), "32 Firmware Waking Vector", 0}, 271 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (GlobalLock), "Global Lock", 0}, 272 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 273 {ACPI_DMT_FLAG0, ACPI_FACS_FLAG_OFFSET (Flags,0), "S4BIOS Support Present", 0}, 274 {ACPI_DMT_FLAG1, ACPI_FACS_FLAG_OFFSET (Flags,0), "64-bit Wake Supported (V2)", 0}, 275 {ACPI_DMT_UINT64, ACPI_FACS_OFFSET (XFirmwareWakingVector), "64 Firmware Waking Vector", 0}, 276 {ACPI_DMT_UINT8, ACPI_FACS_OFFSET (Version), "Version", 0}, 277 {ACPI_DMT_UINT24, ACPI_FACS_OFFSET (Reserved[0]), "Reserved", 0}, 278 {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (OspmFlags), "OspmFlags (decoded below)", DT_FLAG}, 279 {ACPI_DMT_FLAG0, ACPI_FACS_FLAG_OFFSET (OspmFlags,0), "64-bit Wake Env Required (V2)", 0}, 280 ACPI_DMT_TERMINATOR 281 }; 282 283 284 /******************************************************************************* 285 * 286 * FADT - Fixed ACPI Description Table (Signature is FACP) 287 * 288 ******************************************************************************/ 289 290 /* ACPI 1.0 FADT (Version 1) */ 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoFadt1[] = 293 { 294 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Facs), "FACS Address", 0}, 295 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Dsdt), "DSDT Address", DT_NON_ZERO}, 296 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Model), "Model", 0}, 297 {ACPI_DMT_FADTPM, ACPI_FADT_OFFSET (PreferredProfile), "PM Profile", 0}, 298 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (SciInterrupt), "SCI Interrupt", 0}, 299 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (SmiCommand), "SMI Command Port", 0}, 300 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (AcpiEnable), "ACPI Enable Value", 0}, 301 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (AcpiDisable), "ACPI Disable Value", 0}, 302 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (S4BiosRequest), "S4BIOS Command", 0}, 303 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (PstateControl), "P-State Control", 0}, 304 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1aEventBlock), "PM1A Event Block Address", 0}, 305 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1bEventBlock), "PM1B Event Block Address", 0}, 306 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1aControlBlock), "PM1A Control Block Address", 0}, 307 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1bControlBlock), "PM1B Control Block Address", 0}, 308 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm2ControlBlock), "PM2 Control Block Address", 0}, 309 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (PmTimerBlock), "PM Timer Block Address", 0}, 310 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Gpe0Block), "GPE0 Block Address", 0}, 311 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Gpe1Block), "GPE1 Block Address", 0}, 312 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm1EventLength), "PM1 Event Block Length", 0}, 313 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm1ControlLength), "PM1 Control Block Length", 0}, 314 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm2ControlLength), "PM2 Control Block Length", 0}, 315 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (PmTimerLength), "PM Timer Block Length", 0}, 316 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe0BlockLength), "GPE0 Block Length", 0}, 317 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe1BlockLength), "GPE1 Block Length", 0}, 318 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe1Base), "GPE1 Base Offset", 0}, 319 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (CstControl), "_CST Support", 0}, 320 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (C2Latency), "C2 Latency", 0}, 321 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (C3Latency), "C3 Latency", 0}, 322 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (FlushSize), "CPU Cache Size", 0}, 323 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (FlushStride), "Cache Flush Stride", 0}, 324 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DutyOffset), "Duty Cycle Offset", 0}, 325 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DutyWidth), "Duty Cycle Width", 0}, 326 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DayAlarm), "RTC Day Alarm Index", 0}, 327 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (MonthAlarm), "RTC Month Alarm Index", 0}, 328 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Century), "RTC Century Index", 0}, 329 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (BootFlags), "Boot Flags (decoded below)", DT_FLAG}, 330 331 /* Boot Architecture Flags byte 0 */ 332 333 {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "Legacy Devices Supported (V2)", 0}, 334 {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "8042 Present on ports 60/64 (V2)", 0}, 335 {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "VGA Not Present (V4)", 0}, 336 {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "MSI Not Supported (V4)", 0}, 337 {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "PCIe ASPM Not Supported (V4)", 0}, 338 {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (BootFlags,0), "CMOS RTC Not Present (V5)", 0}, 339 340 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Reserved), "Reserved", 0}, 341 {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 342 343 /* Flags byte 0 */ 344 345 {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,0), "WBINVD instruction is operational (V1)", 0}, 346 {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,0), "WBINVD flushes all caches (V1)", 0}, 347 {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,0), "All CPUs support C1 (V1)", 0}, 348 {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,0), "C2 works on MP system (V1)", 0}, 349 {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (Flags,0), "Control Method Power Button (V1)", 0}, 350 {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (Flags,0), "Control Method Sleep Button (V1)", 0}, 351 {ACPI_DMT_FLAG6, ACPI_FADT_FLAG_OFFSET (Flags,0), "RTC wake not in fixed reg space (V1)", 0}, 352 {ACPI_DMT_FLAG7, ACPI_FADT_FLAG_OFFSET (Flags,0), "RTC can wake system from S4 (V1)", 0}, 353 354 /* Flags byte 1 */ 355 356 {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,1), "32-bit PM Timer (V1)", 0}, 357 {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,1), "Docking Supported (V1)", 0}, 358 {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,1), "Reset Register Supported (V2)", 0}, 359 {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,1), "Sealed Case (V3)", 0}, 360 {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (Flags,1), "Headless - No Video (V3)", 0}, 361 {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (Flags,1), "Use native instr after SLP_TYPx (V3)", 0}, 362 {ACPI_DMT_FLAG6, ACPI_FADT_FLAG_OFFSET (Flags,1), "PCIEXP_WAK Bits Supported (V4)", 0}, 363 {ACPI_DMT_FLAG7, ACPI_FADT_FLAG_OFFSET (Flags,1), "Use Platform Timer (V4)", 0}, 364 365 /* Flags byte 2 */ 366 367 {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,2), "RTC_STS valid on S4 wake (V4)", 0}, 368 {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,2), "Remote Power-on capable (V4)", 0}, 369 {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,2), "Use APIC Cluster Model (V4)", 0}, 370 {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,2), "Use APIC Physical Destination Mode (V4)", 0}, 371 {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (Flags,2), "Hardware Reduced (V5)", 0}, 372 {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (Flags,2), "Low Power S0 Idle (V5)", 0}, 373 ACPI_DMT_TERMINATOR 374 }; 375 376 /* ACPI 1.0 MS Extensions (FADT version 2) */ 377 378 ACPI_DMTABLE_INFO AcpiDmTableInfoFadt2[] = 379 { 380 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (ResetRegister), "Reset Register", 0}, 381 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (ResetValue), "Value to cause reset", 0}, 382 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (ArmBootFlags), "Reserved", 0}, 383 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (MinorRevision), "Reserved", 0}, 384 ACPI_DMT_TERMINATOR 385 }; 386 387 /* ACPI 2.0+ Extensions (FADT version 3, 4, and 5) */ 388 389 ACPI_DMTABLE_INFO AcpiDmTableInfoFadt3[] = 390 { 391 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (ResetRegister), "Reset Register", 0}, 392 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (ResetValue), "Value to cause reset", 0}, 393 {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (ArmBootFlags), "ARM Flags (decoded below)", DT_FLAG}, 394 {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET(ArmBootFlags,0), "PSCI Compliant", 0}, 395 {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET(ArmBootFlags,0), "Must use HVC for PSCI", 0}, 396 ACPI_DMT_NEW_LINE, 397 {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (MinorRevision), "FADT Minor Revision", 0}, 398 {ACPI_DMT_UINT64, ACPI_FADT_OFFSET (XFacs), "FACS Address", 0}, 399 {ACPI_DMT_UINT64, ACPI_FADT_OFFSET (XDsdt), "DSDT Address", 0}, 400 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1aEventBlock), "PM1A Event Block", 0}, 401 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1bEventBlock), "PM1B Event Block", 0}, 402 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1aControlBlock), "PM1A Control Block", 0}, 403 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1bControlBlock), "PM1B Control Block", 0}, 404 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm2ControlBlock), "PM2 Control Block", 0}, 405 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPmTimerBlock), "PM Timer Block", 0}, 406 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XGpe0Block), "GPE0 Block", 0}, 407 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XGpe1Block), "GPE1 Block", 0}, 408 ACPI_DMT_TERMINATOR 409 }; 410 411 /* ACPI 5.0 Extensions (FADT version 5) */ 412 413 ACPI_DMTABLE_INFO AcpiDmTableInfoFadt5[] = 414 { 415 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (SleepControl), "Sleep Control Register", 0}, 416 {ACPI_DMT_GAS, ACPI_FADT_OFFSET (SleepStatus), "Sleep Status Register", 0}, 417 ACPI_DMT_TERMINATOR 418 }; 419 420 /* ACPI 6.0 Extensions (FADT version 6) */ 421 422 ACPI_DMTABLE_INFO AcpiDmTableInfoFadt6[] = 423 { 424 {ACPI_DMT_UINT64, ACPI_FADT_OFFSET (HypervisorId), "Hypervisor ID", 0}, 425 ACPI_DMT_TERMINATOR 426 }; 427 428 429 /* 430 * Remaining tables are not consumed directly by the ACPICA subsystem 431 */ 432 433 /******************************************************************************* 434 * 435 * ASF - Alert Standard Format table (Signature "ASF!") 436 * 437 ******************************************************************************/ 438 439 /* Common Subtable header (one per Subtable) */ 440 441 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 442 { 443 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 444 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 445 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 446 ACPI_DMT_TERMINATOR 447 }; 448 449 /* 0: ASF Information */ 450 451 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 452 { 453 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 454 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 455 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 456 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 457 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 458 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 459 ACPI_DMT_TERMINATOR 460 }; 461 462 /* 1: ASF Alerts */ 463 464 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 465 { 466 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 467 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 468 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 469 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 470 ACPI_DMT_TERMINATOR 471 }; 472 473 /* 1a: ASF Alert data */ 474 475 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 476 { 477 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 478 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 479 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 480 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 481 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 482 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 483 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 484 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 485 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 486 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 487 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 488 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 489 ACPI_DMT_TERMINATOR 490 }; 491 492 /* 2: ASF Remote Control */ 493 494 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 495 { 496 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 497 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 498 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 499 ACPI_DMT_TERMINATOR 500 }; 501 502 /* 2a: ASF Control data */ 503 504 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 505 { 506 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 507 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 508 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 509 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 510 ACPI_DMT_TERMINATOR 511 }; 512 513 /* 3: ASF RMCP Boot Options */ 514 515 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 516 { 517 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 518 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 519 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 520 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 521 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 522 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 523 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 524 ACPI_DMT_TERMINATOR 525 }; 526 527 /* 4: ASF Address */ 528 529 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 530 { 531 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 532 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 533 ACPI_DMT_TERMINATOR 534 }; 535 536 537 /******************************************************************************* 538 * 539 * BERT - Boot Error Record table 540 * 541 ******************************************************************************/ 542 543 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 544 { 545 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 546 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 547 ACPI_DMT_TERMINATOR 548 }; 549 550 551 /******************************************************************************* 552 * 553 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 554 * 555 ******************************************************************************/ 556 557 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 558 { 559 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 560 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 561 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 562 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 563 564 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 565 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 566 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 567 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 568 ACPI_DMT_TERMINATOR 569 }; 570 571 572 /******************************************************************************* 573 * 574 * BOOT - Simple Boot Flag Table 575 * 576 ******************************************************************************/ 577 578 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 579 { 580 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 581 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 582 ACPI_DMT_TERMINATOR 583 }; 584 585 586 /******************************************************************************* 587 * 588 * CPEP - Corrected Platform Error Polling table 589 * 590 ******************************************************************************/ 591 592 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 593 { 594 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 595 ACPI_DMT_TERMINATOR 596 }; 597 598 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 599 { 600 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 601 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 602 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 603 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 604 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 605 ACPI_DMT_TERMINATOR 606 }; 607 608 609 /******************************************************************************* 610 * 611 * CSRT - Core System Resource Table 612 * 613 ******************************************************************************/ 614 615 /* Main table consists only of the standard ACPI table header */ 616 617 /* Resource Group subtable */ 618 619 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 620 { 621 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 622 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 623 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 624 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 625 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 626 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 627 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 628 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 629 ACPI_DMT_TERMINATOR 630 }; 631 632 /* Shared Info subtable */ 633 634 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 635 { 636 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 637 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 638 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 639 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 640 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 641 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 642 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 643 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 644 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 645 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 646 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 647 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 648 ACPI_DMT_TERMINATOR 649 }; 650 651 /* Resource Descriptor subtable */ 652 653 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 654 { 655 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 656 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 657 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 658 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 659 ACPI_DMT_TERMINATOR 660 }; 661 662 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 663 { 664 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 665 ACPI_DMT_TERMINATOR 666 }; 667 668 669 /******************************************************************************* 670 * 671 * DBG2 - Debug Port Table 2 672 * 673 ******************************************************************************/ 674 675 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 676 { 677 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 678 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 679 ACPI_DMT_TERMINATOR 680 }; 681 682 /* Debug Device Information Subtable */ 683 684 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 685 { 686 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 687 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 688 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 689 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 690 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 691 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 692 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 693 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 694 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 695 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 696 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 697 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 698 ACPI_DMT_TERMINATOR 699 }; 700 701 /* Variable-length data for the subtable */ 702 703 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 704 { 705 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 706 ACPI_DMT_TERMINATOR 707 }; 708 709 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 710 { 711 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 712 ACPI_DMT_TERMINATOR 713 }; 714 715 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 716 { 717 {ACPI_DMT_STRING, 0, "Namepath", 0}, 718 ACPI_DMT_TERMINATOR 719 }; 720 721 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 722 { 723 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 724 ACPI_DMT_TERMINATOR 725 }; 726 727 728 /******************************************************************************* 729 * 730 * DBGP - Debug Port 731 * 732 ******************************************************************************/ 733 734 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 735 { 736 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 737 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 738 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 739 ACPI_DMT_TERMINATOR 740 }; 741 742 743 /******************************************************************************* 744 * 745 * DMAR - DMA Remapping table 746 * 747 ******************************************************************************/ 748 749 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 750 { 751 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 752 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 753 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 754 ACPI_DMT_TERMINATOR 755 }; 756 757 /* Common Subtable header (one per Subtable) */ 758 759 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 760 { 761 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 762 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 763 ACPI_DMT_TERMINATOR 764 }; 765 766 /* Common device scope entry */ 767 768 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 769 { 770 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 771 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 772 {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 773 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 774 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 775 ACPI_DMT_TERMINATOR 776 }; 777 778 /* DMAR Subtables */ 779 780 /* 0: Hardware Unit Definition */ 781 782 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 783 { 784 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 785 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, 786 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 787 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 788 ACPI_DMT_TERMINATOR 789 }; 790 791 /* 1: Reserved Memory Definition */ 792 793 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 794 { 795 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 796 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 797 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 798 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 799 ACPI_DMT_TERMINATOR 800 }; 801 802 /* 2: Root Port ATS Capability Definition */ 803 804 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 805 { 806 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 807 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 808 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 809 ACPI_DMT_TERMINATOR 810 }; 811 812 /* 3: Remapping Hardware Static Affinity Structure */ 813 814 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 815 { 816 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 817 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 818 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 819 ACPI_DMT_TERMINATOR 820 }; 821 822 /* 4: ACPI Namespace Device Declaration Structure */ 823 824 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 825 { 826 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 827 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 828 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 829 ACPI_DMT_TERMINATOR 830 }; 831 832 833 /******************************************************************************* 834 * 835 * DRTM - Dynamic Root of Trust for Measurement table 836 * 837 ******************************************************************************/ 838 839 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 840 { 841 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 842 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 843 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 844 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 845 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 846 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 847 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 848 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 849 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 850 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 851 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 852 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 853 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 854 ACPI_DMT_TERMINATOR 855 }; 856 857 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 858 { 859 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 860 ACPI_DMT_TERMINATOR 861 }; 862 863 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 864 { 865 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 866 ACPI_DMT_TERMINATOR 867 }; 868 869 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 870 { 871 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 872 ACPI_DMT_TERMINATOR 873 }; 874 875 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 876 { 877 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 878 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 879 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 880 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 881 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 882 ACPI_DMT_TERMINATOR 883 }; 884 885 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 886 { 887 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 888 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 889 ACPI_DMT_TERMINATOR 890 }; 891 892 893 /******************************************************************************* 894 * 895 * ECDT - Embedded Controller Boot Resources Table 896 * 897 ******************************************************************************/ 898 899 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 900 { 901 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 902 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 903 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 904 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 905 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 906 ACPI_DMT_TERMINATOR 907 }; 908 909 910 /******************************************************************************* 911 * 912 * EINJ - Error Injection table 913 * 914 ******************************************************************************/ 915 916 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 917 { 918 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 919 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 920 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 921 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 922 ACPI_DMT_TERMINATOR 923 }; 924 925 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 926 { 927 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 928 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 929 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 930 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 931 932 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 933 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 934 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 935 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 936 ACPI_DMT_TERMINATOR 937 }; 938 939 940 /******************************************************************************* 941 * 942 * ERST - Error Record Serialization table 943 * 944 ******************************************************************************/ 945 946 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 947 { 948 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 949 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 950 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 951 ACPI_DMT_TERMINATOR 952 }; 953 954 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 955 { 956 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 957 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 958 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 959 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 960 961 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 962 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 963 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 964 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 965 ACPI_DMT_TERMINATOR 966 }; 967 968 969 /******************************************************************************* 970 * 971 * FPDT - Firmware Performance Data Table (ACPI 5.0) 972 * 973 ******************************************************************************/ 974 975 /* Main table consists of only the standard ACPI header - subtables follow */ 976 977 /* FPDT subtable header */ 978 979 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 980 { 981 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 982 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 983 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 984 ACPI_DMT_TERMINATOR 985 }; 986 987 /* 0: Firmware Basic Boot Performance Record */ 988 989 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 990 { 991 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 992 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 993 ACPI_DMT_TERMINATOR 994 }; 995 996 /* 1: S3 Performance Table Pointer Record */ 997 998 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 999 { 1000 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 1001 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 1002 ACPI_DMT_TERMINATOR 1003 }; 1004 1005 #if 0 1006 /* Boot Performance Record, not supported at this time. */ 1007 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 1008 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 1009 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 1010 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 1011 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 1012 #endif 1013 1014 1015 /******************************************************************************* 1016 * 1017 * GTDT - Generic Timer Description Table 1018 * 1019 ******************************************************************************/ 1020 1021 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 1022 { 1023 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 1024 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 1025 ACPI_DMT_NEW_LINE, 1026 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 1027 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 1028 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 1029 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 1030 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 1031 ACPI_DMT_NEW_LINE, 1032 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 1033 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 1034 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 1035 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 1036 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 1037 ACPI_DMT_NEW_LINE, 1038 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1039 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 1040 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 1041 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 1042 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 1043 ACPI_DMT_NEW_LINE, 1044 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 1045 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 1046 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 1047 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 1048 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 1049 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 1050 ACPI_DMT_NEW_LINE, 1051 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 1052 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 1053 ACPI_DMT_TERMINATOR 1054 }; 1055 1056 /* GTDT Subtable header (one per Subtable) */ 1057 1058 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1059 { 1060 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1061 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1062 ACPI_DMT_TERMINATOR 1063 }; 1064 1065 /* GTDT Subtables */ 1066 1067 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1068 { 1069 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1070 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1071 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1072 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1073 ACPI_DMT_TERMINATOR 1074 }; 1075 1076 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1077 { 1078 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1079 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1080 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1081 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1082 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1083 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1084 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1085 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1086 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1087 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1088 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1089 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1090 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1091 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1092 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1093 ACPI_DMT_TERMINATOR 1094 }; 1095 1096 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1097 { 1098 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1099 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1100 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1101 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1102 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1103 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1104 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1105 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1106 ACPI_DMT_TERMINATOR 1107 }; 1108 1109 1110 /******************************************************************************* 1111 * 1112 * HEST - Hardware Error Source table 1113 * 1114 ******************************************************************************/ 1115 1116 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1117 { 1118 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1119 ACPI_DMT_TERMINATOR 1120 }; 1121 1122 /* Common HEST structures for subtables */ 1123 1124 #define ACPI_DM_HEST_HEADER \ 1125 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1126 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1127 1128 #define ACPI_DM_HEST_AER \ 1129 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1130 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1131 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1132 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1133 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1134 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1135 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1136 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1137 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1138 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1139 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1140 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1141 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1142 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1143 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1144 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1145 1146 1147 /* HEST Subtables */ 1148 1149 /* 0: IA32 Machine Check Exception */ 1150 1151 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1152 { 1153 ACPI_DM_HEST_HEADER, 1154 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1155 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1156 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1157 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1158 1159 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1160 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1161 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1162 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1163 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1164 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1165 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1166 ACPI_DMT_TERMINATOR 1167 }; 1168 1169 /* 1: IA32 Corrected Machine Check */ 1170 1171 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1172 { 1173 ACPI_DM_HEST_HEADER, 1174 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1175 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1176 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1177 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1178 1179 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1180 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1181 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1182 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1183 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1184 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1185 ACPI_DMT_TERMINATOR 1186 }; 1187 1188 /* 2: IA32 Non-Maskable Interrupt */ 1189 1190 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1191 { 1192 ACPI_DM_HEST_HEADER, 1193 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1194 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1195 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1196 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1197 ACPI_DMT_TERMINATOR 1198 }; 1199 1200 /* 6: PCI Express Root Port AER */ 1201 1202 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1203 { 1204 ACPI_DM_HEST_HEADER, 1205 ACPI_DM_HEST_AER, 1206 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1207 ACPI_DMT_TERMINATOR 1208 }; 1209 1210 /* 7: PCI Express AER (AER Endpoint) */ 1211 1212 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1213 { 1214 ACPI_DM_HEST_HEADER, 1215 ACPI_DM_HEST_AER, 1216 ACPI_DMT_TERMINATOR 1217 }; 1218 1219 /* 8: PCI Express/PCI-X Bridge AER */ 1220 1221 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1222 { 1223 ACPI_DM_HEST_HEADER, 1224 ACPI_DM_HEST_AER, 1225 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1226 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1227 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1228 ACPI_DMT_TERMINATOR 1229 }; 1230 1231 /* 9: Generic Hardware Error Source */ 1232 1233 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1234 { 1235 ACPI_DM_HEST_HEADER, 1236 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1237 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1238 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1239 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1240 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1241 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1242 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1243 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1244 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1245 ACPI_DMT_TERMINATOR 1246 }; 1247 1248 /* 10: Generic Hardware Error Source - Version 2 */ 1249 1250 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1251 { 1252 ACPI_DM_HEST_HEADER, 1253 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1254 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1255 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1256 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1257 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1258 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1259 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1260 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1261 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1262 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1263 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1264 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1265 ACPI_DMT_TERMINATOR 1266 }; 1267 1268 /* 11: IA32 Deferred Machine Check */ 1269 1270 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1271 { 1272 ACPI_DM_HEST_HEADER, 1273 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1274 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1275 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1276 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1277 1278 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1279 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1280 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1281 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1282 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1283 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1284 ACPI_DMT_TERMINATOR 1285 }; 1286 1287 /* Notification Structure */ 1288 1289 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1290 { 1291 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1292 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1293 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1294 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1295 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1296 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1297 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1298 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1299 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1300 ACPI_DMT_TERMINATOR 1301 }; 1302 1303 1304 /* 1305 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1306 * ACPI_HEST_IA_CORRECTED structures. 1307 */ 1308 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1309 { 1310 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1311 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1312 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1313 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1314 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1315 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1316 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1317 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1318 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1319 ACPI_DMT_TERMINATOR 1320 }; 1321 1322 1323 /******************************************************************************* 1324 * 1325 * HPET - High Precision Event Timer table 1326 * 1327 ******************************************************************************/ 1328 1329 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1330 { 1331 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1332 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1333 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1334 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1335 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1336 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1337 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1338 ACPI_DMT_TERMINATOR 1339 }; 1340 1341 1342 /******************************************************************************* 1343 * 1344 * HMAT - Heterogeneous Memory Attributes Table 1345 * 1346 ******************************************************************************/ 1347 1348 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1349 { 1350 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1351 ACPI_DMT_TERMINATOR 1352 }; 1353 1354 /* Common HMAT structure header (one per Subtable) */ 1355 1356 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1357 { 1358 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1359 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1360 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1361 ACPI_DMT_TERMINATOR 1362 }; 1363 1364 /* HMAT subtables */ 1365 1366 /* 0x00: Memory Subsystem Address Range */ 1367 1368 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1369 { 1370 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1371 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1372 {ACPI_DMT_FLAG1, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Memory Proximity Domain Valid", 0}, 1373 {ACPI_DMT_FLAG2, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Reservation Hint", 0}, 1374 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1375 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (ProcessorPD), "Processor Proximity Domain", 0}, 1376 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1377 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1378 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (PhysicalAddressBase), "Physical Address Range Base", 0}, 1379 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (PhysicalAddressLength), "Physical Address Range Size", 0}, 1380 ACPI_DMT_TERMINATOR 1381 }; 1382 1383 /* 0x01: System Locality Latency and Bandwidth Information */ 1384 1385 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1386 { 1387 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1388 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, 1389 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1390 {ACPI_DMT_UINT16, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1391 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1392 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1393 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1394 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1395 ACPI_DMT_TERMINATOR 1396 }; 1397 1398 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1399 { 1400 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1401 ACPI_DMT_TERMINATOR 1402 }; 1403 1404 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1405 { 1406 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1407 ACPI_DMT_TERMINATOR 1408 }; 1409 1410 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1411 { 1412 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1413 ACPI_DMT_TERMINATOR 1414 }; 1415 1416 /* 0x02: Memory Side Cache Information */ 1417 1418 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1419 { 1420 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1421 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1422 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1423 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1424 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1425 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1426 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1427 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1428 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1429 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, 1430 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1431 ACPI_DMT_TERMINATOR 1432 }; 1433 1434 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1435 { 1436 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1437 ACPI_DMT_TERMINATOR 1438 }; 1439 1440 1441 /******************************************************************************* 1442 * 1443 * IORT - IO Remapping Table 1444 * 1445 ******************************************************************************/ 1446 1447 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 1448 { 1449 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 1450 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 1451 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 1452 ACPI_DMT_TERMINATOR 1453 }; 1454 1455 /* Optional padding field */ 1456 1457 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 1458 { 1459 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 1460 ACPI_DMT_TERMINATOR 1461 }; 1462 1463 /* Common Subtable header (one per Subtable) */ 1464 1465 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 1466 { 1467 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 1468 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 1469 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 1470 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Reserved), "Reserved", 0}, 1471 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 1472 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 1473 ACPI_DMT_TERMINATOR 1474 }; 1475 1476 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 1477 { 1478 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 1479 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 1480 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 1481 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 1482 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 1483 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 1484 ACPI_DMT_TERMINATOR 1485 }; 1486 1487 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 1488 { 1489 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 1490 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 1491 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 1492 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 1493 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 1494 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 1495 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 1496 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 1497 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 1498 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 1499 ACPI_DMT_TERMINATOR 1500 }; 1501 1502 /* IORT subtables */ 1503 1504 /* 0x00: ITS Group */ 1505 1506 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 1507 { 1508 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 1509 ACPI_DMT_TERMINATOR 1510 }; 1511 1512 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 1513 { 1514 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 1515 ACPI_DMT_TERMINATOR 1516 }; 1517 1518 /* 0x01: Named Component */ 1519 1520 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 1521 { 1522 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 1523 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 1524 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 1525 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 1526 ACPI_DMT_TERMINATOR 1527 }; 1528 1529 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 1530 { 1531 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 1532 ACPI_DMT_TERMINATOR 1533 }; 1534 1535 /* 0x02: PCI Root Complex */ 1536 1537 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 1538 { 1539 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 1540 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 1541 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 1542 ACPI_DMT_TERMINATOR 1543 }; 1544 1545 /* 0x03: SMMUv1/2 */ 1546 1547 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 1548 { 1549 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 1550 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 1551 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 1552 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 1553 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 1554 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 1555 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 1556 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 1557 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 1558 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 1559 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 1560 ACPI_DMT_TERMINATOR 1561 }; 1562 1563 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 1564 { 1565 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 1566 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 1567 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 1568 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 1569 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 1570 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 1571 ACPI_DMT_TERMINATOR 1572 }; 1573 1574 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 1575 { 1576 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 1577 ACPI_DMT_TERMINATOR 1578 }; 1579 1580 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 1581 { 1582 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 1583 ACPI_DMT_TERMINATOR 1584 }; 1585 1586 /* 0x04: SMMUv3 */ 1587 1588 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 1589 { 1590 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 1591 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 1592 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 1593 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 1594 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 1595 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 1596 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 1597 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 1598 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 1599 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 1600 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 1601 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 1602 {ACPI_DMT_UINT8, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 1603 {ACPI_DMT_UINT8, ACPI_IORT4_OFFSET (Reserved1), "Reserved", 0}, 1604 {ACPI_DMT_UINT16, ACPI_IORT4_OFFSET (Reserved2), "Reserved", 0}, 1605 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 1606 ACPI_DMT_TERMINATOR 1607 }; 1608 1609 1610 /******************************************************************************* 1611 * 1612 * IVRS - I/O Virtualization Reporting Structure 1613 * 1614 ******************************************************************************/ 1615 1616 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 1617 { 1618 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 1619 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 1620 ACPI_DMT_TERMINATOR 1621 }; 1622 1623 /* Common Subtable header (one per Subtable) */ 1624 1625 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHdr[] = 1626 { 1627 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 1628 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags", 0}, 1629 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 1630 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 1631 ACPI_DMT_TERMINATOR 1632 }; 1633 1634 /* IVRS subtables */ 1635 1636 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 1637 1638 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs0[] = 1639 { 1640 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 1641 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 1642 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 1643 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 1644 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (Reserved), "Reserved", 0}, 1645 ACPI_DMT_TERMINATOR 1646 }; 1647 1648 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Block */ 1649 1650 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs1[] = 1651 { 1652 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 1653 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 1654 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 1655 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 1656 ACPI_DMT_TERMINATOR 1657 }; 1658 1659 /* Device entry header for IVHD block */ 1660 1661 #define ACPI_DMT_IVRS_DE_HEADER \ 1662 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (Type), "Entry Type", 0}, \ 1663 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 1664 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting", 0} 1665 1666 /* 4-byte device entry */ 1667 1668 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 1669 { 1670 ACPI_DMT_IVRS_DE_HEADER, 1671 {ACPI_DMT_EXIT, 0, NULL, 0}, 1672 }; 1673 1674 /* 8-byte device entry */ 1675 1676 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 1677 { 1678 ACPI_DMT_IVRS_DE_HEADER, 1679 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 1680 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 1681 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 1682 ACPI_DMT_TERMINATOR 1683 }; 1684 1685 /* 8-byte device entry */ 1686 1687 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 1688 { 1689 ACPI_DMT_IVRS_DE_HEADER, 1690 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 1691 ACPI_DMT_TERMINATOR 1692 }; 1693 1694 /* 8-byte device entry */ 1695 1696 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 1697 { 1698 ACPI_DMT_IVRS_DE_HEADER, 1699 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 1700 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 1701 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 1702 ACPI_DMT_TERMINATOR 1703 }; 1704 1705 1706 /******************************************************************************* 1707 * 1708 * LPIT - Low Power Idle Table 1709 * 1710 ******************************************************************************/ 1711 1712 /* Main table consists only of the standard ACPI table header */ 1713 1714 /* Common Subtable header (one per Subtable) */ 1715 1716 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 1717 { 1718 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 1719 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 1720 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 1721 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 1722 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1723 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 1724 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 1725 ACPI_DMT_TERMINATOR 1726 }; 1727 1728 /* LPIT Subtables */ 1729 1730 /* 0: Native C-state */ 1731 1732 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 1733 { 1734 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 1735 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 1736 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 1737 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 1738 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 1739 ACPI_DMT_TERMINATOR 1740 }; 1741 1742 1743 /******************************************************************************* 1744 * 1745 * MADT - Multiple APIC Description Table and subtables 1746 * 1747 ******************************************************************************/ 1748 1749 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 1750 { 1751 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 1752 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1753 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 1754 ACPI_DMT_TERMINATOR 1755 }; 1756 1757 /* Common Subtable header (one per Subtable) */ 1758 1759 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 1760 { 1761 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 1762 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 1763 ACPI_DMT_TERMINATOR 1764 }; 1765 1766 /* MADT Subtables */ 1767 1768 /* 0: processor APIC */ 1769 1770 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 1771 { 1772 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 1773 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 1774 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 1775 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 1776 ACPI_DMT_TERMINATOR 1777 }; 1778 1779 /* 1: IO APIC */ 1780 1781 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 1782 { 1783 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 1784 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 1785 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 1786 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 1787 ACPI_DMT_TERMINATOR 1788 }; 1789 1790 /* 2: Interrupt Override */ 1791 1792 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 1793 { 1794 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 1795 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 1796 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 1797 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 1798 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 1799 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 1800 ACPI_DMT_TERMINATOR 1801 }; 1802 1803 /* 3: NMI Sources */ 1804 1805 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 1806 { 1807 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 1808 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 1809 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 1810 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 1811 ACPI_DMT_TERMINATOR 1812 }; 1813 1814 /* 4: Local APIC NMI */ 1815 1816 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 1817 { 1818 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 1819 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 1820 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 1821 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 1822 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 1823 ACPI_DMT_TERMINATOR 1824 }; 1825 1826 /* 5: Address Override */ 1827 1828 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 1829 { 1830 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 1831 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 1832 ACPI_DMT_TERMINATOR 1833 }; 1834 1835 /* 6: I/O Sapic */ 1836 1837 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 1838 { 1839 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 1840 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 1841 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 1842 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 1843 ACPI_DMT_TERMINATOR 1844 }; 1845 1846 /* 7: Local Sapic */ 1847 1848 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 1849 { 1850 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 1851 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 1852 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 1853 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 1854 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 1855 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 1856 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 1857 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 1858 ACPI_DMT_TERMINATOR 1859 }; 1860 1861 /* 8: Platform Interrupt Source */ 1862 1863 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 1864 { 1865 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 1866 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 1867 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 1868 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 1869 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 1870 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 1871 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 1872 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 1873 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1874 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 1875 ACPI_DMT_TERMINATOR 1876 }; 1877 1878 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 1879 1880 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 1881 { 1882 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 1883 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 1884 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 1885 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 1886 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 1887 ACPI_DMT_TERMINATOR 1888 }; 1889 1890 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 1891 1892 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 1893 { 1894 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 1895 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 1896 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 1897 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 1898 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 1899 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 1900 ACPI_DMT_TERMINATOR 1901 }; 1902 1903 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 1904 1905 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 1906 { 1907 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 1908 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 1909 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 1910 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1911 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 1912 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 1913 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 1914 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 1915 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 1916 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 1917 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 1918 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 1919 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 1920 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 1921 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 1922 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 1923 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 1924 {ACPI_DMT_UINT24, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 1925 ACPI_DMT_TERMINATOR 1926 }; 1927 1928 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 1929 1930 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 1931 { 1932 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 1933 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 1934 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 1935 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 1936 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 1937 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 1938 ACPI_DMT_TERMINATOR 1939 }; 1940 1941 /* 13: Generic MSI Frame (ACPI 5.1) */ 1942 1943 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 1944 { 1945 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 1946 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 1947 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 1948 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1949 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 1950 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 1951 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 1952 ACPI_DMT_TERMINATOR 1953 }; 1954 1955 /* 14: Generic Redistributor (ACPI 5.1) */ 1956 1957 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 1958 { 1959 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 1960 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 1961 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 1962 ACPI_DMT_TERMINATOR 1963 }; 1964 1965 /* 15: Generic Translator (ACPI 6.0) */ 1966 1967 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 1968 { 1969 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 1970 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 1971 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 1972 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 1973 ACPI_DMT_TERMINATOR 1974 }; 1975 1976 1977 /******************************************************************************* 1978 * 1979 * MCFG - PCI Memory Mapped Configuration table and Subtable 1980 * 1981 ******************************************************************************/ 1982 1983 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 1984 { 1985 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 1986 ACPI_DMT_TERMINATOR 1987 }; 1988 1989 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 1990 { 1991 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 1992 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 1993 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 1994 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 1995 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 1996 ACPI_DMT_TERMINATOR 1997 }; 1998 1999 2000 /******************************************************************************* 2001 * 2002 * MCHI - Management Controller Host Interface table 2003 * 2004 ******************************************************************************/ 2005 2006 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 2007 { 2008 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 2009 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 2010 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 2011 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 2012 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 2013 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 2014 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 2015 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 2016 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 2017 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 2018 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 2019 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 2020 ACPI_DMT_TERMINATOR 2021 }; 2022 2023 2024 /******************************************************************************* 2025 * 2026 * MPST - Memory Power State Table 2027 * 2028 ******************************************************************************/ 2029 2030 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 2031 { 2032 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 2033 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 2034 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 2035 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 2036 ACPI_DMT_TERMINATOR 2037 }; 2038 2039 /* MPST subtables */ 2040 2041 /* 0: Memory Power Node Structure */ 2042 2043 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 2044 { 2045 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2046 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 2047 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 2048 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 2049 2050 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 2051 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 2052 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 2053 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 2054 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 2055 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 2056 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 2057 ACPI_DMT_TERMINATOR 2058 }; 2059 2060 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 2061 2062 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 2063 { 2064 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 2065 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 2066 ACPI_DMT_TERMINATOR 2067 }; 2068 2069 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 2070 2071 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 2072 { 2073 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 2074 ACPI_DMT_TERMINATOR 2075 }; 2076 2077 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 2078 2079 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 2080 { 2081 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 2082 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 2083 ACPI_DMT_TERMINATOR 2084 }; 2085 2086 /* 02: Memory Power State Characteristics Structure */ 2087 2088 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 2089 { 2090 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 2091 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2092 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 2093 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 2094 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 2095 2096 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 2097 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 2098 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 2099 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 2100 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 2101 ACPI_DMT_TERMINATOR 2102 }; 2103 2104 2105 /******************************************************************************* 2106 * 2107 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 2108 * 2109 ******************************************************************************/ 2110 2111 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 2112 { 2113 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 2114 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 2115 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 2116 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 2117 ACPI_DMT_TERMINATOR 2118 }; 2119 2120 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 2121 2122 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 2123 { 2124 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 2125 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 2126 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 2127 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 2128 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 2129 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 2130 ACPI_DMT_TERMINATOR 2131 }; 2132 2133 2134 /******************************************************************************* 2135 * 2136 * MTMR - MID Timer Table 2137 * 2138 ******************************************************************************/ 2139 2140 ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr[] = 2141 { 2142 ACPI_DMT_TERMINATOR 2143 }; 2144 2145 /* MTMR Subtables - MTMR Entry */ 2146 2147 ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr0[] = 2148 { 2149 {ACPI_DMT_GAS, ACPI_MTMR0_OFFSET (PhysicalAddress), "PhysicalAddress", 0}, 2150 {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Frequency), "Frequency", 0}, 2151 {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Irq), "IRQ", 0}, 2152 ACPI_DMT_TERMINATOR 2153 }; 2154 2155 2156 /******************************************************************************* 2157 * 2158 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 2159 * 2160 ******************************************************************************/ 2161 2162 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 2163 { 2164 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 2165 ACPI_DMT_TERMINATOR 2166 }; 2167 2168 /* Common Subtable header */ 2169 2170 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 2171 { 2172 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 2173 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 2174 ACPI_DMT_TERMINATOR 2175 }; 2176 2177 /* 0: System Physical Address Range Structure */ 2178 2179 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 2180 { 2181 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 2182 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2183 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 2184 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 2185 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 2186 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2187 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Address Range GUID", 0}, 2188 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 2189 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 2190 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 2191 ACPI_DMT_TERMINATOR 2192 }; 2193 2194 /* 1: Memory Device to System Address Range Map Structure */ 2195 2196 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 2197 { 2198 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 2199 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 2200 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 2201 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 2202 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 2203 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 2204 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 2205 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 2206 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 2207 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 2208 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 2209 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 2210 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 2211 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 2212 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 2213 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 2214 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 2215 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 2216 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 2217 ACPI_DMT_TERMINATOR 2218 }; 2219 2220 /* 2: Interleave Structure */ 2221 2222 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 2223 { 2224 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 2225 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 2226 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 2227 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 2228 ACPI_DMT_TERMINATOR 2229 }; 2230 2231 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 2232 { 2233 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 2234 ACPI_DMT_TERMINATOR 2235 }; 2236 2237 /* 3: SMBIOS Management Information Structure */ 2238 2239 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 2240 { 2241 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 2242 ACPI_DMT_TERMINATOR 2243 }; 2244 2245 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 2246 { 2247 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 2248 ACPI_DMT_TERMINATOR 2249 }; 2250 2251 /* 4: NVDIMM Control Region Structure */ 2252 2253 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 2254 { 2255 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 2256 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 2257 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 2258 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 2259 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 2260 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 2261 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 2262 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 2263 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 2264 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 2265 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 2266 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 2267 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 2268 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 2269 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 2270 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 2271 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 2272 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 2273 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 2274 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 2275 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 2276 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 2277 ACPI_DMT_TERMINATOR 2278 }; 2279 2280 /* 5: NVDIMM Block Data Window Region Structure */ 2281 2282 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 2283 { 2284 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 2285 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 2286 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 2287 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 2288 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 2289 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 2290 ACPI_DMT_TERMINATOR 2291 }; 2292 2293 /* 6: Flush Hint Address Structure */ 2294 2295 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 2296 { 2297 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 2298 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 2299 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 2300 ACPI_DMT_TERMINATOR 2301 }; 2302 2303 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 2304 { 2305 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 2306 ACPI_DMT_TERMINATOR 2307 }; 2308 2309 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 2310 { 2311 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 2312 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 2313 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 2314 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 2315 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to MVDIMM", 0}, 2316 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 2317 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 2318 ACPI_DMT_TERMINATOR 2319 }; 2320 2321 2322 /******************************************************************************* 2323 * 2324 * PCCT - Platform Communications Channel Table (ACPI 5.0) 2325 * 2326 ******************************************************************************/ 2327 2328 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 2329 { 2330 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2331 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 2332 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 2333 ACPI_DMT_TERMINATOR 2334 }; 2335 2336 /* PCCT subtables */ 2337 2338 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 2339 { 2340 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 2341 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 2342 ACPI_DMT_TERMINATOR 2343 }; 2344 2345 /* 0: Generic Communications Subspace */ 2346 2347 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 2348 { 2349 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 2350 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 2351 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 2352 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 2353 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 2354 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 2355 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 2356 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 2357 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 2358 ACPI_DMT_TERMINATOR 2359 }; 2360 2361 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 2362 2363 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 2364 { 2365 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 2366 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 2367 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 2368 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 2369 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 2370 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 2371 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 2372 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 2373 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 2374 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 2375 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 2376 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 2377 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 2378 ACPI_DMT_TERMINATOR 2379 }; 2380 2381 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 2382 2383 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 2384 { 2385 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 2386 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 2387 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 2388 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 2389 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 2390 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 2391 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 2392 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 2393 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 2394 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 2395 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 2396 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 2397 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 2398 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 2399 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 2400 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 2401 ACPI_DMT_TERMINATOR 2402 }; 2403 2404 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 2405 2406 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 2407 { 2408 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 2409 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 2410 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 2411 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 2412 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 2413 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 2414 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 2415 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 2416 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 2417 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 2418 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 2419 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 2420 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 2421 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 2422 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 2423 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 2424 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 2425 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 2426 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 2427 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 2428 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 2429 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 2430 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 2431 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 2432 ACPI_DMT_TERMINATOR 2433 }; 2434 2435 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 2436 2437 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 2438 { 2439 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 2440 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 2441 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 2442 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 2443 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 2444 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 2445 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 2446 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 2447 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 2448 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 2449 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 2450 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 2451 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 2452 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 2453 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 2454 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 2455 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 2456 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 2457 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 2458 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 2459 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 2460 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 2461 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 2462 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 2463 ACPI_DMT_TERMINATOR 2464 }; 2465 2466 2467 /******************************************************************************* 2468 * 2469 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 2470 * 2471 ******************************************************************************/ 2472 2473 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 2474 { 2475 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 2476 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 2477 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 2478 ACPI_DMT_TERMINATOR 2479 }; 2480 2481 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 2482 { 2483 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 2484 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 2485 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 2486 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 2487 ACPI_DMT_TERMINATOR 2488 }; 2489 2490 2491 /******************************************************************************* 2492 * 2493 * PMTT - Platform Memory Topology Table 2494 * 2495 ******************************************************************************/ 2496 2497 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 2498 { 2499 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (Reserved), "Reserved", 0}, 2500 ACPI_DMT_TERMINATOR 2501 }; 2502 2503 /* Common Subtable header (one per Subtable) */ 2504 2505 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttHdr[] = 2506 { 2507 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, 2508 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, 2509 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, 2510 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2511 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, 2512 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, 2513 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, 2514 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, 2515 ACPI_DMT_TERMINATOR 2516 }; 2517 2518 /* PMTT Subtables */ 2519 2520 /* 0: Socket */ 2521 2522 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 2523 { 2524 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 2525 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 2526 ACPI_DMT_TERMINATOR 2527 }; 2528 2529 /* 1: Memory Controller */ 2530 2531 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 2532 { 2533 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (ReadLatency), "Read Latency", 0}, 2534 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (WriteLatency), "Write Latency", 0}, 2535 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (ReadBandwidth), "Read Bandwidth", 0}, 2536 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (WriteBandwidth), "Write Bandwidth", 0}, 2537 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (AccessWidth), "Access Width", 0}, 2538 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Alignment), "Alignment", 0}, 2539 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 2540 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (DomainCount), "Domain Count", 0}, 2541 ACPI_DMT_TERMINATOR 2542 }; 2543 2544 /* 1a: Proximity Domain */ 2545 2546 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1a[] = 2547 { 2548 {ACPI_DMT_UINT32, ACPI_PMTT1A_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2549 ACPI_DMT_TERMINATOR 2550 }; 2551 2552 /* 2: Physical Component */ 2553 2554 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 2555 { 2556 {ACPI_DMT_UINT16, ACPI_PMTT2_OFFSET (ComponentId), "Component ID", 0}, 2557 {ACPI_DMT_UINT16, ACPI_PMTT2_OFFSET (Reserved), "Reserved", 0}, 2558 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (MemorySize), "Memory Size", 0}, 2559 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 2560 ACPI_DMT_TERMINATOR 2561 }; 2562 2563 2564 /******************************************************************************* 2565 * 2566 * PPTT - Processor Properties Topology Table (ACPI 6.2) 2567 * 2568 ******************************************************************************/ 2569 2570 /* Main table consists of only the standard ACPI header - subtables follow */ 2571 2572 /* Common Subtable header (one per Subtable) */ 2573 2574 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 2575 { 2576 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 2577 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 2578 ACPI_DMT_TERMINATOR 2579 }; 2580 2581 /* 0: Processor hierarchy node */ 2582 2583 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 2584 { 2585 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 2586 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 2587 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 2588 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 2589 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 2590 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 2591 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 2592 ACPI_DMT_TERMINATOR 2593 }; 2594 2595 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 2596 { 2597 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 2598 ACPI_DMT_TERMINATOR 2599 }; 2600 2601 /* 1: Cache type */ 2602 2603 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 2604 { 2605 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 2606 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 2607 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 2608 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 2609 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 2610 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 2611 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 2612 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 2613 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 2614 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 2615 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 2616 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 2617 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 2618 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 2619 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 2620 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 2621 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 2622 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 2623 ACPI_DMT_TERMINATOR 2624 }; 2625 2626 /* 2: ID */ 2627 2628 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 2629 { 2630 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 2631 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "VENDOR_ID", 0}, 2632 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "LEVEL_1_ID", 0}, 2633 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "LEVEL_2_ID", 0}, 2634 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "MAJOR_REV", 0}, 2635 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "MINOR_REV", 0}, 2636 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "SPIN_REV", 0}, 2637 ACPI_DMT_TERMINATOR 2638 }; 2639 2640 2641 /******************************************************************************* 2642 * 2643 * RASF - RAS Feature table 2644 * 2645 ******************************************************************************/ 2646 2647 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 2648 { 2649 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 2650 ACPI_DMT_TERMINATOR 2651 }; 2652 2653 2654 /******************************************************************************* 2655 * 2656 * S3PT - S3 Performance Table 2657 * 2658 ******************************************************************************/ 2659 2660 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2661 { 2662 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2663 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2664 ACPI_DMT_TERMINATOR 2665 }; 2666 2667 /* S3PT subtable header */ 2668 2669 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2670 { 2671 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2672 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2673 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2674 ACPI_DMT_TERMINATOR 2675 }; 2676 2677 /* 0: Basic S3 Resume Performance Record */ 2678 2679 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2680 { 2681 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2682 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2683 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2684 ACPI_DMT_TERMINATOR 2685 }; 2686 2687 /* 1: Basic S3 Suspend Performance Record */ 2688 2689 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2690 { 2691 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2692 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2693 ACPI_DMT_TERMINATOR 2694 }; 2695 2696 2697 /******************************************************************************* 2698 * 2699 * SBST - Smart Battery Specification Table 2700 * 2701 ******************************************************************************/ 2702 2703 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2704 { 2705 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2706 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2707 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2708 ACPI_DMT_TERMINATOR 2709 }; 2710 2711 2712 /******************************************************************************* 2713 * 2714 * SDEI - Software Delegated Execption Interface Descriptor Table 2715 * 2716 ******************************************************************************/ 2717 2718 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2719 { 2720 ACPI_DMT_TERMINATOR 2721 }; 2722 2723 2724 /******************************************************************************* 2725 * 2726 * SDEV - Secure Devices Table (ACPI 6.2) 2727 * 2728 ******************************************************************************/ 2729 2730 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2731 { 2732 ACPI_DMT_TERMINATOR 2733 }; 2734 2735 /* Common Subtable header (one per Subtable) */ 2736 2737 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2738 { 2739 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2740 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2741 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2742 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", 0}, 2743 ACPI_DMT_TERMINATOR 2744 }; 2745 2746 /* SDEV Subtables */ 2747 2748 /* 0: Namespace Device Based Secure Device Structure */ 2749 2750 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2751 { 2752 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2753 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2754 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2755 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2756 ACPI_DMT_TERMINATOR 2757 }; 2758 2759 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2760 { 2761 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2762 ACPI_DMT_TERMINATOR 2763 }; 2764 2765 /* 1: PCIe Endpoint Device Based Device Structure */ 2766 2767 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2768 { 2769 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2770 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2771 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2772 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2773 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2774 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2775 ACPI_DMT_TERMINATOR 2776 }; 2777 2778 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2779 { 2780 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2781 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2782 ACPI_DMT_TERMINATOR 2783 }; 2784 2785 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2786 { 2787 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2788 ACPI_DMT_TERMINATOR 2789 }; 2790 2791 2792 /******************************************************************************* 2793 * 2794 * SLIC - Software Licensing Description Table. This table contains the standard 2795 * ACPI header followed by proprietary data structures 2796 * 2797 ******************************************************************************/ 2798 2799 /* Single subtable, a proprietary format, so treat it as a buffer */ 2800 2801 ACPI_DMTABLE_INFO AcpiDmTableInfoSlic[] = 2802 { 2803 {ACPI_DMT_RAW_BUFFER, 0, "Software Licensing Structure", 0}, 2804 ACPI_DMT_TERMINATOR 2805 }; 2806 2807 2808 /******************************************************************************* 2809 * 2810 * SLIT - System Locality Information Table 2811 * 2812 ******************************************************************************/ 2813 2814 ACPI_DMTABLE_INFO AcpiDmTableInfoSlit[] = 2815 { 2816 {ACPI_DMT_UINT64, ACPI_SLIT_OFFSET (LocalityCount), "Localities", 0}, 2817 ACPI_DMT_TERMINATOR 2818 }; 2819 2820 2821 /******************************************************************************* 2822 * 2823 * SPCR - Serial Port Console Redirection table 2824 * 2825 ******************************************************************************/ 2826 2827 ACPI_DMTABLE_INFO AcpiDmTableInfoSpcr[] = 2828 { 2829 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (InterfaceType), "Interface Type", 0}, 2830 {ACPI_DMT_UINT24, ACPI_SPCR_OFFSET (Reserved[0]), "Reserved", 0}, 2831 {ACPI_DMT_GAS, ACPI_SPCR_OFFSET (SerialPort), "Serial Port Register", 0}, 2832 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (InterruptType), "Interrupt Type", 0}, 2833 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PcInterrupt), "PCAT-compatible IRQ", 0}, 2834 {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (Interrupt), "Interrupt", 0}, 2835 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (BaudRate), "Baud Rate", 0}, 2836 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (Parity), "Parity", 0}, 2837 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (StopBits), "Stop Bits", 0}, 2838 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (FlowControl), "Flow Control", 0}, 2839 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (TerminalType), "Terminal Type", 0}, 2840 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (Reserved2), "Reserved", 0}, 2841 {ACPI_DMT_UINT16, ACPI_SPCR_OFFSET (PciDeviceId), "PCI Device ID", 0}, 2842 {ACPI_DMT_UINT16, ACPI_SPCR_OFFSET (PciVendorId), "PCI Vendor ID", 0}, 2843 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciBus), "PCI Bus", 0}, 2844 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciDevice), "PCI Device", 0}, 2845 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciFunction), "PCI Function", 0}, 2846 {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (PciFlags), "PCI Flags", 0}, 2847 {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciSegment), "PCI Segment", 0}, 2848 {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (Reserved2), "Reserved", 0}, 2849 ACPI_DMT_TERMINATOR 2850 }; 2851 2852 2853 /******************************************************************************* 2854 * 2855 * SPMI - Server Platform Management Interface table 2856 * 2857 ******************************************************************************/ 2858 2859 ACPI_DMTABLE_INFO AcpiDmTableInfoSpmi[] = 2860 { 2861 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (InterfaceType), "Interface Type", 0}, 2862 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved), "Reserved", DT_NON_ZERO}, /* Value must be 1 */ 2863 {ACPI_DMT_UINT16, ACPI_SPMI_OFFSET (SpecRevision), "IPMI Spec Version", 0}, 2864 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (InterruptType), "Interrupt Type", 0}, 2865 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (GpeNumber), "GPE Number", 0}, 2866 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved1), "Reserved", 0}, 2867 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciDeviceFlag), "PCI Device Flag", 0}, 2868 {ACPI_DMT_UINT32, ACPI_SPMI_OFFSET (Interrupt), "Interrupt", 0}, 2869 {ACPI_DMT_GAS, ACPI_SPMI_OFFSET (IpmiRegister), "IPMI Register", 0}, 2870 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciSegment), "PCI Segment", 0}, 2871 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciBus), "PCI Bus", 0}, 2872 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciDevice), "PCI Device", 0}, 2873 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciFunction), "PCI Function", 0}, 2874 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved2), "Reserved", 0}, 2875 ACPI_DMT_TERMINATOR 2876 }; 2877 2878 2879 /******************************************************************************* 2880 * 2881 * SRAT - System Resource Affinity Table and Subtables 2882 * 2883 ******************************************************************************/ 2884 2885 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat[] = 2886 { 2887 {ACPI_DMT_UINT32, ACPI_SRAT_OFFSET (TableRevision), "Table Revision", 0}, 2888 {ACPI_DMT_UINT64, ACPI_SRAT_OFFSET (Reserved), "Reserved", 0}, 2889 ACPI_DMT_TERMINATOR 2890 }; 2891 2892 /* Common Subtable header (one per Subtable) */ 2893 2894 ACPI_DMTABLE_INFO AcpiDmTableInfoSratHdr[] = 2895 { 2896 {ACPI_DMT_SRAT, ACPI_SRATH_OFFSET (Type), "Subtable Type", 0}, 2897 {ACPI_DMT_UINT8, ACPI_SRATH_OFFSET (Length), "Length", DT_LENGTH}, 2898 ACPI_DMT_TERMINATOR 2899 }; 2900 2901 /* SRAT Subtables */ 2902 2903 /* 0: Processor Local APIC/SAPIC Affinity */ 2904 2905 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat0[] = 2906 { 2907 {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (ProximityDomainLo), "Proximity Domain Low(8)", 0}, 2908 {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (ApicId), "Apic ID", 0}, 2909 {ACPI_DMT_UINT32, ACPI_SRAT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2910 {ACPI_DMT_FLAG0, ACPI_SRAT0_FLAG_OFFSET (Flags,0), "Enabled", 0}, 2911 {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (LocalSapicEid), "Local Sapic EID", 0}, 2912 {ACPI_DMT_UINT24, ACPI_SRAT0_OFFSET (ProximityDomainHi[0]), "Proximity Domain High(24)", 0}, 2913 {ACPI_DMT_UINT32, ACPI_SRAT0_OFFSET (ClockDomain), "Clock Domain", 0}, 2914 ACPI_DMT_TERMINATOR 2915 }; 2916 2917 /* 1: Memory Affinity */ 2918 2919 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat1[] = 2920 { 2921 {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2922 {ACPI_DMT_UINT16, ACPI_SRAT1_OFFSET (Reserved), "Reserved1", 0}, 2923 {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (BaseAddress), "Base Address", 0}, 2924 {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (Length), "Address Length", 0}, 2925 {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (Reserved1), "Reserved2", 0}, 2926 {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2927 {ACPI_DMT_FLAG0, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Enabled", 0}, 2928 {ACPI_DMT_FLAG1, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Hot Pluggable", 0}, 2929 {ACPI_DMT_FLAG2, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Non-Volatile", 0}, 2930 {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (Reserved2), "Reserved3", 0}, 2931 ACPI_DMT_TERMINATOR 2932 }; 2933 2934 /* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */ 2935 2936 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat2[] = 2937 { 2938 {ACPI_DMT_UINT16, ACPI_SRAT2_OFFSET (Reserved), "Reserved1", 0}, 2939 {ACPI_DMT_UINT32, ACPI_SRAT2_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2940 {ACPI_DMT_UINT32, ACPI_SRAT2_OFFSET (ApicId), "Apic ID", 0}, 2941 {ACPI_DMT_UINT32, ACPI_SRAT2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2942 {ACPI_DMT_FLAG0, ACPI_SRAT2_FLAG_OFFSET (Flags,0), "Enabled", 0}, 2943 {ACPI_DMT_UINT32, ACPI_SRAT2_OFFSET (ClockDomain), "Clock Domain", 0}, 2944 {ACPI_DMT_UINT32, ACPI_SRAT2_OFFSET (Reserved2), "Reserved2", 0}, 2945 ACPI_DMT_TERMINATOR 2946 }; 2947 2948 /* 3: GICC Affinity (ACPI 5.1) */ 2949 2950 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat3[] = 2951 { 2952 {ACPI_DMT_UINT32, ACPI_SRAT3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2953 {ACPI_DMT_UINT32, ACPI_SRAT3_OFFSET (AcpiProcessorUid), "Acpi Processor UID", 0}, 2954 {ACPI_DMT_UINT32, ACPI_SRAT3_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 2955 {ACPI_DMT_FLAG0, ACPI_SRAT3_FLAG_OFFSET (Flags,0), "Enabled", 0}, 2956 {ACPI_DMT_UINT32, ACPI_SRAT3_OFFSET (ClockDomain), "Clock Domain", 0}, 2957 ACPI_DMT_TERMINATOR 2958 }; 2959 2960 /* 4: GCC ITS Affinity (ACPI 6.2) */ 2961 2962 ACPI_DMTABLE_INFO AcpiDmTableInfoSrat4[] = 2963 { 2964 {ACPI_DMT_UINT32, ACPI_SRAT4_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2965 {ACPI_DMT_UINT16, ACPI_SRAT4_OFFSET (Reserved), "Reserved", 0}, 2966 {ACPI_DMT_UINT32, ACPI_SRAT4_OFFSET (ItsId), "ITS ID", 0}, 2967 ACPI_DMT_TERMINATOR 2968 }; 2969 2970 2971 /******************************************************************************* 2972 * 2973 * STAO - Status Override Table (_STA override) - ACPI 6.0 2974 * 2975 ******************************************************************************/ 2976 2977 ACPI_DMTABLE_INFO AcpiDmTableInfoStao[] = 2978 { 2979 {ACPI_DMT_UINT8, ACPI_STAO_OFFSET (IgnoreUart), "Ignore UART", 0}, 2980 ACPI_DMT_TERMINATOR 2981 }; 2982 2983 ACPI_DMTABLE_INFO AcpiDmTableInfoStaoStr[] = 2984 { 2985 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2986 ACPI_DMT_TERMINATOR 2987 }; 2988 2989 2990 /******************************************************************************* 2991 * 2992 * TCPA - Trusted Computing Platform Alliance table (Client) 2993 * 2994 * NOTE: There are two versions of the table with the same signature -- 2995 * the client version and the server version. The common PlatformClass 2996 * field is used to differentiate the two types of tables. 2997 * 2998 ******************************************************************************/ 2999 3000 ACPI_DMTABLE_INFO AcpiDmTableInfoTcpaHdr[] = 3001 { 3002 {ACPI_DMT_UINT16, ACPI_TCPA_OFFSET (PlatformClass), "Platform Class", 0}, 3003 ACPI_DMT_TERMINATOR 3004 }; 3005 3006 ACPI_DMTABLE_INFO AcpiDmTableInfoTcpaClient[] = 3007 { 3008 {ACPI_DMT_UINT32, ACPI_TCPA_CLIENT_OFFSET (MinimumLogLength), "Min Event Log Length", 0}, 3009 {ACPI_DMT_UINT64, ACPI_TCPA_CLIENT_OFFSET (LogAddress), "Event Log Address", 0}, 3010 ACPI_DMT_TERMINATOR 3011 }; 3012 3013 ACPI_DMTABLE_INFO AcpiDmTableInfoTcpaServer[] = 3014 { 3015 {ACPI_DMT_UINT16, ACPI_TCPA_SERVER_OFFSET (Reserved), "Reserved", 0}, 3016 {ACPI_DMT_UINT64, ACPI_TCPA_SERVER_OFFSET (MinimumLogLength), "Min Event Log Length", 0}, 3017 {ACPI_DMT_UINT64, ACPI_TCPA_SERVER_OFFSET (LogAddress), "Event Log Address", 0}, 3018 {ACPI_DMT_UINT16, ACPI_TCPA_SERVER_OFFSET (SpecRevision), "Specification Revision", 0}, 3019 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (DeviceFlags), "Device Flags (decoded below)", DT_FLAG}, 3020 {ACPI_DMT_FLAG0, ACPI_TCPA_SERVER_OFFSET (DeviceFlags), "Pci Device", 0}, 3021 {ACPI_DMT_FLAG1, ACPI_TCPA_SERVER_OFFSET (DeviceFlags), "Bus is Pnp", 0}, 3022 {ACPI_DMT_FLAG2, ACPI_TCPA_SERVER_OFFSET (DeviceFlags), "Address Valid", 0}, 3023 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (InterruptFlags), "Interrupt Flags (decoded below)", DT_FLAG}, 3024 {ACPI_DMT_FLAG0, ACPI_TCPA_SERVER_OFFSET (InterruptFlags), "Mode", 0}, 3025 {ACPI_DMT_FLAG1, ACPI_TCPA_SERVER_OFFSET (InterruptFlags), "Polarity", 0}, 3026 {ACPI_DMT_FLAG2, ACPI_TCPA_SERVER_OFFSET (InterruptFlags), "GPE SCI Triggered", 0}, 3027 {ACPI_DMT_FLAG3, ACPI_TCPA_SERVER_OFFSET (InterruptFlags), "Global System Interrupt", 0}, 3028 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (GpeNumber), "Gpe Number", 0}, 3029 {ACPI_DMT_UINT24, ACPI_TCPA_SERVER_OFFSET (Reserved2[0]), "Reserved", 0}, 3030 {ACPI_DMT_UINT32, ACPI_TCPA_SERVER_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 3031 {ACPI_DMT_GAS, ACPI_TCPA_SERVER_OFFSET (Address), "Address", 0}, 3032 {ACPI_DMT_UINT32, ACPI_TCPA_SERVER_OFFSET (Reserved3), "Reserved", 0}, 3033 {ACPI_DMT_GAS, ACPI_TCPA_SERVER_OFFSET (ConfigAddress), "Configuration Address", 0}, 3034 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (Group), "Pci Group", 0}, 3035 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (Bus), "Pci Bus", 0}, 3036 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (Device), "Pci Device", 0}, 3037 {ACPI_DMT_UINT8, ACPI_TCPA_SERVER_OFFSET (Function), "Pci Function", 0}, 3038 ACPI_DMT_TERMINATOR 3039 }; 3040 3041 3042 /******************************************************************************* 3043 * 3044 * TPM2 - Trusted Platform Module (TPM) 2.0 Hardware Interface Table 3045 * 3046 ******************************************************************************/ 3047 3048 ACPI_DMTABLE_INFO AcpiDmTableInfoTpm2[] = 3049 { 3050 {ACPI_DMT_UINT16, ACPI_TPM2_OFFSET (PlatformClass), "Platform Class", 0}, 3051 {ACPI_DMT_UINT16, ACPI_TPM2_OFFSET (Reserved), "Reserved", 0}, 3052 {ACPI_DMT_UINT64, ACPI_TPM2_OFFSET (ControlAddress), "Control Address", 0}, 3053 {ACPI_DMT_TPM2, ACPI_TPM2_OFFSET (StartMethod), "Start Method", 0}, 3054 ACPI_DMT_TERMINATOR 3055 }; 3056 3057 /* Optional trailer. LogLength and LogAddress are additionally optional */ 3058 3059 ACPI_DMTABLE_INFO AcpiDmTableInfoTpm2a[] = 3060 { 3061 {ACPI_DMT_BUF12, ACPI_TPM2A_OFFSET (MethodParameters), "Method Parameters", DT_OPTIONAL}, 3062 {ACPI_DMT_UINT32, ACPI_TPM2A_OFFSET (MinimumLogLength), "Minimum Log Length", DT_OPTIONAL}, 3063 {ACPI_DMT_UINT64, ACPI_TPM2A_OFFSET (LogAddress), "Log Address", DT_OPTIONAL}, 3064 ACPI_DMT_TERMINATOR 3065 }; 3066 3067 /* 11: Start Method for ARM SMC */ 3068 3069 ACPI_DMTABLE_INFO AcpiDmTableInfoTpm211[] = 3070 { 3071 {ACPI_DMT_UINT32, ACPI_TPM211_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 3072 {ACPI_DMT_UINT8, ACPI_TPM211_OFFSET (InterruptFlags), "Interrupt Flags", 0}, 3073 {ACPI_DMT_UINT8, ACPI_TPM211_OFFSET (OperationFlags), "Operation Flags", 0}, 3074 {ACPI_DMT_UINT16, ACPI_TPM211_OFFSET (Reserved), "Reserved", 0}, 3075 {ACPI_DMT_UINT32, ACPI_TPM211_OFFSET (FunctionId), "Function ID", 0}, 3076 ACPI_DMT_TERMINATOR 3077 }; 3078 3079 3080 /******************************************************************************* 3081 * 3082 * UEFI - UEFI Boot optimization Table 3083 * 3084 ******************************************************************************/ 3085 3086 ACPI_DMTABLE_INFO AcpiDmTableInfoUefi[] = 3087 { 3088 {ACPI_DMT_UUID, ACPI_UEFI_OFFSET (Identifier[0]), "UUID Identifier", 0}, 3089 {ACPI_DMT_UINT16, ACPI_UEFI_OFFSET (DataOffset), "Data Offset", 0}, 3090 ACPI_DMT_TERMINATOR 3091 }; 3092 3093 3094 /******************************************************************************* 3095 * 3096 * VRTC - Virtual Real Time Clock Table 3097 * 3098 ******************************************************************************/ 3099 3100 ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc[] = 3101 { 3102 ACPI_DMT_TERMINATOR 3103 }; 3104 3105 /* VRTC Subtables - VRTC Entry */ 3106 3107 ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc0[] = 3108 { 3109 {ACPI_DMT_GAS, ACPI_VRTC0_OFFSET (PhysicalAddress), "PhysicalAddress", 0}, 3110 {ACPI_DMT_UINT32, ACPI_VRTC0_OFFSET (Irq), "IRQ", 0}, 3111 ACPI_DMT_TERMINATOR 3112 }; 3113 3114 3115 /******************************************************************************* 3116 * 3117 * WAET - Windows ACPI Emulated devices Table 3118 * 3119 ******************************************************************************/ 3120 3121 ACPI_DMTABLE_INFO AcpiDmTableInfoWaet[] = 3122 { 3123 {ACPI_DMT_UINT32, ACPI_WAET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 3124 {ACPI_DMT_FLAG0, ACPI_WAET_OFFSET (Flags), "RTC needs no INT ack", 0}, 3125 {ACPI_DMT_FLAG1, ACPI_WAET_OFFSET (Flags), "PM timer, one read only", 0}, 3126 ACPI_DMT_TERMINATOR 3127 }; 3128 3129 3130 /******************************************************************************* 3131 * 3132 * WDAT - Watchdog Action Table 3133 * 3134 ******************************************************************************/ 3135 3136 ACPI_DMTABLE_INFO AcpiDmTableInfoWdat[] = 3137 { 3138 {ACPI_DMT_UINT32, ACPI_WDAT_OFFSET (HeaderLength), "Header Length", DT_LENGTH}, 3139 {ACPI_DMT_UINT16, ACPI_WDAT_OFFSET (PciSegment), "PCI Segment", 0}, 3140 {ACPI_DMT_UINT8, ACPI_WDAT_OFFSET (PciBus), "PCI Bus", 0}, 3141 {ACPI_DMT_UINT8, ACPI_WDAT_OFFSET (PciDevice), "PCI Device", 0}, 3142 {ACPI_DMT_UINT8, ACPI_WDAT_OFFSET (PciFunction), "PCI Function", 0}, 3143 {ACPI_DMT_UINT24, ACPI_WDAT_OFFSET (Reserved[0]), "Reserved", 0}, 3144 {ACPI_DMT_UINT32, ACPI_WDAT_OFFSET (TimerPeriod), "Timer Period", 0}, 3145 {ACPI_DMT_UINT32, ACPI_WDAT_OFFSET (MaxCount), "Max Count", 0}, 3146 {ACPI_DMT_UINT32, ACPI_WDAT_OFFSET (MinCount), "Min Count", 0}, 3147 {ACPI_DMT_UINT8, ACPI_WDAT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 3148 {ACPI_DMT_FLAG0, ACPI_WDAT_OFFSET (Flags), "Enabled", 0}, 3149 {ACPI_DMT_FLAG7, ACPI_WDAT_OFFSET (Flags), "Stopped When Asleep", 0}, 3150 {ACPI_DMT_UINT24, ACPI_WDAT_OFFSET (Reserved2[0]), "Reserved", 0}, 3151 {ACPI_DMT_UINT32, ACPI_WDAT_OFFSET (Entries), "Watchdog Entry Count", 0}, 3152 ACPI_DMT_TERMINATOR 3153 }; 3154 3155 /* WDAT Subtables - Watchdog Instruction Entries */ 3156 3157 ACPI_DMTABLE_INFO AcpiDmTableInfoWdat0[] = 3158 { 3159 {ACPI_DMT_UINT8, ACPI_WDAT0_OFFSET (Action), "Watchdog Action", 0}, 3160 {ACPI_DMT_UINT8, ACPI_WDAT0_OFFSET (Instruction), "Instruction", 0}, 3161 {ACPI_DMT_UINT16, ACPI_WDAT0_OFFSET (Reserved), "Reserved", 0}, 3162 {ACPI_DMT_GAS, ACPI_WDAT0_OFFSET (RegisterRegion), "Register Region", 0}, 3163 {ACPI_DMT_UINT32, ACPI_WDAT0_OFFSET (Value), "Value", 0}, 3164 {ACPI_DMT_UINT32, ACPI_WDAT0_OFFSET (Mask), "Register Mask", 0}, 3165 ACPI_DMT_TERMINATOR 3166 }; 3167 3168 3169 /******************************************************************************* 3170 * 3171 * WDDT - Watchdog Description Table 3172 * 3173 ******************************************************************************/ 3174 3175 ACPI_DMTABLE_INFO AcpiDmTableInfoWddt[] = 3176 { 3177 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (SpecVersion), "Specification Version", 0}, 3178 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (TableVersion), "Table Version", 0}, 3179 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (PciVendorId), "PCI Vendor ID", 0}, 3180 {ACPI_DMT_GAS, ACPI_WDDT_OFFSET (Address), "Timer Register", 0}, 3181 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (MaxCount), "Max Count", 0}, 3182 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (MinCount), "Min Count", 0}, 3183 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (Period), "Period", 0}, 3184 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (Status), "Status (decoded below)", 0}, 3185 3186 /* Status Flags byte 0 */ 3187 3188 {ACPI_DMT_FLAG0, ACPI_WDDT_FLAG_OFFSET (Status,0), "Available", 0}, 3189 {ACPI_DMT_FLAG1, ACPI_WDDT_FLAG_OFFSET (Status,0), "Active", 0}, 3190 {ACPI_DMT_FLAG2, ACPI_WDDT_FLAG_OFFSET (Status,0), "OS Owns", 0}, 3191 3192 /* Status Flags byte 1 */ 3193 3194 {ACPI_DMT_FLAG3, ACPI_WDDT_FLAG_OFFSET (Status,1), "User Reset", 0}, 3195 {ACPI_DMT_FLAG4, ACPI_WDDT_FLAG_OFFSET (Status,1), "Timeout Reset", 0}, 3196 {ACPI_DMT_FLAG5, ACPI_WDDT_FLAG_OFFSET (Status,1), "Power Fail Reset", 0}, 3197 {ACPI_DMT_FLAG6, ACPI_WDDT_FLAG_OFFSET (Status,1), "Unknown Reset", 0}, 3198 3199 {ACPI_DMT_UINT16, ACPI_WDDT_OFFSET (Capability), "Capability (decoded below)", 0}, 3200 3201 /* Capability Flags byte 0 */ 3202 3203 {ACPI_DMT_FLAG0, ACPI_WDDT_FLAG_OFFSET (Capability,0), "Auto Reset", 0}, 3204 {ACPI_DMT_FLAG1, ACPI_WDDT_FLAG_OFFSET (Capability,0), "Timeout Alert", 0}, 3205 ACPI_DMT_TERMINATOR 3206 }; 3207 3208 3209 /******************************************************************************* 3210 * 3211 * WDRT - Watchdog Resource Table 3212 * 3213 ******************************************************************************/ 3214 3215 ACPI_DMTABLE_INFO AcpiDmTableInfoWdrt[] = 3216 { 3217 {ACPI_DMT_GAS, ACPI_WDRT_OFFSET (ControlRegister), "Control Register", 0}, 3218 {ACPI_DMT_GAS, ACPI_WDRT_OFFSET (CountRegister), "Count Register", 0}, 3219 {ACPI_DMT_UINT16, ACPI_WDRT_OFFSET (PciDeviceId), "PCI Device ID", 0}, 3220 {ACPI_DMT_UINT16, ACPI_WDRT_OFFSET (PciVendorId), "PCI Vendor ID", 0}, 3221 {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciBus), "PCI Bus", 0}, 3222 {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciDevice), "PCI Device", 0}, 3223 {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciFunction), "PCI Function", 0}, 3224 {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciSegment), "PCI Segment", 0}, 3225 {ACPI_DMT_UINT16, ACPI_WDRT_OFFSET (MaxCount), "Max Count", 0}, 3226 {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (Units), "Counter Units", 0}, 3227 ACPI_DMT_TERMINATOR 3228 }; 3229 3230 3231 /******************************************************************************* 3232 * 3233 * WPBT - Windows Platform Environment Table (ACPI 6.0) 3234 * Version 1 3235 * 3236 * Conforms to "Windows Platform Binary Table (WPBT)" 29 November 2011 3237 * 3238 ******************************************************************************/ 3239 3240 ACPI_DMTABLE_INFO AcpiDmTableInfoWpbt[] = 3241 { 3242 {ACPI_DMT_UINT32, ACPI_WPBT_OFFSET (HandoffSize), "Handoff Size", 0}, 3243 {ACPI_DMT_UINT64, ACPI_WPBT_OFFSET (HandoffAddress), "Handoff Address", 0}, 3244 {ACPI_DMT_UINT8, ACPI_WPBT_OFFSET (Layout), "Layout", 0}, 3245 {ACPI_DMT_UINT8, ACPI_WPBT_OFFSET (Type), "Type", 0}, 3246 {ACPI_DMT_UINT16, ACPI_WPBT_OFFSET (ArgumentsLength), "Arguments Length", 0}, 3247 ACPI_DMT_TERMINATOR 3248 }; 3249 3250 ACPI_DMTABLE_INFO AcpiDmTableInfoWpbt0[] = 3251 { 3252 {ACPI_DMT_UNICODE, sizeof (ACPI_TABLE_WPBT), "Command-line Arguments", 0}, 3253 ACPI_DMT_TERMINATOR 3254 }; 3255 3256 3257 /******************************************************************************* 3258 * 3259 * WSMT - Windows SMM Security Migrations Table 3260 * 3261 ******************************************************************************/ 3262 3263 ACPI_DMTABLE_INFO AcpiDmTableInfoWsmt[] = 3264 { 3265 {ACPI_DMT_UINT32, ACPI_WSMT_OFFSET (ProtectionFlags), "Protection Flags", 0}, 3266 {ACPI_DMT_FLAG0, ACPI_WSMT_FLAG_OFFSET (ProtectionFlags,0), "FIXED_COMM_BUFFERS", 0}, 3267 {ACPI_DMT_FLAG1, ACPI_WSMT_FLAG_OFFSET (ProtectionFlags,0), "COMM_BUFFER_NESTED_PTR_PROTECTION", 0}, 3268 {ACPI_DMT_FLAG2, ACPI_WSMT_FLAG_OFFSET (ProtectionFlags,0), "SYSTEM_RESOURCE_PROTECTION", 0}, 3269 ACPI_DMT_TERMINATOR 3270 }; 3271 3272 3273 /******************************************************************************* 3274 * 3275 * XENV - Xen Environment table (ACPI 6.0) 3276 * 3277 ******************************************************************************/ 3278 3279 ACPI_DMTABLE_INFO AcpiDmTableInfoXenv[] = 3280 { 3281 {ACPI_DMT_UINT64, ACPI_XENV_OFFSET (GrantTableAddress), "Grant Table Address", 0}, 3282 {ACPI_DMT_UINT64, ACPI_XENV_OFFSET (GrantTableSize), "Grant Table Size", 0}, 3283 {ACPI_DMT_UINT32, ACPI_XENV_OFFSET (EventInterrupt), "Event Interrupt", 0}, 3284 {ACPI_DMT_UINT8, ACPI_XENV_OFFSET (EventFlags), "Event Flags", 0}, 3285 ACPI_DMT_TERMINATOR 3286 }; 3287 3288 3289 /*! [Begin] no source code translation */ 3290 3291 /* 3292 * Generic types (used in UEFI and custom tables) 3293 * 3294 * Examples: 3295 * 3296 * Buffer : cc 04 ff bb 3297 * UINT8 : 11 3298 * UINT16 : 1122 3299 * UINT24 : 112233 3300 * UINT32 : 11223344 3301 * UINT56 : 11223344556677 3302 * UINT64 : 1122334455667788 3303 * 3304 * String : "This is string" 3305 * Unicode : "This string encoded to Unicode" 3306 * 3307 * GUID : 11223344-5566-7788-99aa-bbccddeeff00 3308 * DevicePath : "\PciRoot(0)\Pci(0x1f,1)\Usb(0,0)" 3309 */ 3310 3311 #define ACPI_DM_GENERIC_ENTRY(FieldType, FieldName) \ 3312 {{FieldType, 0, FieldName, 0}, ACPI_DMT_TERMINATOR} 3313 3314 ACPI_DMTABLE_INFO AcpiDmTableInfoGeneric[][2] = 3315 { 3316 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT8, "UINT8"), 3317 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT16, "UINT16"), 3318 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT24, "UINT24"), 3319 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT32, "UINT32"), 3320 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT40, "UINT40"), 3321 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT48, "UINT48"), 3322 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT56, "UINT56"), 3323 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UINT64, "UINT64"), 3324 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_STRING, "String"), 3325 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UNICODE, "Unicode"), 3326 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_BUFFER, "Buffer"), 3327 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_UUID, "GUID"), 3328 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_STRING, "DevicePath"), 3329 ACPI_DM_GENERIC_ENTRY (ACPI_DMT_LABEL, "Label"), 3330 {ACPI_DMT_TERMINATOR} 3331 }; 3332 /*! [End] no source code translation !*/ 3333