1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_eth_mac_regs.h 40 * 41 * @brief Ethernet MAC registers 42 * 43 */ 44 45 #ifndef __AL_HAL_ETH_MAC_REGS_H__ 46 #define __AL_HAL_ETH_MAC_REGS_H__ 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 struct al_eth_mac_1g { 58 /* [0x0] */ 59 uint32_t rev; 60 uint32_t scratch; 61 uint32_t cmd_cfg; 62 uint32_t mac_0; 63 /* [0x10] */ 64 uint32_t mac_1; 65 uint32_t frm_len; 66 uint32_t pause_quant; 67 uint32_t rx_section_empty; 68 /* [0x20] */ 69 uint32_t rx_section_full; 70 uint32_t tx_section_empty; 71 uint32_t tx_section_full; 72 uint32_t rx_almost_empty; 73 /* [0x30] */ 74 uint32_t rx_almost_full; 75 uint32_t tx_almost_empty; 76 uint32_t tx_almost_full; 77 uint32_t mdio_addr0; 78 /* [0x40] */ 79 uint32_t mdio_addr1; 80 uint32_t Reserved[5]; 81 /* [0x58] */ 82 uint32_t reg_stat; 83 uint32_t tx_ipg_len; 84 /* [0x60] */ 85 uint32_t Reserved1[104]; 86 /* [0x200] */ 87 uint32_t phy_regs_base; 88 uint32_t Reserved2[127]; 89 }; 90 91 struct al_eth_mac_10g { 92 /* [0x0] */ 93 uint32_t rev; 94 uint32_t scratch; 95 uint32_t cmd_cfg; 96 uint32_t mac_0; 97 /* [0x10] */ 98 uint32_t mac_1; 99 uint32_t frm_len; 100 uint32_t Reserved; 101 uint32_t rx_fifo_sections; 102 /* [0x20] */ 103 uint32_t tx_fifo_sections; 104 uint32_t rx_fifo_almost_f_e; 105 uint32_t tx_fifo_almost_f_e; 106 uint32_t hashtable_load; 107 /* [0x30] */ 108 uint32_t mdio_cfg_status; 109 uint16_t mdio_cmd; 110 uint16_t reserved1; 111 uint16_t mdio_data; 112 uint16_t reserved2; 113 uint16_t mdio_regaddr; 114 uint16_t reserved3; 115 /* [0x40] */ 116 uint32_t status; 117 uint32_t tx_ipg_len; 118 uint32_t Reserved1[3]; 119 /* [0x54] */ 120 uint32_t cl01_pause_quanta; 121 uint32_t cl23_pause_quanta; 122 uint32_t cl45_pause_quanta; 123 /* [0x60] */ 124 uint32_t cl67_pause_quanta; 125 uint32_t cl01_quanta_thresh; 126 uint32_t cl23_quanta_thresh; 127 uint32_t cl45_quanta_thresh; 128 /* [0x70] */ 129 uint32_t cl67_quanta_thresh; 130 uint32_t rx_pause_status; 131 uint32_t Reserved2; 132 uint32_t ts_timestamp; 133 /* [0x80] */ 134 135 uint32_t Reserved3[160]; 136 137 /* [0x300] */ 138 uint32_t control; 139 uint32_t status_reg; 140 uint32_t phy_id[2]; 141 /* [0x310] */ 142 uint32_t dev_ability; 143 uint32_t partner_ability; 144 uint32_t an_expansion; 145 uint32_t device_np; 146 /* [0x320] */ 147 uint32_t partner_np; 148 uint32_t Reserved4[9]; 149 150 /* [0x348] */ 151 uint32_t link_timer_lo; 152 uint32_t link_timer_hi; 153 /* [0x350] */ 154 uint32_t if_mode; 155 156 uint32_t Reserved5[43]; 157 }; 158 159 struct al_eth_mac_gen { 160 /* [0x0] Ethernet Controller Version */ 161 uint32_t version; 162 uint32_t rsrvd_0[2]; 163 /* [0xc] MAC selection configuration */ 164 uint32_t cfg; 165 /* [0x10] 10/100/1000 MAC external configuration */ 166 uint32_t mac_1g_cfg; 167 /* [0x14] 10/100/1000 MAC status */ 168 uint32_t mac_1g_stat; 169 /* [0x18] RGMII external configuration */ 170 uint32_t rgmii_cfg; 171 /* [0x1c] RGMII status */ 172 uint32_t rgmii_stat; 173 /* [0x20] 1/2.5/10G MAC external configuration */ 174 uint32_t mac_10g_cfg; 175 /* [0x24] 1/2.5/10G MAC status */ 176 uint32_t mac_10g_stat; 177 /* [0x28] XAUI PCS configuration */ 178 uint32_t xaui_cfg; 179 /* [0x2c] XAUI PCS status */ 180 uint32_t xaui_stat; 181 /* [0x30] RXAUI PCS configuration */ 182 uint32_t rxaui_cfg; 183 /* [0x34] RXAUI PCS status */ 184 uint32_t rxaui_stat; 185 /* [0x38] Signal detect configuration */ 186 uint32_t sd_cfg; 187 /* [0x3c] MDIO control register for MDIO interface 1 */ 188 uint32_t mdio_ctrl_1; 189 /* [0x40] MDIO information register for MDIO interface 1 */ 190 uint32_t mdio_1; 191 /* [0x44] MDIO control register for MDIO interface 2 */ 192 uint32_t mdio_ctrl_2; 193 /* [0x48] MDIO information register for MDIO interface 2 */ 194 uint32_t mdio_2; 195 /* [0x4c] XGMII 32 to 64 data FIFO control */ 196 uint32_t xgmii_dfifo_32_64; 197 /* [0x50] Reserved 1 out */ 198 uint32_t mac_res_1_out; 199 /* [0x54] XGMII 64 to 32 data FIFO control */ 200 uint32_t xgmii_dfifo_64_32; 201 /* [0x58] Reserved 1 in */ 202 uint32_t mac_res_1_in; 203 /* [0x5c] SerDes TX FIFO control */ 204 uint32_t sd_fifo_ctrl; 205 /* [0x60] SerDes TX FIFO status */ 206 uint32_t sd_fifo_stat; 207 /* [0x64] SerDes in/out selection */ 208 uint32_t mux_sel; 209 /* [0x68] Clock configuration */ 210 uint32_t clk_cfg; 211 uint32_t rsrvd_1; 212 /* [0x70] LOS and SD selection */ 213 uint32_t los_sel; 214 /* [0x74] RGMII selection configuration */ 215 uint32_t rgmii_sel; 216 /* [0x78] Ethernet LED configuration */ 217 uint32_t led_cfg; 218 uint32_t rsrvd[33]; 219 }; 220 struct al_eth_mac_kr { 221 /* [0x0] PCS register file address */ 222 uint32_t pcs_addr; 223 /* [0x4] PCS register file data */ 224 uint32_t pcs_data; 225 /* [0x8] AN register file address */ 226 uint32_t an_addr; 227 /* [0xc] AN register file data */ 228 uint32_t an_data; 229 /* [0x10] PMA register file address */ 230 uint32_t pma_addr; 231 /* [0x14] PMA register file data */ 232 uint32_t pma_data; 233 /* [0x18] MTIP register file address */ 234 uint32_t mtip_addr; 235 /* [0x1c] MTIP register file data */ 236 uint32_t mtip_data; 237 /* [0x20] KR PCS config */ 238 uint32_t pcs_cfg; 239 /* [0x24] KR PCS status */ 240 uint32_t pcs_stat; 241 uint32_t rsrvd[54]; 242 }; 243 struct al_eth_mac_sgmii { 244 /* [0x0] PCS register file address */ 245 uint32_t reg_addr; 246 /* [0x4] PCS register file data */ 247 uint32_t reg_data; 248 /* [0x8] PCS clock divider configuration */ 249 uint32_t clk_div; 250 /* [0xc] PCS Status */ 251 uint32_t link_stat; 252 uint32_t rsrvd[60]; 253 }; 254 struct al_eth_mac_stat { 255 /* [0x0] Receive rate matching error */ 256 uint32_t match_fault; 257 /* [0x4] EEE, number of times the MAC went into low power mode */ 258 uint32_t eee_in; 259 /* [0x8] EEE, number of times the MAC went out of low power mode */ 260 uint32_t eee_out; 261 /* 262 * [0xc] 40G PCS, 263 * FEC corrected error indication 264 */ 265 uint32_t v3_pcs_40g_ll_cerr_0; 266 /* 267 * [0x10] 40G PCS, 268 * FEC corrected error indication 269 */ 270 uint32_t v3_pcs_40g_ll_cerr_1; 271 /* 272 * [0x14] 40G PCS, 273 * FEC corrected error indication 274 */ 275 uint32_t v3_pcs_40g_ll_cerr_2; 276 /* 277 * [0x18] 40G PCS, 278 * FEC corrected error indication 279 */ 280 uint32_t v3_pcs_40g_ll_cerr_3; 281 /* 282 * [0x1c] 40G PCS, 283 * FEC uncorrectable error indication 284 */ 285 uint32_t v3_pcs_40g_ll_ncerr_0; 286 /* 287 * [0x20] 40G PCS, 288 * FEC uncorrectable error indication 289 */ 290 uint32_t v3_pcs_40g_ll_ncerr_1; 291 /* 292 * [0x24] 40G PCS, 293 * FEC uncorrectable error indication 294 */ 295 uint32_t v3_pcs_40g_ll_ncerr_2; 296 /* 297 * [0x28] 40G PCS, 298 * FEC uncorrectable error indication 299 */ 300 uint32_t v3_pcs_40g_ll_ncerr_3; 301 /* 302 * [0x2c] 10G_LL PCS, 303 * FEC corrected error indication 304 */ 305 uint32_t v3_pcs_10g_ll_cerr; 306 /* 307 * [0x30] 10G_LL PCS, 308 * FEC uncorrectable error indication 309 */ 310 uint32_t v3_pcs_10g_ll_ncerr; 311 uint32_t rsrvd[51]; 312 }; 313 struct al_eth_mac_stat_lane { 314 /* [0x0] Character error */ 315 uint32_t char_err; 316 /* [0x4] Disparity error */ 317 uint32_t disp_err; 318 /* [0x8] Comma detection */ 319 uint32_t pat; 320 uint32_t rsrvd[13]; 321 }; 322 struct al_eth_mac_gen_v3 { 323 /* [0x0] ASYNC FIFOs control */ 324 uint32_t afifo_ctrl; 325 /* [0x4] TX ASYNC FIFO configuration */ 326 uint32_t tx_afifo_cfg_1; 327 /* [0x8] TX ASYNC FIFO configuration */ 328 uint32_t tx_afifo_cfg_2; 329 /* [0xc] TX ASYNC FIFO configuration */ 330 uint32_t tx_afifo_cfg_3; 331 /* [0x10] TX ASYNC FIFO configuration */ 332 uint32_t tx_afifo_cfg_4; 333 /* [0x14] TX ASYNC FIFO configuration */ 334 uint32_t tx_afifo_cfg_5; 335 /* [0x18] RX ASYNC FIFO configuration */ 336 uint32_t rx_afifo_cfg_1; 337 /* [0x1c] RX ASYNC FIFO configuration */ 338 uint32_t rx_afifo_cfg_2; 339 /* [0x20] RX ASYNC FIFO configuration */ 340 uint32_t rx_afifo_cfg_3; 341 /* [0x24] RX ASYNC FIFO configuration */ 342 uint32_t rx_afifo_cfg_4; 343 /* [0x28] RX ASYNC FIFO configuration */ 344 uint32_t rx_afifo_cfg_5; 345 /* [0x2c] MAC selection configuration */ 346 uint32_t mac_sel; 347 /* [0x30] 10G LL MAC configuration */ 348 uint32_t mac_10g_ll_cfg; 349 /* [0x34] 10G LL MAC control */ 350 uint32_t mac_10g_ll_ctrl; 351 /* [0x38] 10G LL PCS configuration */ 352 uint32_t pcs_10g_ll_cfg; 353 /* [0x3c] 10G LL PCS status */ 354 uint32_t pcs_10g_ll_status; 355 /* [0x40] 40G LL PCS configuration */ 356 uint32_t pcs_40g_ll_cfg; 357 /* [0x44] 40G LL PCS status */ 358 uint32_t pcs_40g_ll_status; 359 /* [0x48] PCS 40G register file address */ 360 uint32_t pcs_40g_ll_addr; 361 /* [0x4c] PCS 40G register file data */ 362 uint32_t pcs_40g_ll_data; 363 /* [0x50] 40G LL MAC configuration */ 364 uint32_t mac_40g_ll_cfg; 365 /* [0x54] 40G LL MAC status */ 366 uint32_t mac_40g_ll_status; 367 /* [0x58] Preamble configuration (high [55:32]) */ 368 uint32_t preamble_cfg_high; 369 /* [0x5c] Preamble configuration (low [31:0]) */ 370 uint32_t preamble_cfg_low; 371 /* [0x60] MAC 40G register file address */ 372 uint32_t mac_40g_ll_addr; 373 /* [0x64] MAC 40G register file data */ 374 uint32_t mac_40g_ll_data; 375 /* [0x68] 40G LL MAC control */ 376 uint32_t mac_40g_ll_ctrl; 377 /* [0x6c] PCS 40G register file address */ 378 uint32_t pcs_40g_fec_91_ll_addr; 379 /* [0x70] PCS 40G register file data */ 380 uint32_t pcs_40g_fec_91_ll_data; 381 /* [0x74] 40G LL PCS EEE configuration */ 382 uint32_t pcs_40g_ll_eee_cfg; 383 /* [0x78] 40G LL PCS EEE status */ 384 uint32_t pcs_40g_ll_eee_status; 385 /* 386 * [0x7c] SERDES 32-bit interface shift configuration (when swap is 387 * enabled) 388 */ 389 uint32_t serdes_32_tx_shift; 390 /* 391 * [0x80] SERDES 32-bit interface shift configuration (when swap is 392 * enabled) 393 */ 394 uint32_t serdes_32_rx_shift; 395 /* 396 * [0x84] SERDES 32-bit interface bit selection 397 */ 398 uint32_t serdes_32_tx_sel; 399 /* 400 * [0x88] SERDES 32-bit interface bit selection 401 */ 402 uint32_t serdes_32_rx_sel; 403 /* [0x8c] AN/LT wrapper control */ 404 uint32_t an_lt_ctrl; 405 /* [0x90] AN/LT wrapper register file address */ 406 uint32_t an_lt_0_addr; 407 /* [0x94] AN/LT wrapper register file data */ 408 uint32_t an_lt_0_data; 409 /* [0x98] AN/LT wrapper register file address */ 410 uint32_t an_lt_1_addr; 411 /* [0x9c] AN/LT wrapper register file data */ 412 uint32_t an_lt_1_data; 413 /* [0xa0] AN/LT wrapper register file address */ 414 uint32_t an_lt_2_addr; 415 /* [0xa4] AN/LT wrapper register file data */ 416 uint32_t an_lt_2_data; 417 /* [0xa8] AN/LT wrapper register file address */ 418 uint32_t an_lt_3_addr; 419 /* [0xac] AN/LT wrapper register file data */ 420 uint32_t an_lt_3_data; 421 /* [0xb0] External SERDES control */ 422 uint32_t ext_serdes_ctrl; 423 /* [0xb4] spare bits */ 424 uint32_t spare; 425 uint32_t rsrvd[18]; 426 }; 427 428 struct al_eth_mac_regs { 429 struct al_eth_mac_1g mac_1g; /* [0x000] */ 430 struct al_eth_mac_10g mac_10g; /* [0x400] */ 431 uint32_t rsrvd_0[64]; /* [0x800] */ 432 struct al_eth_mac_gen gen; /* [0x900] */ 433 struct al_eth_mac_kr kr; /* [0xa00] */ 434 struct al_eth_mac_sgmii sgmii; /* [0xb00] */ 435 struct al_eth_mac_stat stat; /* [0xc00] */ 436 struct al_eth_mac_stat_lane stat_lane[4]; /* [0xd00] */ 437 struct al_eth_mac_gen_v3 gen_v3; /* [0xe00] */ 438 }; 439 440 441 /* 442 * Registers Fields 443 */ 444 445 /**** control register (1G mac) ****/ 446 /* enable Half Duplex */ 447 #define AL_ETH_1G_MAC_CTRL_HD_EN (1 << 10) 448 /* enable 1G speed */ 449 #define AL_ETH_1G_MAC_CTRL_1G_SPD (1 << 3) 450 /* enable 10M speed */ 451 #define AL_ETH_1G_MAC_CTRL_10M_SPD (1 << 25) 452 453 454 /**** 10G MAC register ****/ 455 /* mdio_cfg_status */ 456 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK 0x0000001c 457 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT 2 458 459 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_1_CLK 0 460 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_3_CLK 1 461 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_5_CLK 2 462 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK 3 463 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK 4 464 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_11_CLK 5 465 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_13_CLK 6 466 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_15_CLK 7 467 468 /**** version register ****/ 469 /* Revision number (Minor) */ 470 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 471 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 472 /* Revision number (Major) */ 473 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 474 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 475 /* Date of release */ 476 #define ETH_MAC_GEN_VERSION_DATE_DAY_MASK 0x001F0000 477 #define ETH_MAC_GEN_VERSION_DATE_DAY_SHIFT 16 478 /* Month of release */ 479 #define ETH_MAC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 480 #define ETH_MAC_GEN_VERSION_DATA_MONTH_SHIFT 21 481 /* Year of release (starting from 2000) */ 482 #define ETH_MAC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 483 #define ETH_MAC_GEN_VERSION_DATE_YEAR_SHIFT 25 484 /* Reserved */ 485 #define ETH_MAC_GEN_VERSION_RESERVED_MASK 0xC0000000 486 #define ETH_MAC_GEN_VERSION_RESERVED_SHIFT 30 487 488 /**** cfg register ****/ 489 /* 490 * Selects between the 10/100/1000 MAC and the 1/2.5/10G MAC: 491 * 0 - 10/100/1000 492 * 1 - 1/2.5/10G 493 */ 494 #define ETH_MAC_GEN_CFG_MAC_1_10 (1 << 0) 495 /* 496 * Selects the operation mode of the 1/2.5/10G MAC: 497 * 00 - 1/2.5G SGMII 498 * 01 - 10G XAUI/RXAUI 499 * 10 – 10G KR 500 * 11 – Reserved 501 */ 502 #define ETH_MAC_GEN_CFG_XGMII_SGMII_MASK 0x00000006 503 #define ETH_MAC_GEN_CFG_XGMII_SGMII_SHIFT 1 504 /* 505 * Selects the operation mode of the PCS: 506 * 0 - XAUI 507 * 1 - RXAUI 508 */ 509 #define ETH_MAC_GEN_CFG_XAUI_RXAUI (1 << 3) 510 /* Swap bits of TBI (SGMII mode) interface */ 511 #define ETH_MAC_GEN_CFG_SWAP_TBI_RX (1 << 4) 512 /* 513 * Determines the offset of the TBI bus on the SerDes interface: 514 * 0 - LSB 515 * 1 - MSB 516 */ 517 #define ETH_MAC_GEN_CFG_TBI_MSB_RX (1 << 5) 518 /* 519 * Selects the SGMII PCS/MAC: 520 * 0 – 10G MAC with SGMII 521 * 1 – 1G MAC with SGMII 522 */ 523 #define ETH_MAC_GEN_CFG_SGMII_SEL (1 << 6) 524 /* 525 * Selects between RGMII and SGMII for the 1G MAC: 526 * 0 – RGMII 527 * 1 – SGMII 528 */ 529 #define ETH_MAC_GEN_CFG_RGMII_SGMII_SEL (1 << 7) 530 /* Swap bits of TBI (SGMII mode) interface */ 531 #define ETH_MAC_GEN_CFG_SWAP_TBI_TX (1 << 8) 532 /* 533 * Determines the offset of the TBI bus on the SerDes interface: 534 * 0 - LSB 535 * 1 - MSB 536 */ 537 #define ETH_MAC_GEN_CFG_TBI_MSB_TX (1 << 9) 538 /* 539 * Selection between the MDIO from 10/100/1000 MAC or the 1/2.5/10G MAC 540 * 0 - 10/100/1000 541 * 1 - 1/2.5/10G 542 */ 543 #define ETH_MAC_GEN_CFG_MDIO_1_10 (1 << 10) 544 /* 545 * Swap MDC output 546 * 0 – Normal 547 * 1 – Flipped 548 */ 549 #define ETH_MAC_GEN_CFG_MDIO_POL (1 << 11) 550 /* Swap bits on SerDes interface */ 551 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_MASK 0x000F0000 552 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_SHIFT 16 553 /* Swap bits on SerDes interface */ 554 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_MASK 0x0F000000 555 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_SHIFT 24 556 557 /**** mac_1g_cfg register ****/ 558 /* 559 * Selection of the input for the "set_1000" input of the Ethernet 10/100/1000 560 * MAC: 561 * 0 - From RGMII converter (automatic speed selection) 562 * 1 - From register set_1000_def 563 */ 564 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_SEL (1 << 0) 565 /* Default value for the 10/100/1000 MAC "set_1000" input */ 566 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_DEF (1 << 1) 567 /* 568 * Selection of the input for the "set_10" input of the Ethernet 10/100/1000 569 * MAC: 570 * 0 - From RGMII converter (automatic speed selection) 571 * 1 - From register set_10_def 572 */ 573 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_SEL (1 << 4) 574 /* Default value for the 10/100/1000 MAC "set_10" input */ 575 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_DEF (1 << 5) 576 /* Transmit low power enable */ 577 #define ETH_MAC_GEN_MAC_1G_CFG_LOWP_ENA (1 << 8) 578 /* 579 * Enable magic packet mode: 580 * 0 - Sleep mode 581 * 1 - Normal operation 582 */ 583 #define ETH_MAC_GEN_MAC_1G_CFG_SLEEPN (1 << 9) 584 /* Swap ff_tx_crc input */ 585 #define ETH_MAC_GEN_MAC_1G_CFG_SWAP_FF_TX_CRC (1 << 12) 586 587 /**** mac_1g_stat register ****/ 588 /* Status of the en_10 output form the 10/100/1000 MAC */ 589 #define ETH_MAC_GEN_MAC_1G_STAT_EN_10 (1 << 0) 590 /* Status of the eth_mode output from th 10/100/1000 MAC */ 591 #define ETH_MAC_GEN_MAC_1G_STAT_ETH_MODE (1 << 1) 592 /* Status of the lowp output from the 10/100/1000 MAC */ 593 #define ETH_MAC_GEN_MAC_1G_STAT_LOWP (1 << 4) 594 /* Status of the wakeup output from the 10/100/1000 MAC */ 595 #define ETH_MAC_GEN_MAC_1G_STAT_WAKEUP (1 << 5) 596 597 /**** rgmii_cfg register ****/ 598 /* 599 * Selection of the input for the "set_1000" input of the RGMII converter 600 * 0 - From MAC 601 * 1 - From register set_1000_def (automatic speed selection) 602 */ 603 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL (1 << 0) 604 /* Default value for the RGMII converter "set_1000" input */ 605 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_DEF (1 << 1) 606 /* 607 * Selection of the input for the "set_10" input of the RGMII converter: 608 * 0 - From MAC 609 * 1 - From register set_10_def (automatic speed selection) 610 */ 611 #define ETH_MAC_GEN_RGMII_CFG_SET_10_SEL (1 << 4) 612 /* Default value for the 10/100/1000 MAC "set_10" input */ 613 #define ETH_MAC_GEN_RGMII_CFG_SET_10_DEF (1 << 5) 614 /* Enable automatic speed selection (based on PHY in-band status information) */ 615 #define ETH_MAC_GEN_RGMII_CFG_ENA_AUTO (1 << 8) 616 /* Force full duplex, only valid when ena_auto is '1'. */ 617 #define ETH_MAC_GEN_RGMII_CFG_SET_FD (1 << 9) 618 619 /**** rgmii_stat register ****/ 620 /* 621 * Status of the speed output form the RGMII converter 622 * 00 - 10 Mbps 623 * 01 - 100 Mbps 624 * 10 - 1000 Mbps 625 * 11 - Reserved 626 */ 627 #define ETH_MAC_GEN_RGMII_STAT_SPEED_MASK 0x00000003 628 #define ETH_MAC_GEN_RGMII_STAT_SPEED_SHIFT 0 629 /* 630 * Link indication from the RGMII converter (valid only if the external PHY 631 * supports in-band status signaling) 632 */ 633 #define ETH_MAC_GEN_RGMII_STAT_LINK (1 << 4) 634 /* 635 * Full duplex indication from the RGMII converter (valid only if the external 636 * PHY supports in-band status signaling) 637 */ 638 #define ETH_MAC_GEN_RGMII_STAT_DUP (1 << 5) 639 640 /**** mac_10g_cfg register ****/ 641 /* Instruct the XGMII to transmit local fault. */ 642 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LOC_FAULT (1 << 0) 643 /* Instruct the XGMII to transmit remote fault. */ 644 #define ETH_MAC_GEN_MAC_10G_CFG_TX_REM_FAULT (1 << 1) 645 /* Instruct the XGMII to transmit link fault. */ 646 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LI_FAULT (1 << 2) 647 /* 648 * Synchronous reset for the PCS layer. Can be used after SerDes lock assertion 649 * to reset the PCS state machine. 650 */ 651 #define ETH_MAC_GEN_MAC_10G_CFG_SG_SRESET (1 << 3) 652 /* 653 * PHY LOS indication selection 654 * 00 - Select register value from phy_los_def 655 * 01 - Select input from the SerDes 656 * 10 - Select input from GPIO 657 * 11 - Select inverted input from GPIO 658 */ 659 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_MASK 0x00000030 660 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_SHIFT 4 661 /* 662 * Default value for PHY LOS indication. Reflects the LOS indication from the 663 * SerDes. ('0' if not used) 664 */ 665 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_DEF (1 << 6) 666 /* Reverse polarity of the LOS signal from the SerDes */ 667 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_POL (1 << 7) 668 /* Transmit low power enable */ 669 #define ETH_MAC_GEN_MAC_10G_CFG_LOWP_ENA (1 << 8) 670 /* Swap ff_tx_crc input */ 671 #define ETH_MAC_GEN_MAC_10G_CFG_SWAP_FF_TX_CRC (1 << 12) 672 673 /**** mac_10g_stat register ****/ 674 /* XGMII RS detects local fault */ 675 #define ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT (1 << 0) 676 /* XGMII RS detects remote fault */ 677 #define ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT (1 << 1) 678 /* XGMII RS detects link fault */ 679 #define ETH_MAC_GEN_MAC_10G_STAT_LI_FAULT (1 << 2) 680 /* PFC mode */ 681 #define ETH_MAC_GEN_MAC_10G_STAT_PFC_MODE (1 << 3) 682 683 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ENA (1 << 4) 684 685 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ANDONE (1 << 5) 686 687 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SYNC (1 << 6) 688 689 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_MASK 0x00000180 690 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_SHIFT 7 691 /* Status of the lowp output form the 1/2.5/10G MAC */ 692 #define ETH_MAC_GEN_MAC_10G_STAT_LOWP (1 << 9) 693 /* Status of the ts_avail output from th 1/2.5/10G MAC */ 694 #define ETH_MAC_GEN_MAC_10G_STAT_TS_AVAIL (1 << 10) 695 /* Transmit pause indication */ 696 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_MASK 0xFF000000 697 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_SHIFT 24 698 699 /**** xaui_cfg register ****/ 700 /* Increase rate matching FIFO threshold */ 701 #define ETH_MAC_GEN_XAUI_CFG_JUMBO_EN (1 << 0) 702 703 /**** xaui_stat register ****/ 704 /* Lane alignment status */ 705 #define ETH_MAC_GEN_XAUI_STAT_ALIGN_DONE (1 << 0) 706 /* Lane synchronization */ 707 #define ETH_MAC_GEN_XAUI_STAT_SYNC_MASK 0x000000F0 708 #define ETH_MAC_GEN_XAUI_STAT_SYNC_SHIFT 4 709 /* Code group alignment indication */ 710 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_MASK 0x00000F00 711 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_SHIFT 8 712 713 /**** rxaui_cfg register ****/ 714 /* Increase rate matching FIFO threshold */ 715 #define ETH_MAC_GEN_RXAUI_CFG_JUMBO_EN (1 << 0) 716 /* Scrambler enable */ 717 #define ETH_MAC_GEN_RXAUI_CFG_SRBL_EN (1 << 1) 718 /* Disparity calculation across lanes enabled */ 719 #define ETH_MAC_GEN_RXAUI_CFG_DISP_ACROSS_LANE (1 << 2) 720 721 /**** rxaui_stat register ****/ 722 /* Lane alignment status */ 723 #define ETH_MAC_GEN_RXAUI_STAT_ALIGN_DONE (1 << 0) 724 /* Lane synchronization */ 725 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_MASK 0x000000F0 726 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_SHIFT 4 727 /* Code group alignment indication */ 728 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_MASK 0x00000F00 729 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_SHIFT 8 730 731 /**** sd_cfg register ****/ 732 /* 733 * Signal detect selection 734 * 0 - from register 735 * 1 - from SerDes 736 */ 737 #define ETH_MAC_GEN_SD_CFG_SEL_MASK 0x0000000F 738 #define ETH_MAC_GEN_SD_CFG_SEL_SHIFT 0 739 /* Signal detect value */ 740 #define ETH_MAC_GEN_SD_CFG_VAL_MASK 0x000000F0 741 #define ETH_MAC_GEN_SD_CFG_VAL_SHIFT 4 742 /* Signal detect revers polarity (reverse polarity of signal from the SerDes */ 743 #define ETH_MAC_GEN_SD_CFG_POL_MASK 0x00000F00 744 #define ETH_MAC_GEN_SD_CFG_POL_SHIFT 8 745 746 /**** mdio_ctrl_1 register ****/ 747 /* 748 * Available indication 749 * 0 - The port was available and it is captured by this Ethernet controller. 750 * 1 - The port is used by another Ethernet controller. 751 */ 752 #define ETH_MAC_GEN_MDIO_CTRL_1_AVAIL (1 << 0) 753 754 /**** mdio_1 register ****/ 755 /* Current Ethernet interface number that controls the MDIO port */ 756 #define ETH_MAC_GEN_MDIO_1_INFO_MASK 0x000000FF 757 #define ETH_MAC_GEN_MDIO_1_INFO_SHIFT 0 758 759 /**** mdio_ctrl_2 register ****/ 760 /* 761 * Available indication 762 * 0 - The port was available and it is captured by this Ethernet controller. 763 * 1 - The port is used by another Ethernet controller. 764 */ 765 #define ETH_MAC_GEN_MDIO_CTRL_2_AVAIL (1 << 0) 766 767 /**** mdio_2 register ****/ 768 /* Current Ethernet interface number that controls the MDIO port */ 769 #define ETH_MAC_GEN_MDIO_2_INFO_MASK 0x000000FF 770 #define ETH_MAC_GEN_MDIO_2_INFO_SHIFT 0 771 772 /**** xgmii_dfifo_32_64 register ****/ 773 /* FIFO enable */ 774 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_ENABLE (1 << 0) 775 /* Read Write command every 2 cycles */ 776 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_RW_2_CYCLES (1 << 1) 777 /* Swap LSB MSB when creating wider bus */ 778 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SWAP_LSB_MSB (1 << 2) 779 /* Software reset */ 780 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SW_RESET (1 << 4) 781 /* Read threshold */ 782 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_MASK 0x0000FF00 783 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_SHIFT 8 784 /* FIFO used */ 785 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_MASK 0x00FF0000 786 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_SHIFT 16 787 788 /**** xgmii_dfifo_64_32 register ****/ 789 /* FIFO enable */ 790 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_ENABLE (1 << 0) 791 /* Read Write command every 2 cycles */ 792 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_RW_2_CYCLES (1 << 1) 793 /* Swap LSB MSB when creating wider bus */ 794 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SWAP_LSB_MSB (1 << 2) 795 /* Software reset */ 796 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SW_RESET (1 << 4) 797 /* Read threshold */ 798 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_MASK 0x0000FF00 799 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_SHIFT 8 800 /* FIFO used */ 801 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_MASK 0x00FF0000 802 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_SHIFT 16 803 804 /**** sd_fifo_ctrl register ****/ 805 /* FIFO enable */ 806 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_MASK 0x0000000F 807 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_SHIFT 0 808 /* Software reset */ 809 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_MASK 0x000000F0 810 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_SHIFT 4 811 /* Read threshold */ 812 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_MASK 0x0000FF00 813 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_SHIFT 8 814 815 /**** sd_fifo_stat register ****/ 816 /* FIFO 0 used */ 817 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_MASK 0x000000FF 818 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_SHIFT 0 819 /* FIFO 1 used */ 820 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_MASK 0x0000FF00 821 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_SHIFT 8 822 /* FIFO 2 used */ 823 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_MASK 0x00FF0000 824 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_SHIFT 16 825 /* FIFO 3 used */ 826 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_MASK 0xFF000000 827 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_SHIFT 24 828 829 /**** mux_sel register ****/ 830 /* 831 * SGMII input selection selector 832 * 00 – SerDes 0 833 * 01 – SerDes 1 834 * 10 – SerDes 2 835 * 11 – SerDes 3 836 */ 837 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_MASK 0x00000003 838 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_SHIFT 0 839 /* 840 * RXAUI Lane 0 Input 841 * 00 – SerDes 0 842 * 01 – SerDes 1 843 * 10 – SerDes 2 844 * 11 – SerDes 3 845 */ 846 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_MASK 0x0000000C 847 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_SHIFT 2 848 /* 849 * RXAUI Lane 1 Input 850 * 00 – SERDES 0 851 * 01 – SERDES 1 852 * 10 – SERDES 2 853 * 11 – SERDES 3 854 */ 855 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_MASK 0x00000030 856 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_SHIFT 4 857 /* 858 * XAUI Lane 0 Input 859 * 00 – SERDES 0 860 * 01 – SERDES 1 861 * 10 – SERDES 2 862 * 11 – SERDES 3 863 */ 864 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_MASK 0x000000C0 865 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_SHIFT 6 866 /* 867 * XAUI Lane 1 Input 868 * 00 – SERDES 0 869 * 01 – SERDES 1 870 * 10 – SERDES 2 871 * 11 – SERDES 3 872 */ 873 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_MASK 0x00000300 874 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_SHIFT 8 875 /* 876 * XAUI Lane 2 Input 877 * 00 – SERDES 0 878 * 01 – SERDES 1 879 * 10 – SERDES 2 880 * 11 – SERDES 3 881 */ 882 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_MASK 0x00000C00 883 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_SHIFT 10 884 /* 885 * XAUI Lane 3 Input 886 * 00 – SERDES 0 887 * 01 – SERDES 1 888 * 10 – SERDES 2 889 * 11 – SERDES 3 890 */ 891 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_MASK 0x00003000 892 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_SHIFT 12 893 /* 894 * KR PCS Input 895 * 00 - SERDES 0 896 * 01 - SERDES 1 897 * 10 - SERDES 2 898 * 11 - SERDES 3 899 */ 900 #define ETH_MAC_GEN_MUX_SEL_KR_IN_MASK 0x0000C000 901 #define ETH_MAC_GEN_MUX_SEL_KR_IN_SHIFT 14 902 /* 903 * SerDes 0 input selection (TX) 904 * 000 – XAUI lane 0 905 * 001 – XAUI lane 1 906 * 010 – XAUI lane 2 907 * 011 – XAUI lane 3 908 * 100 – RXAUI lane 0 909 * 101 – RXAUI lane 1 910 * 110 – SGMII 911 * 111 – KR 912 */ 913 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_MASK 0x00070000 914 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_SHIFT 16 915 /* 916 * SERDES 1 input selection (Tx) 917 * 000 – XAUI lane 0 918 * 001 – XAUI lane 1 919 * 010 – XAUI lane 2 920 * 011 – XAUI lane 3 921 * 100 – RXAUI lane 0 922 * 101 – RXAUI lane 1 923 * 110 – SGMII 924 * 111 – KR 925 */ 926 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_MASK 0x00380000 927 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_SHIFT 19 928 /* 929 * SerDes 2 input selection (Tx) 930 * 000 – XAUI lane 0 931 * 001 – XAUI lane 1 932 * 010 – XAUI lane 2 933 * 011 – XAUI lane 3 934 * 100 – RXAUI lane 0 935 * 101 – RXAUI lane 1 936 * 110 – SGMII 937 * 111 – KR 938 */ 939 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_MASK 0x01C00000 940 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_SHIFT 22 941 /* 942 * SerDes 3 input selection (Tx) 943 * 000 – XAUI lane 0 944 * 001 – XAUI lane 1 945 * 010 – XAUI lane 2 946 * 011 – XAUI lane 3 947 * 100 – RXAUI lane 0 948 * 101 – RXAUI lane 1 949 * 110 – SGMII 950 * 111 – KR 951 */ 952 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_MASK 0x0E000000 953 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_SHIFT 25 954 955 /**** clk_cfg register ****/ 956 /* 957 * Rx/Tx lane 0 clock MUX select 958 * must be aligned with data selector MUXs) 959 * 0 – SerDes 0 clock 960 * 0 – SerDes 1 clock 961 * 2 – SerDes 2 clock 962 * 3 – SerDes 3 clock 963 */ 964 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_MASK 0x00000003 965 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_SHIFT 0 966 /* 967 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs) 968 * 0 - SerDes 0 clock 969 * 1 - SerDes 1 clock 970 * 2 - SerDes 2 clock 971 * 3 - SerDes 3 clock 972 */ 973 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_MASK 0x00000030 974 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_SHIFT 4 975 /* 976 * RX/TX lane 0 clock MUX select (should be aligned with data selector MUXs) 977 * 0 - SERDES 0 clock 978 * 1 - SERDES 1 clock 979 * 2 - SERDES 2 clock 980 * 3 - SERDES 3 clock 981 */ 982 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_MASK 0x00000300 983 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_SHIFT 8 984 /* 985 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs) 986 * 0 - SerDes 0 clock 987 * 1 - SerDes 1 clock 988 * 2 - SerDes 2 clock 989 * 3 - SerDes 3 clock 990 */ 991 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_MASK 0x00003000 992 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_SHIFT 12 993 /* 994 * MAC GMII Rx clock MUX select must be aligned with data selector MUXs) 995 * 0 – RGMII 996 * 1 – SGMII 997 */ 998 #define ETH_MAC_GEN_CLK_CFG_GMII_RX_CLK_SEL (1 << 16) 999 /* 1000 * MAC GMII Tx clock MUX select (should be aligned with data selector MUXs) 1001 * 0 - RGMII 1002 * 1 - SGMII 1003 */ 1004 #define ETH_MAC_GEN_CLK_CFG_GMII_TX_CLK_SEL (1 << 18) 1005 /* 1006 * Tx clock MUX select, 1007 * Selects the internal clock for the Tx data path 1008 * 0 – SerDes[0] TX DWORD CLK REF (for RXAUI and SGMII) 1009 * 1 – SerDes[0] TX WORD CLK REF (for XAUI and KR) 1010 */ 1011 #define ETH_MAC_GEN_CLK_CFG_TX_CLK_SEL (1 << 28) 1012 /* 1013 * Rxclock MUX select 1014 * Selects the internal clock for the Rx data path 1015 * 0 – XGMII TX CLK 32 LOCAL (for XAUI and RXAUI and KR) 1016 * 1 – SerDes[0] RX DWORD CLK GENERATED (125M) 1017 * (for SGMII) 1018 */ 1019 #define ETH_MAC_GEN_CLK_CFG_RX_CLK_SEL (1 << 30) 1020 1021 /**** los_sel register ****/ 1022 /* 1023 * Selected LOS/SD select 1024 * 00 – SerDes 0 1025 * 01 – SerDes 1 1026 * 10 – SerDes 2 1027 * 11 – SerDes 3 1028 */ 1029 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_MASK 0x00000003 1030 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_SHIFT 0 1031 /* 1032 * Selected LOS/SD select 1033 * 00 - SerDes 0 1034 * 01 - SerDes 1 1035 * 10 - SerDes 2 1036 * 11 - SerDes 3 1037 */ 1038 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_MASK 0x00000030 1039 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_SHIFT 4 1040 /* 1041 * Selected LOS/SD select 1042 * 00 - SerDes 0 1043 * 01 - SerDes 1 1044 * 10 - SerDes 2 1045 * 11 - SerDes 3 1046 */ 1047 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_MASK 0x00000300 1048 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_SHIFT 8 1049 /* 1050 * Selected LOS/SD select 1051 * 00 - SerDes 0 1052 * 01 - SerDes 1 1053 * 10 - SerDes 2 1054 * 11 - SerDes 3 1055 */ 1056 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_MASK 0x00003000 1057 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_SHIFT 12 1058 1059 /**** rgmii_sel register ****/ 1060 /* Swap [3:0] input with [7:4] */ 1061 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_3_0 (1 << 0) 1062 /* Swap [4] input with [9] */ 1063 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_4 (1 << 1) 1064 /* Swap [7:4] input with [3:0] */ 1065 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_7_3 (1 << 2) 1066 /* Swap [9] input with [4] */ 1067 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_9 (1 << 3) 1068 /* Swap [3:0] input with [7:4] */ 1069 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_3_0 (1 << 4) 1070 /* Swap [4] input with [9] */ 1071 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_4 (1 << 5) 1072 /* Swap [7:4] input with [3:0] */ 1073 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_7_3 (1 << 6) 1074 /* Swap [9] input with [4] */ 1075 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_9 (1 << 7) 1076 1077 /**** led_cfg register ****/ 1078 /* 1079 * LED source selection: 1080 * 0 – Default reg 1081 * 1 – Rx activity 1082 * 2 – Tx activity 1083 * 3 – Rx | Tx activity 1084 * 4-9 – SGMII LEDs 1085 */ 1086 #define ETH_MAC_GEN_LED_CFG_SEL_MASK 0x0000000F 1087 #define ETH_MAC_GEN_LED_CFG_SEL_SHIFT 0 1088 1089 /* turn the led on/off based on default value field (ETH_MAC_GEN_LED_CFG_DEF) */ 1090 #define ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG 0 1091 #define ETH_MAC_GEN_LED_CFG_SEL_RX_ACTIVITY_DEPRECIATED 1 1092 #define ETH_MAC_GEN_LED_CFG_SEL_TX_ACTIVITY_DEPRECIATED 2 1093 #define ETH_MAC_GEN_LED_CFG_SEL_RX_TX_ACTIVITY_DEPRECIATED 3 1094 #define ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY 10 1095 1096 /* LED default value */ 1097 #define ETH_MAC_GEN_LED_CFG_DEF (1 << 4) 1098 /* LED signal polarity */ 1099 #define ETH_MAC_GEN_LED_CFG_POL (1 << 5) 1100 /* 1101 * activity timer (MSB) 1102 * 32 bit timer @SB clock 1103 */ 1104 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK 0x00FF0000 1105 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT 16 1106 /* 1107 * activity timer (MSB) 1108 * 32 bit timer @SB clock 1109 */ 1110 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK 0xFF000000 1111 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT 24 1112 1113 /**** pcs_addr register ****/ 1114 /* Address value */ 1115 #define ETH_MAC_KR_PCS_ADDR_VAL_MASK 0x0000FFFF 1116 #define ETH_MAC_KR_PCS_ADDR_VAL_SHIFT 0 1117 1118 /**** pcs_data register ****/ 1119 /* Data value */ 1120 #define ETH_MAC_KR_PCS_DATA_VAL_MASK 0x0000FFFF 1121 #define ETH_MAC_KR_PCS_DATA_VAL_SHIFT 0 1122 1123 /**** an_addr register ****/ 1124 /* Address value */ 1125 #define ETH_MAC_KR_AN_ADDR_VAL_MASK 0x0000FFFF 1126 #define ETH_MAC_KR_AN_ADDR_VAL_SHIFT 0 1127 1128 /**** an_data register ****/ 1129 /* Data value */ 1130 #define ETH_MAC_KR_AN_DATA_VAL_MASK 0x0000FFFF 1131 #define ETH_MAC_KR_AN_DATA_VAL_SHIFT 0 1132 1133 /**** pma_addr register ****/ 1134 /* Dddress value */ 1135 #define ETH_MAC_KR_PMA_ADDR_VAL_MASK 0x0000FFFF 1136 #define ETH_MAC_KR_PMA_ADDR_VAL_SHIFT 0 1137 1138 /**** pma_data register ****/ 1139 /* Data value */ 1140 #define ETH_MAC_KR_PMA_DATA_VAL_MASK 0x0000FFFF 1141 #define ETH_MAC_KR_PMA_DATA_VAL_SHIFT 0 1142 1143 /**** mtip_addr register ****/ 1144 /* Address value */ 1145 #define ETH_MAC_KR_MTIP_ADDR_VAL_MASK 0x0000FFFF 1146 #define ETH_MAC_KR_MTIP_ADDR_VAL_SHIFT 0 1147 1148 /**** mtip_data register ****/ 1149 /* Data value */ 1150 #define ETH_MAC_KR_MTIP_DATA_VAL_MASK 0x0000FFFF 1151 #define ETH_MAC_KR_MTIP_DATA_VAL_SHIFT 0 1152 1153 /**** pcs_cfg register ****/ 1154 /* Enable Auto-Negotiation after Reset */ 1155 #define ETH_MAC_KR_PCS_CFG_STRAP_AN_ENA (1 << 0) 1156 /* 1157 * Signal detect selector for the EEE 1158 * 0 – Register default value 1159 * 1 – SerDes value 1160 */ 1161 #define ETH_MAC_KR_PCS_CFG_EEE_SD_SEL (1 << 4) 1162 /* Signal detect default value for the EEE */ 1163 #define ETH_MAC_KR_PCS_CFG_EEE_DEF_VAL (1 << 5) 1164 /* Signal detect polarity reversal for the EEE */ 1165 #define ETH_MAC_KR_PCS_CFG_EEE_SD_POL (1 << 6) 1166 /* EEE timer value */ 1167 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK 0x0000FF00 1168 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT 8 1169 /* 1170 * Selects source for the enable SerDes DME signal 1171 * 0 – Register value 1172 * 1 – PCS output 1173 */ 1174 #define ETH_MAC_KR_PCS_CFG_DME_SEL (1 << 16) 1175 /* DME default value */ 1176 #define ETH_MAC_KR_PCS_CFG_DME_VAL (1 << 17) 1177 /* DME default polarity reversal when selecting PCS output */ 1178 #define ETH_MAC_KR_PCS_CFG_DME_POL (1 << 18) 1179 1180 /**** pcs_stat register ****/ 1181 /* Link enable by the Auto-Negotiation */ 1182 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_MASK 0x0000003F 1183 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_SHIFT 0 1184 /* Block lock */ 1185 #define ETH_MAC_KR_PCS_STAT_BLOCK_LOCK (1 << 8) 1186 /* hi BER */ 1187 #define ETH_MAC_KR_PCS_STAT_HI_BER (1 << 9) 1188 1189 #define ETH_MAC_KR_PCS_STAT_RX_WAKE_ERR (1 << 16) 1190 1191 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_ALERT (1 << 17) 1192 1193 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_QUIET (1 << 18) 1194 1195 #define ETH_MAC_KR_PCS_STAT_PMA_RXMODE_QUIET (1 << 19) 1196 1197 #define ETH_MAC_KR_PCS_STAT_RX_LPI_ACTIVE (1 << 20) 1198 1199 #define ETH_MAC_KR_PCS_STAT_TX_LPI_ACTIVE (1 << 21) 1200 1201 /**** reg_addr register ****/ 1202 /* Address value */ 1203 #define ETH_MAC_SGMII_REG_ADDR_VAL_MASK 0x0000001F 1204 #define ETH_MAC_SGMII_REG_ADDR_VAL_SHIFT 0 1205 1206 #define ETH_MAC_SGMII_REG_ADDR_CTRL_REG 0x0 1207 #define ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG 0x14 1208 1209 /**** reg_data register ****/ 1210 /* Data value */ 1211 #define ETH_MAC_SGMII_REG_DATA_VAL_MASK 0x0000FFFF 1212 #define ETH_MAC_SGMII_REG_DATA_VAL_SHIFT 0 1213 1214 #define ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE (1 << 12) 1215 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN (1 << 0) 1216 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN (1 << 1) 1217 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_MASK 0xC 1218 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_SHIFT 2 1219 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_10 0x0 1220 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100 0x1 1221 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000 0x2 1222 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX (1 << 4) 1223 1224 /**** clk_div register ****/ 1225 /* Value for 1000M selection */ 1226 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_MASK 0x000000FF 1227 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_SHIFT 0 1228 /* Value for 100M selection */ 1229 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_MASK 0x0000FF00 1230 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_SHIFT 8 1231 /* Value for 10M selection */ 1232 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_MASK 0x00FF0000 1233 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_SHIFT 16 1234 /* Bypass PCS selection */ 1235 #define ETH_MAC_SGMII_CLK_DIV_BYPASS (1 << 24) 1236 /* 1237 * Divider selection when bypass field is '1', one hot 1238 * 001 – 1000M 1239 * 010 – 100M 1240 * 100 – 10M 1241 */ 1242 #define ETH_MAC_SGMII_CLK_DIV_SEL_MASK 0x0E000000 1243 #define ETH_MAC_SGMII_CLK_DIV_SEL_SHIFT 25 1244 1245 /**** link_stat register ****/ 1246 1247 #define ETH_MAC_SGMII_LINK_STAT_SET_1000 (1 << 0) 1248 1249 #define ETH_MAC_SGMII_LINK_STAT_SET_100 (1 << 1) 1250 1251 #define ETH_MAC_SGMII_LINK_STAT_SET_10 (1 << 2) 1252 1253 #define ETH_MAC_SGMII_LINK_STAT_LED_AN (1 << 3) 1254 1255 #define ETH_MAC_SGMII_LINK_STAT_HD_ENA (1 << 4) 1256 1257 #define ETH_MAC_SGMII_LINK_STAT_LED_LINK (1 << 5) 1258 1259 /**** afifo_ctrl register ****/ 1260 /* enable tx input operation */ 1261 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_IN (1 << 0) 1262 /* enable tx output operation */ 1263 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_OUT (1 << 1) 1264 /* enable rx input operation */ 1265 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_IN (1 << 4) 1266 /* enable rx output operation */ 1267 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_OUT (1 << 5) 1268 /* enable tx FIFO input operation */ 1269 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_IN (1 << 8) 1270 /* enable tx FIFO output operation */ 1271 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_OUT (1 << 9) 1272 /* enable rx FIFO input operation */ 1273 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_IN (1 << 12) 1274 /* enable rx FIFO output operation */ 1275 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_OUT (1 << 13) 1276 1277 /**** tx_afifo_cfg_1 register ****/ 1278 /* minimum packet size configuration */ 1279 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF 1280 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0 1281 1282 /**** tx_afifo_cfg_2 register ****/ 1283 /* maximum packet size configuration */ 1284 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF 1285 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0 1286 1287 /**** tx_afifo_cfg_3 register ****/ 1288 /* input bus width */ 1289 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF 1290 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0 1291 /* input bus width divide factor */ 1292 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000 1293 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16 1294 1295 /**** tx_afifo_cfg_4 register ****/ 1296 /* output bus width */ 1297 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF 1298 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0 1299 /* output bus width divide factor */ 1300 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000 1301 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16 1302 1303 /**** tx_afifo_cfg_5 register ****/ 1304 /* 1305 * determines if the input bus is valid/read or “write enable”. 1306 * 0 – write enable 1307 * 1 – valid/ready 1308 */ 1309 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0) 1310 /* 1311 * determines if the output bus is valid/read or “write enable”. 1312 * 0 – write enable 1313 * 1 – valid/ready 1314 */ 1315 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1) 1316 /* Swap input bus bytes */ 1317 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4) 1318 /* Swap output bus bytes */ 1319 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5) 1320 /* 1321 * output clock select 1322 * 0 – mac_ll_tx_clk 1323 * 1 – clk_mac_sys_clk 1324 */ 1325 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_CLK_SEL (1 << 8) 1326 1327 /**** rx_afifo_cfg_1 register ****/ 1328 /* minimum packet size configuration */ 1329 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF 1330 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0 1331 1332 /**** rx_afifo_cfg_2 register ****/ 1333 /* maximum packet size configuration */ 1334 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF 1335 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0 1336 1337 /**** rx_afifo_cfg_3 register ****/ 1338 /* input bus width */ 1339 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF 1340 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0 1341 /* input bus width divide factor */ 1342 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000 1343 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16 1344 1345 /**** rx_afifo_cfg_4 register ****/ 1346 /* output bus width */ 1347 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF 1348 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0 1349 /* output bus width divide factor */ 1350 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000 1351 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16 1352 1353 /**** rx_afifo_cfg_5 register ****/ 1354 /* 1355 * determines if the input bus is valid/read or “write enable”. 1356 * 0 – write enable 1357 * 1 – valid/ready 1358 */ 1359 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0) 1360 /* 1361 * determines if the output bus is valid/read or “write enable”. 1362 * 0 – write enable 1363 * 1 – valid/ready 1364 */ 1365 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1) 1366 /* Swap input bus bytes */ 1367 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4) 1368 /* Swap output bus bytes */ 1369 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5) 1370 /* 1371 * input clock select 1372 * 0 – mac_ll_rx_clk 1373 * 1 – clk_serdes_int_0_tx_dword_ref 1374 * 2 – clk_mac_sys_clk 1375 * 3 – mac_ll_tx_clk 1376 */ 1377 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_MASK 0x00000300 1378 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_SHIFT 8 1379 1380 /**** mac_sel register ****/ 1381 /* 1382 * Select the MAC that is connected to the SGMII PCS. 1383 * 0 – 1G MAC 1384 * 1 – 10G MAC 1385 */ 1386 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_SGMII (1 << 0) 1387 /* 1388 * Select between the 10G and 40G MAC 1389 * 0 – 10G MAC 1390 * 1 – 40G MAC 1391 */ 1392 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_40G (1 << 4) 1393 1394 /**** mac_10g_ll_cfg register ****/ 1395 /* 1396 * select between 10G (KR PCS) and 1G (SGMII) mode. 1397 * 0 – 10G 1398 * 1 – 1G 1399 */ 1400 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MODE_1G (1 << 0) 1401 /* enable Magic packet detection in the MAC (all other packets are dropped) */ 1402 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MAGIC_ENA (1 << 5) 1403 1404 /**** mac_10g_ll_ctrl register ****/ 1405 /* Force the MAC to stop TX transmission after low power mode. */ 1406 #define ETH_MAC_GEN_V3_MAC_10G_LL_CTRL_LPI_TXHOLD (1 << 0) 1407 1408 /**** pcs_10g_ll_cfg register ****/ 1409 /* RX FEC Enable */ 1410 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX (1 << 0) 1411 /* TX FEC enable */ 1412 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX (1 << 1) 1413 /* 1414 * RX FEC error propagation enable, 1415 * (debug, always 0) 1416 */ 1417 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_ERR_ENA (1 << 2) 1418 /* 1419 * Gearbox configuration: 1420 * 00 -16 1421 * 01 – 20 1422 * 10 – 32 1423 * 11 – reserved 1424 */ 1425 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_MASK 0x00000030 1426 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_SHIFT 4 1427 /* 1428 * Gearbox configuration: 1429 * 00 -16 1430 * 01 – 20 1431 * 10 – 32 1432 * 11 – reserved 1433 */ 1434 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_MASK 0x000000C0 1435 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_SHIFT 6 1436 1437 /**** pcs_10g_ll_status register ****/ 1438 /* FEC locked indication */ 1439 #define ETH_MAC_GEN_V3_PCS_10G_LL_STATUS_FEC_LOCKED (1 << 0) 1440 1441 /**** pcs_40g_ll_cfg register ****/ 1442 /* RX FEC Enable */ 1443 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_MASK 0x0000000F 1444 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_SHIFT 0 1445 /* TX FEC enable */ 1446 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_MASK 0x000000F0 1447 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_SHIFT 4 1448 /* 1449 * RX FEC error propagation enable, 1450 * (debug, always 0) 1451 */ 1452 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_MASK 0x00000F00 1453 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_SHIFT 8 1454 /* 1455 * SERDES width, 16 bit enable 1456 * 1 – 16 1457 * 2 – 32 1458 */ 1459 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_SD_16B (1 << 12) 1460 /* FEC 91 enable */ 1461 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC91_ENA (1 << 13) 1462 /* 1463 * PHY LOS indication selection 1464 * 00 - Select register value from phy_los_def 1465 * 01 - Select input from the SerDes 1466 * 10 - Select input from GPIO 1467 * 11 - Select inverted input from GPIO 1468 */ 1469 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00030000 1470 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_SHIFT 16 1471 /* PHY LOS default value */ 1472 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_DEF (1 << 18) 1473 /* PHY LOS polarity */ 1474 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_POL (1 << 19) 1475 /* 1476 * Energy detect indication selection 1477 * 00 - Select register value from phy_los_def 1478 * 01 - Select input from the SerDes 1479 * 10 - Select input from GPIO 1480 * 11 - Select inverted input from GPIO 1481 */ 1482 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_MASK 0x00300000 1483 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_SHIFT 20 1484 /* Energy detect default value */ 1485 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_DEF (1 << 22) 1486 /* Energy detect polarity */ 1487 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_POL (1 << 23) 1488 1489 /**** pcs_40g_ll_status register ****/ 1490 /* Block lock */ 1491 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_MASK 0x0000000F 1492 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_SHIFT 0 1493 /* align done */ 1494 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_ALIGN_DONE (1 << 4) 1495 /* high BER */ 1496 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_HIGH_BER (1 << 8) 1497 /* FEC locked indication */ 1498 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_MASK 0x0000F000 1499 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_SHIFT 12 1500 1501 /**** pcs_40g_ll_addr register ****/ 1502 /* Address value */ 1503 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_MASK 0x0001FFFF 1504 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_SHIFT 0 1505 1506 /**** pcs_40g_ll_data register ****/ 1507 /* Data value */ 1508 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_MASK 0x0000FFFF 1509 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_SHIFT 0 1510 1511 /**** mac_40g_ll_cfg register ****/ 1512 /* change TX CRC polarity */ 1513 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_SWAP_FF_TX_CRC (1 << 0) 1514 /* force TX remote fault */ 1515 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_REM_FAULT (1 << 4) 1516 /* force TX local fault */ 1517 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LOC_FAULT (1 << 5) 1518 /* force TX Link fault */ 1519 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LI_FAULT (1 << 6) 1520 /* 1521 * PHY LOS indication selection 1522 * 00 - Select register value from phy_los_def 1523 * 01 - Select input from the SerDes 1524 * 10 - Select input from GPIO 1525 * 11 - Select inverted input from GPIO 1526 */ 1527 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00000300 1528 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_SHIFT 8 1529 /* PHY LOS default value */ 1530 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_DEF (1 << 10) 1531 /* PHY LOS polarity */ 1532 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_POL (1 << 11) 1533 1534 /**** mac_40g_ll_status register ****/ 1535 /* pause on indication */ 1536 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_MASK 0x000000FF 1537 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_SHIFT 0 1538 /* local fault indication received */ 1539 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT (1 << 8) 1540 /* remote fault indication received */ 1541 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT (1 << 9) 1542 /* Link fault indication */ 1543 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LI_FAULT (1 << 10) 1544 1545 /**** preamble_cfg_high register ****/ 1546 /* preamble value */ 1547 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_MASK 0x00FFFFFF 1548 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_SHIFT 0 1549 1550 /**** mac_40g_ll_addr register ****/ 1551 /* Address value */ 1552 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_MASK 0x000003FF 1553 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_SHIFT 0 1554 1555 /**** mac_40g_ll_ctrl register ****/ 1556 /* Force the MAC to stop TX transmission after low power mode. */ 1557 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_LPI_TXHOLD (1 << 0) 1558 1559 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_REG_LOWP_ENA (1 << 1) 1560 1561 /**** pcs_40g_fec_91_ll_addr register ****/ 1562 /* Address value */ 1563 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_MASK 0x000001FF 1564 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_SHIFT 0 1565 1566 /**** pcs_40g_fec_91_ll_data register ****/ 1567 /* Data value */ 1568 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_MASK 0x0000FFFF 1569 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_SHIFT 0 1570 1571 /**** pcs_40g_ll_eee_cfg register ****/ 1572 /* Low power timer configuration */ 1573 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK 0x000000FF 1574 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT 0 1575 /* Low power Fast wake */ 1576 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_LPI_FW (1 << 8) 1577 1578 /**** pcs_40g_ll_eee_status register ****/ 1579 /* TX LPI mode */ 1580 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_MASK 0x00000003 1581 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_SHIFT 0 1582 /* TX LPI state */ 1583 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_MASK 0x00000070 1584 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_SHIFT 4 1585 /* TX LPI mode */ 1586 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_MODE (1 << 8) 1587 /* TX LPI state */ 1588 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_MASK 0x00007000 1589 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_SHIFT 12 1590 /* TX LPI active */ 1591 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_ACTIVE (1 << 15) 1592 1593 /**** serdes_32_tx_shift register ****/ 1594 /* bit shift */ 1595 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_MASK 0x0000001F 1596 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_SHIFT 0 1597 /* bit shift */ 1598 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_MASK 0x000003E0 1599 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_SHIFT 5 1600 /* bit shift */ 1601 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_MASK 0x00007C00 1602 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_SHIFT 10 1603 /* bit shift */ 1604 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_MASK 0x000F8000 1605 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_SHIFT 15 1606 1607 /**** serdes_32_rx_shift register ****/ 1608 /* bit shift */ 1609 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_MASK 0x0000001F 1610 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_SHIFT 0 1611 /* bit shift */ 1612 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_MASK 0x000003E0 1613 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_SHIFT 5 1614 /* bit shift */ 1615 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_MASK 0x00007C00 1616 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_SHIFT 10 1617 /* bit shift */ 1618 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_MASK 0x000F8000 1619 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_SHIFT 15 1620 1621 /**** serdes_32_tx_sel register ****/ 1622 /* 1623 * 0 – directly from serdes 1624 * 1 – swapped 1625 * 2 – swapped with shift 1626 * 3 - legacy (based on gen cfg register) 1627 */ 1628 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_MASK 0x00000003 1629 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_SHIFT 0 1630 /* 1631 * 0 – directly from serdes 1632 * 1 – swapped 1633 * 2 – swapped with shift 1634 * 3 - legacy (based on gen cfg register) 1635 */ 1636 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_MASK 0x00000030 1637 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_SHIFT 4 1638 /* 1639 * 0 – directly from serdes 1640 * 1 – swapped 1641 * 2 – swapped with shift 1642 * 3 - legacy (based on gen cfg register) 1643 */ 1644 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_MASK 0x00000300 1645 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_SHIFT 8 1646 /* 1647 * 0 – directly from serdes 1648 * 1 – swapped 1649 * 2 – swapped with shift 1650 * 3 - legacy (based on gen cfg register) 1651 */ 1652 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_MASK 0x00003000 1653 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_SHIFT 12 1654 1655 /**** serdes_32_rx_sel register ****/ 1656 /* 1657 * 0 – directly from serdes 1658 * 1 – swapped 1659 * 2 – swapped with shift 1660 * 3 - legacy (based on gen cfg register) 1661 */ 1662 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_MASK 0x00000003 1663 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_SHIFT 0 1664 /* 1665 * 0 – directly from serdes 1666 * 1 – swapped 1667 * 2 – swapped with shift 1668 * 3 - legacy (based on gen cfg register) 1669 */ 1670 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_MASK 0x00000030 1671 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_SHIFT 4 1672 /* 1673 * 0 – directly from serdes 1674 * 1 – swapped 1675 * 2 – swapped with shift 1676 * 3 - legacy (based on gen cfg register) 1677 */ 1678 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_MASK 0x00000300 1679 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_SHIFT 8 1680 /* 1681 * 0 – directly from serdes 1682 * 1 – swapped 1683 * 2 – swapped with shift 1684 * 3 - legacy (based on gen cfg register) 1685 */ 1686 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_MASK 0x00003000 1687 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_SHIFT 12 1688 1689 /**** an_lt_ctrl register ****/ 1690 /* reset lane [3:0] */ 1691 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_MASK 0x0000000F 1692 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_SHIFT 0 1693 1694 /* PHY LOS indication input selection 1695 * 0 - from serdes 1696 * 1 - from an_lt 1697 */ 1698 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_0 (1 << 8) 1699 /* PHY LOS indication input selection 1700 * 0 - from serdes 1701 * 1 - from an_lt 1702 */ 1703 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_1 (1 << 9) 1704 /* PHY LOS indication input selection 1705 * 0 - from serdes 1706 * 1 - from an_lt 1707 */ 1708 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_2 (1 << 10) 1709 /* PHY LOS indication input selection 1710 * 0 - from serdes 1711 * 1 - from an_lt 1712 */ 1713 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_3 (1 << 11) 1714 1715 /**** an_lt_0_addr register ****/ 1716 /* Address value */ 1717 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_MASK 0x0000FFFF 1718 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_SHIFT 0 1719 1720 /**** an_lt_1_addr register ****/ 1721 /* Address value */ 1722 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_MASK 0x0000FFFF 1723 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_SHIFT 0 1724 1725 /**** an_lt_2_addr register ****/ 1726 /* Address value */ 1727 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_MASK 0x0000FFFF 1728 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_SHIFT 0 1729 1730 /**** an_lt_3_addr register ****/ 1731 /* Address value */ 1732 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_MASK 0x0000FFFF 1733 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_SHIFT 0 1734 1735 /**** ext_serdes_ctrl register ****/ 1736 /* 1737 * Lane 0, SERDES selection: 1738 * 0 – 10G SERDES, lane 0 1739 * 1 – 25G SERDES, lane 0 1740 */ 1741 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_SEL_25_10 (1 << 0) 1742 /* 1743 * Lane 1, SERDES selection: 1744 * 0 – 10G SERDES, lane 1 1745 * 1 – 25G SERDES, lane 1 1746 */ 1747 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_SEL_25_10 (1 << 1) 1748 /* 1749 * Lane 2, SERDES selection: 1750 * 0 – 10G SERDES, lane 2 1751 * 1 – 25G SERDES, lane 0 1752 */ 1753 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_2_SEL_25_10 (1 << 2) 1754 /* 1755 * Lane 3, SERDES selection: 1756 * 0 – 10G SERDES, lane 3 1757 * 1 – 25G SERDES, lane 1 1758 */ 1759 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_3_SEL_25_10 (1 << 3) 1760 1761 /* Lane 0 Rx, 25G 40bit-32bit gearshitf sw reset */ 1762 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET (1 << 4) 1763 /* Lane 0 Tx, 25G 40bit-32bit gearshitf sw reset */ 1764 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET (1 << 5) 1765 /* Lane 1 Rx, 25G 40bit-32bit gearshitf sw reset */ 1766 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET (1 << 6) 1767 /* Lane 1 Tx, 25G 40bit-32bit gearshitf sw reset */ 1768 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET (1 << 7) 1769 /* SerDes 25G gear shift Tx lane selector */ 1770 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_SRDS25_GS_TX_LANE_CLK_SEL (1 << 8) 1771 1772 /*** MAC Core registers addresses ***/ 1773 /* command config */ 1774 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR 0x00000008 1775 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA (1 << 0) 1776 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA (1 << 1) 1777 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE (1 << 19) 1778 1779 /* frame length */ 1780 #define ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR 0x00000014 1781 1782 #define ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR 0x00000054 1783 #define ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR 0x00000058 1784 #define ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR 0x0000005C 1785 #define ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR 0x00000060 1786 #define ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR 0x00000064 1787 #define ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR 0x00000068 1788 #define ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR 0x0000006C 1789 #define ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR 0x00000070 1790 1791 /* spare */ 1792 #define ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH (1 << 0) 1793 1794 /*** PCS Core registers addresses ***/ 1795 /* 40g control/status */ 1796 #define ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR 0x00000000 1797 /* 10g control_1 */ 1798 #define ETH_MAC_KR_PCS_CONTROL_1_ADDR 0x00000000 1799 1800 #define ETH_MAC_KR_AN_MILLISECONDS_COUNTER_ADDR 0x00008000 1801 #define ETH_MAC_AN_LT_MILLISECONDS_COUNTER_ADDR 0x00000020 1802 1803 #ifdef __cplusplus 1804 } 1805 #endif 1806 1807 #endif /* __AL_HAL_ETH_MAC_REGS_H__ */ 1808 1809 /** @} end of Ethernet group */ 1810