1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_eth_ec_regs.h 40 * 41 * @brief Ethernet controller registers 42 * 43 */ 44 45 #ifndef __AL_HAL_EC_REG_H 46 #define __AL_HAL_EC_REG_H 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 58 59 struct al_ec_gen { 60 /* [0x0] Ethernet controller Version */ 61 uint32_t version; 62 /* [0x4] Enable modules operation. */ 63 uint32_t en; 64 /* [0x8] Enable FIFO operation on the EC side. */ 65 uint32_t fifo_en; 66 /* [0xc] General L2 configuration for the Ethernet controlle ... */ 67 uint32_t l2; 68 /* [0x10] Configure protocol index values */ 69 uint32_t cfg_i; 70 /* [0x14] Configure protocol index values (extended protocols ... */ 71 uint32_t cfg_i_ext; 72 /* [0x18] Enable modules operation (extended operations). */ 73 uint32_t en_ext; 74 uint32_t rsrvd[9]; 75 }; 76 struct al_ec_mac { 77 /* [0x0] General configuration of the MAC side of the Ethern ... */ 78 uint32_t gen; 79 /* [0x4] Minimum packet size */ 80 uint32_t min_pkt; 81 /* [0x8] Maximum packet size */ 82 uint32_t max_pkt; 83 uint32_t rsrvd[13]; 84 }; 85 struct al_ec_rxf { 86 /* [0x0] Rx FIFO input controller configuration 1 */ 87 uint32_t cfg_1; 88 /* [0x4] Rx FIFO input controller configuration 2 */ 89 uint32_t cfg_2; 90 /* [0x8] Threshold to start reading packet from the Rx FIFO */ 91 uint32_t rd_fifo; 92 /* [0xc] Threshold to stop writing packet to the Rx FIFO */ 93 uint32_t wr_fifo; 94 /* [0x10] Threshold to stop writing packet to the loopback FI ... */ 95 uint32_t lb_fifo; 96 /* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */ 97 uint32_t cfg_lb; 98 /* [0x18] Configuration for dropping packet at the FIFO outpu ... */ 99 uint32_t out_drop; 100 uint32_t rsrvd[25]; 101 }; 102 struct al_ec_epe { 103 /* [0x0] Ethernet parsing engine configuration 1 */ 104 uint32_t parse_cfg; 105 /* [0x4] Protocol index action table address */ 106 uint32_t act_table_addr; 107 /* [0x8] Protocol index action table data */ 108 uint32_t act_table_data_1; 109 /* [0xc] Protocol index action table data */ 110 uint32_t act_table_data_2; 111 /* [0x10] Protocol index action table data */ 112 uint32_t act_table_data_3; 113 /* [0x14] Protocol index action table data */ 114 uint32_t act_table_data_4; 115 /* [0x18] Protocol index action table data */ 116 uint32_t act_table_data_5; 117 /* [0x1c] Protocol index action table data */ 118 uint32_t act_table_data_6; 119 /* [0x20] Input result vector, default values for parser inpu ... */ 120 uint32_t res_def; 121 /* [0x24] Result input vector selection */ 122 uint32_t res_in; 123 uint32_t rsrvd[6]; 124 }; 125 struct al_ec_epe_res { 126 /* [0x0] Parser result vector pointer */ 127 uint32_t p1; 128 /* [0x4] Parser result vector pointer */ 129 uint32_t p2; 130 /* [0x8] Parser result vector pointer */ 131 uint32_t p3; 132 /* [0xc] Parser result vector pointer */ 133 uint32_t p4; 134 /* [0x10] Parser result vector pointer */ 135 uint32_t p5; 136 /* [0x14] Parser result vector pointer */ 137 uint32_t p6; 138 /* [0x18] Parser result vector pointer */ 139 uint32_t p7; 140 /* [0x1c] Parser result vector pointer */ 141 uint32_t p8; 142 /* [0x20] Parser result vector pointer */ 143 uint32_t p9; 144 /* [0x24] Parser result vector pointer */ 145 uint32_t p10; 146 /* [0x28] Parser result vector pointer */ 147 uint32_t p11; 148 /* [0x2c] Parser result vector pointer */ 149 uint32_t p12; 150 /* [0x30] Parser result vector pointer */ 151 uint32_t p13; 152 /* [0x34] Parser result vector pointer */ 153 uint32_t p14; 154 /* [0x38] Parser result vector pointer */ 155 uint32_t p15; 156 /* [0x3c] Parser result vector pointer */ 157 uint32_t p16; 158 /* [0x40] Parser result vector pointer */ 159 uint32_t p17; 160 /* [0x44] Parser result vector pointer */ 161 uint32_t p18; 162 /* [0x48] Parser result vector pointer */ 163 uint32_t p19; 164 /* [0x4c] Parser result vector pointer */ 165 uint32_t p20; 166 uint32_t rsrvd[12]; 167 }; 168 struct al_ec_epe_h { 169 /* [0x0] Header length, support for header length table for ... */ 170 uint32_t hdr_len; 171 }; 172 struct al_ec_epe_p { 173 /* [0x0] Data for comparison */ 174 uint32_t comp_data; 175 /* [0x4] Mask for comparison */ 176 uint32_t comp_mask; 177 /* [0x8] Compare control */ 178 uint32_t comp_ctrl; 179 uint32_t rsrvd[4]; 180 }; 181 struct al_ec_epe_a { 182 /* [0x0] Protocol index action register */ 183 uint32_t prot_act; 184 }; 185 struct al_ec_rfw { 186 /* [0x0] Tuple (4/2) Hash configuration */ 187 uint32_t thash_cfg_1; 188 /* [0x4] Tuple (4/2) Hash configuration */ 189 uint32_t thash_cfg_2; 190 /* [0x8] MAC Hash configuration */ 191 uint32_t mhash_cfg_1; 192 /* [0xc] MAC Hash configuration */ 193 uint32_t mhash_cfg_2; 194 /* [0x10] MAC Hash configuration */ 195 uint32_t hdr_split; 196 /* [0x14] Masking the errors described in register rxf_drop ... */ 197 uint32_t meta_err; 198 /* [0x18] Configuration for generating the MetaData for the R ... */ 199 uint32_t meta; 200 /* [0x1c] Configuration for generating the MetaData for the R ... */ 201 uint32_t filter; 202 /* [0x20] 4 tupple hash table address */ 203 uint32_t thash_table_addr; 204 /* [0x24] 4 tupple hash table data */ 205 uint32_t thash_table_data; 206 /* [0x28] MAC hash table address */ 207 uint32_t mhash_table_addr; 208 /* [0x2c] MAC hash table data */ 209 uint32_t mhash_table_data; 210 /* [0x30] VLAN table address */ 211 uint32_t vid_table_addr; 212 /* [0x34] VLAN table data */ 213 uint32_t vid_table_data; 214 /* [0x38] VLAN p-bits table address */ 215 uint32_t pbits_table_addr; 216 /* [0x3c] VLAN p-bits table data */ 217 uint32_t pbits_table_data; 218 /* [0x40] DSCP table address */ 219 uint32_t dscp_table_addr; 220 /* [0x44] DSCP table data */ 221 uint32_t dscp_table_data; 222 /* [0x48] TC table address */ 223 uint32_t tc_table_addr; 224 /* [0x4c] TC table data */ 225 uint32_t tc_table_data; 226 /* [0x50] Control table address */ 227 uint32_t ctrl_table_addr; 228 /* [0x54] Control table data */ 229 uint32_t ctrl_table_data; 230 /* [0x58] Forwarding output configuration */ 231 uint32_t out_cfg; 232 /* [0x5c] Flow steering mechanism, 233 Table address */ 234 uint32_t fsm_table_addr; 235 /* [0x60] Flow steering mechanism, 236 Table data */ 237 uint32_t fsm_table_data; 238 /* [0x64] Selection of data to be used in packet forwarding0 ... */ 239 uint32_t ctrl_sel; 240 /* [0x68] Default VLAN data, used for untagged packets */ 241 uint32_t default_vlan; 242 /* [0x6c] Default HASH output values */ 243 uint32_t default_hash; 244 /* [0x70] Default override values, if a packet was filtered b ... */ 245 uint32_t default_or; 246 /* [0x74] Latched information when a drop condition occurred */ 247 uint32_t drop_latch; 248 /* [0x78] Check sum calculation configuration */ 249 uint32_t checksum; 250 /* [0x7c] LRO offload engine configuration register */ 251 uint32_t lro_cfg_1; 252 /* [0x80] LRO offload engine Check rules configurations for I ... */ 253 uint32_t lro_check_ipv4; 254 /* [0x84] LRO offload engine IPv4 values configuration */ 255 uint32_t lro_ipv4; 256 /* [0x88] LRO offload engine Check rules configurations for I ... */ 257 uint32_t lro_check_ipv6; 258 /* [0x8c] LRO offload engine IPv6 values configuration */ 259 uint32_t lro_ipv6; 260 /* [0x90] LRO offload engine Check rules configurations for T ... */ 261 uint32_t lro_check_tcp; 262 /* [0x94] LRO offload engine IPv6 values configuration */ 263 uint32_t lro_tcp; 264 /* [0x98] LRO offload engine Check rules configurations for U ... */ 265 uint32_t lro_check_udp; 266 /* [0x9c] LRO offload engine Check rules configurations for U ... */ 267 uint32_t lro_check_l2; 268 /* [0xa0] LRO offload engine Check rules configurations for U ... */ 269 uint32_t lro_check_gen; 270 /* [0xa4] Rules for storing packet information into the cache ... */ 271 uint32_t lro_store; 272 /* [0xa8] VLAN table default */ 273 uint32_t vid_table_def; 274 /* [0xac] Control table default */ 275 uint32_t ctrl_table_def; 276 /* [0xb0] Additional configuration 0 */ 277 uint32_t cfg_a_0; 278 /* [0xb4] Tuple (4/2) Hash configuration (extended for RoCE a ... */ 279 uint32_t thash_cfg_3; 280 /* [0xb8] Tuple (4/2) Hash configuration , mask for the input ... */ 281 uint32_t thash_mask_outer_ipv6; 282 /* [0xbc] Tuple (4/2) Hash configuration , mask for the input ... */ 283 uint32_t thash_mask_outer; 284 /* [0xc0] Tuple (4/2) Hash configuration , mask for the input ... */ 285 uint32_t thash_mask_inner_ipv6; 286 /* [0xc4] Tuple (4/2) Hash configuration , mask for the input ... */ 287 uint32_t thash_mask_inner; 288 uint32_t rsrvd[10]; 289 }; 290 struct al_ec_rfw_udma { 291 /* [0x0] Per UDMA default configuration */ 292 uint32_t def_cfg; 293 }; 294 struct al_ec_rfw_hash { 295 /* [0x0] key configuration (320 bits) */ 296 uint32_t key; 297 }; 298 struct al_ec_rfw_priority { 299 /* [0x0] Priority to queue mapping configuration */ 300 uint32_t queue; 301 }; 302 struct al_ec_rfw_default { 303 /* [0x0] Default forwarding configuration options */ 304 uint32_t opt_1; 305 }; 306 struct al_ec_fwd_mac { 307 /* [0x0] MAC address data [31:0] */ 308 uint32_t data_l; 309 /* [0x4] MAC address data [15:0] */ 310 uint32_t data_h; 311 /* [0x8] MAC address mask [31:0] */ 312 uint32_t mask_l; 313 /* [0xc] MAC address mask [15:0] */ 314 uint32_t mask_h; 315 /* [0x10] MAC compare control */ 316 uint32_t ctrl; 317 }; 318 struct al_ec_msw { 319 /* [0x0] Configuration for unicast packets */ 320 uint32_t uc; 321 /* [0x4] Configuration for multicast packets */ 322 uint32_t mc; 323 /* [0x8] Configuration for broadcast packets */ 324 uint32_t bc; 325 uint32_t rsrvd[3]; 326 }; 327 struct al_ec_tso { 328 /* [0x0] Input configuration */ 329 uint32_t in_cfg; 330 /* [0x4] MetaData default cache table address */ 331 uint32_t cache_table_addr; 332 /* [0x8] MetaData default cache table data */ 333 uint32_t cache_table_data_1; 334 /* [0xc] MetaData default cache table data */ 335 uint32_t cache_table_data_2; 336 /* [0x10] MetaData default cache table data */ 337 uint32_t cache_table_data_3; 338 /* [0x14] MetaData default cache table data */ 339 uint32_t cache_table_data_4; 340 /* [0x18] TCP control bit operation for first segment */ 341 uint32_t ctrl_first; 342 /* [0x1c] TCP control bit operation for middle segments */ 343 uint32_t ctrl_middle; 344 /* [0x20] TCP control bit operation for last segment */ 345 uint32_t ctrl_last; 346 /* [0x24] Additional TSO configurations */ 347 uint32_t cfg_add_0; 348 /* [0x28] TSO configuration for tunnelled packets */ 349 uint32_t cfg_tunnel; 350 uint32_t rsrvd[13]; 351 }; 352 struct al_ec_tso_sel { 353 /* [0x0] MSS value */ 354 uint32_t mss; 355 }; 356 struct al_ec_tpe { 357 /* [0x0] Parsing configuration */ 358 uint32_t parse; 359 uint32_t rsrvd[15]; 360 }; 361 struct al_ec_tpm_udma { 362 /* [0x0] Default VLAN data */ 363 uint32_t vlan_data; 364 /* [0x4] UDMA MAC SA information for spoofing */ 365 uint32_t mac_sa_1; 366 /* [0x8] UDMA MAC SA information for spoofing */ 367 uint32_t mac_sa_2; 368 }; 369 struct al_ec_tpm_sel { 370 /* [0x0] Ethertype values for VLAN modification */ 371 uint32_t etype; 372 }; 373 struct al_ec_tfw { 374 /* [0x0] Tx FIFO Wr configuration */ 375 uint32_t tx_wr_fifo; 376 /* [0x4] VLAN table address */ 377 uint32_t tx_vid_table_addr; 378 /* [0x8] VLAN table data */ 379 uint32_t tx_vid_table_data; 380 /* [0xc] Tx FIFO Rd configuration */ 381 uint32_t tx_rd_fifo; 382 /* [0x10] Tx FIFO Rd configuration, checksum insertion */ 383 uint32_t tx_checksum; 384 /* [0x14] Tx forwarding general configuration register */ 385 uint32_t tx_gen; 386 /* [0x18] Tx spoofing configuration */ 387 uint32_t tx_spf; 388 /* [0x1c] TX data FIFO status */ 389 uint32_t data_fifo; 390 /* [0x20] Tx control FIFO status */ 391 uint32_t ctrl_fifo; 392 /* [0x24] Tx header FIFO status */ 393 uint32_t hdr_fifo; 394 uint32_t rsrvd[14]; 395 }; 396 struct al_ec_tfw_udma { 397 /* [0x0] Default GMDA output bitmap for unicast packet */ 398 uint32_t uc_udma; 399 /* [0x4] Default GMDA output bitmap for multicast packet */ 400 uint32_t mc_udma; 401 /* [0x8] Default GMDA output bitmap for broadcast packet */ 402 uint32_t bc_udma; 403 /* [0xc] Tx spoofing configuration */ 404 uint32_t spf_cmd; 405 /* [0x10] Forwarding decision control */ 406 uint32_t fwd_dec; 407 uint32_t rsrvd; 408 }; 409 struct al_ec_tmi { 410 /* [0x0] Forward packets back to the Rx data path for local ... */ 411 uint32_t tx_cfg; 412 uint32_t rsrvd[3]; 413 }; 414 struct al_ec_efc { 415 /* [0x0] Mask of pause_on [7:0] for the Ethernet controller ... */ 416 uint32_t ec_pause; 417 /* [0x4] Mask of Ethernet controller Almost Full indication ... */ 418 uint32_t ec_xoff; 419 /* [0x8] Mask for generating XON indication pulse */ 420 uint32_t xon; 421 /* [0xc] Mask for generating GPIO output XOFF indication fro ... */ 422 uint32_t gpio; 423 /* [0x10] Rx FIFO threshold for generating the Almost Full in ... */ 424 uint32_t rx_fifo_af; 425 /* [0x14] Rx FIFO threshold for generating the Almost Full in ... */ 426 uint32_t rx_fifo_hyst; 427 /* [0x18] Rx FIFO threshold for generating the Almost Full in ... */ 428 uint32_t stat; 429 /* [0x1c] XOFF timer for the 1G MACSets the interval (in SB_C ... */ 430 uint32_t xoff_timer_1g; 431 /* [0x20] PFC force flow control generation */ 432 uint32_t ec_pfc; 433 uint32_t rsrvd[3]; 434 }; 435 struct al_ec_fc_udma { 436 /* [0x0] Mask of "pause_on" [0] for all queues */ 437 uint32_t q_pause_0; 438 /* [0x4] Mask of "pause_on" [1] for all queues */ 439 uint32_t q_pause_1; 440 /* [0x8] Mask of "pause_on" [2] for all queues */ 441 uint32_t q_pause_2; 442 /* [0xc] Mask of "pause_on" [3] for all queues */ 443 uint32_t q_pause_3; 444 /* [0x10] Mask of "pause_on" [4] for all queues */ 445 uint32_t q_pause_4; 446 /* [0x14] Mask of "pause_on" [5] for all queues */ 447 uint32_t q_pause_5; 448 /* [0x18] Mask of "pause_on" [6] for all queues */ 449 uint32_t q_pause_6; 450 /* [0x1c] Mask of "pause_on" [7] for all queues */ 451 uint32_t q_pause_7; 452 /* [0x20] Mask of external GPIO input pause [0] for all queue ... */ 453 uint32_t q_gpio_0; 454 /* [0x24] Mask of external GPIO input pause [1] for all queue ... */ 455 uint32_t q_gpio_1; 456 /* [0x28] Mask of external GPIO input pause [2] for all queue ... */ 457 uint32_t q_gpio_2; 458 /* [0x2c] Mask of external GPIO input pause [3] for all queue ... */ 459 uint32_t q_gpio_3; 460 /* [0x30] Mask of external GPIO input [4] for all queues */ 461 uint32_t q_gpio_4; 462 /* [0x34] Mask of external GPIO input [5] for all queues */ 463 uint32_t q_gpio_5; 464 /* [0x38] Mask of external GPIO input [6] for all queues */ 465 uint32_t q_gpio_6; 466 /* [0x3c] Mask of external GPIO input [7] for all queues */ 467 uint32_t q_gpio_7; 468 /* [0x40] Mask of "pause_on" [7:0] for the UDMA stream inter ... */ 469 uint32_t s_pause; 470 /* [0x44] Mask of Rx Almost Full indication for generating XO ... */ 471 uint32_t q_xoff_0; 472 /* [0x48] Mask of Rx Almost Full indication for generating XO ... */ 473 uint32_t q_xoff_1; 474 /* [0x4c] Mask of Rx Almost Full indication for generating XO ... */ 475 uint32_t q_xoff_2; 476 /* [0x50] Mask of Rx Almost Full indication for generating XO ... */ 477 uint32_t q_xoff_3; 478 /* [0x54] Mask of Rx Almost Full indication for generating XO ... */ 479 uint32_t q_xoff_4; 480 /* [0x58] Mask of Rx Almost Full indication for generating XO ... */ 481 uint32_t q_xoff_5; 482 /* [0x5c] Mask of Rx Almost Full indication for generating XO ... */ 483 uint32_t q_xoff_6; 484 /* [0x60] Mask of Rx Almost Full indication for generating XO ... */ 485 uint32_t q_xoff_7; 486 uint32_t rsrvd[7]; 487 }; 488 struct al_ec_tpg_rpa_res { 489 /* [0x0] NOT used */ 490 uint32_t not_used; 491 uint32_t rsrvd[63]; 492 }; 493 struct al_ec_eee { 494 /* [0x0] EEE configuration */ 495 uint32_t cfg_e; 496 /* [0x4] Number of clocks to get into EEE mode. */ 497 uint32_t pre_cnt; 498 /* [0x8] Number of clocks to stop MAC EEE mode after getting ... */ 499 uint32_t post_cnt; 500 /* [0xc] Number of clocks to stop the Tx MAC interface after ... */ 501 uint32_t stop_cnt; 502 /* [0x10] EEE status */ 503 uint32_t stat_eee; 504 uint32_t rsrvd[59]; 505 }; 506 struct al_ec_stat { 507 /* [0x0] Rx Frequency adjust FIFO input packets */ 508 uint32_t faf_in_rx_pkt; 509 /* [0x4] Rx Frequency adjust FIFO input short error packets */ 510 uint32_t faf_in_rx_short; 511 /* [0x8] Rx Frequency adjust FIFO input long error packets */ 512 uint32_t faf_in_rx_long; 513 /* [0xc] Rx Frequency adjust FIFO output packets */ 514 uint32_t faf_out_rx_pkt; 515 /* [0x10] Rx Frequency adjust FIFO output short error packets ... */ 516 uint32_t faf_out_rx_short; 517 /* [0x14] Rx Frequency adjust FIFO output long error packets */ 518 uint32_t faf_out_rx_long; 519 /* [0x18] Rx Frequency adjust FIFO output drop packets */ 520 uint32_t faf_out_drop; 521 /* [0x1c] Number of packets written into the Rx FIFO (without ... */ 522 uint32_t rxf_in_rx_pkt; 523 /* [0x20] Number of error packets written into the Rx FIFO (w ... */ 524 uint32_t rxf_in_fifo_err; 525 /* [0x24] Number of packets written into the loopback FIFO (w ... */ 526 uint32_t lbf_in_rx_pkt; 527 /* [0x28] Number of error packets written into the loopback F ... */ 528 uint32_t lbf_in_fifo_err; 529 /* [0x2c] Number of packets read from Rx FIFO 1 */ 530 uint32_t rxf_out_rx_1_pkt; 531 /* [0x30] Number of packets read from Rx FIFO 2 (loopback FIF ... */ 532 uint32_t rxf_out_rx_2_pkt; 533 /* [0x34] Rx FIFO output drop packets from FIFO 1 */ 534 uint32_t rxf_out_drop_1_pkt; 535 /* [0x38] Rx FIFO output drop packets from FIFO 2 (loopback) */ 536 uint32_t rxf_out_drop_2_pkt; 537 /* [0x3c] Rx Parser 1, input packet counter */ 538 uint32_t rpe_1_in_rx_pkt; 539 /* [0x40] Rx Parser 1, output packet counter */ 540 uint32_t rpe_1_out_rx_pkt; 541 /* [0x44] Rx Parser 2, input packet counter */ 542 uint32_t rpe_2_in_rx_pkt; 543 /* [0x48] Rx Parser 2, output packet counter */ 544 uint32_t rpe_2_out_rx_pkt; 545 /* [0x4c] Rx Parser 3 (MACsec), input packet counter */ 546 uint32_t rpe_3_in_rx_pkt; 547 /* [0x50] Rx Parser 3 (MACsec), output packet counter */ 548 uint32_t rpe_3_out_rx_pkt; 549 /* [0x54] Tx parser, input packet counter */ 550 uint32_t tpe_in_tx_pkt; 551 /* [0x58] Tx parser, output packet counter */ 552 uint32_t tpe_out_tx_pkt; 553 /* [0x5c] Tx packet modification, input packet counter */ 554 uint32_t tpm_tx_pkt; 555 /* [0x60] Tx forwarding input packet counter */ 556 uint32_t tfw_in_tx_pkt; 557 /* [0x64] Tx forwarding input packet counter */ 558 uint32_t tfw_out_tx_pkt; 559 /* [0x68] Rx forwarding input packet counter */ 560 uint32_t rfw_in_rx_pkt; 561 /* [0x6c] Rx Forwarding, packet with VLAN command drop indica ... */ 562 uint32_t rfw_in_vlan_drop; 563 /* [0x70] Rx Forwarding, packets with parse drop indication */ 564 uint32_t rfw_in_parse_drop; 565 /* [0x74] Rx Forwarding, multicast packets */ 566 uint32_t rfw_in_mc; 567 /* [0x78] Rx Forwarding, broadcast packets */ 568 uint32_t rfw_in_bc; 569 /* [0x7c] Rx Forwarding, tagged packets */ 570 uint32_t rfw_in_vlan_exist; 571 /* [0x80] Rx Forwarding, untagged packets */ 572 uint32_t rfw_in_vlan_nexist; 573 /* [0x84] Rx Forwarding, packets with MAC address drop indica ... */ 574 uint32_t rfw_in_mac_drop; 575 /* [0x88] Rx Forwarding, packets with undetected MAC address */ 576 uint32_t rfw_in_mac_ndet_drop; 577 /* [0x8c] Rx Forwarding, packets with drop indication from th ... */ 578 uint32_t rfw_in_ctrl_drop; 579 /* [0x90] Rx Forwarding, packets with L3_protocol_index drop ... */ 580 uint32_t rfw_in_prot_i_drop; 581 /* [0x94] EEE, number of times the system went into EEE state ... */ 582 uint32_t eee_in; 583 uint32_t rsrvd[90]; 584 }; 585 struct al_ec_stat_udma { 586 /* [0x0] Rx forwarding output packet counter */ 587 uint32_t rfw_out_rx_pkt; 588 /* [0x4] Rx forwarding output drop packet counter */ 589 uint32_t rfw_out_drop; 590 /* [0x8] Multi-stream write, number of Rx packets */ 591 uint32_t msw_in_rx_pkt; 592 /* [0xc] Multi-stream write, number of dropped packets at SO ... */ 593 uint32_t msw_drop_q_full; 594 /* [0x10] Multi-stream write, number of dropped packets at SO ... */ 595 uint32_t msw_drop_sop; 596 /* [0x14] Multi-stream write, number of dropped packets at EO ... */ 597 uint32_t msw_drop_eop; 598 /* [0x18] Multi-stream write, number of packets written to th ... */ 599 uint32_t msw_wr_eop; 600 /* [0x1c] Multi-stream write, number of packets read from the ... */ 601 uint32_t msw_out_rx_pkt; 602 /* [0x20] Number of transmitted packets without TSO enabled */ 603 uint32_t tso_no_tso_pkt; 604 /* [0x24] Number of transmitted packets with TSO enabled */ 605 uint32_t tso_tso_pkt; 606 /* [0x28] Number of TSO segments that were generated */ 607 uint32_t tso_seg_pkt; 608 /* [0x2c] Number of TSO segments that required padding */ 609 uint32_t tso_pad_pkt; 610 /* [0x30] Tx Packet modification, MAC SA spoof error */ 611 uint32_t tpm_tx_spoof; 612 /* [0x34] Tx MAC interface, input packet counter */ 613 uint32_t tmi_in_tx_pkt; 614 /* [0x38] Tx MAC interface, number of packets forwarded to th ... */ 615 uint32_t tmi_out_to_mac; 616 /* [0x3c] Tx MAC interface, number of packets forwarded to th ... */ 617 uint32_t tmi_out_to_rx; 618 /* [0x40] Tx MAC interface, number of transmitted bytes */ 619 uint32_t tx_q0_bytes; 620 /* [0x44] Tx MAC interface, number of transmitted bytes */ 621 uint32_t tx_q1_bytes; 622 /* [0x48] Tx MAC interface, number of transmitted bytes */ 623 uint32_t tx_q2_bytes; 624 /* [0x4c] Tx MAC interface, number of transmitted bytes */ 625 uint32_t tx_q3_bytes; 626 /* [0x50] Tx MAC interface, number of transmitted packets */ 627 uint32_t tx_q0_pkts; 628 /* [0x54] Tx MAC interface, number of transmitted packets */ 629 uint32_t tx_q1_pkts; 630 /* [0x58] Tx MAC interface, number of transmitted packets */ 631 uint32_t tx_q2_pkts; 632 /* [0x5c] Tx MAC interface, number of transmitted packets */ 633 uint32_t tx_q3_pkts; 634 uint32_t rsrvd[40]; 635 }; 636 struct al_ec_msp { 637 /* [0x0] Ethernet parsing engine configuration 1 */ 638 uint32_t p_parse_cfg; 639 /* [0x4] Protocol index action table address */ 640 uint32_t p_act_table_addr; 641 /* [0x8] Protocol index action table data */ 642 uint32_t p_act_table_data_1; 643 /* [0xc] Protocol index action table data */ 644 uint32_t p_act_table_data_2; 645 /* [0x10] Protocol index action table data */ 646 uint32_t p_act_table_data_3; 647 /* [0x14] Protocol index action table data */ 648 uint32_t p_act_table_data_4; 649 /* [0x18] Protocol index action table data */ 650 uint32_t p_act_table_data_5; 651 /* [0x1c] Protocol index action table data */ 652 uint32_t p_act_table_data_6; 653 /* [0x20] Input result vector, default values for parser inpu ... */ 654 uint32_t p_res_def; 655 /* [0x24] Result input vector selection */ 656 uint32_t p_res_in; 657 uint32_t rsrvd[6]; 658 }; 659 struct al_ec_msp_p { 660 /* [0x0] Header length, support for header length table for ... */ 661 uint32_t h_hdr_len; 662 }; 663 struct al_ec_msp_c { 664 /* [0x0] Data for comparison */ 665 uint32_t p_comp_data; 666 /* [0x4] Mask for comparison */ 667 uint32_t p_comp_mask; 668 /* [0x8] Compare control */ 669 uint32_t p_comp_ctrl; 670 uint32_t rsrvd[4]; 671 }; 672 struct al_ec_wol { 673 /* [0x0] WoL enable configuration,Packet forwarding and inte ... */ 674 uint32_t wol_en; 675 /* [0x4] Password for magic_password packet detection - bits ... */ 676 uint32_t magic_pswd_l; 677 /* [0x8] Password for magic+password packet detection - 47: ... */ 678 uint32_t magic_pswd_h; 679 /* [0xc] Configured L3 Destination IP address for WoL IPv6 p ... */ 680 uint32_t ipv6_dip_word0; 681 /* [0x10] Configured L3 Destination IP address for WoL IPv6 p ... */ 682 uint32_t ipv6_dip_word1; 683 /* [0x14] Configured L3 Destination IP address for WoL IPv6 p ... */ 684 uint32_t ipv6_dip_word2; 685 /* [0x18] Configured L3 Destination IP address for WoL IPv6 p ... */ 686 uint32_t ipv6_dip_word3; 687 /* [0x1c] Configured L3 Destination IP address for WoL IPv4 p ... */ 688 uint32_t ipv4_dip; 689 /* [0x20] Configured EtherType for WoL EtherType_da/EtherType ... */ 690 uint32_t ethertype; 691 uint32_t rsrvd[7]; 692 }; 693 struct al_ec_pth { 694 /* [0x0] System time counter (Time of Day) */ 695 uint32_t system_time_seconds; 696 /* [0x4] System time subseconds in a second (MSBs) */ 697 uint32_t system_time_subseconds_msb; 698 /* [0x8] System time subseconds in a second (LSBs) */ 699 uint32_t system_time_subseconds_lsb; 700 /* [0xc] Clock period in femtoseconds (MSB) */ 701 uint32_t clock_period_msb; 702 /* [0x10] Clock period in femtoseconds (LSB) */ 703 uint32_t clock_period_lsb; 704 /* [0x14] Control register for internal updates to the system ... */ 705 uint32_t int_update_ctrl; 706 /* [0x18] Value to update system_time_seconds with */ 707 uint32_t int_update_seconds; 708 /* [0x1c] Value to update system_time_subseconds_msb with */ 709 uint32_t int_update_subseconds_msb; 710 /* [0x20] Value to update system_time_subseconds_lsb with */ 711 uint32_t int_update_subseconds_lsb; 712 /* [0x24] Control register for external updates to the system ... */ 713 uint32_t ext_update_ctrl; 714 /* [0x28] Value to update system_time_seconds with */ 715 uint32_t ext_update_seconds; 716 /* [0x2c] Value to update system_time_subseconds_msb with */ 717 uint32_t ext_update_subseconds_msb; 718 /* [0x30] Value to update system_time_subseconds_lsb with */ 719 uint32_t ext_update_subseconds_lsb; 720 /* [0x34] This value represents the APB transaction delay fro ... */ 721 uint32_t read_compensation_subseconds_msb; 722 /* [0x38] This value represents the APB transaction delay fro ... */ 723 uint32_t read_compensation_subseconds_lsb; 724 /* [0x3c] This value is used for two purposes:1 */ 725 uint32_t int_write_compensation_subseconds_msb; 726 /* [0x40] This value is used for two purposes:1 */ 727 uint32_t int_write_compensation_subseconds_lsb; 728 /* [0x44] This value represents the number of cycles it for a ... */ 729 uint32_t ext_write_compensation_subseconds_msb; 730 /* [0x48] This value represents the number of cycles it for a ... */ 731 uint32_t ext_write_compensation_subseconds_lsb; 732 /* [0x4c] Value to be added to system_time before transferrin ... */ 733 uint32_t sync_compensation_subseconds_msb; 734 /* [0x50] Value to be added to system_time before transferrin ... */ 735 uint32_t sync_compensation_subseconds_lsb; 736 uint32_t rsrvd[11]; 737 }; 738 struct al_ec_pth_egress { 739 /* [0x0] Control register for egress trigger #k */ 740 uint32_t trigger_ctrl; 741 /* [0x4] threshold for next egress trigger (#k) - secondsWri ... */ 742 uint32_t trigger_seconds; 743 /* [0x8] Threshold for next egress trigger (#k) - subseconds ... */ 744 uint32_t trigger_subseconds_msb; 745 /* [0xc] threshold for next egress trigger (#k) - subseconds ... */ 746 uint32_t trigger_subseconds_lsb; 747 /* [0x10] External output pulse width (subseconds_msb)(Atomic ... */ 748 uint32_t pulse_width_subseconds_msb; 749 /* [0x14] External output pulse width (subseconds_lsb)(Atomic ... */ 750 uint32_t pulse_width_subseconds_lsb; 751 uint32_t rsrvd[2]; 752 }; 753 struct al_ec_pth_db { 754 /* [0x0] timestamp[k], in resolution of 2^18 femtosec =~ 0 */ 755 uint32_t ts; 756 /* [0x4] Timestamp entry is valid */ 757 uint32_t qual; 758 uint32_t rsrvd[4]; 759 }; 760 struct al_ec_gen_v3 { 761 /* [0x0] Bypass enable */ 762 uint32_t bypass; 763 /* [0x4] Rx Completion descriptor */ 764 uint32_t rx_comp_desc; 765 /* [0x8] general configuration */ 766 uint32_t conf; 767 uint32_t rsrvd[13]; 768 }; 769 struct al_ec_tfw_v3 { 770 /* [0x0] Generic protocol detect Cam compare table address */ 771 uint32_t tx_gpd_cam_addr; 772 /* [0x4] Tx Generic protocol detect Cam compare data_1 (low) ... */ 773 uint32_t tx_gpd_cam_data_1; 774 /* [0x8] Tx Generic protocol detect Cam compare data_2 (high ... */ 775 uint32_t tx_gpd_cam_data_2; 776 /* [0xc] Tx Generic protocol detect Cam compare mask_1 (low) ... */ 777 uint32_t tx_gpd_cam_mask_1; 778 /* [0x10] Tx Generic protocol detect Cam compare mask_1 (high ... */ 779 uint32_t tx_gpd_cam_mask_2; 780 /* [0x14] Tx Generic protocol detect Cam compare control */ 781 uint32_t tx_gpd_cam_ctrl; 782 /* [0x18] Tx Generic crc parameters legacy */ 783 uint32_t tx_gcp_legacy; 784 /* [0x1c] Tx Generic crc prameters table address */ 785 uint32_t tx_gcp_table_addr; 786 /* [0x20] Tx Generic crc prameters table general */ 787 uint32_t tx_gcp_table_gen; 788 /* [0x24] Tx Generic crc parametrs tabel mask word 1 */ 789 uint32_t tx_gcp_table_mask_1; 790 /* [0x28] Tx Generic crc parametrs tabel mask word 2 */ 791 uint32_t tx_gcp_table_mask_2; 792 /* [0x2c] Tx Generic crc parametrs tabel mask word 3 */ 793 uint32_t tx_gcp_table_mask_3; 794 /* [0x30] Tx Generic crc parametrs tabel mask word 4 */ 795 uint32_t tx_gcp_table_mask_4; 796 /* [0x34] Tx Generic crc parametrs tabel mask word 5 */ 797 uint32_t tx_gcp_table_mask_5; 798 /* [0x38] Tx Generic crc parametrs tabel mask word 6 */ 799 uint32_t tx_gcp_table_mask_6; 800 /* [0x3c] Tx Generic crc parametrs tabel crc init */ 801 uint32_t tx_gcp_table_crc_init; 802 /* [0x40] Tx Generic crc parametrs tabel result configuration ... */ 803 uint32_t tx_gcp_table_res; 804 /* [0x44] Tx Generic crc parameters table alu opcode */ 805 uint32_t tx_gcp_table_alu_opcode; 806 /* [0x48] Tx Generic crc parameters table alu opsel */ 807 uint32_t tx_gcp_table_alu_opsel; 808 /* [0x4c] Tx Generic crc parameters table alu constant value */ 809 uint32_t tx_gcp_table_alu_val; 810 /* [0x50] Tx CRC/Checksum replace */ 811 uint32_t crc_csum_replace; 812 /* [0x54] CRC/Checksum replace table address */ 813 uint32_t crc_csum_replace_table_addr; 814 /* [0x58] CRC/Checksum replace table */ 815 uint32_t crc_csum_replace_table; 816 uint32_t rsrvd[9]; 817 }; 818 819 struct al_ec_rfw_v3 { 820 /* [0x0] Rx Generic protocol detect Cam compare table addres ... */ 821 uint32_t rx_gpd_cam_addr; 822 /* [0x4] Rx Generic protocol detect Cam compare data_1 (low) ... */ 823 uint32_t rx_gpd_cam_data_1; 824 /* [0x8] Rx Generic protocol detect Cam compare data_2 (high ... */ 825 uint32_t rx_gpd_cam_data_2; 826 /* [0xc] Rx Generic protocol detect Cam compare mask_1 (low) ... */ 827 uint32_t rx_gpd_cam_mask_1; 828 /* [0x10] Rx Generic protocol detect Cam compare mask_1 (high ... */ 829 uint32_t rx_gpd_cam_mask_2; 830 /* [0x14] Rx Generic protocol detect Cam compare control */ 831 uint32_t rx_gpd_cam_ctrl; 832 /* [0x18] Generic protocol detect Parser result vector pointe ... */ 833 uint32_t gpd_p1; 834 /* [0x1c] Generic protocol detect Parser result vector pointe ... */ 835 uint32_t gpd_p2; 836 /* [0x20] Generic protocol detect Parser result vector pointe ... */ 837 uint32_t gpd_p3; 838 /* [0x24] Generic protocol detect Parser result vector pointe ... */ 839 uint32_t gpd_p4; 840 /* [0x28] Generic protocol detect Parser result vector pointe ... */ 841 uint32_t gpd_p5; 842 /* [0x2c] Generic protocol detect Parser result vector pointe ... */ 843 uint32_t gpd_p6; 844 /* [0x30] Generic protocol detect Parser result vector pointe ... */ 845 uint32_t gpd_p7; 846 /* [0x34] Generic protocol detect Parser result vector pointe ... */ 847 uint32_t gpd_p8; 848 /* [0x38] Rx Generic crc parameters legacy */ 849 uint32_t rx_gcp_legacy; 850 /* [0x3c] Rx Generic crc prameters table address */ 851 uint32_t rx_gcp_table_addr; 852 /* [0x40] Rx Generic crc prameters table general */ 853 uint32_t rx_gcp_table_gen; 854 /* [0x44] Rx Generic crc parametrs tabel mask word 1 */ 855 uint32_t rx_gcp_table_mask_1; 856 /* [0x48] Rx Generic crc parametrs tabel mask word 2 */ 857 uint32_t rx_gcp_table_mask_2; 858 /* [0x4c] Rx Generic crc parametrs tabel mask word 3 */ 859 uint32_t rx_gcp_table_mask_3; 860 /* [0x50] Rx Generic crc parametrs tabel mask word 4 */ 861 uint32_t rx_gcp_table_mask_4; 862 /* [0x54] Rx Generic crc parametrs tabel mask word 5 */ 863 uint32_t rx_gcp_table_mask_5; 864 /* [0x58] Rx Generic crc parametrs tabel mask word 6 */ 865 uint32_t rx_gcp_table_mask_6; 866 /* [0x5c] Rx Generic crc parametrs tabel crc init */ 867 uint32_t rx_gcp_table_crc_init; 868 /* [0x60] Rx Generic crc parametrs tabel result configuration ... */ 869 uint32_t rx_gcp_table_res; 870 /* [0x64] Rx Generic crc parameters table alu opcode */ 871 uint32_t rx_gcp_table_alu_opcode; 872 /* [0x68] Rx Generic crc parameters table alu opsel */ 873 uint32_t rx_gcp_table_alu_opsel; 874 /* [0x6c] Rx Generic crc parameters table alu constant value ... */ 875 uint32_t rx_gcp_table_alu_val; 876 /* [0x70] Generic crc engin parameters alu Parser result vect ... */ 877 uint32_t rx_gcp_alu_p1; 878 /* [0x74] Generic crc engine parameters alu Parser result vec ... */ 879 uint32_t rx_gcp_alu_p2; 880 /* [0x78] Header split control table address */ 881 uint32_t hs_ctrl_table_addr; 882 /* [0x7c] Header split control table */ 883 uint32_t hs_ctrl_table; 884 /* [0x80] Header split control alu opcode */ 885 uint32_t hs_ctrl_table_alu_opcode; 886 /* [0x84] Header split control alu opsel */ 887 uint32_t hs_ctrl_table_alu_opsel; 888 /* [0x88] Header split control alu constant value */ 889 uint32_t hs_ctrl_table_alu_val; 890 /* [0x8c] Header split control configuration */ 891 uint32_t hs_ctrl_cfg; 892 /* [0x90] Header split control alu Parser result vector point ... */ 893 uint32_t hs_ctrl_alu_p1; 894 /* [0x94] Header split control alu Parser result vector point ... */ 895 uint32_t hs_ctrl_alu_p2; 896 uint32_t rsrvd[26]; 897 }; 898 struct al_ec_crypto { 899 /* [0x0] Tx inline crypto configuration */ 900 uint32_t tx_config; 901 /* [0x4] Rx inline crypto configuration */ 902 uint32_t rx_config; 903 /* [0x8] reserved FFU */ 904 uint32_t tx_override; 905 /* [0xc] reserved FFU */ 906 uint32_t rx_override; 907 /* [0x10] inline XTS alpha [31:0] */ 908 uint32_t xts_alpha_1; 909 /* [0x14] inline XTS alpha [63:32] */ 910 uint32_t xts_alpha_2; 911 /* [0x18] inline XTS alpha [95:64] */ 912 uint32_t xts_alpha_3; 913 /* [0x1c] inline XTS alpha [127:96] */ 914 uint32_t xts_alpha_4; 915 /* [0x20] inline XTS sector ID increment [31:0] */ 916 uint32_t xts_sector_id_1; 917 /* [0x24] inline XTS sector ID increment [63:32] */ 918 uint32_t xts_sector_id_2; 919 /* [0x28] inline XTS sector ID increment [95:64] */ 920 uint32_t xts_sector_id_3; 921 /* [0x2c] inline XTS sector ID increment [127:96] */ 922 uint32_t xts_sector_id_4; 923 /* [0x30] IV formation configuration */ 924 uint32_t tx_enc_iv_construction; 925 /* [0x34] IV formation configuration */ 926 uint32_t rx_enc_iv_construction; 927 /* [0x38] IV formation configuration */ 928 uint32_t rx_enc_iv_map; 929 /* 930 [0x3c] effectively shorten shift-registers used for 931 eop-pkt-trim, in order to improve performance. 932 Each value must be built of consecutive 1's (bypassed regs), 933 and then consecutive 0's (non-bypassed regs) 934 */ 935 uint32_t tx_pkt_trim_len; 936 /* 937 [0x40] effectively shorten shift-registers used for 938 eop-pkt-trim, in order to improve performance. 939 Each value must be built of consecutive 1's (bypassed regs), 940 and then consecutive 0's (non-bypassed regs) 941 */ 942 uint32_t rx_pkt_trim_len; 943 /* [0x44] reserved FFU */ 944 uint32_t tx_reserved; 945 /* [0x48] reserved FFU */ 946 uint32_t rx_reserved; 947 uint32_t rsrvd[13]; 948 }; 949 struct al_ec_crypto_perf_cntr { 950 /* [0x0] */ 951 uint32_t total_tx_pkts; 952 /* [0x4] */ 953 uint32_t total_rx_pkts; 954 /* [0x8] */ 955 uint32_t total_tx_secured_pkts; 956 /* [0xc] */ 957 uint32_t total_rx_secured_pkts; 958 /* [0x10] */ 959 uint32_t total_tx_secured_pkts_cipher_mode; 960 /* [0x14] */ 961 uint32_t total_tx_secured_pkts_cipher_mode_cmpr; 962 /* [0x18] */ 963 uint32_t total_rx_secured_pkts_cipher_mode; 964 /* [0x1c] */ 965 uint32_t total_rx_secured_pkts_cipher_mode_cmpr; 966 /* [0x20] */ 967 uint32_t total_tx_secured_bytes_low; 968 /* [0x24] */ 969 uint32_t total_tx_secured_bytes_high; 970 /* [0x28] */ 971 uint32_t total_rx_secured_bytes_low; 972 /* [0x2c] */ 973 uint32_t total_rx_secured_bytes_high; 974 /* [0x30] */ 975 uint32_t total_tx_sign_calcs; 976 /* [0x34] */ 977 uint32_t total_rx_sign_calcs; 978 /* [0x38] */ 979 uint32_t total_tx_sign_errs; 980 /* [0x3c] */ 981 uint32_t total_rx_sign_errs; 982 }; 983 struct al_ec_crypto_tx_tid { 984 /* [0x0] tid_default_entry */ 985 uint32_t def_val; 986 }; 987 988 struct al_ec_regs { 989 uint32_t rsrvd_0[32]; 990 struct al_ec_gen gen; /* [0x80] */ 991 struct al_ec_mac mac; /* [0xc0] */ 992 struct al_ec_rxf rxf; /* [0x100] */ 993 struct al_ec_epe epe[2]; /* [0x180] */ 994 struct al_ec_epe_res epe_res; /* [0x200] */ 995 struct al_ec_epe_h epe_h[32]; /* [0x280] */ 996 struct al_ec_epe_p epe_p[32]; /* [0x300] */ 997 struct al_ec_epe_a epe_a[32]; /* [0x680] */ 998 struct al_ec_rfw rfw; /* [0x700] */ 999 struct al_ec_rfw_udma rfw_udma[4]; /* [0x7f0] */ 1000 struct al_ec_rfw_hash rfw_hash[10]; /* [0x800] */ 1001 struct al_ec_rfw_priority rfw_priority[8]; /* [0x828] */ 1002 struct al_ec_rfw_default rfw_default[8]; /* [0x848] */ 1003 struct al_ec_fwd_mac fwd_mac[32]; /* [0x868] */ 1004 struct al_ec_msw msw; /* [0xae8] */ 1005 struct al_ec_tso tso; /* [0xb00] */ 1006 struct al_ec_tso_sel tso_sel[8]; /* [0xb60] */ 1007 struct al_ec_tpe tpe; /* [0xb80] */ 1008 struct al_ec_tpm_udma tpm_udma[4]; /* [0xbc0] */ 1009 struct al_ec_tpm_sel tpm_sel[4]; /* [0xbf0] */ 1010 struct al_ec_tfw tfw; /* [0xc00] */ 1011 struct al_ec_tfw_udma tfw_udma[4]; /* [0xc60] */ 1012 struct al_ec_tmi tmi; /* [0xcc0] */ 1013 struct al_ec_efc efc; /* [0xcd0] */ 1014 struct al_ec_fc_udma fc_udma[4]; /* [0xd00] */ 1015 struct al_ec_tpg_rpa_res tpg_rpa_res; /* [0xf00] */ 1016 struct al_ec_eee eee; /* [0x1000] */ 1017 struct al_ec_stat stat; /* [0x1100] */ 1018 struct al_ec_stat_udma stat_udma[4]; /* [0x1300] */ 1019 struct al_ec_msp msp; /* [0x1700] */ 1020 struct al_ec_msp_p msp_p[32]; /* [0x1740] */ 1021 struct al_ec_msp_c msp_c[32]; /* [0x17c0] */ 1022 uint32_t rsrvd_1[16]; 1023 struct al_ec_wol wol; /* [0x1b80] */ 1024 uint32_t rsrvd_2[80]; 1025 struct al_ec_pth pth; /* [0x1d00] */ 1026 struct al_ec_pth_egress pth_egress[8]; /* [0x1d80] */ 1027 struct al_ec_pth_db pth_db[16]; /* [0x1e80] */ 1028 uint32_t rsrvd_3[416]; 1029 struct al_ec_gen_v3 gen_v3; /* [0x2680] */ 1030 struct al_ec_tfw_v3 tfw_v3; /* [0x26c0] */ 1031 struct al_ec_rfw_v3 rfw_v3; /* [0x2740] */ 1032 struct al_ec_crypto crypto; /* [0x2840] */ 1033 struct al_ec_crypto_perf_cntr crypto_perf_cntr[2]; /* [0x28c0] */ 1034 uint32_t rsrvd_4[48]; 1035 struct al_ec_crypto_tx_tid crypto_tx_tid[8]; /* [0x2a00] */ 1036 }; 1037 1038 1039 /* 1040 * Registers Fields 1041 */ 1042 1043 1044 /**** version register ****/ 1045 /* Revision number (Minor) */ 1046 #define EC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 1047 #define EC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 1048 /* Revision number (Major) */ 1049 #define EC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 1050 #define EC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 1051 /* Day of release */ 1052 #define EC_GEN_VERSION_DATE_DAY_MASK 0x001F0000 1053 #define EC_GEN_VERSION_DATE_DAY_SHIFT 16 1054 /* Month of release */ 1055 #define EC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 1056 #define EC_GEN_VERSION_DATA_MONTH_SHIFT 21 1057 /* Year of release (starting from 2000) */ 1058 #define EC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 1059 #define EC_GEN_VERSION_DATE_YEAR_SHIFT 25 1060 /* Reserved */ 1061 #define EC_GEN_VERSION_RESERVED_MASK 0xC0000000 1062 #define EC_GEN_VERSION_RESERVED_SHIFT 30 1063 1064 /**** en register ****/ 1065 /* Enable Frequency adjust FIFO input controller operation. */ 1066 #define EC_GEN_EN_FAF_IN (1 << 0) 1067 /* Enable Frequency adjust FIFO output controller operation. */ 1068 #define EC_GEN_EN_FAF_OUT (1 << 1) 1069 /* Enable Rx FIFO input controller 1 operation. */ 1070 #define EC_GEN_EN_RXF_IN (1 << 2) 1071 /* Enable Rx FIFO output controller operation. */ 1072 #define EC_GEN_EN_RXF_OUT (1 << 3) 1073 /* Enable Rx forwarding input controller operation. */ 1074 #define EC_GEN_EN_RFW_IN (1 << 4) 1075 /* Enable Rx forwarding output controller operation. */ 1076 #define EC_GEN_EN_RFW_OUT (1 << 5) 1077 /* Enable Rx multi-stream write controller operation. */ 1078 #define EC_GEN_EN_MSW_IN (1 << 6) 1079 /* Enable Rx first parsing engine output operation. */ 1080 #define EC_GEN_EN_RPE_1_OUT (1 << 7) 1081 /* Enable Rx first parsing engine input operation. */ 1082 #define EC_GEN_EN_RPE_1_IN (1 << 8) 1083 /* Enable Rx second parsing engine output operation. */ 1084 #define EC_GEN_EN_RPE_2_OUT (1 << 9) 1085 /* Enable Rx second parsing engine input operation. */ 1086 #define EC_GEN_EN_RPE_2_IN (1 << 10) 1087 /* Enable Rx MACsec parsing engine output operation. */ 1088 #define EC_GEN_EN_RPE_3_OUT (1 << 11) 1089 /* Enable Rx MACsec parsing engine input operation. */ 1090 #define EC_GEN_EN_RPE_3_IN (1 << 12) 1091 /* Enable Loopback FIFO input controller 1 operation. */ 1092 #define EC_GEN_EN_LBF_IN (1 << 13) 1093 /* Enable Rx packet analyzer operation. */ 1094 #define EC_GEN_EN_RPA (1 << 14) 1095 1096 #define EC_GEN_EN_RESERVED_15 (1 << 15) 1097 /* Enable Tx stream interface operation. */ 1098 #define EC_GEN_EN_TSO (1 << 16) 1099 /* Enable Tx parser input controller operation. */ 1100 #define EC_GEN_EN_TPE_IN (1 << 17) 1101 /* Enable Tx parser output controller operation. */ 1102 #define EC_GEN_EN_TPE_OUT (1 << 18) 1103 /* Enable Tx packet modification operation. */ 1104 #define EC_GEN_EN_TPM (1 << 19) 1105 /* Enable Tx forwarding input controller operation. */ 1106 #define EC_GEN_EN_TFW_IN (1 << 20) 1107 /* Enable Tx forwarding output controller operation. */ 1108 #define EC_GEN_EN_TFW_OUT (1 << 21) 1109 /* Enable Tx MAC interface controller operation. */ 1110 #define EC_GEN_EN_TMI (1 << 22) 1111 /* Enable Tx packet generator operation. */ 1112 #define EC_GEN_EN_TPG (1 << 23) 1113 1114 #define EC_GEN_EN_RESERVED_31_MASK 0xFF000000 1115 #define EC_GEN_EN_RESERVED_31_SHIFT 24 1116 1117 /**** fifo_en register ****/ 1118 /* Enable Frequency adjust FIFO operation (input). */ 1119 #define EC_GEN_FIFO_EN_FAF_IN (1 << 0) 1120 /* Enable Frequency adjust FIFO operation (output). */ 1121 #define EC_GEN_FIFO_EN_FAF_OUT (1 << 1) 1122 /* Enable Rx FIFO operation. */ 1123 #define EC_GEN_FIFO_EN_RX_FIFO (1 << 2) 1124 /* Enable Rx forwarding FIFO operation. */ 1125 #define EC_GEN_FIFO_EN_RFW_FIFO (1 << 3) 1126 /* Enable Rx multi-stream write FIFO operation */ 1127 #define EC_GEN_FIFO_EN_MSW_FIFO (1 << 4) 1128 /* Enable Rx first parser FIFO operation. */ 1129 #define EC_GEN_FIFO_EN_RPE_1_FIFO (1 << 5) 1130 /* Enable Rx second parser FIFO operation. */ 1131 #define EC_GEN_FIFO_EN_RPE_2_FIFO (1 << 6) 1132 /* Enable Rx MACsec parser FIFO operation. */ 1133 #define EC_GEN_FIFO_EN_RPE_3_FIFO (1 << 7) 1134 /* Enable Loopback FIFO operation. */ 1135 #define EC_GEN_FIFO_EN_LB_FIFO (1 << 8) 1136 1137 #define EC_GEN_FIFO_EN_RESERVED_15_9_MASK 0x0000FE00 1138 #define EC_GEN_FIFO_EN_RESERVED_15_9_SHIFT 9 1139 /* Enable Tx parser FIFO operation. */ 1140 #define EC_GEN_FIFO_EN_TPE_FIFO (1 << 16) 1141 /* Enable Tx forwarding FIFO operation. */ 1142 #define EC_GEN_FIFO_EN_TFW_FIFO (1 << 17) 1143 1144 #define EC_GEN_FIFO_EN_RESERVED_31_18_MASK 0xFFFC0000 1145 #define EC_GEN_FIFO_EN_RESERVED_31_18_SHIFT 18 1146 1147 /**** l2 register ****/ 1148 /* Size of a 802.3 Ethernet header (DA+SA) */ 1149 #define EC_GEN_L2_SIZE_802_3_MASK 0x0000003F 1150 #define EC_GEN_L2_SIZE_802_3_SHIFT 0 1151 /* Size of a 802.3 + MACsec 8 byte header */ 1152 #define EC_GEN_L2_SIZE_802_3_MS_8_MASK 0x00003F00 1153 #define EC_GEN_L2_SIZE_802_3_MS_8_SHIFT 8 1154 /* Offset of the L2 header from the beginning of the packet. */ 1155 #define EC_GEN_L2_OFFSET_MASK 0x7F000000 1156 #define EC_GEN_L2_OFFSET_SHIFT 24 1157 1158 /**** cfg_i register ****/ 1159 /* IPv4 protocol index */ 1160 #define EC_GEN_CFG_I_IPV4_INDEX_MASK 0x0000001F 1161 #define EC_GEN_CFG_I_IPV4_INDEX_SHIFT 0 1162 /* IPv6 protocol index */ 1163 #define EC_GEN_CFG_I_IPV6_INDEX_MASK 0x000003E0 1164 #define EC_GEN_CFG_I_IPV6_INDEX_SHIFT 5 1165 /* TCP protocol index */ 1166 #define EC_GEN_CFG_I_TCP_INDEX_MASK 0x00007C00 1167 #define EC_GEN_CFG_I_TCP_INDEX_SHIFT 10 1168 /* UDP protocol index */ 1169 #define EC_GEN_CFG_I_UDP_INDEX_MASK 0x000F8000 1170 #define EC_GEN_CFG_I_UDP_INDEX_SHIFT 15 1171 /* MACsec with 8 bytes SecTAG */ 1172 #define EC_GEN_CFG_I_MACSEC_8_INDEX_MASK 0x01F00000 1173 #define EC_GEN_CFG_I_MACSEC_8_INDEX_SHIFT 20 1174 /* MACsec with 16 bytes SecTAG */ 1175 #define EC_GEN_CFG_I_MACSEC_16_INDEX_MASK 0x3E000000 1176 #define EC_GEN_CFG_I_MACSEC_16_INDEX_SHIFT 25 1177 1178 /**** cfg_i_ext register ****/ 1179 /* FcoE protocol index */ 1180 #define EC_GEN_CFG_I_EXT_FCOE_INDEX_MASK 0x0000001F 1181 #define EC_GEN_CFG_I_EXT_FCOE_INDEX_SHIFT 0 1182 /* RoCE protocol index */ 1183 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_MASK 0x000003E0 1184 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_SHIFT 5 1185 /* RoCE protocol index */ 1186 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_MASK 0x00007C00 1187 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_SHIFT 10 1188 /* RoCE protocol index */ 1189 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_MASK 0x000F8000 1190 #define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_SHIFT 15 1191 1192 /**** en_ext register ****/ 1193 /* Enable Usage of Ethernet port memories for testing */ 1194 #define EC_GEN_EN_EXT_MEM_FOR_TEST_MASK 0x0000000F 1195 #define EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT 0 1196 #define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_EN \ 1197 (0xa << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT) 1198 #define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_DIS \ 1199 (0x0 << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT) 1200 /* Enable MAC loop back (Rx --> Tx, after MAC layer) for 802 */ 1201 #define EC_GEN_EN_EXT_MAC_LB (1 << 4) 1202 /* CRC forward value for the MAC Tx when working in loopback mod ... */ 1203 #define EC_GEN_EN_EXT_MAC_LB_CRC_FWD (1 << 5) 1204 /* Ready signal configuration when in loopback mode:00 - Ready f ... */ 1205 #define EC_GEN_EN_EXT_MAC_LB_READY_CFG_MASK 0x000000C0 1206 #define EC_GEN_EN_EXT_MAC_LB_READY_CFG_SHIFT 6 1207 /* Bypass the PTH completion update. */ 1208 #define EC_GEN_EN_EXT_PTH_COMPLETION_BYPASS (1 << 16) 1209 /* Selection between the 1G and 10G MAC: 1210 0 - 1G 1211 1 - 10G */ 1212 #define EC_GEN_EN_EXT_PTH_1_10_SEL (1 << 17) 1213 /* avoid timestamping every pkt in 1G */ 1214 #define EC_GEN_EN_EXT_PTH_CFG_1G_TIMESTAMP_OPT (1 << 18) 1215 /* Selection between descriptor caching options (WORD selection) ... */ 1216 #define EC_GEN_EN_EXT_CACHE_WORD_SPLIT (1 << 20) 1217 1218 /**** gen register ****/ 1219 /* Enable swap of input byte order */ 1220 #define EC_MAC_GEN_SWAP_IN_BYTE (1 << 0) 1221 1222 /**** min_pkt register ****/ 1223 /* Minimum packet size */ 1224 #define EC_MAC_MIN_PKT_SIZE_MASK 0x000FFFFF 1225 #define EC_MAC_MIN_PKT_SIZE_SHIFT 0 1226 1227 /**** max_pkt register ****/ 1228 /* Maximum packet size */ 1229 #define EC_MAC_MAX_PKT_SIZE_MASK 0x000FFFFF 1230 #define EC_MAC_MAX_PKT_SIZE_SHIFT 0 1231 1232 /**** cfg_1 register ****/ 1233 /* Drop packet at the ingress0 - Packets are not dropped at the ... */ 1234 #define EC_RXF_CFG_1_DROP_AT_INGRESS (1 << 0) 1235 /* Accept packet criteria at start of packet indication */ 1236 #define EC_RXF_CFG_1_SOP_ACCEPT (1 << 1) 1237 /* Select the arbiter between Rx packets and Tx packets (packets ... */ 1238 #define EC_RXF_CFG_1_ARB_SEL (1 << 2) 1239 /* Arbiter priority when strict priority is selected in arb_sel0 ... */ 1240 #define EC_RXF_CFG_1_ARB_P (1 << 3) 1241 /* Force loopback operation */ 1242 #define EC_RXF_CFG_1_FORCE_LB (1 << 4) 1243 /* Forwarding selection between Rx path and/or packet analyzer */ 1244 #define EC_RXF_CFG_1_FWD_SEL_MASK 0x00000300 1245 #define EC_RXF_CFG_1_FWD_SEL_SHIFT 8 1246 1247 /**** cfg_2 register ****/ 1248 /* FIFO USED threshold for accepting new packets, low threshold ... */ 1249 #define EC_RXF_CFG_2_FIFO_USED_TH_L_MASK 0x0000FFFF 1250 #define EC_RXF_CFG_2_FIFO_USED_TH_L_SHIFT 0 1251 /* FIFO USED threshold for accepting new packets, high threshold ... */ 1252 #define EC_RXF_CFG_2_FIFO_USED_TH_H_MASK 0xFFFF0000 1253 #define EC_RXF_CFG_2_FIFO_USED_TH_H_SHIFT 16 1254 1255 /**** rd_fifo register ****/ 1256 /* Minimum number of entries in the data FIFO to start reading p ... */ 1257 #define EC_RXF_RD_FIFO_TH_DATA_MASK 0x0000FFFF 1258 #define EC_RXF_RD_FIFO_TH_DATA_SHIFT 0 1259 /* Enable cut through operation */ 1260 #define EC_RXF_RD_FIFO_EN_CUT_TH (1 << 16) 1261 1262 /**** wr_fifo register ****/ 1263 1264 #define EC_RXF_WR_FIFO_TH_DATA_MASK 0x0000FFFF 1265 #define EC_RXF_WR_FIFO_TH_DATA_SHIFT 0 1266 1267 #define EC_RXF_WR_FIFO_TH_INFO_MASK 0xFFFF0000 1268 #define EC_RXF_WR_FIFO_TH_INFO_SHIFT 16 1269 1270 /**** lb_fifo register ****/ 1271 1272 #define EC_RXF_LB_FIFO_TH_DATA_MASK 0x0000FFFF 1273 #define EC_RXF_LB_FIFO_TH_DATA_SHIFT 0 1274 1275 #define EC_RXF_LB_FIFO_TH_INFO_MASK 0xFFFF0000 1276 #define EC_RXF_LB_FIFO_TH_INFO_SHIFT 16 1277 1278 /**** cfg_lb register ****/ 1279 /* FIFO USED threshold for accepting new packets */ 1280 #define EC_RXF_CFG_LB_FIFO_USED_TH_INT_MASK 0x0000FFFF 1281 #define EC_RXF_CFG_LB_FIFO_USED_TH_INT_SHIFT 0 1282 /* FIFO USED threshold for generating ready for the Tx path */ 1283 #define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_MASK 0xFFFF0000 1284 #define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_SHIFT 16 1285 1286 /**** out_drop register ****/ 1287 1288 #define EC_RXF_OUT_DROP_MAC_ERR (1 << 0) 1289 1290 #define EC_RXF_OUT_DROP_MAC_COL (1 << 1) 1291 1292 #define EC_RXF_OUT_DROP_MAC_DEC (1 << 2) 1293 1294 #define EC_RXF_OUT_DROP_MAC_LEN (1 << 3) 1295 1296 #define EC_RXF_OUT_DROP_MAC_PHY (1 << 4) 1297 1298 #define EC_RXF_OUT_DROP_MAC_FIFO (1 << 5) 1299 1300 #define EC_RXF_OUT_DROP_MAC_FCS (1 << 6) 1301 1302 #define EC_RXF_OUT_DROP_MAC_ETYPE (1 << 7) 1303 1304 #define EC_RXF_OUT_DROP_EC_LEN (1 << 8) 1305 1306 #define EC_RXF_OUT_DROP_EC_FIFO (1 << 9) 1307 1308 /**** parse_cfg register ****/ 1309 /* MAX number of beats for packet parsing */ 1310 #define EC_EPE_PARSE_CFG_MAX_BEATS_MASK 0x000000FF 1311 #define EC_EPE_PARSE_CFG_MAX_BEATS_SHIFT 0 1312 /* MAX number of parsing iterations for packet parsing */ 1313 #define EC_EPE_PARSE_CFG_MAX_ITER_MASK 0x0000FF00 1314 #define EC_EPE_PARSE_CFG_MAX_ITER_SHIFT 8 1315 1316 /**** act_table_addr register ****/ 1317 /* Address for accessing the table */ 1318 #define EC_EPE_ACT_TABLE_ADDR_VAL_MASK 0x0000001F 1319 #define EC_EPE_ACT_TABLE_ADDR_VAL_SHIFT 0 1320 1321 /**** act_table_data_1 register ****/ 1322 /* Table data[5:0] - Offset to next protocol [bytes][6] - Next p ... */ 1323 #define EC_EPE_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF 1324 #define EC_EPE_ACT_TABLE_DATA_1_VAL_SHIFT 0 1325 1326 /**** act_table_data_2 register ****/ 1327 /* Table Data [8:0] - Offset to data in the packet [bits][17:9] ... */ 1328 #define EC_EPE_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF 1329 #define EC_EPE_ACT_TABLE_DATA_2_VAL_SHIFT 0 1330 1331 /**** act_table_data_3 register ****/ 1332 /* Table Data [8:0] - Offset to data in the packet [bits] [17:9 ... */ 1333 #define EC_EPE_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF 1334 #define EC_EPE_ACT_TABLE_DATA_3_VAL_SHIFT 0 1335 1336 /**** act_table_data_4 register ****/ 1337 /* Table data[7:0] - Offset to header length location in the pac ... */ 1338 #define EC_EPE_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF 1339 #define EC_EPE_ACT_TABLE_DATA_4_VAL_SHIFT 0 1340 1341 /**** act_table_data_6 register ****/ 1342 /* Table data[0] - WR header length[10:1] - Write header length ... */ 1343 #define EC_EPE_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF 1344 #define EC_EPE_ACT_TABLE_DATA_6_VAL_SHIFT 0 1345 1346 /**** res_in register ****/ 1347 /* Selector for input parse_en0 - Input vector1 - Default value ... */ 1348 #define EC_EPE_RES_IN_SEL_PARSE_EN (1 << 0) 1349 /* Selector for input protocol_index 0 - Input vector 1 - Defaul ... */ 1350 #define EC_EPE_RES_IN_SEL_PROT_INDEX (1 << 1) 1351 /* Selector for input hdr_offset 0 - Input vector 1 - Default va ... */ 1352 #define EC_EPE_RES_IN_SEL_HDR_OFFSET (1 << 2) 1353 1354 /**** p1 register ****/ 1355 /* Location of the input protocol index in the parser result vec ... */ 1356 #define EC_EPE_RES_P1_IN_PROT_INDEX_MASK 0x000003FF 1357 #define EC_EPE_RES_P1_IN_PROT_INDEX_SHIFT 0 1358 1359 /**** p2 register ****/ 1360 /* Location of the input offset in the parser result vector */ 1361 #define EC_EPE_RES_P2_IN_OFFSET_MASK 0x000003FF 1362 #define EC_EPE_RES_P2_IN_OFFSET_SHIFT 0 1363 1364 /**** p3 register ****/ 1365 /* Location of the input parse enable in the parser result vecto ... */ 1366 #define EC_EPE_RES_P3_IN_PARSE_EN_MASK 0x000003FF 1367 #define EC_EPE_RES_P3_IN_PARSE_EN_SHIFT 0 1368 1369 /**** p4 register ****/ 1370 /* Location of the control bits in the parser result vector */ 1371 #define EC_EPE_RES_P4_CTRL_BITS_MASK 0x000003FF 1372 #define EC_EPE_RES_P4_CTRL_BITS_SHIFT 0 1373 1374 /**** p5 register ****/ 1375 /* Location of the MAC DA in the parser result vector */ 1376 #define EC_EPE_RES_P5_DA_MASK 0x000003FF 1377 #define EC_EPE_RES_P5_DA_SHIFT 0 1378 1379 /**** p6 register ****/ 1380 /* Location of the MAC SA in the parser result vector */ 1381 #define EC_EPE_RES_P6_SA_MASK 0x000003FF 1382 #define EC_EPE_RES_P6_SA_SHIFT 0 1383 1384 /**** p7 register ****/ 1385 /* Location of the first VLAN in the parser result vector */ 1386 #define EC_EPE_RES_P7_VLAN_1_MASK 0x000003FF 1387 #define EC_EPE_RES_P7_VLAN_1_SHIFT 0 1388 1389 /**** p8 register ****/ 1390 /* Location of the second VLAN in the parser result vector */ 1391 #define EC_EPE_RES_P8_VLAN_2_MASK 0x000003FF 1392 #define EC_EPE_RES_P8_VLAN_2_SHIFT 0 1393 1394 /**** p9 register ****/ 1395 /* Location of the L3 protocol index in the parser result vector ... */ 1396 #define EC_EPE_RES_P9_L3_PROT_INDEX_MASK 0x000003FF 1397 #define EC_EPE_RES_P9_L3_PROT_INDEX_SHIFT 0 1398 1399 /**** p10 register ****/ 1400 /* Location of the L3 offset in the parser result vector */ 1401 #define EC_EPE_RES_P10_L3_OFFSET_MASK 0x000003FF 1402 #define EC_EPE_RES_P10_L3_OFFSET_SHIFT 0 1403 1404 /**** p11 register ****/ 1405 /* Location of the L3 SIP in the parser result vector */ 1406 #define EC_EPE_RES_P11_L3_SIP_MASK 0x000003FF 1407 #define EC_EPE_RES_P11_L3_SIP_SHIFT 0 1408 1409 /**** p12 register ****/ 1410 /* Location of the L3 DIP in the parser result vector */ 1411 #define EC_EPE_RES_P12_L3_DIP_MASK 0x000003FF 1412 #define EC_EPE_RES_P12_L3_DIP_SHIFT 0 1413 1414 /**** p13 register ****/ 1415 /* Location of the L3 priority in the parser result vector */ 1416 #define EC_EPE_RES_P13_L3_PRIORITY_MASK 0x000003FF 1417 #define EC_EPE_RES_P13_L3_PRIORITY_SHIFT 0 1418 1419 /**** p14 register ****/ 1420 /* Location of the L3 header length in the parser result vector */ 1421 #define EC_EPE_RES_P14_L3_HDR_LEN_MASK 0x000003FF 1422 #define EC_EPE_RES_P14_L3_HDR_LEN_SHIFT 0 1423 1424 /**** p15 register ****/ 1425 /* Location of the L4 protocol index in the parser result vector ... */ 1426 #define EC_EPE_RES_P15_L4_PROT_INDEX_MASK 0x000003FF 1427 #define EC_EPE_RES_P15_L4_PROT_INDEX_SHIFT 0 1428 1429 /**** p16 register ****/ 1430 /* Location of the L4 source port in the parser result vector */ 1431 #define EC_EPE_RES_P16_L4_SRC_PORT_MASK 0x000003FF 1432 #define EC_EPE_RES_P16_L4_SRC_PORT_SHIFT 0 1433 1434 /**** p17 register ****/ 1435 /* Location of the L4 destination port in the parser result vect ... */ 1436 #define EC_EPE_RES_P17_L4_DST_PORT_MASK 0x000003FF 1437 #define EC_EPE_RES_P17_L4_DST_PORT_SHIFT 0 1438 1439 /**** p18 register ****/ 1440 /* Location of the L4 offset in the parser result vector */ 1441 #define EC_EPE_RES_P18_L4_OFFSET_MASK 0x000003FF 1442 #define EC_EPE_RES_P18_L4_OFFSET_SHIFT 0 1443 1444 /**** p19 register ****/ 1445 /* Location of the Ether type in the parser result vector when w ... */ 1446 #define EC_EPE_RES_P19_WOL_ETYPE_MASK 0x000003FF 1447 #define EC_EPE_RES_P19_WOL_ETYPE_SHIFT 0 1448 1449 /**** p20 register ****/ 1450 /* Location of the RoCE QP number field in the parser result vec ... */ 1451 #define EC_EPE_RES_P20_ROCE_QPN_MASK 0x000003FF 1452 #define EC_EPE_RES_P20_ROCE_QPN_SHIFT 0 1453 1454 /**** hdr_len register ****/ 1455 /* Value for selecting table 1 */ 1456 #define EC_EPE_H_HDR_LEN_TABLE_1_MASK 0x000000FF 1457 #define EC_EPE_H_HDR_LEN_TABLE_1_SHIFT 0 1458 /* Value for selecting table 2 */ 1459 #define EC_EPE_H_HDR_LEN_TABLE_2_MASK 0x00FF0000 1460 #define EC_EPE_H_HDR_LEN_TABLE_2_SHIFT 16 1461 1462 /**** comp_data register ****/ 1463 /* Data 1 for comparison */ 1464 #define EC_EPE_P_COMP_DATA_DATA_1_MASK 0x0000FFFF 1465 #define EC_EPE_P_COMP_DATA_DATA_1_SHIFT 0 1466 /* Data 2 for comparison 1467 [18:16] - Stage 1468 [24:19] - Branch ID */ 1469 #define EC_EPE_P_COMP_DATA_DATA_2_MASK 0x01FF0000 1470 #define EC_EPE_P_COMP_DATA_DATA_2_SHIFT 16 1471 1472 /**** comp_mask register ****/ 1473 /* Data 1 for comparison */ 1474 #define EC_EPE_P_COMP_MASK_DATA_1_MASK 0x0000FFFF 1475 #define EC_EPE_P_COMP_MASK_DATA_1_SHIFT 0 1476 /* Data 2 for comparison 1477 [18:16] - Stage 1478 [24:19] - Branch ID */ 1479 #define EC_EPE_P_COMP_MASK_DATA_2_MASK 0x01FF0000 1480 #define EC_EPE_P_COMP_MASK_DATA_2_SHIFT 16 1481 1482 /**** comp_ctrl register ****/ 1483 /* Output result value */ 1484 #define EC_EPE_P_COMP_CTRL_RES_MASK 0x0000001F 1485 #define EC_EPE_P_COMP_CTRL_RES_SHIFT 0 1486 /* Compare command for the data_1 field00 - Compare01 - <=10 - > ... */ 1487 #define EC_EPE_P_COMP_CTRL_CMD_1_MASK 0x00030000 1488 #define EC_EPE_P_COMP_CTRL_CMD_1_SHIFT 16 1489 /* Compare command for the data_2 field 00 - Compare 01 - <= 10 ... */ 1490 #define EC_EPE_P_COMP_CTRL_CMD_2_MASK 0x000C0000 1491 #define EC_EPE_P_COMP_CTRL_CMD_2_SHIFT 18 1492 /* Entry is valid */ 1493 #define EC_EPE_P_COMP_CTRL_VALID (1 << 31) 1494 1495 /**** prot_act register ****/ 1496 /* Drop indication for the selected protocol index */ 1497 #define EC_EPE_A_PROT_ACT_DROP (1 << 0) 1498 /* Mapping value Used when mapping the entire protocol index ran ... */ 1499 #define EC_EPE_A_PROT_ACT_MAP_MASK 0x00000F00 1500 #define EC_EPE_A_PROT_ACT_MAP_SHIFT 8 1501 1502 /**** thash_cfg_1 register ****/ 1503 /* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */ 1504 #define EC_RFW_THASH_CFG_1_OUT_SEL_MASK 0x00000007 1505 #define EC_RFW_THASH_CFG_1_OUT_SEL_SHIFT 0 1506 /* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */ 1507 #define EC_RFW_THASH_CFG_1_FUNC_SEL_MASK 0x00000300 1508 #define EC_RFW_THASH_CFG_1_FUNC_SEL_SHIFT 8 1509 /* Enable SIP/DIP swap if SIP<DIP */ 1510 #define EC_RFW_THASH_CFG_1_ENABLE_IP_SWAP (1 << 16) 1511 /* Enable PORT swap if SPORT<DPORT */ 1512 #define EC_RFW_THASH_CFG_1_ENABLE_PORT_SWAP (1 << 17) 1513 1514 /**** mhash_cfg_1 register ****/ 1515 /* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */ 1516 #define EC_RFW_MHASH_CFG_1_OUT_SEL_MASK 0x00000007 1517 #define EC_RFW_MHASH_CFG_1_OUT_SEL_SHIFT 0 1518 /* Selects the input to the MAC hash function0 - DA1 - DA + SA ... */ 1519 #define EC_RFW_MHASH_CFG_1_INPUT_SEL (1 << 4) 1520 /* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */ 1521 #define EC_RFW_MHASH_CFG_1_FUNC_SEL_MASK 0x00000300 1522 #define EC_RFW_MHASH_CFG_1_FUNC_SEL_SHIFT 8 1523 1524 /**** hdr_split register ****/ 1525 /* Default header length for header split */ 1526 #define EC_RFW_HDR_SPLIT_DEF_LEN_MASK 0x0000FFFF 1527 #define EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT 0 1528 /* Enable header split operation */ 1529 #define EC_RFW_HDR_SPLIT_EN (1 << 16) 1530 1531 /**** meta_err register ****/ 1532 /* Mask for error 1 in the Rx descriptor */ 1533 #define EC_RFW_META_ERR_MASK_1_MASK 0x000003FF 1534 #define EC_RFW_META_ERR_MASK_1_SHIFT 0 1535 /* Mask for error 2 in the Rx descriptor */ 1536 #define EC_RFW_META_ERR_MASK_2_MASK 0x03FF0000 1537 #define EC_RFW_META_ERR_MASK_2_SHIFT 16 1538 1539 /**** meta register ****/ 1540 /* Selection of the L3 offset source: 1 - Inner packet 0 - Outer ... */ 1541 #define EC_RFW_META_L3_LEN_SEL (1 << 0) 1542 /* Selection of the L3 offset source:1 - Inner packet0 - Outer p ... */ 1543 #define EC_RFW_META_L3_OFFSET_SEL (1 << 1) 1544 /* Selection of the l3 protocol index source: 1 - Inner packet 0 ... */ 1545 #define EC_RFW_META_L3_PROT_SEL (1 << 2) 1546 /* Selection of the l4 protocol index source: 1 - Inner packet ... */ 1547 #define EC_RFW_META_L4_PROT_SEL (1 << 3) 1548 /* Selects how to calculate the L3 header length when L3 is IpPv ... */ 1549 #define EC_RFW_META_L3_LEN_CALC (1 << 4) 1550 /* Selection of the IPv4 fragment indication source: 1 - Inner ... */ 1551 #define EC_RFW_META_FRAG_SEL (1 << 5) 1552 /* Selection of the L4 offset source:1 - Inner packet0 - Outer p ... */ 1553 #define EC_RFW_META_L4_OFFSET_SEL (1 << 6) 1554 1555 /**** filter register ****/ 1556 /* Filter undetected MAC DA */ 1557 #define EC_RFW_FILTER_UNDET_MAC (1 << 0) 1558 /* Filter specific MAC DA based on MAC table output. */ 1559 #define EC_RFW_FILTER_DET_MAC (1 << 1) 1560 /* Filter all tagged. */ 1561 #define EC_RFW_FILTER_TAGGED (1 << 2) 1562 /* Filter all untagged. */ 1563 #define EC_RFW_FILTER_UNTAGGED (1 << 3) 1564 /* Filter all broadcast. */ 1565 #define EC_RFW_FILTER_BC (1 << 4) 1566 /* Filter all multicast. */ 1567 #define EC_RFW_FILTER_MC (1 << 5) 1568 /* Filter based on parsing output (used to drop selected protoco ... */ 1569 #define EC_RFW_FILTER_PARSE (1 << 6) 1570 /* Filter packet based on VLAN table output. */ 1571 #define EC_RFW_FILTER_VLAN_VID (1 << 7) 1572 /* Filter packet based on control table output. */ 1573 #define EC_RFW_FILTER_CTRL_TABLE (1 << 8) 1574 /* Filter packet based on protocol index action register. */ 1575 #define EC_RFW_FILTER_PROT_INDEX (1 << 9) 1576 /* Filter packet based on WoL decision */ 1577 #define EC_RFW_FILTER_WOL (1 << 10) 1578 /* Override filter decision and forward to default UDMA/queue;dr ... */ 1579 #define EC_RFW_FILTER_OR_UNDET_MAC (1 << 16) 1580 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1581 #define EC_RFW_FILTER_OR_DET_MAC (1 << 17) 1582 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1583 #define EC_RFW_FILTER_OR_TAGGED (1 << 18) 1584 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1585 #define EC_RFW_FILTER_OR_UNTAGGED (1 << 19) 1586 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1587 #define EC_RFW_FILTER_OR_BC (1 << 20) 1588 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1589 #define EC_RFW_FILTER_OR_MC (1 << 21) 1590 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1591 #define EC_RFW_FILTER_OR_PARSE (1 << 22) 1592 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1593 #define EC_RFW_FILTER_OR_VLAN_VID (1 << 23) 1594 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1595 #define EC_RFW_FILTER_OR_CTRL_TABLE (1 << 24) 1596 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1597 #define EC_RFW_FILTER_OR_PROT_INDEX (1 << 25) 1598 /* Override filter decision and forward to default UDMA/queue;Dr ... */ 1599 #define EC_RFW_FILTER_OR_WOL (1 << 26) 1600 1601 /**** thash_table_addr register ****/ 1602 /* Address for accessing the table */ 1603 #define EC_RFW_THASH_TABLE_ADDR_VAL_MASK 0x000000FF 1604 #define EC_RFW_THASH_TABLE_ADDR_VAL_SHIFT 0 1605 1606 /**** thash_table_data register ****/ 1607 /* Table data (valid only after configuring the table address re ... */ 1608 #define EC_RFW_THASH_TABLE_DATA_VAL_MASK 0x00003FFF 1609 #define EC_RFW_THASH_TABLE_DATA_VAL_SHIFT 0 1610 1611 /**** mhash_table_addr register ****/ 1612 /* Address for accessing the table */ 1613 #define EC_RFW_MHASH_TABLE_ADDR_VAL_MASK 0x000000FF 1614 #define EC_RFW_MHASH_TABLE_ADDR_VAL_SHIFT 0 1615 1616 /**** mhash_table_data register ****/ 1617 /* Table data (valid only after configuring the table address re ... */ 1618 #define EC_RFW_MHASH_TABLE_DATA_VAL_MASK 0x0000003F 1619 #define EC_RFW_MHASH_TABLE_DATA_VAL_SHIFT 0 1620 1621 /**** vid_table_addr register ****/ 1622 /* Address for accessing the table */ 1623 #define EC_RFW_VID_TABLE_ADDR_VAL_MASK 0x00000FFF 1624 #define EC_RFW_VID_TABLE_ADDR_VAL_SHIFT 0 1625 1626 /**** vid_table_data register ****/ 1627 /* Table data (valid only after configuring the table address re ... */ 1628 #define EC_RFW_VID_TABLE_DATA_VAL_MASK 0x0000003F 1629 #define EC_RFW_VID_TABLE_DATA_VAL_SHIFT 0 1630 1631 /**** pbits_table_addr register ****/ 1632 /* Address for accessing the table */ 1633 #define EC_RFW_PBITS_TABLE_ADDR_VAL_MASK 0x00000007 1634 #define EC_RFW_PBITS_TABLE_ADDR_VAL_SHIFT 0 1635 1636 /**** pbits_table_data register ****/ 1637 /* VLAN P-bits to internal priority mapping */ 1638 #define EC_RFW_PBITS_TABLE_DATA_VAL_MASK 0x00000007 1639 #define EC_RFW_PBITS_TABLE_DATA_VAL_SHIFT 0 1640 1641 /**** dscp_table_addr register ****/ 1642 /* Address for accessing the table */ 1643 #define EC_RFW_DSCP_TABLE_ADDR_VAL_MASK 0x000000FF 1644 #define EC_RFW_DSCP_TABLE_ADDR_VAL_SHIFT 0 1645 1646 /**** dscp_table_data register ****/ 1647 /* IPv4 DSCP to internal priority mapping */ 1648 #define EC_RFW_DSCP_TABLE_DATA_VAL_MASK 0x00000007 1649 #define EC_RFW_DSCP_TABLE_DATA_VAL_SHIFT 0 1650 1651 /**** tc_table_addr register ****/ 1652 /* Address for accessing the table */ 1653 #define EC_RFW_TC_TABLE_ADDR_VAL_MASK 0x000000FF 1654 #define EC_RFW_TC_TABLE_ADDR_VAL_SHIFT 0 1655 1656 /**** tc_table_data register ****/ 1657 /* IPv6 TC to internal priority mapping */ 1658 #define EC_RFW_TC_TABLE_DATA_VAL_MASK 0x00000007 1659 #define EC_RFW_TC_TABLE_DATA_VAL_SHIFT 0 1660 1661 /**** ctrl_table_addr register ****/ 1662 /* Address for accessing the table[0] - VLAN table control out[1 ... */ 1663 #define EC_RFW_CTRL_TABLE_ADDR_VAL_MASK 0x000007FF 1664 #define EC_RFW_CTRL_TABLE_ADDR_VAL_SHIFT 0 1665 1666 /**** ctrl_table_data register ****/ 1667 /* Control table output for selecting the forwarding MUXs[3:0] - ... */ 1668 #define EC_RFW_CTRL_TABLE_DATA_VAL_MASK 0x000FFFFF 1669 #define EC_RFW_CTRL_TABLE_DATA_VAL_SHIFT 0 1670 1671 /**** out_cfg register ****/ 1672 /* Number of MetaData at the end of the packet1 - One MetaData b ... */ 1673 #define EC_RFW_OUT_CFG_META_CNT_MASK 0x00000003 1674 #define EC_RFW_OUT_CFG_META_CNT_SHIFT 0 1675 /* Enable packet drop */ 1676 #define EC_RFW_OUT_CFG_DROP_EN (1 << 2) 1677 /* Swap output byte order */ 1678 #define EC_RFW_OUT_CFG_SWAP_OUT_BYTE (1 << 3) 1679 /* Enable the insertion of the MACsec decoding result into the M ... */ 1680 #define EC_RFW_OUT_CFG_EN_MACSEC_DEC (1 << 4) 1681 /* Sample time of the time stamp:0 - SOP (for 10G MAC)1 - EOP (f ... */ 1682 #define EC_RFW_OUT_CFG_TIMESTAMP_SAMPLE (1 << 5) 1683 /* Determines which queue to write into the packet header0 - Ori ... */ 1684 #define EC_RFW_OUT_CFG_QUEUE_OR_SEL (1 << 6) 1685 /* Determines the logic of the drop indication:0 - Sample the dr ... */ 1686 #define EC_RFW_OUT_CFG_DROP_LOGIC_SEL (1 << 7) 1687 /* Determines the logic of the drop indication:0 - Sample the dr ... */ 1688 #define EC_RFW_OUT_CFG_PKT_TYPE_DEF (1 << 8) 1689 1690 /**** fsm_table_addr register ****/ 1691 /* Address for accessing the table :[2:0] - Outer header control ... */ 1692 #define EC_RFW_FSM_TABLE_ADDR_VAL_MASK 0x0000007F 1693 #define EC_RFW_FSM_TABLE_ADDR_VAL_SHIFT 0 1694 1695 /**** fsm_table_data register ****/ 1696 /* Flow steering mechanism output selectors:[1:0] - Input select ... */ 1697 #define EC_RFW_FSM_TABLE_DATA_VAL_MASK 0x00000007 1698 #define EC_RFW_FSM_TABLE_DATA_VAL_SHIFT 0 1699 1700 /**** ctrl_sel register ****/ 1701 /* Packet type (UC/MC/BC) for the control table */ 1702 #define EC_RFW_CTRL_SEL_PKT_TYPE (1 << 0) 1703 /* L3 protocol index for the control table */ 1704 #define EC_RFW_CTRL_SEL_L3_PROTOCOL (1 << 1) 1705 /* Selects the content and structure of the control table addres ... */ 1706 #define EC_RFW_CTRL_SEL_ADDR_MASK 0x0000000C 1707 #define EC_RFW_CTRL_SEL_ADDR_SHIFT 2 1708 1709 /**** default_vlan register ****/ 1710 /* Default VLAN data, used for untagged packets */ 1711 #define EC_RFW_DEFAULT_VLAN_DATA_MASK 0x0000FFFF 1712 #define EC_RFW_DEFAULT_VLAN_DATA_SHIFT 0 1713 1714 /**** default_hash register ****/ 1715 /* Default UDMA */ 1716 #define EC_RFW_DEFAULT_HASH_UDMA_MASK 0x0000000F 1717 #define EC_RFW_DEFAULT_HASH_UDMA_SHIFT 0 1718 /* Default queue */ 1719 #define EC_RFW_DEFAULT_HASH_QUEUE_MASK 0x00030000 1720 #define EC_RFW_DEFAULT_HASH_QUEUE_SHIFT 16 1721 1722 /**** default_or register ****/ 1723 /* Default UDMA */ 1724 #define EC_RFW_DEFAULT_OR_UDMA_MASK 0x0000000F 1725 #define EC_RFW_DEFAULT_OR_UDMA_SHIFT 0 1726 /* Default queue */ 1727 #define EC_RFW_DEFAULT_OR_QUEUE_MASK 0x00030000 1728 #define EC_RFW_DEFAULT_OR_QUEUE_SHIFT 16 1729 1730 /**** checksum register ****/ 1731 /* Check that the length in the UDP header matches the length in ... */ 1732 #define EC_RFW_CHECKSUM_UDP_LEN (1 << 0) 1733 /* Select the header that will be used for the checksum when a t ... */ 1734 #define EC_RFW_CHECKSUM_HDR_SEL (1 << 1) 1735 /* Enable L4 checksum when L3 fragmentation is detected */ 1736 #define EC_RFW_CHECKSUM_L4_FRAG_EN (1 << 2) 1737 /* L3 Checksum result selection for the Metadata descriptor0 - O ... */ 1738 #define EC_RFW_CHECKSUM_L3_CKS_SEL (1 << 4) 1739 /* L4 Checksum result selection for the Metadata descriptor0 - O ... */ 1740 #define EC_RFW_CHECKSUM_L4_CKS_SEL (1 << 5) 1741 1742 /**** lro_cfg_1 register ****/ 1743 /* Select the header that will be used for the LRO offload engin ... */ 1744 #define EC_RFW_LRO_CFG_1_HDR_SEL (1 << 0) 1745 /* Select the L2 header that will be used for the LRO offload en ... */ 1746 #define EC_RFW_LRO_CFG_1_HDR_L2_SEL (1 << 1) 1747 1748 /**** lro_check_ipv4 register ****/ 1749 /* Check version field. */ 1750 #define EC_RFW_LRO_CHECK_IPV4_VER (1 << 0) 1751 /* Check IHL field == 5. */ 1752 #define EC_RFW_LRO_CHECK_IPV4_IHL_0 (1 << 1) 1753 /* Check IHL field >= 5. */ 1754 #define EC_RFW_LRO_CHECK_IPV4_IHL_1 (1 << 2) 1755 /* Compare to previous packet. */ 1756 #define EC_RFW_LRO_CHECK_IPV4_IHL_2 (1 << 3) 1757 /* Compare DSCP to previous packet. */ 1758 #define EC_RFW_LRO_CHECK_IPV4_DSCP (1 << 4) 1759 /* Check that Total length >= lro_ipv4_tlen_val. */ 1760 #define EC_RFW_LRO_CHECK_IPV4_TLEN (1 << 5) 1761 /* Compare to previous packet value +1. */ 1762 #define EC_RFW_LRO_CHECK_IPV4_ID (1 << 6) 1763 /* Compare to lro_ipv4_flags_val with lro_ipv4_flags_mask_0. */ 1764 #define EC_RFW_LRO_CHECK_IPV4_FLAGS_0 (1 << 7) 1765 /* Compare to previous packet flags with lro_ipv4_flags_mask_1. */ 1766 #define EC_RFW_LRO_CHECK_IPV4_FLAGS_1 (1 << 8) 1767 /* Verify that the fragment offset field is 0. */ 1768 #define EC_RFW_LRO_CHECK_IPV4_FRAG (1 << 9) 1769 /* Verify that the TTL value >0. */ 1770 #define EC_RFW_LRO_CHECK_IPV4_TTL_0 (1 << 10) 1771 /* Compare TTL value to previous packet. */ 1772 #define EC_RFW_LRO_CHECK_IPV4_TTL_1 (1 << 11) 1773 /* Compare to previous packet protocol field. */ 1774 #define EC_RFW_LRO_CHECK_IPV4_PROT_0 (1 << 12) 1775 /* Verify that the protocol is TCP or UDP. */ 1776 #define EC_RFW_LRO_CHECK_IPV4_PROT_1 (1 << 13) 1777 /* Verify that the check sum is correct. */ 1778 #define EC_RFW_LRO_CHECK_IPV4_CHECKSUM (1 << 14) 1779 /* Compare SIP to previous packet. */ 1780 #define EC_RFW_LRO_CHECK_IPV4_SIP (1 << 15) 1781 /* Compare DIP to previous packet. */ 1782 #define EC_RFW_LRO_CHECK_IPV4_DIP (1 << 16) 1783 1784 /**** lro_ipv4 register ****/ 1785 /* Total length minimum value */ 1786 #define EC_RFW_LRO_IPV4_TLEN_VAL_MASK 0x0000FFFF 1787 #define EC_RFW_LRO_IPV4_TLEN_VAL_SHIFT 0 1788 /* Flags value */ 1789 #define EC_RFW_LRO_IPV4_FLAGS_VAL_MASK 0x00070000 1790 #define EC_RFW_LRO_IPV4_FLAGS_VAL_SHIFT 16 1791 /* Flags mask */ 1792 #define EC_RFW_LRO_IPV4_FLAGS_MASK_0_MASK 0x00380000 1793 #define EC_RFW_LRO_IPV4_FLAGS_MASK_0_SHIFT 19 1794 /* Flags mask */ 1795 #define EC_RFW_LRO_IPV4_FLAGS_MASK_1_MASK 0x01C00000 1796 #define EC_RFW_LRO_IPV4_FLAGS_MASK_1_SHIFT 22 1797 /* Version value */ 1798 #define EC_RFW_LRO_IPV4_VER_MASK 0xF0000000 1799 #define EC_RFW_LRO_IPV4_VER_SHIFT 28 1800 1801 /**** lro_check_ipv6 register ****/ 1802 /* Check version field */ 1803 #define EC_RFW_LRO_CHECK_IPV6_VER (1 << 0) 1804 /* Compare TC to previous packet. */ 1805 #define EC_RFW_LRO_CHECK_IPV6_TC (1 << 1) 1806 /* Compare flow label field to previous packet. */ 1807 #define EC_RFW_LRO_CHECK_IPV6_FLOW (1 << 2) 1808 /* Check that Total length >= lro_ipv6_pen_val. */ 1809 #define EC_RFW_LRO_CHECK_IPV6_PLEN (1 << 3) 1810 /* Compare to previous packet next header field. */ 1811 #define EC_RFW_LRO_CHECK_IPV6_NEXT_0 (1 << 4) 1812 /* Verify that the next header is TCP or UDP. */ 1813 #define EC_RFW_LRO_CHECK_IPV6_NEXT_1 (1 << 5) 1814 /* Verify that hop limit is >0. */ 1815 #define EC_RFW_LRO_CHECK_IPV6_HOP_0 (1 << 6) 1816 /* Compare hop limit to previous packet. */ 1817 #define EC_RFW_LRO_CHECK_IPV6_HOP_1 (1 << 7) 1818 /* Compare SIP to previous packet. */ 1819 #define EC_RFW_LRO_CHECK_IPV6_SIP (1 << 8) 1820 /* Compare DIP to previous packet. */ 1821 #define EC_RFW_LRO_CHECK_IPV6_DIP (1 << 9) 1822 1823 /**** lro_ipv6 register ****/ 1824 /* Payload length minimum value */ 1825 #define EC_RFW_LRO_IPV6_PLEN_VAL_MASK 0x0000FFFF 1826 #define EC_RFW_LRO_IPV6_PLEN_VAL_SHIFT 0 1827 /* Version value */ 1828 #define EC_RFW_LRO_IPV6_VER_MASK 0x0F000000 1829 #define EC_RFW_LRO_IPV6_VER_SHIFT 24 1830 1831 /**** lro_check_tcp register ****/ 1832 /* Compare to previous packet. */ 1833 #define EC_RFW_LRO_CHECK_TCP_SRC_PORT (1 << 0) 1834 /* Compare to previous packet. */ 1835 #define EC_RFW_LRO_CHECK_TCP_DST_PORT (1 << 1) 1836 /* If (SYN == 1), don't check */ 1837 #define EC_RFW_LRO_CHECK_TCP_SN (1 << 2) 1838 /* Check data offset field == 5. */ 1839 #define EC_RFW_LRO_CHECK_TCP_OFFSET_0 (1 << 3) 1840 /* Check data offset field >= 5. */ 1841 #define EC_RFW_LRO_CHECK_TCP_OFFSET_1 (1 << 4) 1842 /* Compare to previous packet. */ 1843 #define EC_RFW_LRO_CHECK_TCP_OFFSET_2 (1 << 5) 1844 /* Compare reserved field to lro_tcp_res. */ 1845 #define EC_RFW_LRO_CHECK_TCP_RES (1 << 6) 1846 /* Compare to lro_tcp_ecn_val and lro_tcp_ecn_mask_0. */ 1847 #define EC_RFW_LRO_CHECK_TCP_ECN_0 (1 << 7) 1848 /* Compare to previous packet ECN field with lro_tcp_ecn_mask_1 */ 1849 #define EC_RFW_LRO_CHECK_TCP_ECN_1 (1 << 8) 1850 /* Compare to lro_tcp_ctrl_val and lro_tcp_ctrl_mask_0. */ 1851 #define EC_RFW_LRO_CHECK_TCP_CTRL_0 (1 << 9) 1852 /* Compare to previous packet ECN field with lro_tcp_ctrl_mask_1 */ 1853 #define EC_RFW_LRO_CHECK_TCP_CTRL_1 (1 << 10) 1854 /* Verify that check sum is correct. */ 1855 #define EC_RFW_LRO_CHECK_TCP_CHECKSUM (1 << 11) 1856 1857 /**** lro_tcp register ****/ 1858 /* Reserved field default value */ 1859 #define EC_RFW_LRO_TCP_RES_MASK 0x00000007 1860 #define EC_RFW_LRO_TCP_RES_SHIFT 0 1861 /* ECN field value */ 1862 #define EC_RFW_LRO_TCP_ECN_VAL_MASK 0x00000038 1863 #define EC_RFW_LRO_TCP_ECN_VAL_SHIFT 3 1864 /* ECN field mask */ 1865 #define EC_RFW_LRO_TCP_ECN_MASK_0_MASK 0x000001C0 1866 #define EC_RFW_LRO_TCP_ECN_MASK_0_SHIFT 6 1867 /* ECN field mask */ 1868 #define EC_RFW_LRO_TCP_ECN_MASK_1_MASK 0x00000E00 1869 #define EC_RFW_LRO_TCP_ECN_MASK_1_SHIFT 9 1870 /* Control field value */ 1871 #define EC_RFW_LRO_TCP_CTRL_VAL_MASK 0x0003F000 1872 #define EC_RFW_LRO_TCP_CTRL_VAL_SHIFT 12 1873 /* Control field mask */ 1874 #define EC_RFW_LRO_TCP_CTRL_MASK_0_MASK 0x00FC0000 1875 #define EC_RFW_LRO_TCP_CTRL_MASK_0_SHIFT 18 1876 /* Control field mask */ 1877 #define EC_RFW_LRO_TCP_CTRL_MASK_1_MASK 0x3F000000 1878 #define EC_RFW_LRO_TCP_CTRL_MASK_1_SHIFT 24 1879 1880 /**** lro_check_udp register ****/ 1881 /* Compare to previous packet. */ 1882 #define EC_RFW_LRO_CHECK_UDP_SRC_PORT (1 << 0) 1883 /* Compare to previous packet. */ 1884 #define EC_RFW_LRO_CHECK_UDP_DST_PORT (1 << 1) 1885 /* Verify that check sum is correct. */ 1886 #define EC_RFW_LRO_CHECK_UDP_CHECKSUM (1 << 2) 1887 1888 /**** lro_check_l2 register ****/ 1889 /* Compare to previous packet. */ 1890 #define EC_RFW_LRO_CHECK_L2_MAC_DA (1 << 0) 1891 /* Compare to previous packet. */ 1892 #define EC_RFW_LRO_CHECK_L2_MAC_SA (1 << 1) 1893 /* Compare to previous packet. */ 1894 #define EC_RFW_LRO_CHECK_L2_VLAN_1_EXIST (1 << 2) 1895 /* Compare to previous packet. */ 1896 #define EC_RFW_LRO_CHECK_L2_VLAN_1_VID (1 << 3) 1897 /* Compare to previous packet. */ 1898 #define EC_RFW_LRO_CHECK_L2_VLAN_1_CFI (1 << 4) 1899 /* Compare to previous packet. */ 1900 #define EC_RFW_LRO_CHECK_L2_VLAN_1_PBITS (1 << 5) 1901 /* Compare to previous packet. */ 1902 #define EC_RFW_LRO_CHECK_L2_VLAN_2_EXIST (1 << 6) 1903 /* Compare to previous packet. */ 1904 #define EC_RFW_LRO_CHECK_L2_VLAN_2_VID (1 << 7) 1905 /* Compare to previous packet. */ 1906 #define EC_RFW_LRO_CHECK_L2_VLAN_2_CFI (1 << 8) 1907 /* Compare to previous packet. */ 1908 #define EC_RFW_LRO_CHECK_L2_VLAN_2_PBITS (1 << 9) 1909 /* Verify that the FCS is correct. */ 1910 #define EC_RFW_LRO_CHECK_L2_FCS (1 << 10) 1911 1912 /**** lro_check_gen register ****/ 1913 /* Compare to previous packet */ 1914 #define EC_RFW_LRO_CHECK_GEN_UDMA (1 << 0) 1915 /* Compare to previous packet */ 1916 #define EC_RFW_LRO_CHECK_GEN_QUEUE (1 << 1) 1917 1918 /**** lro_store register ****/ 1919 /* Store packet information if protocol match. */ 1920 #define EC_RFW_LRO_STORE_IPV4 (1 << 0) 1921 /* Store packet information if protocol match. */ 1922 #define EC_RFW_LRO_STORE_IPV6 (1 << 1) 1923 /* Store packet information if protocol match. */ 1924 #define EC_RFW_LRO_STORE_TCP (1 << 2) 1925 /* Store packet information if protocol match. */ 1926 #define EC_RFW_LRO_STORE_UDP (1 << 3) 1927 /* Store packet if IPv4 flags match the register value with mask */ 1928 #define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_MASK 0x00000070 1929 #define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_SHIFT 4 1930 /* Mask for IPv4 flags */ 1931 #define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_MASK 0x00000380 1932 #define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_SHIFT 7 1933 /* Store packet if TCP control and ECN match the register value ... */ 1934 #define EC_RFW_LRO_STORE_TCP_CTRL_VAL_MASK 0x0007FC00 1935 #define EC_RFW_LRO_STORE_TCP_CTRL_VAL_SHIFT 10 1936 /* Mask for TCP control */ 1937 #define EC_RFW_LRO_STORE_TCP_CTRL_MASK_MASK 0x0FF80000 1938 #define EC_RFW_LRO_STORE_TCP_CTRL_MASK_SHIFT 19 1939 1940 /**** vid_table_def register ****/ 1941 /* Table default data (valid only after configuring the table ad ... */ 1942 #define EC_RFW_VID_TABLE_DEF_VAL_MASK 0x0000003F 1943 #define EC_RFW_VID_TABLE_DEF_VAL_SHIFT 0 1944 /* Default data selection 1945 0 - Default value 1946 1 - Table data out */ 1947 #define EC_RFW_VID_TABLE_DEF_SEL (1 << 6) 1948 1949 /**** ctrl_table_def register ****/ 1950 /* Control table output for selecting the forwarding MUXs [3:0] ... */ 1951 #define EC_RFW_CTRL_TABLE_DEF_VAL_MASK 0x000FFFFF 1952 #define EC_RFW_CTRL_TABLE_DEF_VAL_SHIFT 0 1953 /* Default data selection 0 - Default value 1 - Table data out ... */ 1954 #define EC_RFW_CTRL_TABLE_DEF_SEL (1 << 20) 1955 1956 /**** cfg_a_0 register ****/ 1957 /* Selection of the L3 checksum result in the Metadata00 - L3 ch ... */ 1958 #define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_MASK 0x00000003 1959 #define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT 0 1960 /* Selection of the L4 checksum result in the Metadata0 - L4 che ... */ 1961 #define EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL (1 << 2) 1962 /* Selection of the LRO_context_value result in the Metadata0 - ... */ 1963 #define EC_RFW_CFG_A_0_LRO_CONTEXT_SEL (1 << 4) 1964 1965 /**** thash_cfg_3 register ****/ 1966 /* Enable Hash value for RoCE packets in outer packet. */ 1967 #define EC_RFW_THASH_CFG_3_ENABLE_OUTER_ROCE (1 << 0) 1968 /* Enable Hash value for RoCE packets in inner packet. */ 1969 #define EC_RFW_THASH_CFG_3_ENABLE_INNER_ROCE (1 << 1) 1970 /* Enable Hash value for FcoE packets in outer packet. */ 1971 #define EC_RFW_THASH_CFG_3_ENABLE_OUTER_FCOE (1 << 2) 1972 /* Enable Hash value for FcoE packets in inner packet. */ 1973 #define EC_RFW_THASH_CFG_3_ENABLE_INNER_FCOE (1 << 3) 1974 1975 /**** thash_mask_outer_ipv6 register ****/ 1976 /* IPv6 source IP address */ 1977 #define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_MASK 0x0000FFFF 1978 #define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_SHIFT 0 1979 /* IPv6 destination IP address */ 1980 #define EC_RFW_THASH_MASK_OUTER_IPV6_DST_MASK 0xFFFF0000 1981 #define EC_RFW_THASH_MASK_OUTER_IPV6_DST_SHIFT 16 1982 1983 /**** thash_mask_outer register ****/ 1984 /* IPv4 source IP address */ 1985 #define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_MASK 0x0000000F 1986 #define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_SHIFT 0 1987 /* IPv4 destination IP address */ 1988 #define EC_RFW_THASH_MASK_OUTER_IPV4_DST_MASK 0x000000F0 1989 #define EC_RFW_THASH_MASK_OUTER_IPV4_DST_SHIFT 4 1990 /* TCP source port */ 1991 #define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_MASK 0x00000300 1992 #define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_SHIFT 8 1993 /* TCP destination port */ 1994 #define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_MASK 0x00000C00 1995 #define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_SHIFT 10 1996 /* UDP source port */ 1997 #define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_MASK 0x00003000 1998 #define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_SHIFT 12 1999 /* UDP destination port */ 2000 #define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_MASK 0x0000C000 2001 #define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_SHIFT 14 2002 2003 /**** thash_mask_inner_ipv6 register ****/ 2004 /* IPv6 source IP address */ 2005 #define EC_RFW_THASH_MASK_INNER_IPV6_SRC_MASK 0x0000FFFF 2006 #define EC_RFW_THASH_MASK_INNER_IPV6_SRC_SHIFT 0 2007 /* IPv6 destination IP address */ 2008 #define EC_RFW_THASH_MASK_INNER_IPV6_DST_MASK 0xFFFF0000 2009 #define EC_RFW_THASH_MASK_INNER_IPV6_DST_SHIFT 16 2010 2011 /**** thash_mask_inner register ****/ 2012 /* IPv4 source IP address */ 2013 #define EC_RFW_THASH_MASK_INNER_IPV4_SRC_MASK 0x0000000F 2014 #define EC_RFW_THASH_MASK_INNER_IPV4_SRC_SHIFT 0 2015 /* IPv4 destination IP address */ 2016 #define EC_RFW_THASH_MASK_INNER_IPV4_DST_MASK 0x000000F0 2017 #define EC_RFW_THASH_MASK_INNER_IPV4_DST_SHIFT 4 2018 /* TCP source port */ 2019 #define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_MASK 0x00000300 2020 #define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_SHIFT 8 2021 /* TCP destination port */ 2022 #define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_MASK 0x00000C00 2023 #define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_SHIFT 10 2024 /* UDP source port */ 2025 #define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_MASK 0x00003000 2026 #define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_SHIFT 12 2027 /* UDP destination port */ 2028 #define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_MASK 0x0000C000 2029 #define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_SHIFT 14 2030 2031 /**** def_cfg register ****/ 2032 /* Number of padding bytes to add at the beginning of each Ether ... */ 2033 #define EC_RFW_UDMA_DEF_CFG_RX_PAD_MASK 0x0000003F 2034 #define EC_RFW_UDMA_DEF_CFG_RX_PAD_SHIFT 0 2035 2036 /**** queue register ****/ 2037 /* Mapping between priority and queue number */ 2038 #define EC_RFW_PRIORITY_QUEUE_MAP_MASK 0x00000003 2039 #define EC_RFW_PRIORITY_QUEUE_MAP_SHIFT 0 2040 2041 /**** opt_1 register ****/ 2042 /* Default UDMA for forwarding */ 2043 #define EC_RFW_DEFAULT_OPT_1_UDMA_MASK 0x0000000F 2044 #define EC_RFW_DEFAULT_OPT_1_UDMA_SHIFT 0 2045 /* Default priority for forwarding */ 2046 #define EC_RFW_DEFAULT_OPT_1_PRIORITY_MASK 0x00000700 2047 #define EC_RFW_DEFAULT_OPT_1_PRIORITY_SHIFT 8 2048 /* Default queue for forwarding */ 2049 #define EC_RFW_DEFAULT_OPT_1_QUEUE_MASK 0x00030000 2050 #define EC_RFW_DEFAULT_OPT_1_QUEUE_SHIFT 16 2051 2052 /**** data_h register ****/ 2053 /* MAC address data */ 2054 #define EC_FWD_MAC_DATA_H_VAL_MASK 0x0000FFFF 2055 #define EC_FWD_MAC_DATA_H_VAL_SHIFT 0 2056 2057 /**** mask_h register ****/ 2058 /* MAC address mask */ 2059 #define EC_FWD_MAC_MASK_H_VAL_MASK 0x0000FFFF 2060 #define EC_FWD_MAC_MASK_H_VAL_SHIFT 0 2061 2062 /**** ctrl register ****/ 2063 /* Control value for Rx forwarding engine[0] - Drop indication[2 ... */ 2064 #define EC_FWD_MAC_CTRL_RX_VAL_MASK 0x000001FF 2065 #define EC_FWD_MAC_CTRL_RX_VAL_SHIFT 0 2066 2067 /* Drop indication */ 2068 #define EC_FWD_MAC_CTRL_RX_VAL_DROP (1 << 0) 2069 2070 /* control table command input */ 2071 #define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_MASK 0x00000006 2072 #define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_SHIFT 1 2073 2074 /* UDMA selection */ 2075 #define EC_FWD_MAC_CTRL_RX_VAL_UDMA_MASK 0x000000078 2076 #define EC_FWD_MAC_CTRL_RX_VAL_UDMA_SHIFT 3 2077 2078 /* queue number */ 2079 #define EC_FWD_MAC_CTRL_RX_VAL_QID_MASK 0x00000180 2080 #define EC_FWD_MAC_CTRL_RX_VAL_QID_SHIFT 7 2081 2082 /* Entry is valid for Rx forwarding engine. */ 2083 #define EC_FWD_MAC_CTRL_RX_VALID (1 << 15) 2084 /* Control value for Tx forwarding engine */ 2085 #define EC_FWD_MAC_CTRL_TX_VAL_MASK 0x001F0000 2086 #define EC_FWD_MAC_CTRL_TX_VAL_SHIFT 16 2087 /* Entry is valid for Tx forwarding engine. */ 2088 #define EC_FWD_MAC_CTRL_TX_VALID (1 << 31) 2089 2090 /**** uc register ****/ 2091 /* timer max value for waiting for a stream to be ready to accep ... */ 2092 #define EC_MSW_UC_TIMER_MASK 0x0000FFFF 2093 #define EC_MSW_UC_TIMER_SHIFT 0 2094 /* Drop packet if target queue in the UDMA is full */ 2095 #define EC_MSW_UC_Q_FULL_DROP_MASK 0x000F0000 2096 #define EC_MSW_UC_Q_FULL_DROP_SHIFT 16 2097 /* Drop packet if timer expires. */ 2098 #define EC_MSW_UC_TIMER_DROP_MASK 0x0F000000 2099 #define EC_MSW_UC_TIMER_DROP_SHIFT 24 2100 2101 /**** mc register ****/ 2102 /* Timer max value for waiting for a stream to be ready to accep ... */ 2103 #define EC_MSW_MC_TIMER_MASK 0x0000FFFF 2104 #define EC_MSW_MC_TIMER_SHIFT 0 2105 /* Drop packet if target queue in UDMA is full. */ 2106 #define EC_MSW_MC_Q_FULL_DROP_MASK 0x000F0000 2107 #define EC_MSW_MC_Q_FULL_DROP_SHIFT 16 2108 /* Drop packet if timer expires. */ 2109 #define EC_MSW_MC_TIMER_DROP_MASK 0x0F000000 2110 #define EC_MSW_MC_TIMER_DROP_SHIFT 24 2111 2112 /**** bc register ****/ 2113 /* Timer max value for waiting for a stream to be ready to accep ... */ 2114 #define EC_MSW_BC_TIMER_MASK 0x0000FFFF 2115 #define EC_MSW_BC_TIMER_SHIFT 0 2116 /* Drop packet if target queue in UDMA is full. */ 2117 #define EC_MSW_BC_Q_FULL_DROP_MASK 0x000F0000 2118 #define EC_MSW_BC_Q_FULL_DROP_SHIFT 16 2119 /* Drop packet if timer expires. */ 2120 #define EC_MSW_BC_TIMER_DROP_MASK 0x0F000000 2121 #define EC_MSW_BC_TIMER_DROP_SHIFT 24 2122 2123 /**** in_cfg register ****/ 2124 /* Swap input bytes order */ 2125 #define EC_TSO_IN_CFG_SWAP_BYTES (1 << 0) 2126 /* Selects strict priority or round robin scheduling between GDM ... */ 2127 #define EC_TSO_IN_CFG_SEL_SP_RR (1 << 1) 2128 /* Selects scheduler numbering direction */ 2129 #define EC_TSO_IN_CFG_SEL_SCH_DIR (1 << 2) 2130 /* Minimum L2 packet size (not including FCS) */ 2131 #define EC_TSO_IN_CFG_L2_MIN_SIZE_MASK 0x00007F00 2132 #define EC_TSO_IN_CFG_L2_MIN_SIZE_SHIFT 8 2133 /* Swap input bytes order */ 2134 #define EC_TSO_IN_CFG_SP_INIT_VAL_MASK 0x000F0000 2135 #define EC_TSO_IN_CFG_SP_INIT_VAL_SHIFT 16 2136 2137 /**** cache_table_addr register ****/ 2138 /* Address for accessing the table */ 2139 #define EC_TSO_CACHE_TABLE_ADDR_VAL_MASK 0x0000000F 2140 #define EC_TSO_CACHE_TABLE_ADDR_VAL_SHIFT 0 2141 2142 /**** ctrl_first register ****/ 2143 /* Data to be written into the control BIS. */ 2144 #define EC_TSO_CTRL_FIRST_DATA_MASK 0x000001FF 2145 #define EC_TSO_CTRL_FIRST_DATA_SHIFT 0 2146 /* Mask for control bits */ 2147 #define EC_TSO_CTRL_FIRST_MASK_MASK 0x01FF0000 2148 #define EC_TSO_CTRL_FIRST_MASK_SHIFT 16 2149 2150 /**** ctrl_middle register ****/ 2151 /* Data to be written into the control BIS. */ 2152 #define EC_TSO_CTRL_MIDDLE_DATA_MASK 0x000001FF 2153 #define EC_TSO_CTRL_MIDDLE_DATA_SHIFT 0 2154 /* Mask for the control bits */ 2155 #define EC_TSO_CTRL_MIDDLE_MASK_MASK 0x01FF0000 2156 #define EC_TSO_CTRL_MIDDLE_MASK_SHIFT 16 2157 2158 /**** ctrl_last register ****/ 2159 /* Data to be written into the control BIS. */ 2160 #define EC_TSO_CTRL_LAST_DATA_MASK 0x000001FF 2161 #define EC_TSO_CTRL_LAST_DATA_SHIFT 0 2162 /* Mask for the control bits */ 2163 #define EC_TSO_CTRL_LAST_MASK_MASK 0x01FF0000 2164 #define EC_TSO_CTRL_LAST_MASK_SHIFT 16 2165 2166 /**** cfg_add_0 register ****/ 2167 /* MSS selection option:0 - MSS value is selected using MSS_sel ... */ 2168 #define EC_TSO_CFG_ADD_0_MSS_SEL (1 << 0) 2169 2170 /**** cfg_tunnel register ****/ 2171 /* Enable TSO with tunnelling */ 2172 #define EC_TSO_CFG_TUNNEL_EN_TUNNEL_TSO (1 << 0) 2173 /* Enable outer UDP checksum update */ 2174 #define EC_TSO_CFG_TUNNEL_EN_UDP_CHKSUM (1 << 8) 2175 /* Enable outer UDP length update */ 2176 #define EC_TSO_CFG_TUNNEL_EN_UDP_LEN (1 << 9) 2177 /* Enable outer Ip6 length update */ 2178 #define EC_TSO_CFG_TUNNEL_EN_IPV6_PLEN (1 << 10) 2179 /* Enable outer IPv4 checksum update */ 2180 #define EC_TSO_CFG_TUNNEL_EN_IPV4_CHKSUM (1 << 11) 2181 /* Enable outer IPv4 Identification update */ 2182 #define EC_TSO_CFG_TUNNEL_EN_IPV4_IDEN (1 << 12) 2183 /* Enable outer IPv4 length update */ 2184 #define EC_TSO_CFG_TUNNEL_EN_IPV4_TLEN (1 << 13) 2185 2186 /**** mss register ****/ 2187 /* MSS value */ 2188 #define EC_TSO_SEL_MSS_VAL_MASK 0x000FFFFF 2189 #define EC_TSO_SEL_MSS_VAL_SHIFT 0 2190 2191 /**** parse register ****/ 2192 /* Max number of bus beats for parsing */ 2193 #define EC_TPE_PARSE_MAX_BEATS_MASK 0x0000FFFF 2194 #define EC_TPE_PARSE_MAX_BEATS_SHIFT 0 2195 2196 /**** vlan_data register ****/ 2197 /* UDMA default VLAN 1 data */ 2198 #define EC_TPM_UDMA_VLAN_DATA_DEF_1_MASK 0x0000FFFF 2199 #define EC_TPM_UDMA_VLAN_DATA_DEF_1_SHIFT 0 2200 /* UDMA default VLAN 2 data */ 2201 #define EC_TPM_UDMA_VLAN_DATA_DEF_2_MASK 0xFFFF0000 2202 #define EC_TPM_UDMA_VLAN_DATA_DEF_2_SHIFT 16 2203 2204 /**** mac_sa_2 register ****/ 2205 /* MAC source address data [47:32] */ 2206 #define EC_TPM_UDMA_MAC_SA_2_H_VAL_MASK 0x0000FFFF 2207 #define EC_TPM_UDMA_MAC_SA_2_H_VAL_SHIFT 0 2208 /* Drop indication for MAC SA spoofing0 – Don't drop */ 2209 #define EC_TPM_UDMA_MAC_SA_2_DROP (1 << 16) 2210 /* Replace indication for MAC SA spoofing 0 - Don't replace */ 2211 #define EC_TPM_UDMA_MAC_SA_2_REPLACE (1 << 17) 2212 2213 /**** etype register ****/ 2214 /* Ether type value */ 2215 #define EC_TPM_SEL_ETYPE_VAL_MASK 0x0000FFFF 2216 #define EC_TPM_SEL_ETYPE_VAL_SHIFT 0 2217 2218 /**** tx_wr_fifo register ****/ 2219 /* Max data beats that can be used in the Tx FIFO */ 2220 #define EC_TFW_TX_WR_FIFO_DATA_TH_MASK 0x0000FFFF 2221 #define EC_TFW_TX_WR_FIFO_DATA_TH_SHIFT 0 2222 /* Max packets that can be stored in the Tx FIFO */ 2223 #define EC_TFW_TX_WR_FIFO_INFO_TH_MASK 0xFFFF0000 2224 #define EC_TFW_TX_WR_FIFO_INFO_TH_SHIFT 16 2225 2226 /**** tx_vid_table_addr register ****/ 2227 /* Address for accessing the table */ 2228 #define EC_TFW_TX_VID_TABLE_ADDR_VAL_MASK 0x00000FFF 2229 #define EC_TFW_TX_VID_TABLE_ADDR_VAL_SHIFT 0 2230 2231 /**** tx_vid_table_data register ****/ 2232 /* Table data (valid only after configuring the table address re ... */ 2233 #define EC_TFW_TX_VID_TABLE_DATA_VAL_MASK 0x0000001F 2234 #define EC_TFW_TX_VID_TABLE_DATA_VAL_SHIFT 0 2235 2236 /**** tx_rd_fifo register ****/ 2237 /* Read data threshold when cut through mode is enabled. */ 2238 #define EC_TFW_TX_RD_FIFO_READ_TH_MASK 0x0000FFFF 2239 #define EC_TFW_TX_RD_FIFO_READ_TH_SHIFT 0 2240 /* Enable cut through operation of the Tx FIFO. */ 2241 #define EC_TFW_TX_RD_FIFO_EN_CUT_THROUGH (1 << 16) 2242 2243 /**** tx_checksum register ****/ 2244 /* Enable L3 checksum insertion. */ 2245 #define EC_TFW_TX_CHECKSUM_L3_EN (1 << 0) 2246 /* Enable L4 checksum insertion. */ 2247 #define EC_TFW_TX_CHECKSUM_L4_EN (1 << 1) 2248 /* Enable L4 checksum when L3 fragmentation is detected. */ 2249 #define EC_TFW_TX_CHECKSUM_L4_FRAG_EN (1 << 2) 2250 2251 /**** tx_gen register ****/ 2252 /* Force forward of all Tx packets to MAC. */ 2253 #define EC_TFW_TX_GEN_FWD_ALL_TO_MAC (1 << 0) 2254 /* Select the Packet generator as the source of Tx packets0 - Tx ... */ 2255 #define EC_TFW_TX_GEN_SELECT_PKT_GEN (1 << 1) 2256 2257 /**** tx_spf register ****/ 2258 /* Select the VID for spoofing check:[0] - Packet VID[1] - Forwa ... */ 2259 #define EC_TFW_TX_SPF_VID_SEL (1 << 0) 2260 2261 /**** data_fifo register ****/ 2262 /* FIFO used value (number of entries) */ 2263 #define EC_TFW_DATA_FIFO_USED_MASK 0x0000FFFF 2264 #define EC_TFW_DATA_FIFO_USED_SHIFT 0 2265 /* FIFO FULL status */ 2266 #define EC_TFW_DATA_FIFO_FULL (1 << 16) 2267 /* FIFO EMPTY status */ 2268 #define EC_TFW_DATA_FIFO_EMPTY (1 << 17) 2269 2270 /**** ctrl_fifo register ****/ 2271 /* FIFO used value (number of entries) */ 2272 #define EC_TFW_CTRL_FIFO_USED_MASK 0x0000FFFF 2273 #define EC_TFW_CTRL_FIFO_USED_SHIFT 0 2274 /* FIFO FULL status */ 2275 #define EC_TFW_CTRL_FIFO_FULL (1 << 16) 2276 /* FIFO EMPTY status */ 2277 #define EC_TFW_CTRL_FIFO_EMPTY (1 << 17) 2278 2279 /**** hdr_fifo register ****/ 2280 /* FIFO used value (number of entries) */ 2281 #define EC_TFW_HDR_FIFO_USED_MASK 0x0000FFFF 2282 #define EC_TFW_HDR_FIFO_USED_SHIFT 0 2283 /* FIFO FULL status */ 2284 #define EC_TFW_HDR_FIFO_FULL (1 << 16) 2285 /* FIFO EMPTY status */ 2286 #define EC_TFW_HDR_FIFO_EMPTY (1 << 17) 2287 2288 /**** uc_udma register ****/ 2289 /* Default UDMA bitmap 2290 (MSB represents physical port) */ 2291 #define EC_TFW_UDMA_UC_UDMA_DEF_MASK 0x0000001F 2292 #define EC_TFW_UDMA_UC_UDMA_DEF_SHIFT 0 2293 2294 /**** mc_udma register ****/ 2295 /* Default UDMA bitmap (MSB represents physical port.) */ 2296 #define EC_TFW_UDMA_MC_UDMA_DEF_MASK 0x0000001F 2297 #define EC_TFW_UDMA_MC_UDMA_DEF_SHIFT 0 2298 2299 /**** bc_udma register ****/ 2300 /* Default UDMA bitmap (MSB represents physical port.) */ 2301 #define EC_TFW_UDMA_BC_UDMA_DEF_MASK 0x0000001F 2302 #define EC_TFW_UDMA_BC_UDMA_DEF_SHIFT 0 2303 2304 /**** spf_cmd register ****/ 2305 /* Command for the VLAN spoofing00 – Ignore mismatch */ 2306 #define EC_TFW_UDMA_SPF_CMD_VID_MASK 0x00000003 2307 #define EC_TFW_UDMA_SPF_CMD_VID_SHIFT 0 2308 /* Command for VLAN spoofing 00 - Ignore mismatch */ 2309 #define EC_TFW_UDMA_SPF_CMD_MAC_MASK 0x0000000C 2310 #define EC_TFW_UDMA_SPF_CMD_MAC_SHIFT 2 2311 2312 /**** fwd_dec register ****/ 2313 /* Forwarding decision control:[0] – Enable internal switch */ 2314 #define EC_TFW_UDMA_FWD_DEC_CTRL_MASK 0x000003FF 2315 #define EC_TFW_UDMA_FWD_DEC_CTRL_SHIFT 0 2316 2317 /**** tx_cfg register ****/ 2318 /* Swap output byte order */ 2319 #define EC_TMI_TX_CFG_SWAP_BYTES (1 << 0) 2320 /* Enable forwarding to the Rx data path. */ 2321 #define EC_TMI_TX_CFG_EN_FWD_TO_RX (1 << 1) 2322 /* Force forwarding all packets to the MAC. */ 2323 #define EC_TMI_TX_CFG_FORCE_FWD_MAC (1 << 2) 2324 /* Force forwarding all packets to the MAC. */ 2325 #define EC_TMI_TX_CFG_FORCE_FWD_RX (1 << 3) 2326 /* Force loop back operation */ 2327 #define EC_TMI_TX_CFG_FORCE_LB (1 << 4) 2328 2329 /**** ec_pause register ****/ 2330 /* Mask of pause_on [7:0] */ 2331 #define EC_EFC_EC_PAUSE_MASK_MAC_MASK 0x000000FF 2332 #define EC_EFC_EC_PAUSE_MASK_MAC_SHIFT 0 2333 /* Mask of GPIO input [7:0] */ 2334 #define EC_EFC_EC_PAUSE_MASK_GPIO_MASK 0x0000FF00 2335 #define EC_EFC_EC_PAUSE_MASK_GPIO_SHIFT 8 2336 2337 /**** ec_xoff register ****/ 2338 /* Mask 1 for XOFF [7:0] 2339 Mask 1 for Almost Full indication, */ 2340 #define EC_EFC_EC_XOFF_MASK_1_MASK 0x000000FF 2341 #define EC_EFC_EC_XOFF_MASK_1_SHIFT 0 2342 /* Mask 2 for XOFF [7:0] Mask 2 for sampled Almost Full indicati ... */ 2343 #define EC_EFC_EC_XOFF_MASK_2_MASK 0x0000FF00 2344 #define EC_EFC_EC_XOFF_MASK_2_SHIFT 8 2345 2346 /**** xon register ****/ 2347 /* Mask 1 for generating XON pulse, masking XOFF [0] */ 2348 #define EC_EFC_XON_MASK_1 (1 << 0) 2349 /* Mask 2 for generating XON pulse, masking Almost Full indicati ... */ 2350 #define EC_EFC_XON_MASK_2 (1 << 1) 2351 2352 /**** gpio register ****/ 2353 /* Mask for generating GPIO output XOFF indication from XOFF[0] */ 2354 #define EC_EFC_GPIO_MASK_1 (1 << 0) 2355 2356 /**** rx_fifo_af register ****/ 2357 /* Threshold */ 2358 #define EC_EFC_RX_FIFO_AF_TH_MASK 0x0000FFFF 2359 #define EC_EFC_RX_FIFO_AF_TH_SHIFT 0 2360 2361 /**** rx_fifo_hyst register ****/ 2362 /* Threshold low */ 2363 #define EC_EFC_RX_FIFO_HYST_TH_LOW_MASK 0x0000FFFF 2364 #define EC_EFC_RX_FIFO_HYST_TH_LOW_SHIFT 0 2365 /* Threshold high */ 2366 #define EC_EFC_RX_FIFO_HYST_TH_HIGH_MASK 0xFFFF0000 2367 #define EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT 16 2368 2369 /**** stat register ****/ 2370 /* 10G MAC PFC mode, input from the 10 MAC */ 2371 #define EC_EFC_STAT_PFC_MODE (1 << 0) 2372 2373 /**** ec_pfc register ****/ 2374 /* Force PFC flow control */ 2375 #define EC_EFC_EC_PFC_FORCE_MASK 0x000000FF 2376 #define EC_EFC_EC_PFC_FORCE_SHIFT 0 2377 2378 /**** q_pause_0 register ****/ 2379 /* [i] – Mask for Q[i] */ 2380 #define EC_FC_UDMA_Q_PAUSE_0_MASK_MASK 0x0000000F 2381 #define EC_FC_UDMA_Q_PAUSE_0_MASK_SHIFT 0 2382 2383 /**** q_pause_1 register ****/ 2384 /* [i] - Mask for Q[i] */ 2385 #define EC_FC_UDMA_Q_PAUSE_1_MASK_MASK 0x0000000F 2386 #define EC_FC_UDMA_Q_PAUSE_1_MASK_SHIFT 0 2387 2388 /**** q_pause_2 register ****/ 2389 /* [i] - Mask for Q[i] */ 2390 #define EC_FC_UDMA_Q_PAUSE_2_MASK_MASK 0x0000000F 2391 #define EC_FC_UDMA_Q_PAUSE_2_MASK_SHIFT 0 2392 2393 /**** q_pause_3 register ****/ 2394 /* [i] - Mask for Q[i] */ 2395 #define EC_FC_UDMA_Q_PAUSE_3_MASK_MASK 0x0000000F 2396 #define EC_FC_UDMA_Q_PAUSE_3_MASK_SHIFT 0 2397 2398 /**** q_pause_4 register ****/ 2399 /* [i] - Mask for Q[i] */ 2400 #define EC_FC_UDMA_Q_PAUSE_4_MASK_MASK 0x0000000F 2401 #define EC_FC_UDMA_Q_PAUSE_4_MASK_SHIFT 0 2402 2403 /**** q_pause_5 register ****/ 2404 /* [i] - Mask for Q[i] */ 2405 #define EC_FC_UDMA_Q_PAUSE_5_MASK_MASK 0x0000000F 2406 #define EC_FC_UDMA_Q_PAUSE_5_MASK_SHIFT 0 2407 2408 /**** q_pause_6 register ****/ 2409 /* [i] - Mask for Q[i] */ 2410 #define EC_FC_UDMA_Q_PAUSE_6_MASK_MASK 0x0000000F 2411 #define EC_FC_UDMA_Q_PAUSE_6_MASK_SHIFT 0 2412 2413 /**** q_pause_7 register ****/ 2414 /* [i] - Mask for Q[i] */ 2415 #define EC_FC_UDMA_Q_PAUSE_7_MASK_MASK 0x0000000F 2416 #define EC_FC_UDMA_Q_PAUSE_7_MASK_SHIFT 0 2417 2418 /**** q_gpio_0 register ****/ 2419 /* [i] - Mask for Q[i] */ 2420 #define EC_FC_UDMA_Q_GPIO_0_MASK_MASK 0x0000000F 2421 #define EC_FC_UDMA_Q_GPIO_0_MASK_SHIFT 0 2422 2423 /**** q_gpio_1 register ****/ 2424 /* [i] - Mask for Q[i] */ 2425 #define EC_FC_UDMA_Q_GPIO_1_MASK_MASK 0x0000000F 2426 #define EC_FC_UDMA_Q_GPIO_1_MASK_SHIFT 0 2427 2428 /**** q_gpio_2 register ****/ 2429 /* [i] - Mask for Q[i] */ 2430 #define EC_FC_UDMA_Q_GPIO_2_MASK_MASK 0x0000000F 2431 #define EC_FC_UDMA_Q_GPIO_2_MASK_SHIFT 0 2432 2433 /**** q_gpio_3 register ****/ 2434 /* [i] - Mask for Q[i] */ 2435 #define EC_FC_UDMA_Q_GPIO_3_MASK_MASK 0x0000000F 2436 #define EC_FC_UDMA_Q_GPIO_3_MASK_SHIFT 0 2437 2438 /**** q_gpio_4 register ****/ 2439 /* [i] - Mask for Q[i] */ 2440 #define EC_FC_UDMA_Q_GPIO_4_MASK_MASK 0x0000000F 2441 #define EC_FC_UDMA_Q_GPIO_4_MASK_SHIFT 0 2442 2443 /**** q_gpio_5 register ****/ 2444 /* [i] - Mask for Q[i] */ 2445 #define EC_FC_UDMA_Q_GPIO_5_MASK_MASK 0x0000000F 2446 #define EC_FC_UDMA_Q_GPIO_5_MASK_SHIFT 0 2447 2448 /**** q_gpio_6 register ****/ 2449 /* [i] - Mask for Q[i] */ 2450 #define EC_FC_UDMA_Q_GPIO_6_MASK_MASK 0x0000000F 2451 #define EC_FC_UDMA_Q_GPIO_6_MASK_SHIFT 0 2452 2453 /**** q_gpio_7 register ****/ 2454 /* [i] - Mask for Q[i] */ 2455 #define EC_FC_UDMA_Q_GPIO_7_MASK_MASK 0x0000000F 2456 #define EC_FC_UDMA_Q_GPIO_7_MASK_SHIFT 0 2457 2458 /**** s_pause register ****/ 2459 /* Mask of pause_on [7:0] */ 2460 #define EC_FC_UDMA_S_PAUSE_MASK_MAC_MASK 0x000000FF 2461 #define EC_FC_UDMA_S_PAUSE_MASK_MAC_SHIFT 0 2462 /* Mask of GPIO input [7:0] */ 2463 #define EC_FC_UDMA_S_PAUSE_MASK_GPIO_MASK 0x0000FF00 2464 #define EC_FC_UDMA_S_PAUSE_MASK_GPIO_SHIFT 8 2465 2466 /**** q_xoff_0 register ****/ 2467 /* [i] - Mask for Q[i] */ 2468 #define EC_FC_UDMA_Q_XOFF_0_MASK_MASK 0x0000000F 2469 #define EC_FC_UDMA_Q_XOFF_0_MASK_SHIFT 0 2470 2471 /**** q_xoff_1 register ****/ 2472 /* [i] - Mask for Q[i] */ 2473 #define EC_FC_UDMA_Q_XOFF_1_MASK_MASK 0x0000000F 2474 #define EC_FC_UDMA_Q_XOFF_1_MASK_SHIFT 0 2475 2476 /**** q_xoff_2 register ****/ 2477 /* [i] - Mask for Q[i] */ 2478 #define EC_FC_UDMA_Q_XOFF_2_MASK_MASK 0x0000000F 2479 #define EC_FC_UDMA_Q_XOFF_2_MASK_SHIFT 0 2480 2481 /**** q_xoff_3 register ****/ 2482 /* [i] - Mask for Q[i] */ 2483 #define EC_FC_UDMA_Q_XOFF_3_MASK_MASK 0x0000000F 2484 #define EC_FC_UDMA_Q_XOFF_3_MASK_SHIFT 0 2485 2486 /**** q_xoff_4 register ****/ 2487 /* [i] - Mask for Q[i] */ 2488 #define EC_FC_UDMA_Q_XOFF_4_MASK_MASK 0x0000000F 2489 #define EC_FC_UDMA_Q_XOFF_4_MASK_SHIFT 0 2490 2491 /**** q_xoff_5 register ****/ 2492 /* [i] - Mask for Q[i] */ 2493 #define EC_FC_UDMA_Q_XOFF_5_MASK_MASK 0x0000000F 2494 #define EC_FC_UDMA_Q_XOFF_5_MASK_SHIFT 0 2495 2496 /**** q_xoff_6 register ****/ 2497 /* [i] - Mask for Q[i] */ 2498 #define EC_FC_UDMA_Q_XOFF_6_MASK_MASK 0x0000000F 2499 #define EC_FC_UDMA_Q_XOFF_6_MASK_SHIFT 0 2500 2501 /**** q_xoff_7 register ****/ 2502 /* [i] - Mask for Q[i] */ 2503 #define EC_FC_UDMA_Q_XOFF_7_MASK_MASK 0x0000000F 2504 #define EC_FC_UDMA_Q_XOFF_7_MASK_SHIFT 0 2505 2506 /**** cfg_e register ****/ 2507 /* Use MAC Tx FIFO empty status for EEE control. */ 2508 #define EC_EEE_CFG_E_USE_MAC_TX_FIFO (1 << 0) 2509 /* Use MAC Rx FIFO empty status for EEE control. */ 2510 #define EC_EEE_CFG_E_USE_MAC_RX_FIFO (1 << 1) 2511 /* Use Ethernet controller Tx FIFO empty status for EEE control */ 2512 #define EC_EEE_CFG_E_USE_EC_TX_FIFO (1 << 2) 2513 /* Use Ethernet controller Rx FIFO empty status for EEE control */ 2514 #define EC_EEE_CFG_E_USE_EC_RX_FIFO (1 << 3) 2515 /* Enable Low power signalling. */ 2516 #define EC_EEE_CFG_E_ENABLE (1 << 4) 2517 /* Mask output to MAC. */ 2518 #define EC_EEE_CFG_E_MASK_MAC_EEE (1 << 8) 2519 /* Mask output to stop MAC interface. */ 2520 #define EC_EEE_CFG_E_MASK_EC_TMI_STOP (1 << 9) 2521 2522 /**** stat_eee register ****/ 2523 /* EEE state */ 2524 #define EC_EEE_STAT_EEE_STATE_MASK 0x0000000F 2525 #define EC_EEE_STAT_EEE_STATE_SHIFT 0 2526 /* EEE detected */ 2527 #define EC_EEE_STAT_EEE_DET (1 << 4) 2528 2529 /**** p_parse_cfg register ****/ 2530 /* MAX number of beats for packet parsing */ 2531 #define EC_MSP_P_PARSE_CFG_MAX_BEATS_MASK 0x000000FF 2532 #define EC_MSP_P_PARSE_CFG_MAX_BEATS_SHIFT 0 2533 /* MAX number of parsing iterations for packet parsing */ 2534 #define EC_MSP_P_PARSE_CFG_MAX_ITER_MASK 0x0000FF00 2535 #define EC_MSP_P_PARSE_CFG_MAX_ITER_SHIFT 8 2536 2537 /**** p_act_table_addr register ****/ 2538 /* Address for accessing the table */ 2539 #define EC_MSP_P_ACT_TABLE_ADDR_VAL_MASK 0x0000001F 2540 #define EC_MSP_P_ACT_TABLE_ADDR_VAL_SHIFT 0 2541 2542 /**** p_act_table_data_1 register ****/ 2543 /* Table data[5:0] - Offset to next protocol [bytes] [6] - Next ... */ 2544 #define EC_MSP_P_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF 2545 #define EC_MSP_P_ACT_TABLE_DATA_1_VAL_SHIFT 0 2546 2547 /**** p_act_table_data_2 register ****/ 2548 /* Table data [8:0] - Offset to data in the packet [bits][17:9] ... */ 2549 #define EC_MSP_P_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF 2550 #define EC_MSP_P_ACT_TABLE_DATA_2_VAL_SHIFT 0 2551 2552 /**** p_act_table_data_3 register ****/ 2553 /* Table data [8:0] - Offset to data in the packet [bits] [17 ... */ 2554 #define EC_MSP_P_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF 2555 #define EC_MSP_P_ACT_TABLE_DATA_3_VAL_SHIFT 0 2556 2557 /**** p_act_table_data_4 register ****/ 2558 /* Table data [7:0] - Offset to the header length location in th ... */ 2559 #define EC_MSP_P_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF 2560 #define EC_MSP_P_ACT_TABLE_DATA_4_VAL_SHIFT 0 2561 2562 /**** p_act_table_data_6 register ****/ 2563 /* Table data [0] - Wr header length [10:1] - Write header lengt ... */ 2564 #define EC_MSP_P_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF 2565 #define EC_MSP_P_ACT_TABLE_DATA_6_VAL_SHIFT 0 2566 2567 /**** p_res_in register ****/ 2568 /* Selector for input parse_en 0 - Input vector 1 - Default valu ... */ 2569 #define EC_MSP_P_RES_IN_SEL_PARSE_EN (1 << 0) 2570 /* Selector for input protocol_index 0 - Input vector 1 - Defa ... */ 2571 #define EC_MSP_P_RES_IN_SEL_PROT_INDEX (1 << 1) 2572 /* Selector for input hdr_offset 0 - Input vector 1 - Default v ... */ 2573 #define EC_MSP_P_RES_IN_SEL_HDR_OFFSET (1 << 2) 2574 2575 /**** h_hdr_len register ****/ 2576 /* Value for selecting table 1 */ 2577 #define EC_MSP_P_H_HDR_LEN_TABLE_1_MASK 0x000000FF 2578 #define EC_MSP_P_H_HDR_LEN_TABLE_1_SHIFT 0 2579 /* Value for selecting table 2 */ 2580 #define EC_MSP_P_H_HDR_LEN_TABLE_2_MASK 0x00FF0000 2581 #define EC_MSP_P_H_HDR_LEN_TABLE_2_SHIFT 16 2582 2583 /**** p_comp_data register ****/ 2584 /* Data 1 for comparison */ 2585 #define EC_MSP_C_P_COMP_DATA_DATA_1_MASK 0x0000FFFF 2586 #define EC_MSP_C_P_COMP_DATA_DATA_1_SHIFT 0 2587 /* Data 2 for comparison 2588 [18:16] - Stage 2589 [24:19] - Branch ID */ 2590 #define EC_MSP_C_P_COMP_DATA_DATA_2_MASK 0x01FF0000 2591 #define EC_MSP_C_P_COMP_DATA_DATA_2_SHIFT 16 2592 2593 /**** p_comp_mask register ****/ 2594 /* Data 1 for comparison */ 2595 #define EC_MSP_C_P_COMP_MASK_DATA_1_MASK 0x0000FFFF 2596 #define EC_MSP_C_P_COMP_MASK_DATA_1_SHIFT 0 2597 /* Data 2 for comparison 2598 [18:16] - Stage 2599 [24:19] - Branch ID */ 2600 #define EC_MSP_C_P_COMP_MASK_DATA_2_MASK 0x01FF0000 2601 #define EC_MSP_C_P_COMP_MASK_DATA_2_SHIFT 16 2602 2603 /**** p_comp_ctrl register ****/ 2604 /* Output result value */ 2605 #define EC_MSP_C_P_COMP_CTRL_RES_MASK 0x0000001F 2606 #define EC_MSP_C_P_COMP_CTRL_RES_SHIFT 0 2607 /* Compare command for the data_1 field 00 - Compare 01 - <= 10 ... */ 2608 #define EC_MSP_C_P_COMP_CTRL_CMD_1_MASK 0x00030000 2609 #define EC_MSP_C_P_COMP_CTRL_CMD_1_SHIFT 16 2610 /* Compare command for the data_2 field 00 - Compare 01 - <= 10 ... */ 2611 #define EC_MSP_C_P_COMP_CTRL_CMD_2_MASK 0x000C0000 2612 #define EC_MSP_C_P_COMP_CTRL_CMD_2_SHIFT 18 2613 /* Entry is valid */ 2614 #define EC_MSP_C_P_COMP_CTRL_VALID (1 << 31) 2615 2616 /**** wol_en register ****/ 2617 /* Interrupt enable WoL MAC DA Unicast detected packet */ 2618 #define EC_WOL_WOL_EN_INTRPT_EN_UNICAST (1 << 0) 2619 /* Interrupt enable WoL L2 Multicast detected packet */ 2620 #define EC_WOL_WOL_EN_INTRPT_EN_MULTICAST (1 << 1) 2621 /* Interrupt enable WoL L2 Broadcast detected packet */ 2622 #define EC_WOL_WOL_EN_INTRPT_EN_BROADCAST (1 << 2) 2623 /* Interrupt enable WoL IPv4 detected packet */ 2624 #define EC_WOL_WOL_EN_INTRPT_EN_IPV4 (1 << 3) 2625 /* Interrupt enable WoL IPv6 detected packet */ 2626 #define EC_WOL_WOL_EN_INTRPT_EN_IPV6 (1 << 4) 2627 /* Interrupt enable WoL EtherType+MAC DA detected packet */ 2628 #define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_DA (1 << 5) 2629 /* Interrupt enable WoL EtherType+L2 Broadcast detected packet */ 2630 #define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_BC (1 << 6) 2631 /* Interrupt enable WoL parser detected packet */ 2632 #define EC_WOL_WOL_EN_INTRPT_EN_PARSER (1 << 7) 2633 /* Interrupt enable WoL magic detected packet */ 2634 #define EC_WOL_WOL_EN_INTRPT_EN_MAGIC (1 << 8) 2635 /* Interrupt enable WoL magic+password detected packet */ 2636 #define EC_WOL_WOL_EN_INTRPT_EN_MAGIC_PSWD (1 << 9) 2637 /* Forward enable WoL MAC DA Unicast detected packet */ 2638 #define EC_WOL_WOL_EN_FWRD_EN_UNICAST (1 << 16) 2639 /* Forward enable WoL L2 Multicast detected packet */ 2640 #define EC_WOL_WOL_EN_FWRD_EN_MULTICAST (1 << 17) 2641 /* Forward enable WoL L2 Broadcast detected packet */ 2642 #define EC_WOL_WOL_EN_FWRD_EN_BROADCAST (1 << 18) 2643 /* Forward enable WoL IPv4 detected packet */ 2644 #define EC_WOL_WOL_EN_FWRD_EN_IPV4 (1 << 19) 2645 /* Forward enable WoL IPv6 detected packet */ 2646 #define EC_WOL_WOL_EN_FWRD_EN_IPV6 (1 << 20) 2647 /* Forward enable WoL EtherType+MAC DA detected packet */ 2648 #define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_DA (1 << 21) 2649 /* Forward enable WoL EtherType+L2 Broadcast detected packet */ 2650 #define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_BC (1 << 22) 2651 /* Forward enable WoL parser detected packet */ 2652 #define EC_WOL_WOL_EN_FWRD_EN_PARSER (1 << 23) 2653 2654 /**** magic_pswd_h register ****/ 2655 /* Password for magic_password packet detection - bits 47:32 */ 2656 #define EC_WOL_MAGIC_PSWD_H_VAL_MASK 0x0000FFFF 2657 #define EC_WOL_MAGIC_PSWD_H_VAL_SHIFT 0 2658 2659 /**** ethertype register ****/ 2660 /* Configured EtherType 1 for WoL EtherType_da/EtherType_bc pack ... */ 2661 #define EC_WOL_ETHERTYPE_VAL_1_MASK 0x0000FFFF 2662 #define EC_WOL_ETHERTYPE_VAL_1_SHIFT 0 2663 /* Configured EtherType 2 for WoL EtherType_da/EtherType_bc pack ... */ 2664 #define EC_WOL_ETHERTYPE_VAL_2_MASK 0xFFFF0000 2665 #define EC_WOL_ETHERTYPE_VAL_2_SHIFT 16 2666 2667 #define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2668 #define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_SHIFT 14 2669 2670 #define EC_PTH_CLOCK_PERIOD_LSB_VAL_MASK 0xFFFFC000 2671 #define EC_PTH_CLOCK_PERIOD_LSB_VAL_SHIFT 14 2672 2673 /**** int_update_ctrl register ****/ 2674 /* This field chooses between two methods for SW to update the s ... */ 2675 #define EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG (1 << 0) 2676 /* 3'b000 - Set system time according to the value in {int_updat ... */ 2677 #define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E 2678 #define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1 2679 /* 1'b1 - Next update writes to system_time_subseconds1'b0 - Nex ... */ 2680 #define EC_PTH_INT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4) 2681 /* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */ 2682 #define EC_PTH_INT_UPDATE_CTRL_SECOND_MASK (1 << 5) 2683 /* Enabling / disabling the internal ingress trigger (ingress_tr ... */ 2684 #define EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN (1 << 16) 2685 /* Determines if internal ingress trigger (ingress_trigger #0) s ... */ 2686 #define EC_PTH_INT_UPDATE_CTRL_PULSE_LEVEL_N (1 << 17) 2687 /* Internal ingress trigger polarity (ingress_trigger #0)1'b0 - ... */ 2688 #define EC_PTH_INT_UPDATE_CTRL_POLARITY (1 << 18) 2689 2690 /**** int_update_subseconds_lsb register ****/ 2691 2692 #define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF 2693 #define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0 2694 2695 #define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2696 #define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14 2697 /* 3'b000 - Set system time according to the value in {int_updat ... */ 2698 #define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E 2699 #define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1 2700 /* 1'b1 - next update writes to system_time_subseconds1'b0 - nex ... */ 2701 #define EC_PTH_EXT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4) 2702 /* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */ 2703 #define EC_PTH_EXT_UPDATE_CTRL_SECOND_MASK (1 << 5) 2704 /* Enabling / disabling the external ingress triggers (ingress_t ... */ 2705 #define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK 0x00001F00 2706 #define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_SHIFT 8 2707 /* Determines if external ingress triggers (ingress_triggers #1- ... */ 2708 #define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_MASK 0x001F0000 2709 #define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_SHIFT 16 2710 /* bit-field configurations of external ingress trigger polarity ... */ 2711 #define EC_PTH_EXT_UPDATE_CTRL_POLARITY_MASK 0x1F000000 2712 #define EC_PTH_EXT_UPDATE_CTRL_POLARITY_SHIFT 24 2713 2714 /**** ext_update_subseconds_lsb register ****/ 2715 2716 #define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF 2717 #define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0 2718 2719 #define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2720 #define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14 2721 2722 #define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2723 #define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14 2724 2725 #define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2726 #define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14 2727 2728 #define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2729 #define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14 2730 2731 #define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2732 #define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14 2733 2734 /**** trigger_ctrl register ****/ 2735 /* Enabling / disabling the egress trigger1'b1 - Enabled1'b0 - D ... */ 2736 #define EC_PTH_EGRESS_TRIGGER_CTRL_EN (1 << 0) 2737 /* Configuration that determines if the egress trigger is a peri ... */ 2738 #define EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC (1 << 1) 2739 /* Configuration of egress trigger polarity */ 2740 #define EC_PTH_EGRESS_TRIGGER_CTRL_POLARITY (1 << 2) 2741 /* If the pulse is marked as periodic (see periodic field), this ... */ 2742 #define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK 0x00FFFFF0 2743 #define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_SHIFT 4 2744 /* If the pulse is marked as periodic (see periodic field), this ... */ 2745 #define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK 0xFF000000 2746 #define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_SHIFT 24 2747 2748 /**** trigger_subseconds_lsb register ****/ 2749 2750 #define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF 2751 #define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0 2752 2753 #define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2754 #define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_SHIFT 14 2755 2756 /**** pulse_width_subseconds_lsb register ****/ 2757 2758 #define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF 2759 #define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0 2760 2761 #define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000 2762 #define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_SHIFT 14 2763 2764 /**** qual register ****/ 2765 2766 #define EC_PTH_DB_QUAL_TS_VALID (1 << 0) 2767 2768 #define EC_PTH_DB_QUAL_RESERVED_31_1_MASK 0xFFFFFFFE 2769 #define EC_PTH_DB_QUAL_RESERVED_31_1_SHIFT 1 2770 2771 /**** rx_comp_desc register ****/ 2772 /* Selection for word0[13]:0- legacy SR-A01- per generic protoco ... */ 2773 #define EC_GEN_V3_RX_COMP_DESC_W0_L3_CKS_RES_SEL (1 << 0) 2774 /* Selection for word0[14]:0- legacy SR-A01- per generic protoco ... */ 2775 #define EC_GEN_V3_RX_COMP_DESC_W0_L4_CKS_RES_SEL (1 << 1) 2776 /* Selection for word3[29]:0-macsec decryption status[13] (legac ... */ 2777 #define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_13_L4_CKS_RES_SEL (1 << 8) 2778 /* Selection for word3[30]:0-macsec decryption status[14] (legac ... */ 2779 #define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_14_L3_CKS_RES_SEL (1 << 9) 2780 /* Selection for word3[31]:0-macsec decryption status[15] (legac ... */ 2781 #define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_15_CRC_RES_SEL (1 << 10) 2782 /* Selection for word 0 [6:5], source VLAN count0- source vlan c ... */ 2783 #define EC_GEN_V3_RX_COMP_DESC_W0_SRC_VLAN_CNT (1 << 12) 2784 /* Selection for word 0 [4:0], l3 protocol index0- l3 protocol ... */ 2785 #define EC_GEN_V3_RX_COMP_DESC_W0_L3_PROT_INDEX (1 << 13) 2786 /* Selection for word 1 [31:16], lP fragment checksum0- IP frag ... */ 2787 #define EC_GEN_V3_RX_COMP_DESC_W1_IP_FRAG_CHECKSUM (1 << 14) 2788 /* Selection for word 2 [15:9], L3 offset0- LL3 offset1- CRC re ... */ 2789 #define EC_GEN_V3_RX_COMP_DESC_W2_L3_OFFSET (1 << 15) 2790 /* Selection for word 2 [8:0], tunnel offset0- tunnel offset1- ... */ 2791 #define EC_GEN_V3_RX_COMP_DESC_W2_TUNNEL_OFFSET (1 << 16) 2792 2793 /**** conf register ****/ 2794 /* Valid signal configuration when in loopback mode:00 - valid f ... */ 2795 #define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_MASK 0x00000003 2796 #define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_SHIFT 0 2797 /* Valid signal configuration when in loopback mode:00 – valid f ... */ 2798 #define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_MASK 0x0000000C 2799 #define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_SHIFT 2 2800 2801 /**** tx_gpd_cam_addr register ****/ 2802 /* Cam compare table address */ 2803 #define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_MASK 0x0000001F 2804 #define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_SHIFT 0 2805 /* cam entry is valid */ 2806 #define EC_TFW_V3_TX_GPD_CAM_CTRL_VALID (1 << 31) 2807 2808 /**** tx_gcp_legacy register ****/ 2809 /* 0-choose parameters from table1- choose legacy crce roce para ... */ 2810 #define EC_TFW_V3_TX_GCP_LEGACY_PARAM_SEL (1 << 0) 2811 2812 /**** tx_gcp_table_addr register ****/ 2813 /* parametrs table address */ 2814 #define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F 2815 #define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_SHIFT 0 2816 2817 /**** tx_gcp_table_gen register ****/ 2818 /* polynomial selcet 2819 0-crc32(0x104C11DB7) 2820 1-crc32c(0x11EDC6F41) */ 2821 #define EC_TFW_V3_TX_GCP_TABLE_GEN_POLY_SEL (1 << 0) 2822 /* Enable bit complement on crc result */ 2823 #define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1) 2824 /* Enable bit swap on crc result */ 2825 #define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2) 2826 /* Enable byte swap on crc result */ 2827 #define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3) 2828 /* Enable bit swap on input data */ 2829 #define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4) 2830 /* Enable byte swap on input data */ 2831 #define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5) 2832 /* Number of bytes in trailer which are not part of crc calculat ... */ 2833 #define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0 2834 #define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6 2835 /* Number of bytes in header which are not part of crc calculati ... */ 2836 #define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000 2837 #define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16 2838 /* corrected offset calculation0- subtract head_size (roce)1- ad ... */ 2839 #define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_CALC (1 << 24) 2840 /* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */ 2841 #define EC_TFW_V3_TX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25) 2842 2843 /**** tx_gcp_table_res register ****/ 2844 /* Not in use */ 2845 #define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_MASK 0x0000001F 2846 #define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_SHIFT 0 2847 /* Not in use */ 2848 #define EC_TFW_V3_TX_GCP_TABLE_RES_EN (1 << 5) 2849 /* Not in use */ 2850 #define EC_TFW_V3_TX_GCP_TABLE_RES_DEF (1 << 6) 2851 2852 /**** tx_gcp_table_alu_opcode register ****/ 2853 /* first opcode 2854 e.g. (A op1 B) op3 (C op2 D) */ 2855 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F 2856 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0 2857 /* second opcode 2858 e.g. (A op1 B) op3 (C op2 D) */ 2859 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0 2860 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6 2861 /* third opcode 2862 e.g. (A op1 B) op3 (C op2 D) */ 2863 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000 2864 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12 2865 2866 /**** tx_gcp_table_alu_opsel register ****/ 2867 /* frst opsel, input selection */ 2868 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F 2869 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0 2870 /* second opsel, input selection */ 2871 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0 2872 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4 2873 /* third opsel, input selction */ 2874 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00 2875 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8 2876 /* fourth opsel, input selction */ 2877 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000 2878 #define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12 2879 2880 /**** tx_gcp_table_alu_val register ****/ 2881 /* value for alu input */ 2882 #define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF 2883 #define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0 2884 2885 /**** crc_csum_replace register ****/ 2886 /* 0- use table 2887 1- legacy SR-A0 */ 2888 #define EC_TFW_V3_CRC_CSUM_REPLACE_L3_CSUM_LEGACY_SEL (1 << 0) 2889 /* 0- use table 2890 1- legacy SR-A0 */ 2891 #define EC_TFW_V3_CRC_CSUM_REPLACE_L4_CSUM_LEGACY_SEL (1 << 1) 2892 /* 0- use table 2893 1- legacy SR-A0 */ 2894 #define EC_TFW_V3_CRC_CSUM_REPLACE_CRC_LEGACY_SEL (1 << 2) 2895 2896 /**** crc_csum_replace_table_addr register ****/ 2897 /* parametrs table address */ 2898 #define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_MASK 0x0000007F 2899 #define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_SHIFT 0 2900 2901 /**** crc_csum_replace_table register ****/ 2902 /* L3 Checksum replace enable */ 2903 #define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L3_CSUM_EN (1 << 0) 2904 /* L4 Checksum replace enable */ 2905 #define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L4_CSUM_EN (1 << 1) 2906 /* CRC replace enable */ 2907 #define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_CRC_EN (1 << 2) 2908 2909 /**** rx_gpd_cam_addr register ****/ 2910 /* Cam compare table address */ 2911 #define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_MASK 0x0000001F 2912 #define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_SHIFT 0 2913 /* cam entry is valid */ 2914 #define EC_RFW_V3_RX_GPD_CAM_CTRL_VALID (1 << 31) 2915 2916 /**** gpd_p1 register ****/ 2917 /* Location in bytes of the gpd cam data1 in the parser result v ... */ 2918 #define EC_RFW_V3_GPD_P1_OFFSET_MASK 0x000003FF 2919 #define EC_RFW_V3_GPD_P1_OFFSET_SHIFT 0 2920 2921 /**** gpd_p2 register ****/ 2922 /* Location in bytes of the gpd cam data2 in the parser result v ... */ 2923 #define EC_RFW_V3_GPD_P2_OFFSET_MASK 0x000003FF 2924 #define EC_RFW_V3_GPD_P2_OFFSET_SHIFT 0 2925 2926 /**** gpd_p3 register ****/ 2927 /* Location in bytes of the gpd cam data3 in the parser result v ... */ 2928 #define EC_RFW_V3_GPD_P3_OFFSET_MASK 0x000003FF 2929 #define EC_RFW_V3_GPD_P3_OFFSET_SHIFT 0 2930 2931 /**** gpd_p4 register ****/ 2932 /* Location in bytes of the gpd cam data4 in the parser result v ... */ 2933 #define EC_RFW_V3_GPD_P4_OFFSET_MASK 0x000003FF 2934 #define EC_RFW_V3_GPD_P4_OFFSET_SHIFT 0 2935 2936 /**** gpd_p5 register ****/ 2937 /* Location in bytes of the gpd cam data5 in the parser result v ... */ 2938 #define EC_RFW_V3_GPD_P5_OFFSET_MASK 0x000003FF 2939 #define EC_RFW_V3_GPD_P5_OFFSET_SHIFT 0 2940 2941 /**** gpd_p6 register ****/ 2942 /* Location in bytes of the gpd cam data6 in the parser result v ... */ 2943 #define EC_RFW_V3_GPD_P6_OFFSET_MASK 0x000003FF 2944 #define EC_RFW_V3_GPD_P6_OFFSET_SHIFT 0 2945 2946 /**** gpd_p7 register ****/ 2947 /* Location in bytes of the gpd cam data7 in the parser result v ... */ 2948 #define EC_RFW_V3_GPD_P7_OFFSET_MASK 0x000003FF 2949 #define EC_RFW_V3_GPD_P7_OFFSET_SHIFT 0 2950 2951 /**** gpd_p8 register ****/ 2952 /* Location in bytes of the gpd cam data8 in the parser result v ... */ 2953 #define EC_RFW_V3_GPD_P8_OFFSET_MASK 0x000003FF 2954 #define EC_RFW_V3_GPD_P8_OFFSET_SHIFT 0 2955 2956 /**** rx_gcp_legacy register ****/ 2957 /* 0-choose parameters from table1- choose legacy crce roce para ... */ 2958 #define EC_RFW_V3_RX_GCP_LEGACY_PARAM_SEL (1 << 0) 2959 2960 /**** rx_gcp_table_addr register ****/ 2961 /* parametrs table address */ 2962 #define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F 2963 #define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_SHIFT 0 2964 2965 /**** rx_gcp_table_gen register ****/ 2966 /* polynomial selcet 2967 0-crc32(0x104C11DB7) 2968 1-crc32c(0x11EDC6F41) */ 2969 #define EC_RFW_V3_RX_GCP_TABLE_GEN_POLY_SEL (1 << 0) 2970 /* Enable bit complement on crc result */ 2971 #define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1) 2972 /* Enable bit swap on crc result */ 2973 #define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2) 2974 /* Enable byte swap on crc result */ 2975 #define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3) 2976 /* Enable bit swap on input data */ 2977 #define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4) 2978 /* Enable byte swap on input data */ 2979 #define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5) 2980 /* Number of bytes in trailer which are not part of crc calculat ... */ 2981 #define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0 2982 #define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6 2983 /* Number of bytes in header which are not part of crc calculati ... */ 2984 #define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000 2985 #define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16 2986 /* corrected offset calculation0- subtract head_size (roce)1- ad ... */ 2987 #define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_CALC (1 << 24) 2988 /* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */ 2989 #define EC_RFW_V3_RX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25) 2990 2991 /**** rx_gcp_table_res register ****/ 2992 /* Bit mask for crc/checksum result options for metadata W0[13][ ... */ 2993 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_MASK 0x0000001F 2994 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_SHIFT 0 2995 /* Bit mask for crc/checksum result options for metadata W0[14][ ... */ 2996 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_MASK 0x000003E0 2997 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_SHIFT 5 2998 /* Bit mask for crc/checksum result options for metadata W3[29][ ... */ 2999 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_MASK 0x00007C00 3000 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_SHIFT 10 3001 /* Bit mask for crc/checksum result options for metadata W3[30][ ... */ 3002 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_MASK 0x000F8000 3003 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_SHIFT 15 3004 /* Bit mask for crc/checksum result options for metadata W3[31][ ... */ 3005 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_MASK 0x01F00000 3006 #define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_SHIFT 20 3007 /* enable crc result check */ 3008 #define EC_RFW_V3_RX_GCP_TABLE_RES_EN (1 << 25) 3009 /* default value for crc check for non-crc protocol */ 3010 #define EC_RFW_V3_RX_GCP_TABLE_RES_DEF (1 << 26) 3011 3012 /**** rx_gcp_table_alu_opcode register ****/ 3013 /* first opcode 3014 e.g. (A op1 B) op3 (C op2 D) */ 3015 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F 3016 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0 3017 /* second opcode 3018 e.g. (A op1 B) op3 (C op2 D) */ 3019 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0 3020 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6 3021 /* third opcode 3022 e.g. (A op1 B) op3 (C op2 D) */ 3023 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000 3024 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12 3025 3026 /**** rx_gcp_table_alu_opsel register ****/ 3027 /* frst opsel, input selection */ 3028 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F 3029 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0 3030 /* second opsel, input selection */ 3031 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0 3032 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4 3033 /* third opsel, input selction */ 3034 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00 3035 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8 3036 /* fourth opsel, input selction */ 3037 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000 3038 #define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12 3039 3040 /**** rx_gcp_table_alu_val register ****/ 3041 /* value for alu input */ 3042 #define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF 3043 #define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0 3044 3045 /**** rx_gcp_alu_p1 register ****/ 3046 /* Location in bytes of field 1 in the parser result vector */ 3047 #define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_MASK 0x000003FF 3048 #define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_SHIFT 0 3049 /* Right shift for field 1 in the parser result vector */ 3050 #define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_MASK 0x000F0000 3051 #define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_SHIFT 16 3052 3053 /**** rx_gcp_alu_p2 register ****/ 3054 /* Location in bytes of field 2 in the parser result vector */ 3055 #define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_MASK 0x000003FF 3056 #define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_SHIFT 0 3057 /* Right shift for field 2 in the parser result vector */ 3058 #define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_MASK 0x000F0000 3059 #define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_SHIFT 16 3060 3061 /**** hs_ctrl_table_addr register ****/ 3062 /* Header split control table address */ 3063 #define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_MASK 0x000000FF 3064 #define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_SHIFT 0 3065 3066 /**** hs_ctrl_table register ****/ 3067 /* Header split length select */ 3068 #define EC_RFW_V3_HS_CTRL_TABLE_SEL_MASK 0x00000003 3069 #define EC_RFW_V3_HS_CTRL_TABLE_SEL_SHIFT 0 3070 /* enable header split */ 3071 #define EC_RFW_V3_HS_CTRL_TABLE_ENABLE (1 << 2) 3072 3073 /**** hs_ctrl_table_alu_opcode register ****/ 3074 /* first opcode 3075 e.g. (A op1 B) op3 (C op2 D) */ 3076 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F 3077 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0 3078 /* second opcode 3079 e.g. (A op1 B) op3 (C op2 D) */ 3080 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0 3081 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6 3082 /* third opcode 3083 e.g. (A op1 B) op3 (C op2 D) */ 3084 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000 3085 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12 3086 3087 /**** hs_ctrl_table_alu_opsel register ****/ 3088 /* frst opsel, input selection */ 3089 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F 3090 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0 3091 /* second opsel, input selection */ 3092 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0 3093 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4 3094 /* third opsel, input selction */ 3095 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00 3096 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8 3097 /* fourth opsel, input selction */ 3098 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000 3099 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12 3100 3101 /**** hs_ctrl_table_alu_val register ****/ 3102 /* value for alu input */ 3103 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_MASK 0x0000FFFF 3104 #define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_SHIFT 0 3105 3106 /**** hs_ctrl_cfg register ****/ 3107 /* Header split enable static selction0 – legacy1 – header split ... */ 3108 #define EC_RFW_V3_HS_CTRL_CFG_ENABLE_SEL (1 << 0) 3109 /* Header split length static selction0 – legacy1 – header split ... */ 3110 #define EC_RFW_V3_HS_CTRL_CFG_LENGTH_SEL (1 << 1) 3111 3112 /**** hs_ctrl_alu_p1 register ****/ 3113 /* Location in bytes of field 1 in the parser result vector */ 3114 #define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_MASK 0x000003FF 3115 #define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_SHIFT 0 3116 /* Right shift for field 1 in the parser result vector */ 3117 #define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_MASK 0x000F0000 3118 #define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_SHIFT 16 3119 3120 /**** hs_ctrl_alu_p2 register ****/ 3121 /* Location in bytes of field 2 in the parser result vector */ 3122 #define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_MASK 0x000003FF 3123 #define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_SHIFT 0 3124 /* Right shift for field 2 in the parser result vector */ 3125 #define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_MASK 0x000F0000 3126 #define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_SHIFT 16 3127 3128 /**** tx_config register ****/ 3129 /* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */ 3130 #define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F 3131 #define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0 3132 /* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */ 3133 #define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00 3134 #define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8 3135 /* direction flip, used in order to use same TID entry for both TX & RX traffic */ 3136 #define EC_CRYPTO_TX_CONFIG_CRYPTO_DIR_FLIP (1 << 14) 3137 /* Enabling pipe line optimization */ 3138 #define EC_CRYPTO_TX_CONFIG_PIPE_CALC_EN (1 << 16) 3139 /* enable performance counters */ 3140 #define EC_CRYPTO_TX_CONFIG_PERF_CNT_EN (1 << 17) 3141 /* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */ 3142 #define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000 3143 #define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20 3144 /* [0] pre aes key word swap[1] pre aes key byte swap[2] pre aes ... */ 3145 #define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000 3146 #define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26 3147 3148 /**** rx_config register ****/ 3149 /* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */ 3150 #define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F 3151 #define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0 3152 /* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */ 3153 #define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00 3154 #define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8 3155 /* direction flip, used in order to use same TID entry for both TX & RX traffic */ 3156 #define EC_CRYPTO_RX_CONFIG_CRYPTO_DIR_FLIP (1 << 14) 3157 /* Enabling pipe line optimization */ 3158 #define EC_CRYPTO_RX_CONFIG_PIPE_CALC_EN (1 << 16) 3159 /* enable performance counters */ 3160 #define EC_CRYPTO_RX_CONFIG_PERF_CNT_EN (1 << 17) 3161 /* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */ 3162 #define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000 3163 #define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20 3164 /* [0] data aes key word swap[1] data aes key byte swap[2] data ... */ 3165 #define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000 3166 #define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26 3167 3168 /**** tx_override register ****/ 3169 /* all transactions are encrypted */ 3170 #define EC_CRYPTO_TX_OVERRIDE_ENCRYPT_ONLY (1 << 0) 3171 /* all transactions are decrypted */ 3172 #define EC_CRYPTO_TX_OVERRIDE_DECRYPT_ONLY (1 << 1) 3173 /* all pkts use IV */ 3174 #define EC_CRYPTO_TX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2) 3175 /* no pkt uses IV */ 3176 #define EC_CRYPTO_TX_OVERRIDE_NEVER_DRIVE_IV (1 << 3) 3177 /* all pkts perform authentication calculation */ 3178 #define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4) 3179 /* no pkt performs authentication calculation */ 3180 #define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5) 3181 /* all pkts perform encryption calculation */ 3182 #define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6) 3183 /* no pkt performs encryption calculation */ 3184 #define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7) 3185 /* Enforce pkt trimming 3186 bit[0] relates to metadata_pkt_trim 3187 bit[1] relates to trailer_pkt_trime 3188 bit[2] relates to sign_trim 3189 bit[3] relates to aes_padding_trim */ 3190 #define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00 3191 #define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8 3192 /* Enforce no pkt trimming 3193 bit[0] relates to metadata_pkt_trim 3194 bit[1] relates to trailer_pkt_trime 3195 bit[2] relates to sign_trim 3196 bit[3] relates to aes_padding_trim */ 3197 #define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000 3198 #define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12 3199 /* chicken bit to disable metadata handling optimization */ 3200 #define EC_CRYPTO_TX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 16) 3201 3202 /**** rx_override register ****/ 3203 /* all transactions are encrypted */ 3204 #define EC_CRYPTO_RX_OVERRIDE_ENCRYPT_ONLY (1 << 0) 3205 /* all transactions are decrypted */ 3206 #define EC_CRYPTO_RX_OVERRIDE_DECRYPT_ONLY (1 << 1) 3207 /* all pkts use IV */ 3208 #define EC_CRYPTO_RX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2) 3209 /* no pkt uses IV */ 3210 #define EC_CRYPTO_RX_OVERRIDE_NEVER_DRIVE_IV (1 << 3) 3211 /* all pkts perform authentication calculation */ 3212 #define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4) 3213 /* no pkt performs authentication calculation */ 3214 #define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5) 3215 /* all pkts perform encryption calculation */ 3216 #define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6) 3217 /* no pkt performs encryption calculation */ 3218 #define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7) 3219 /* Enforce pkt trimming 3220 bit[0] relates to metadata_pkt_trim 3221 bit[1] relates to trailer_pkt_trime 3222 bit[2] relates to sign_trim 3223 bit[3] relates to aes_padding_trim */ 3224 #define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00 3225 #define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8 3226 /* Enforce no pkt trimming 3227 bit[0] relates to metadata_pkt_trim 3228 bit[1] relates to trailer_pkt_trime 3229 bit[2] relates to sign_trim 3230 bit[3] relates to aes_padding_trim */ 3231 #define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000 3232 #define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12 3233 /* bit enable for writing to rx_cmpl metadata info */ 3234 #define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_MASK 0x00070000 3235 #define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_SHIFT 16 3236 /* chicken bit to disable metadata handling optimization */ 3237 #define EC_CRYPTO_RX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 19) 3238 /* crypto metadata offset in the rx cmpl_desc */ 3239 #define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_MASK 0x07F00000 3240 #define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_SHIFT 20 3241 3242 /**** tx_enc_iv_construction register ****/ 3243 /* for each IV byte, select between src1 & src2. Src1 & src2 ... */ 3244 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF 3245 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0 3246 /* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 f... */ 3247 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000 3248 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16 3249 /* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 ... */ 3250 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000 3251 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18 3252 /* Per-byte mux select taken from Crypto table (otherwise ... */ 3253 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20) 3254 /* [0] word swap en 3255 [1] byte swap en 3256 [2] bit swap en */ 3257 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000 3258 #define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21 3259 3260 /**** rx_enc_iv_construction register ****/ 3261 /* for each IV byte, select between src1 & src2. Src1 & src2 ... */ 3262 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF 3263 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0 3264 /* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 – ... */ 3265 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000 3266 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16 3267 /* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 – ... */ 3268 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000 3269 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18 3270 /* Per-byte mux select taken from Crypto table (otherwise from ... */ 3271 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20) 3272 /* [0] word swap en 3273 [1] byte swap en 3274 [2] bit swap en */ 3275 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000 3276 #define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21 3277 3278 /**** rx_enc_iv_map register ****/ 3279 /* [0] word swap en 3280 [1] byte swap en 3281 [2] bit swap en */ 3282 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_MASK 0x0000001F 3283 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_SHIFT 0 3284 /* number of valid bytes in word, as generated by field extract ... */ 3285 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_MASK 0x000000E0 3286 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_SHIFT 5 3287 /* [0] word swap en 3288 [1] byte swap en 3289 [2] bit swap en */ 3290 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_MASK 0x00001F00 3291 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_SHIFT 8 3292 /* number of valid bytes in word, as generated by field extract ... */ 3293 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_MASK 0x0000E000 3294 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_SHIFT 13 3295 /* [0] word swap en 3296 [1] byte swap en 3297 [2] bit swap en */ 3298 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_MASK 0x001F0000 3299 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_SHIFT 16 3300 /* number of valid bytes in word, as generated by field extract ... */ 3301 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_MASK 0x00E00000 3302 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_SHIFT 21 3303 /* [0] word swap en 3304 [1] byte swap en 3305 [2] bit swap en */ 3306 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_MASK 0x1F000000 3307 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_SHIFT 24 3308 /* number of valid bytes in word, as generated by field extract ... */ 3309 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_MASK 0xE0000000 3310 #define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_SHIFT 29 3311 3312 /**** tx_pkt_trim_len register ****/ 3313 /* metadata shift-reg length */ 3314 #define EC_CRYPTO_TX_PKT_TRIM_LEN_META_MASK 0x00000007 3315 #define EC_CRYPTO_TX_PKT_TRIM_LEN_META_SHIFT 0 3316 /* pkt trailer shift-reg length */ 3317 #define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0 3318 #define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_SHIFT 4 3319 /* sign shift-reg length */ 3320 #define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_MASK 0x00000300 3321 #define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_SHIFT 8 3322 /* crypto padding shift-reg length */ 3323 #define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000 3324 #define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12 3325 /* hardware chooses shift-registers configurations automatically – no need for sw configuration */ 3326 #define EC_CRYPTO_TX_PKT_TRIM_LEN_AUTO_MODE (1 << 16) 3327 3328 /**** rx_pkt_trim_len register ****/ 3329 /* metadata shift-reg length */ 3330 #define EC_CRYPTO_RX_PKT_TRIM_LEN_META_MASK 0x00000007 3331 #define EC_CRYPTO_RX_PKT_TRIM_LEN_META_SHIFT 0 3332 /* pkt trailer shift-reg length */ 3333 #define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0 3334 #define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_SHIFT 4 3335 /* sign shift-reg length */ 3336 #define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_MASK 0x00000300 3337 #define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_SHIFT 8 3338 /* crypto padding shift-reg length */ 3339 #define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000 3340 #define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12 3341 /* hardware chooses shift-registers configurations automatically – no need for sw configuration */ 3342 #define EC_CRYPTO_RX_PKT_TRIM_LEN_AUTO_MODE (1 << 16) 3343 3344 /**** total_tx_secured_pkts_cipher_mode_cmpr register ****/ 3345 3346 #define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F 3347 #define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0 3348 3349 /**** total_rx_secured_pkts_cipher_mode_cmpr register ****/ 3350 3351 #define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F 3352 #define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0 3353 3354 #ifdef __cplusplus 3355 } 3356 #endif 3357 3358 #endif /* __AL_HAL_EC_REG_H */ 3359 3360 /** @} end of ... group */ 3361 3362 3363