1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @defgroup group_eth_api API 39 * Ethernet Controller HAL driver API 40 * @ingroup group_eth 41 * @{ 42 * @file al_hal_eth.h 43 * 44 * @brief Header file for Unified GbE and 10GbE Ethernet Controllers This is a 45 * common header file that covers both Standard and Advanced Controller 46 * 47 * 48 */ 49 50 #ifndef __AL_HAL_ETH_H__ 51 #define __AL_HAL_ETH_H__ 52 53 #include "al_hal_common.h" 54 #include "al_hal_udma.h" 55 #include "al_hal_eth_alu.h" 56 #ifdef AL_ETH_EX 57 #include "al_hal_eth_ex.h" 58 #include "al_hal_eth_ex_internal.h" 59 #endif 60 61 /* *INDENT-OFF* */ 62 #ifdef __cplusplus 63 extern "C" { 64 #endif 65 /* *INDENT-ON* */ 66 67 #ifndef AL_ETH_PKT_MAX_BUFS 68 #ifndef AL_ETH_EX 69 #define AL_ETH_PKT_MAX_BUFS 19 70 #else 71 #define AL_ETH_PKT_MAX_BUFS 30 72 #endif 73 #endif 74 75 #define AL_ETH_UDMA_TX_QUEUES 4 76 #define AL_ETH_UDMA_RX_QUEUES 4 77 78 /* PCI Adapter Device/Revision ID */ 79 #define AL_ETH_DEV_ID_STANDARD 0x0001 80 #define AL_ETH_DEV_ID_ADVANCED 0x0002 81 #define AL_ETH_REV_ID_0 0 /* Alpine V1 Rev 0 */ 82 #define AL_ETH_REV_ID_1 1 /* Alpine V1 Rev 1 */ 83 #define AL_ETH_REV_ID_2 2 /* Alpine V2 basic */ 84 #define AL_ETH_REV_ID_3 3 /* Alpine V2 advanced */ 85 86 /* PCI BARs */ 87 #define AL_ETH_UDMA_BAR 0 88 #define AL_ETH_EC_BAR 4 89 #define AL_ETH_MAC_BAR 2 90 91 #define AL_ETH_MAX_FRAME_LEN 10000 92 #define AL_ETH_MIN_FRAME_LEN 60 93 94 #define AL_ETH_TSO_MSS_MAX_IDX 8 95 #define AL_ETH_TSO_MSS_MIN_VAL 1 96 /*TODO: update with correct value*/ 97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200) 98 99 enum AL_ETH_PROTO_ID { 100 AL_ETH_PROTO_ID_UNKNOWN = 0, 101 AL_ETH_PROTO_ID_IPv4 = 8, 102 AL_ETH_PROTO_ID_IPv6 = 11, 103 AL_ETH_PROTO_ID_TCP = 12, 104 AL_ETH_PROTO_ID_UDP = 13, 105 AL_ETH_PROTO_ID_FCOE = 21, 106 AL_ETH_PROTO_ID_GRH = 22, /** RoCE l3 header */ 107 AL_ETH_PROTO_ID_BTH = 23, /** RoCE l4 header */ 108 AL_ETH_PROTO_ID_ANY = 32, /**< for sw usage only */ 109 }; 110 #define AL_ETH_PROTOCOLS_NUM (AL_ETH_PROTO_ID_ANY) 111 112 enum AL_ETH_TX_TUNNEL_MODE { 113 AL_ETH_NO_TUNNELING = 0, 114 AL_ETH_TUNNEL_NO_UDP = 1, /* NVGRE / IP over IP */ 115 AL_ETH_TUNNEL_WITH_UDP = 3, /* VXLAN */ 116 }; 117 118 #define AL_ETH_RX_THASH_TABLE_SIZE (1 << 8) 119 #define AL_ETH_RX_FSM_TABLE_SIZE (1 << 7) 120 #define AL_ETH_RX_CTRL_TABLE_SIZE (1 << 11) 121 #define AL_ETH_RX_HASH_KEY_NUM 10 122 #define AL_ETH_FWD_MAC_NUM 32 123 #define AL_ETH_FWD_MAC_HASH_NUM 256 124 #define AL_ETH_FWD_PBITS_TABLE_NUM (1 << 3) 125 #define AL_ETH_FWD_PRIO_TABLE_NUM (1 << 3) 126 #define AL_ETH_FWD_VID_TABLE_NUM (1 << 12) 127 #define AL_ETH_FWD_DSCP_TABLE_NUM (1 << 8) 128 #define AL_ETH_FWD_TC_TABLE_NUM (1 << 8) 129 130 /** MAC media mode */ 131 enum al_eth_mac_mode { 132 AL_ETH_MAC_MODE_RGMII, 133 AL_ETH_MAC_MODE_SGMII, 134 AL_ETH_MAC_MODE_SGMII_2_5G, 135 AL_ETH_MAC_MODE_10GbE_Serial, /**< Applies to XFI and KR modes */ 136 AL_ETH_MAC_MODE_10G_SGMII, /**< SGMII using the 10G MAC, don't use*/ 137 AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */ 138 AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */ 139 AL_ETH_MAC_MODE_XLG_LL_50G, /**< applies to 50G mode using the 40/50G low latency (LL) MAC */ 140 AL_ETH_MAC_MODE_XLG_LL_25G /**< applies to 25G mode using the 40/50G low latency (LL) MAC */ 141 }; 142 143 struct al_eth_capabilities { 144 al_bool speed_10_HD; 145 al_bool speed_10_FD; 146 al_bool speed_100_HD; 147 al_bool speed_100_FD; 148 al_bool speed_1000_HD; 149 al_bool speed_1000_FD; 150 al_bool speed_10000_HD; 151 al_bool speed_10000_FD; 152 al_bool pfc; /**< priority flow control */ 153 al_bool eee; /**< Energy Efficient Ethernet */ 154 }; 155 156 /** interface type used for MDIO */ 157 enum al_eth_mdio_if { 158 AL_ETH_MDIO_IF_1G_MAC = 0, 159 AL_ETH_MDIO_IF_10G_MAC = 1 160 }; 161 162 /** MDIO protocol type */ 163 enum al_eth_mdio_type { 164 AL_ETH_MDIO_TYPE_CLAUSE_22 = 0, 165 AL_ETH_MDIO_TYPE_CLAUSE_45 = 1 166 }; 167 168 /** flow control mode */ 169 enum al_eth_flow_control_type { 170 AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE, 171 AL_ETH_FLOW_CONTROL_TYPE_PFC 172 }; 173 174 /** Tx to Rx switching decision type */ 175 enum al_eth_tx_switch_dec_type { 176 AL_ETH_TX_SWITCH_TYPE_MAC = 0, 177 AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE = 1, 178 AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2, 179 AL_ETH_TX_SWITCH_TYPE_BITMAP = 3 180 }; 181 182 /** Tx to Rx VLAN ID selection type */ 183 enum al_eth_tx_switch_vid_sel_type { 184 AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN1 = 0, 185 AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN2 = 1, 186 AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN1 = 2, 187 AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN2 = 3, 188 AL_ETH_TX_SWITCH_VID_SEL_TYPE_DEFAULT_VLAN1 = 4, 189 AL_ETH_TX_SWITCH_VID_SEL_TYPE_FINAL_VLAN1 = 5 190 }; 191 192 /** Rx descriptor configurations */ 193 /* Note: when selecting rx descriptor field to inner packet, then that field 194 * will be set according to inner packet when packet is tunneled, for non-tunneled 195 * packets, the field will be set according to the packets header */ 196 197 /** selection of the LRO_context_value result in the Metadata */ 198 enum al_eth_rx_desc_lro_context_val_res { 199 AL_ETH_LRO_CONTEXT_VALUE = 0, /**< LRO_context_value */ 200 AL_ETH_L4_OFFSET = 1, /**< L4_offset */ 201 }; 202 203 /** selection of the L4 offset in the Metadata */ 204 enum al_eth_rx_desc_l4_offset_sel { 205 AL_ETH_L4_OFFSET_OUTER = 0, /**< set L4 offset of the outer packet */ 206 AL_ETH_L4_OFFSET_INNER = 1, /**< set L4 offset of the inner packet */ 207 }; 208 209 /** selection of the L4 checksum result in the Metadata */ 210 enum al_eth_rx_desc_l4_chk_res_sel { 211 AL_ETH_L4_INNER_CHK = 0, /**< L4 checksum */ 212 AL_ETH_L4_INNER_OUTER_CHK = 1, /**< Logic AND between outer and inner 213 L4 checksum result */ 214 }; 215 216 /** selection of the L3 checksum result in the Metadata */ 217 enum al_eth_rx_desc_l3_chk_res_sel { 218 AL_ETH_L3_CHK_TYPE_0 = 0, /**< L3 checksum */ 219 AL_ETH_L3_CHK_TYPE_1 = 1, /**< L3 checksum or RoCE/FCoE CRC, 220 based on outer header */ 221 AL_ETH_L3_CHK_TYPE_2 = 2, /**< If tunnel exist = 0, 222 L3 checksum or RoCE/FCoE CRC, 223 based on outer header. 224 Else, 225 logic AND between outer L3 checksum 226 (Ipv4) and inner CRC (RoCE or FcoE) */ 227 AL_ETH_L3_CHK_TYPE_3 = 3, /**< combination of the L3 checksum result and 228 CRC result,based on the checksum and 229 RoCE/FCoE CRC input selections. */ 230 }; 231 232 /** selection of the L3 protocol index in the Metadata */ 233 enum al_eth_rx_desc_l3_proto_idx_sel { 234 AL_ETH_L3_PROTO_IDX_OUTER = 0, /**< set L3 proto index of the outer packet */ 235 AL_ETH_L3_PROTO_IDX_INNER = 1, /**< set L3 proto index of the inner packet */ 236 }; 237 238 /** selection of the L3 offset in the Metadata */ 239 enum al_eth_rx_desc_l3_offset_sel { 240 AL_ETH_L3_OFFSET_OUTER = 0, /**< set L3 offset of the outer packet */ 241 AL_ETH_L3_OFFSET_INNER = 1, /**< set L3 offset of the inner packet */ 242 }; 243 244 245 /** selection of the L4 protocol index in the Metadata */ 246 enum al_eth_rx_desc_l4_proto_idx_sel { 247 AL_ETH_L4_PROTO_IDX_OUTER = 0, /**< set L4 proto index of the outer packet */ 248 AL_ETH_L4_PROTO_IDX_INNER = 1, /**< set L4 proto index of the inner packet */ 249 }; 250 251 /** selection of the frag indication in the Metadata */ 252 enum al_eth_rx_desc_frag_sel { 253 AL_ETH_FRAG_OUTER = 0, /**< set frag of the outer packet */ 254 AL_ETH_FRAG_INNER = 1, /**< set frag of the inner packet */ 255 }; 256 257 /** Ethernet Rx completion descriptor */ 258 typedef struct { 259 uint32_t ctrl_meta; 260 uint32_t len; 261 uint32_t word2; 262 uint32_t word3; 263 } al_eth_rx_cdesc; 264 265 /** Flow Contol parameters */ 266 struct al_eth_flow_control_params{ 267 enum al_eth_flow_control_type type; /**< flow control type */ 268 al_bool obay_enable; /**< stop tx when pause received */ 269 al_bool gen_enable; /**< generate pause frames */ 270 uint16_t rx_fifo_th_high; 271 uint16_t rx_fifo_th_low; 272 uint16_t quanta; 273 uint16_t quanta_th; 274 uint8_t prio_q_map[4][8]; /**< for each UDMA, defines the mapping between 275 * PFC priority and queues(in bit mask). 276 * same mapping used for obay and generation. 277 * for example: 278 * if prio_q_map[1][7] = 0xC, then TX queues 2 279 * and 3 of UDMA 1 will be stopped when pause 280 * received with priority 7, also, when RX queues 281 * 2 and 3 of UDMA 1 become almost full, then 282 * pause frame with priority 7 will be sent. 283 * 284 *note: 285 * 1) if specific a queue is not used, the caller must 286 * make set the prio_q_map to 0 otherwise that queue 287 * will make the controller keep sending PAUSE packets. 288 * 2) queues of unused UDMA must be treated as above. 289 * 3) when working in LINK PAUSE mode, only entries at 290 * priority 0 will be considered. 291 */ 292 }; 293 294 /* Packet Tx flags */ 295 #define AL_ETH_TX_FLAGS_TSO AL_BIT(7) /**< Enable TCP/UDP segmentation offloading */ 296 #define AL_ETH_TX_FLAGS_IPV4_L3_CSUM AL_BIT(13) /**< Enable IPv4 header checksum calculation */ 297 #define AL_ETH_TX_FLAGS_L4_CSUM AL_BIT(14) /**< Enable TCP/UDP checksum calculation */ 298 #define AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM AL_BIT(17) /**< L4 partial checksum calculation */ 299 #define AL_ETH_TX_FLAGS_L2_MACSEC_PKT AL_BIT(16) /**< L2 Packet type 802_3 or 802_3_MACSEC, V2 */ 300 #define AL_ETH_TX_FLAGS_ENCRYPT AL_BIT(16) /**< Enable TX packet encryption, V3 */ 301 #define AL_ETH_TX_FLAGS_L2_DIS_FCS AL_BIT(15) /**< Disable CRC calculation*/ 302 #define AL_ETH_TX_FLAGS_TS AL_BIT(21) /**< Timestamp the packet */ 303 304 #define AL_ETH_TX_FLAGS_INT AL_M2S_DESC_INT_EN 305 #define AL_ETH_TX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 306 307 /** this structure used for tx packet meta data */ 308 struct al_eth_meta_data{ 309 uint8_t store :1; /**< store the meta into the queues cache */ 310 uint8_t words_valid :4; /**< valid bit per word */ 311 312 uint8_t vlan1_cfi_sel:2; 313 uint8_t vlan2_vid_sel:2; 314 uint8_t vlan2_cfi_sel:2; 315 uint8_t vlan2_pbits_sel:2; 316 uint8_t vlan2_ether_sel:2; 317 318 uint16_t vlan1_new_vid:12; 319 uint8_t vlan1_new_cfi :1; 320 uint8_t vlan1_new_pbits :3; 321 uint16_t vlan2_new_vid:12; 322 uint8_t vlan2_new_cfi :1; 323 uint8_t vlan2_new_pbits :3; 324 325 uint8_t l3_header_len; /**< in bytes */ 326 uint8_t l3_header_offset; 327 uint8_t l4_header_len; /**< in words(32-bits) */ 328 329 /* rev 0 specific */ 330 uint8_t mss_idx_sel:3; /**< for TSO, select the register that holds the MSS */ 331 332 /* rev 1 specific */ 333 uint8_t ts_index:4; /**< index of regiser where to store the tx timestamp */ 334 uint16_t mss_val :14; /**< for TSO, set the mss value */ 335 uint8_t outer_l3_offset; /**< for tunneling mode. up to 64 bytes */ 336 uint8_t outer_l3_len; /**< for tunneling mode. up to 128 bytes */ 337 }; 338 339 /* Packet Rx flags when adding buffer to receive queue */ 340 341 /**< 342 * Target-ID to be assigned to the packet descriptors 343 * Requires Target-ID in descriptor to be enabled for the specific UDMA 344 * queue. 345 */ 346 #define AL_ETH_RX_FLAGS_TGTID_MASK AL_FIELD_MASK(15, 0) 347 #define AL_ETH_RX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 348 #define AL_ETH_RX_FLAGS_INT AL_M2S_DESC_INT_EN 349 #define AL_ETH_RX_FLAGS_DUAL_BUF AL_BIT(31) 350 351 /* Packet Rx flags set by HW when receiving packet */ 352 #define AL_ETH_RX_ERROR AL_BIT(16) /**< layer 2 errors (FCS, bad len, etc) */ 353 #define AL_ETH_RX_FLAGS_L4_CSUM_ERR AL_BIT(14) 354 #define AL_ETH_RX_FLAGS_L3_CSUM_ERR AL_BIT(13) 355 356 /* Packet Rx flags - word 3 in Rx completion descriptor */ 357 #define AL_ETH_RX_FLAGS_CRC AL_BIT(31) 358 #define AL_ETH_RX_FLAGS_L3_CSUM_2 AL_BIT(30) 359 #define AL_ETH_RX_FLAGS_L4_CSUM_2 AL_BIT(29) 360 #define AL_ETH_RX_FLAGS_SW_SRC_PORT_SHIFT 13 361 #define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK AL_FIELD_MASK(15, 13) 362 #define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_SHIFT 3 363 #define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK AL_FIELD_MASK(10, 3) 364 #define AL_ETH_RX_FLAGS_L4_OFFSET_SHIFT 3 365 #define AL_ETH_RX_FLAGS_L4_OFFSET_MASK AL_FIELD_MASK(10, 3) 366 #define AL_ETH_RX_FLAGS_PRIORITY_SHIFT 0 367 #define AL_ETH_RX_FLAGS_PRIORITY_MASK AL_FIELD_MASK(2, 0) 368 369 /** packet structure. used for packet transmission and reception */ 370 struct al_eth_pkt{ 371 uint32_t flags; /**< see flags above, depends on context(tx or rx) */ 372 enum AL_ETH_PROTO_ID l3_proto_idx; 373 enum AL_ETH_PROTO_ID l4_proto_idx; 374 uint8_t source_vlan_count:2; 375 uint8_t vlan_mod_add_count:2; 376 uint8_t vlan_mod_del_count:2; 377 uint8_t vlan_mod_v1_ether_sel:2; 378 uint8_t vlan_mod_v1_vid_sel:2; 379 uint8_t vlan_mod_v1_pbits_sel:2; 380 381 /* rev 1 specific */ 382 enum AL_ETH_TX_TUNNEL_MODE tunnel_mode; 383 enum AL_ETH_PROTO_ID outer_l3_proto_idx; /**< for tunneling mode */ 384 385 /**< 386 * Target-ID to be assigned to the packet descriptors 387 * Requires Target-ID in descriptor to be enabled for the specific UDMA 388 * queue. 389 */ 390 uint16_t tgtid; 391 392 uint32_t rx_header_len; /**< header buffer length of rx packet, not used */ 393 struct al_eth_meta_data *meta; /**< if null, then no meta added */ 394 #ifdef AL_ETH_RX_DESC_RAW_GET 395 uint32_t rx_desc_raw[4]; 396 #endif 397 uint16_t rxhash; 398 uint16_t l3_offset; 399 400 #ifdef AL_ETH_EX 401 struct al_eth_ext_metadata *ext_meta_data; 402 #endif 403 404 uint8_t num_of_bufs; 405 struct al_buf bufs[AL_ETH_PKT_MAX_BUFS]; 406 }; 407 408 struct al_ec_regs; 409 410 411 /** Ethernet Adapter private data structure used by this driver */ 412 struct al_hal_eth_adapter{ 413 uint8_t rev_id; /**<PCI adapter revision ID */ 414 uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 415 struct unit_regs __iomem * unit_regs; 416 void __iomem *udma_regs_base; 417 struct al_ec_regs __iomem *ec_regs_base; 418 void __iomem *ec_ints_base; 419 struct al_eth_mac_regs __iomem *mac_regs_base; 420 struct interrupt_controller_ctrl __iomem *mac_ints_base; 421 422 char *name; /**< the upper layer must keep the string area */ 423 424 struct al_udma tx_udma; 425 /* uint8_t tx_queues;*//* number of tx queues */ 426 struct al_udma rx_udma; 427 /* uint8_t rx_queues;*//* number of tx queues */ 428 429 uint8_t enable_rx_parser; /**< config and enable rx parsing */ 430 431 enum al_eth_flow_control_type fc_type; /**< flow control*/ 432 433 enum al_eth_mac_mode mac_mode; 434 enum al_eth_mdio_if mdio_if; /**< which mac mdio interface to use */ 435 enum al_eth_mdio_type mdio_type; /**< mdio protocol type */ 436 al_bool shared_mdio_if; /**< when AL_TRUE, the mdio interface is shared with other controllers.*/ 437 uint8_t curr_lt_unit; 438 uint8_t serdes_lane; 439 #ifdef AL_ETH_EX 440 struct al_eth_ex_state ex_state; 441 #endif 442 }; 443 444 /** parameters from upper layer */ 445 struct al_eth_adapter_params{ 446 uint8_t rev_id; /**<PCI adapter revision ID */ 447 uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 448 uint8_t enable_rx_parser; /**< when true, the rx epe parser will be enabled */ 449 void __iomem *udma_regs_base; /**< UDMA register base address */ 450 void __iomem *ec_regs_base; /**< Ethernet controller registers base address 451 * can be null if the function is virtual 452 */ 453 void __iomem *mac_regs_base; /**< Ethernet MAC registers base address 454 * can be null if the function is virtual 455 */ 456 char *name; /**< the upper layer must keep the string area */ 457 458 uint8_t serdes_lane; /**< serdes lane (relevant to 25G macs only) */ 459 }; 460 461 /* adapter management */ 462 /** 463 * initialize the ethernet adapter's DMA 464 * - initialize the adapter data structure 465 * - initialize the Tx and Rx UDMA 466 * - enable the Tx and Rx UDMA, the rings will be still disabled at this point. 467 * 468 * @param adapter pointer to the private structure 469 * @param params the parameters passed from upper layer 470 * 471 * @return 0 on success. otherwise on failure. 472 */ 473 int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params); 474 475 /** 476 * stop the DMA of the ethernet adapter 477 * 478 * @param adapter pointer to the private structure 479 * 480 * @return 0 on success. otherwise on failure. 481 */ 482 int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter); 483 484 int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter); 485 486 /** 487 * enable the ec and mac interrupts 488 * 489 * @param adapter pointer to the private structure 490 * 491 * @return 0 on success. otherwise on failure. 492 */ 493 int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter); 494 495 /** 496 * ec and mac interrupt service routine 497 * read and print asserted interrupts 498 * 499 * @param adapter pointer to the private structure 500 * 501 * @return 0 on success. otherwise on failure. 502 */ 503 int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter); 504 505 /* Q management */ 506 /** 507 * Configure and enable a queue ring 508 * 509 * @param adapter pointer to the private structure 510 * @param type tx or rx 511 * @param qid queue index 512 * @param q_params queue parameters 513 * 514 * @return 0 on success. otherwise on failure. 515 */ 516 int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid, 517 struct al_udma_q_params *q_params); 518 519 520 /** 521 * enable a queue if it was previously disabled 522 * 523 * @param adapter pointer to the private structure 524 * @param type tx or rx 525 * @param qid queue index 526 * 527 * @return -EPERM (not implemented yet). 528 */ 529 int al_eth_queue_enable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 530 531 /** 532 * disable a queue 533 * @param adapter pointer to the private structure 534 * @param type tx or rx 535 * @param qid queue index 536 * 537 * @return -EPERM (not implemented yet). 538 */ 539 int al_eth_queue_disable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 540 541 /* MAC layer */ 542 543 /** 544 * configure the mac media type. 545 * this function only sets the mode, but not the speed as certain mac modes 546 * support multiple speeds as will be negotiated by the link layer. 547 * @param adapter pointer to the private structure. 548 * @param mode media mode 549 * 550 * @return 0 on success. negative errno on failure. 551 */ 552 int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode); 553 554 /** 555 * stop the mac tx and rx paths. 556 * @param adapter pointer to the private structure. 557 * 558 * @return 0 on success. negative error on failure. 559 */ 560 int al_eth_mac_stop(struct al_hal_eth_adapter *adapter); 561 562 /** 563 * start the mac tx and rx paths. 564 * @param adapter pointer to the private structure. 565 * 566 * @return 0 on success. negative error on failure. 567 */ 568 int al_eth_mac_start(struct al_hal_eth_adapter *adapter); 569 570 /** 571 * Perform gearbox reset for tx lanes And/Or Rx lanes. 572 * applicable only when the controller is connected to srds25G. 573 * This reset should be performed after each operation that changes the clocks 574 * (such as serdes reset, mac stop, etc.) 575 * 576 * @param adapter pointer to the private structure. 577 * @param tx_reset assert and de-assert reset for tx lanes 578 * @param rx_reset assert and de-assert reset for rx lanes 579 */ 580 void al_eth_gearbox_reset(struct al_hal_eth_adapter *adapter, al_bool tx_reset, al_bool rx_reset); 581 582 /** 583 * Enable / Disable forward error correction (FEC) 584 * 585 * @param adapter pointer to the private structure. 586 * @param enable true to enable FEC. false to disable FEC. 587 * 588 * @return 0 on success. negative error on failure. 589 */ 590 int al_eth_fec_enable(struct al_hal_eth_adapter *adapter, al_bool enable); 591 592 /** 593 * Get forward error correction (FEC) statistics 594 * 595 * @param adapter pointer to the private structure. 596 * @param corrected number of bits been corrected by the FEC 597 * @param uncorrectable number of bits that FEC couldn't correct. 598 * 599 * @return 0 on success. negative error on failure. 600 */ 601 int al_eth_fec_stats_get(struct al_hal_eth_adapter *adapter, 602 uint32_t *corrected, uint32_t *uncorrectable); 603 604 /** 605 * get the adapter capabilities (speed, duplex,..) 606 * this function must not be called before configuring the mac mode using al_eth_mac_config() 607 * @param adapter pointer to the private structure. 608 * @param caps pointer to structure that will be updated by this function 609 * 610 * @return 0 on success. negative errno on failure. 611 */ 612 int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps); 613 614 /** 615 * update link auto negotiation speed and duplex mode 616 * this function assumes the mac mode already set using the al_eth_mac_config() 617 * function. 618 * 619 * @param adapter pointer to the private structure 620 * @param force_1000_base_x set to AL_TRUE to force the mac to work on 1000baseX 621 * (not relevant to RGMII) 622 * @param an_enable set to AL_TRUE to enable auto negotiation 623 * (not relevant to RGMII) 624 * @param speed in mega bits, e.g 1000 stands for 1Gbps (relevant only in case 625 * an_enable is AL_FALSE) 626 * @param full_duplex set to AL_TRUE to enable full duplex mode (relevant only 627 * in case an_enable is AL_FALSE) 628 * 629 * @return 0 on success. otherwise on failure. 630 */ 631 int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter, 632 al_bool force_1000_base_x, 633 al_bool an_enable, 634 uint32_t speed, 635 al_bool full_duplex); 636 /** 637 * Enable/Disable Loopback mode 638 * 639 * @param adapter pointer to the private structure 640 * @param enable set to AL_TRUE to enable full duplex mode 641 * 642 * @return 0 on success. otherwise on failure. 643 */ 644 int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable); 645 646 /** 647 * configure minimum and maximum rx packet length 648 * 649 * @param adapter pointer to the private structure 650 * @param min_rx_len minimum rx packet length 651 * @param max_rx_len maximum rx packet length 652 * both length limits in bytes and it includes the MAC Layer header and FCS. 653 * @return 0 on success, otherwise on failure. 654 */ 655 int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len); 656 657 658 /* MDIO */ 659 660 /* Reference clock frequency (platform specific) */ 661 enum al_eth_ref_clk_freq { 662 AL_ETH_REF_FREQ_375_MHZ = 0, 663 AL_ETH_REF_FREQ_187_5_MHZ = 1, 664 AL_ETH_REF_FREQ_250_MHZ = 2, 665 AL_ETH_REF_FREQ_500_MHZ = 3, 666 AL_ETH_REF_FREQ_428_MHZ = 4, 667 }; 668 669 /** 670 * configure the MDIO hardware interface 671 * @param adapter pointer to the private structure 672 * @param mdio_type clause type 673 * @param shared_mdio_if set to AL_TRUE if multiple controllers using the same 674 * @param ref_clk_freq reference clock frequency 675 * @param mdio_clk_freq_khz the required MDC/MDIO clock frequency [Khz] 676 * MDIO pins of the chip. 677 * 678 * @return 0 on success, otherwise on failure. 679 */ 680 int al_eth_mdio_config(struct al_hal_eth_adapter *adapter, 681 enum al_eth_mdio_type mdio_type, 682 al_bool shared_mdio_if, 683 enum al_eth_ref_clk_freq ref_clk_freq, 684 unsigned int mdio_clk_freq_khz); 685 686 /** 687 * read mdio register 688 * this function uses polling mode, and as the mdio is slow interface, it might 689 * block the cpu for long time (milliseconds). 690 * @param adapter pointer to the private structure 691 * @param phy_addr address of mdio phy 692 * @param device address of mdio device (used only in CLAUSE 45) 693 * @param reg index of the register 694 * @param val pointer for read value of the register 695 * 696 * @return 0 on success, negative errno on failure 697 */ 698 int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 699 uint32_t device, uint32_t reg, uint16_t *val); 700 701 /** 702 * write mdio register 703 * this function uses polling mode, and as the mdio is slow interface, it might 704 * block the cpu for long time (milliseconds). 705 * @param adapter pointer to the private structure 706 * @param phy_addr address of mdio phy 707 * @param device address of mdio device (used only in CLAUSE 45) 708 * @param reg index of the register 709 * @param val value to write 710 * 711 * @return 0 on success, negative errno on failure 712 */ 713 int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 714 uint32_t device, uint32_t reg, uint16_t val); 715 716 /* TX */ 717 /** 718 * get number of free tx descriptors 719 * 720 * @param adapter adapter handle 721 * @param qid queue index 722 * 723 * @return num of free descriptors. 724 */ 725 static INLINE uint32_t al_eth_tx_available_get(struct al_hal_eth_adapter *adapter, 726 uint32_t qid) 727 { 728 struct al_udma_q *udma_q; 729 730 al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q); 731 732 return al_udma_available_get(udma_q); 733 } 734 735 /** 736 * prepare packet descriptors in tx queue. 737 * 738 * This functions prepares the descriptors for the given packet in the tx 739 * submission ring. the caller must call al_eth_tx_pkt_action() below 740 * in order to notify the hardware about the new descriptors. 741 * 742 * @param tx_dma_q pointer to UDMA tx queue 743 * @param pkt the packet to transmit 744 * 745 * @return number of descriptors used for this packet, 0 if no free 746 * room in the descriptors ring 747 */ 748 int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt); 749 750 751 /** 752 * Trigger the DMA about previously added tx descriptors. 753 * 754 * @param tx_dma_q pointer to UDMA tx queue 755 * @param tx_descs number of descriptors to notify the DMA about. 756 * the tx_descs can be sum of descriptor numbers of multiple prepared packets, 757 * this way the caller can use this function to notify the DMA about multiple 758 * packets. 759 */ 760 void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs); 761 762 /** 763 * get number of completed tx descriptors, upper layer should derive from 764 * this information which packets were completed. 765 * 766 * @param tx_dma_q pointer to UDMA tx queue 767 * 768 * @return number of completed tx descriptors. 769 */ 770 int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q); 771 772 /** 773 * configure a TSO MSS val 774 * 775 * the TSO MSS vals are preconfigured values for MSS stored in hardware and the 776 * packet could use them when not working in MSS explicit mode. 777 * @param adapter pointer to the private structure 778 * @param idx the mss index 779 * @param mss_val the MSS value 780 * 781 * @return 0 on success. otherwise on failure. 782 */ 783 int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val); 784 785 /* RX */ 786 /** 787 * Config the RX descriptor fields 788 * 789 * @param adapter pointer to the private structure 790 * @param lro_sel select LRO context or l4 offset 791 * @param l4_offset_sel select l4 offset source 792 * @param l4_sel select the l4 checksum result 793 * @param l3_sel select the l3 checksum result 794 * @param l3_proto_sel select the l3 protocol index source 795 * @param l4_proto_sel select the l4 protocol index source 796 * @param frag_sel select the frag indication source 797 */ 798 void al_eth_rx_desc_config( 799 struct al_hal_eth_adapter *adapter, 800 enum al_eth_rx_desc_lro_context_val_res lro_sel, 801 enum al_eth_rx_desc_l4_offset_sel l4_offset_sel, 802 enum al_eth_rx_desc_l3_offset_sel l3_offset_sel, 803 enum al_eth_rx_desc_l4_chk_res_sel l4_sel, 804 enum al_eth_rx_desc_l3_chk_res_sel l3_sel, 805 enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel, 806 enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel, 807 enum al_eth_rx_desc_frag_sel frag_sel); 808 809 /** 810 * Configure RX header split 811 * 812 * @param adapter pointer to the private structure 813 * @param enable header split when AL_TRUE 814 * @param header_split_len length in bytes of the header split, this value used when 815 * CTRL TABLE header split len select is set to 816 * AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG, in this case the controller will 817 * store the first header_split_len bytes into buf2, then the rest (if any) into buf1. 818 * when CTRL_TABLE header split len select set to other value, then the header_len 819 * determined according to the parser, and the header_split_len parameter is not 820 * used. 821 * 822 * return 0 on success. otherwise on failure. 823 */ 824 int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len); 825 826 /** 827 * enable / disable header split in the udma queue. 828 * length will be taken from the udma configuration to enable different length per queue. 829 * 830 * @param adapter pointer to the private structure 831 * @param enable header split when AL_TRUE 832 * @param qid the queue id to enable/disable header split 833 * @param header_len in what len the udma will cut the header 834 * 835 * return 0 on success. 836 */ 837 int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter, 838 al_bool enable, 839 uint32_t qid, 840 uint32_t header_len); 841 842 /** 843 * add buffer to receive queue 844 * 845 * @param rx_dma_q pointer to UDMA rx queue 846 * @param buf pointer to data buffer 847 * @param flags bitwise of AL_ETH_RX_FLAGS 848 * @param header_buf this is not used for far and header_buf should be set to 849 * NULL. 850 * 851 * @return 0 on success. otherwise on failure. 852 */ 853 int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q, 854 struct al_buf *buf, uint32_t flags, 855 struct al_buf *header_buf); 856 857 /** 858 * notify the hw engine about rx descriptors that were added to the receive queue 859 * 860 * @param rx_dma_q pointer to UDMA rx queue 861 * @param descs_num number of rx descriptors 862 */ 863 void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q, 864 uint32_t descs_num); 865 866 /** 867 * get packet from RX completion ring 868 * 869 * @param rx_dma_q pointer to UDMA rx queue 870 * @param pkt pointer to a packet data structure, this function fills this 871 * structure with the information about the received packet. the buffers 872 * structures filled only with the length of the data written into the buffer, 873 * the address fields are not updated as the upper layer can retrieve this 874 * information by itself because the hardware uses the buffers in the same order 875 * were those buffers inserted into the ring of the receive queue. 876 * this structure should be allocated by the caller function. 877 * 878 * @return return number of descriptors or 0 if no completed packet found. 879 */ 880 uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q, struct al_eth_pkt *pkt); 881 882 883 /* RX parser table */ 884 struct al_eth_epe_p_reg_entry { 885 uint32_t data; 886 uint32_t mask; 887 uint32_t ctrl; 888 }; 889 890 struct al_eth_epe_control_entry { 891 uint32_t data[6]; 892 }; 893 894 /** 895 * update rx parser entry 896 * 897 * @param adapter pointer to the private structure 898 * @param idx the protocol index to update 899 * @param reg_entry contents of parser register entry 900 * @param control entry contents of control table entry 901 * 902 * @return 0 on success. otherwise on failure. 903 */ 904 int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx, 905 struct al_eth_epe_p_reg_entry *reg_entry, 906 struct al_eth_epe_control_entry *control_entry); 907 908 /* Flow Steering and filtering */ 909 int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue); 910 911 /* FSM table bits */ 912 /** FSM table has 7 bits input address: 913 * bits[2:0] are the outer packet's type (IPv4, TCP...) 914 * bits[5:3] are the inner packet's type 915 * bit[6] is set when packet is tunneled. 916 * 917 * The output of each entry: 918 * bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer) 919 * bit[2] - selects whether to use thash output, or default values for the queue and udma 920 * bits[6:3] default UDMA mask: the UDMAs to select when bit 2 above was unset 921 * bits[9:5] defualt queue: the queue index to select when bit 2 above was unset 922 */ 923 924 #define AL_ETH_FSM_ENTRY_IPV4_TCP 0 925 #define AL_ETH_FSM_ENTRY_IPV4_UDP 1 926 #define AL_ETH_FSM_ENTRY_IPV6_TCP 2 927 #define AL_ETH_FSM_ENTRY_IPV6_UDP 3 928 #define AL_ETH_FSM_ENTRY_IPV6_NO_UDP_TCP 4 929 #define AL_ETH_FSM_ENTRY_IPV4_NO_UDP_TCP 5 930 #define AL_ETH_FSM_ENTRY_IPV4_FRAGMENTED 6 931 #define AL_ETH_FSM_ENTRY_NOT_IP 7 932 933 #define AL_ETH_FSM_ENTRY_OUTER(idx) ((idx) & 7) 934 #define AL_ETH_FSM_ENTRY_INNER(idx) (((idx) >> 3) & 7) 935 #define AL_ETH_FSM_ENTRY_TUNNELED(idx) (((idx) >> 6) & 1) 936 937 /* FSM DATA format */ 938 #define AL_ETH_FSM_DATA_OUTER_2_TUPLE 0 939 #define AL_ETH_FSM_DATA_OUTER_4_TUPLE 1 940 #define AL_ETH_FSM_DATA_INNER_2_TUPLE 2 941 #define AL_ETH_FSM_DATA_INNER_4_TUPLE 3 942 943 #define AL_ETH_FSM_DATA_HASH_SEL (1 << 2) 944 945 #define AL_ETH_FSM_DATA_DEFAULT_Q_SHIFT 5 946 #define AL_ETH_FSM_DATA_DEFAULT_UDMA_SHIFT 3 947 948 /* set fsm table entry */ 949 int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 950 951 enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT { 952 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_0 = 0, 953 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_1 = 1, 954 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY = 2, 955 }; 956 957 enum AL_ETH_FWD_CTRL_IDX_TUNNEL { 958 AL_ETH_FWD_CTRL_IDX_TUNNEL_NOT_EXIST = 0, 959 AL_ETH_FWD_CTRL_IDX_TUNNEL_EXIST = 1, 960 AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY = 2, 961 }; 962 963 enum AL_ETH_FWD_CTRL_IDX_VLAN { 964 AL_ETH_FWD_CTRL_IDX_VLAN_NOT_EXIST = 0, 965 AL_ETH_FWD_CTRL_IDX_VLAN_EXIST = 1, 966 AL_ETH_FWD_CTRL_IDX_VLAN_ANY = 2, 967 }; 968 969 enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE { 970 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_NO_MATCH = 0, 971 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_MATCH = 1, 972 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY = 2, 973 }; 974 975 enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE { 976 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_UC = 0, /**< unicast */ 977 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_MC = 1, /**< multicast */ 978 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_BC = 2, /**< broadcast */ 979 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY = 4, /**< for sw usage */ 980 }; 981 982 /** 983 * This structure defines the index or group of indeces within the control table. 984 * each field has special enum value (with _ANY postfix) that indicates all 985 * possible values of that field. 986 */ 987 struct al_eth_fwd_ctrl_table_index { 988 enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT vlan_table_out; 989 enum AL_ETH_FWD_CTRL_IDX_TUNNEL tunnel_exist; 990 enum AL_ETH_FWD_CTRL_IDX_VLAN vlan_exist; 991 enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE mac_table_match; 992 enum AL_ETH_PROTO_ID protocol_id; 993 enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE mac_type; 994 }; 995 996 enum AL_ETH_CTRL_TABLE_PRIO_SEL { 997 AL_ETH_CTRL_TABLE_PRIO_SEL_PBITS_TABLE = 0, 998 AL_ETH_CTRL_TABLE_PRIO_SEL_DSCP_TABLE = 1, 999 AL_ETH_CTRL_TABLE_PRIO_SEL_TC_TABLE = 2, 1000 AL_ETH_CTRL_TABLE_PRIO_SEL_REG1 = 3, 1001 AL_ETH_CTRL_TABLE_PRIO_SEL_REG2 = 4, 1002 AL_ETH_CTRL_TABLE_PRIO_SEL_REG3 = 5, 1003 AL_ETH_CTRL_TABLE_PRIO_SEL_REG4 = 6, 1004 AL_ETH_CTRL_TABLE_PRIO_SEL_REG5 = 7, 1005 AL_ETH_CTRL_TABLE_PRIO_SEL_REG6 = 7, 1006 AL_ETH_CTRL_TABLE_PRIO_SEL_REG7 = 9, 1007 AL_ETH_CTRL_TABLE_PRIO_SEL_REG8 = 10, 1008 AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_3 = 11, 1009 AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_0 = 12, 1010 }; 1011 /** where to select the initial queue from */ 1012 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 { 1013 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_PRIO_TABLE = 0, 1014 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_THASH_TABLE = 1, 1015 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MAC_TABLE = 2, 1016 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MHASH_TABLE = 3, 1017 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG1 = 4, 1018 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG2 = 5, 1019 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG3 = 6, 1020 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG4 = 7, 1021 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_3 = 12, 1022 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_0 = 13, 1023 }; 1024 1025 /** target queue will be built up from the priority and initial queue */ 1026 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 { 1027 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE = 0, /**< target queue is the output of priority table */ 1028 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO = 1, /**< target queue is the priority */ 1029 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE = 2, /**< target queue is initial queue[0], priority[1] */ 1030 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO = 3, /**< target queue is the initial */ 1031 }; 1032 1033 enum AL_ETH_CTRL_TABLE_UDMA_SEL { 1034 AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_TABLE = 0, 1035 AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_AND_VLAN = 1, 1036 AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_TABLE = 2, 1037 AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_AND_MAC = 3, 1038 AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_TABLE = 4, 1039 AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_AND_MHASH = 5, 1040 AL_ETH_CTRL_TABLE_UDMA_SEL_MHASH_TABLE = 6, 1041 AL_ETH_CTRL_TABLE_UDMA_SEL_REG1 = 7, 1042 AL_ETH_CTRL_TABLE_UDMA_SEL_REG2 = 8, 1043 AL_ETH_CTRL_TABLE_UDMA_SEL_REG3 = 9, 1044 AL_ETH_CTRL_TABLE_UDMA_SEL_REG4 = 10, 1045 AL_ETH_CTRL_TABLE_UDMA_SEL_REG5 = 11, 1046 AL_ETH_CTRL_TABLE_UDMA_SEL_REG6 = 12, 1047 AL_ETH_CTRL_TABLE_UDMA_SEL_REG7 = 13, 1048 AL_ETH_CTRL_TABLE_UDMA_SEL_REG8 = 14, 1049 AL_ETH_CTRL_TABLE_UDMA_SEL_VAL_0 = 15, 1050 }; 1051 1052 enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL { 1053 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0 = 0, 1054 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG = 1, /**< select header len from the hdr_split register (set by al_eth_rx_header_split_config())*/ 1055 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L3_OFFSET = 2, 1056 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L4_OFFSET = 3, 1057 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_TUNNEL_START_OFFSET = 4, 1058 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L3_OFFSET = 5, 1059 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L4_OFFSET = 6, 1060 }; 1061 1062 struct al_eth_fwd_ctrl_table_entry { 1063 enum AL_ETH_CTRL_TABLE_PRIO_SEL prio_sel; 1064 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 queue_sel_1; /**< queue id source */ 1065 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 queue_sel_2; /**< mix queue id with priority */ 1066 enum AL_ETH_CTRL_TABLE_UDMA_SEL udma_sel; 1067 enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL hdr_split_len_sel; 1068 al_bool filter; /**< set to AL_TRUE to enable filtering */ 1069 }; 1070 /** 1071 * Configure default control table entry 1072 * 1073 * @param adapter pointer to the private structure 1074 * @param use_table set to AL_TRUE if control table is used, when set to AL_FALSE 1075 * then control table will be bypassed and the entry value will be used. 1076 * @param entry defines the value to be used when bypassing control table. 1077 * 1078 * @return 0 on success. otherwise on failure. 1079 */ 1080 int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter, 1081 al_bool use_table, 1082 struct al_eth_fwd_ctrl_table_entry *entry); 1083 1084 /** 1085 * Configure control table entry 1086 * 1087 * @param adapter pointer to the private structure 1088 * @param index the entry index within the control table. 1089 * @param entry the value to write to the control table entry 1090 * 1091 * @return 0 on success. otherwise on failure. 1092 */ 1093 int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter, 1094 struct al_eth_fwd_ctrl_table_index *index, 1095 struct al_eth_fwd_ctrl_table_entry *entry); 1096 1097 int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 1098 int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val); 1099 1100 /** 1101 * Configure hash key initial registers 1102 * Those registers define the initial key values, those values used for 1103 * the THASH and MHASH hash functions. 1104 * 1105 * @param adapter pointer to the private structure 1106 * @param idx the register index 1107 * @param val the register value 1108 * 1109 * @return 0 on success. otherwise on failure. 1110 */ 1111 int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val); 1112 1113 struct al_eth_fwd_mac_table_entry { 1114 uint8_t addr[6]; /**< byte 0 is the first byte seen on the wire */ 1115 uint8_t mask[6]; 1116 al_bool tx_valid; 1117 uint8_t tx_target; 1118 al_bool rx_valid; 1119 uint8_t udma_mask; /**< target udma */ 1120 uint8_t qid; /**< target queue */ 1121 al_bool filter; /**< set to AL_TRUE to enable filtering */ 1122 }; 1123 1124 /** 1125 * Configure mac table entry 1126 * The HW traverse this table and looks for match from lowest index, 1127 * when the packets MAC DA & mask == addr, and the valid bit is set, then match occurs. 1128 * 1129 * @param adapter pointer to the private structure 1130 * @param idx the entry index within the mac table. 1131 * @param entry the contents of the MAC table entry 1132 * 1133 * @return 0 on success. otherwise on failure. 1134 */ 1135 int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1136 struct al_eth_fwd_mac_table_entry *entry); 1137 1138 int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1139 uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi); 1140 int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl); 1141 1142 int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1143 int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1144 1145 /** 1146 * Configure pbits table entry 1147 * The HW uses this table to translate between vlan pbits field to priority. 1148 * The vlan pbits is used as the index of this table. 1149 * 1150 * @param adapter pointer to the private structure 1151 * @param idx the entry index within the table. 1152 * @param prio the priority to set for this entry 1153 * 1154 * @return 0 on success. otherwise on failure. 1155 */ 1156 int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1157 1158 /** 1159 * Configure priority table entry 1160 * The HW uses this table to translate between priority to queue index. 1161 * The priority is used as the index of this table. 1162 * 1163 * @param adapter pointer to the private structure 1164 * @param prio the entry index within the table. 1165 * @param qid the queue index to set for this entry (priority). 1166 * 1167 * @return 0 on success. otherwise on failure. 1168 */ 1169 int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid); 1170 1171 /** 1172 * Configure DSCP table entry 1173 * The HW uses this table to translate between IPv4 DSCP field to priority. 1174 * The IPv4 byte 1 (DSCP+ECN) used as index to this table. 1175 * 1176 * @param adapter pointer to the private structure 1177 * @param idx the entry index within the table. 1178 * @param prio the queue index to set for this entry (priority). 1179 * 1180 * @return 0 on success. otherwise on failure. 1181 */ 1182 int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1183 1184 /** 1185 * Configure TC table entry 1186 * The HW uses this table to translate between IPv6 TC field to priority. 1187 * The IPv6 TC used as index to this table. 1188 * 1189 * @param adapter pointer to the private structure 1190 * @param idx the entry index within the table. 1191 * @param prio the queue index to set for this entry (priority). 1192 * 1193 * @return 0 on success. otherwise on failure. 1194 */ 1195 int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1196 1197 /** 1198 * Configure MAC HASH table entry 1199 * The HW uses 8 bits from the hash result on the MAC DA as index to this table. 1200 * 1201 * @param adapter pointer to the private structure 1202 * @param idx the entry index within the table. 1203 * @param udma_mask the target udma to set for this entry. 1204 * @param qid the target queue index to set for this entry. 1205 * 1206 * @return 0 on success. otherwise on failure. 1207 */ 1208 int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid); 1209 1210 struct al_eth_fwd_vid_table_entry { 1211 uint8_t control:1; /**< used as input for the control table */ 1212 uint8_t filter:1; /**< set to 1 to enable filtering */ 1213 uint8_t udma_mask:4; /**< target udmas */ 1214 }; 1215 1216 /** 1217 * Configure default vlan table entry 1218 * 1219 * @param adapter pointer to the private structure 1220 * @param use_table set to AL_TRUE if vlan table is used, when set to AL_FALSE 1221 * then vid table will be bypassed and the default_entry value will be used. 1222 * @param default_entry defines the value to be used when bypassing vid table. 1223 * @param default_vlan defines the value will be used when untagget packet 1224 * received. this value will be used only for steering and filtering control, 1225 * the packet's data will not be changed. 1226 * 1227 * @return 0 on success. otherwise on failure. 1228 */ 1229 int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table, 1230 struct al_eth_fwd_vid_table_entry *default_entry, 1231 uint32_t default_vlan); 1232 /** 1233 * Configure vlan table entry 1234 * 1235 * @param adapter pointer to the private structure 1236 * @param idx the entry index within the vlan table. The HW uses the vlan id 1237 * field of the packet when accessing this table. 1238 * @param entry the value to write to the vlan table entry 1239 * 1240 * @return 0 on success. otherwise on failure. 1241 */ 1242 int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1243 struct al_eth_fwd_vid_table_entry *entry); 1244 1245 1246 /** 1247 * Configure default UDMA register 1248 * When the control table entry udma selection set to AL_ETH_CTRL_TABLE_UDMA_SEL_REG<n>, 1249 * then the target UDMA will be set according to the register n of the default 1250 * UDMA registers. 1251 * 1252 * @param adapter pointer to the private structure 1253 * @param idx the index of the default register. 1254 * @param udma_mask the value of the register. 1255 * 1256 * @return 0 on success. otherwise on failure. 1257 */ 1258 int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1259 uint8_t udma_mask); 1260 1261 /** 1262 * Configure default queue register 1263 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>, 1264 * then the target queue will be set according to the register n of the default 1265 * queue registers. 1266 * 1267 * @param adapter pointer to the private structure 1268 * @param idx the index of the default register. 1269 * @param qid the value of the register. 1270 * 1271 * @return 0 on success. otherwise on failure. 1272 */ 1273 int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1274 uint8_t qid); 1275 1276 /** 1277 * Configure default priority register 1278 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>, 1279 * then the target priority will be set according to the register n of the default 1280 * priority registers. 1281 * 1282 * @param adapter pointer to the private structure 1283 * @param idx the index of the default register. 1284 * @param prio the value of the register. 1285 * 1286 * @return 0 on success. otherwise on failure. 1287 */ 1288 int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1289 uint8_t prio); 1290 1291 1292 1293 /* filter undetected MAC DA */ 1294 #define AL_ETH_RFW_FILTER_UNDET_MAC (1 << 0) 1295 /* filter specific MAC DA based on MAC table output */ 1296 #define AL_ETH_RFW_FILTER_DET_MAC (1 << 1) 1297 /* filter all tagged */ 1298 #define AL_ETH_RFW_FILTER_TAGGED (1 << 2) 1299 /* filter all untagged */ 1300 #define AL_ETH_RFW_FILTER_UNTAGGED (1 << 3) 1301 /* filter all broadcast */ 1302 #define AL_ETH_RFW_FILTER_BC (1 << 4) 1303 /* filter all multicast */ 1304 #define AL_ETH_RFW_FILTER_MC (1 << 5) 1305 /* filter packet based on parser drop */ 1306 #define AL_ETH_RFW_FILTER_PARSE (1 << 6) 1307 /* filter packet based on VLAN table output */ 1308 #define AL_ETH_RFW_FILTER_VLAN_VID (1 << 7) 1309 /* filter packet based on control table output */ 1310 #define AL_ETH_RFW_FILTER_CTRL_TABLE (1 << 8) 1311 /* filter packet based on protocol index */ 1312 #define AL_ETH_RFW_FILTER_PROT_INDEX (1 << 9) 1313 /* filter packet based on WoL decision */ 1314 #define AL_ETH_RFW_FILTER_WOL (1 << 10) 1315 1316 1317 struct al_eth_filter_params { 1318 al_bool enable; 1319 uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to enable */ 1320 al_bool filter_proto[AL_ETH_PROTOCOLS_NUM]; /**< set AL_TRUE for protocols to filter */ 1321 }; 1322 1323 struct al_eth_filter_override_params { 1324 uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to override */ 1325 uint8_t udma; /**< target udma id */ 1326 uint8_t qid; /**< target queue id */ 1327 }; 1328 1329 /** 1330 * Configure the receive filters 1331 * this function enables/disables filtering packets and which filtering 1332 * types to apply. 1333 * filters that indicated in tables (MAC table, VLAN and Control tables) 1334 * are not configured by this function. This functions only enables/disables 1335 * respecting the filter indication from those tables. 1336 * 1337 * @param adapter pointer to the private structure 1338 * @param params the parameters passed from upper layer 1339 * 1340 * @return 0 on success. otherwise on failure. 1341 */ 1342 int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params); 1343 1344 /** 1345 * Configure the receive override filters 1346 * This function controls whither to force forwarding filtered packets 1347 * to a specific UDMA/queue. The override filters apply only for 1348 * filters that enabled by al_eth_filter_config(). 1349 * 1350 * @param adapter pointer to the private structure 1351 * @param params override config parameters 1352 * 1353 * @return 0 on success. otherwise on failure. 1354 */ 1355 int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter, 1356 struct al_eth_filter_override_params *params); 1357 1358 1359 int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching, 1360 enum al_eth_tx_switch_vid_sel_type vid_sel_type, 1361 enum al_eth_tx_switch_dec_type uc_dec, 1362 enum al_eth_tx_switch_dec_type mc_dec, 1363 enum al_eth_tx_switch_dec_type bc_dec); 1364 int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask, 1365 uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask); 1366 int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params); 1367 1368 struct al_eth_eee_params{ 1369 uint8_t enable; 1370 uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */ 1371 uint32_t min_interval; /**< minimum interval in cycles between two eee states */ 1372 uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */ 1373 al_bool fast_wake; /**< fast_wake is only applicable to 40/50G, otherwise the mode is deep_sleep */ 1374 }; 1375 1376 /** 1377 * configure EEE mode 1378 * @param adapter pointer to the private structure. 1379 * @param params pointer to the eee input parameters. 1380 * 1381 * @return return 0 on success. otherwise on failure. 1382 */ 1383 int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1384 1385 /** 1386 * get EEE configuration 1387 * @param adapter pointer to the private structure. 1388 * @param params pointer to the eee output parameters. 1389 * 1390 * @return return 0 on success. otherwise on failure. 1391 */ 1392 int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1393 1394 int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data); 1395 1396 /* Timestamp 1397 * This is a generic time-stamp mechanism that can be used as generic to 1398 * time-stamp every received or transmit packet it can also support IEEE 1588v2 1399 * PTP time synchronization protocol. 1400 * In addition to time-stamp, an internal system time is maintained. For 1401 * further accuracy, the chip support transmit/receive clock synchronization 1402 * including recovery of master clock from one of the ports and distributing it 1403 * to the rest of the ports - that is outside the scope of the Ethernet 1404 * Controller - please refer to Annapurna Labs Alpine Hardware Wiki 1405 */ 1406 1407 /* Timestamp management APIs */ 1408 1409 /** 1410 * prepare the adapter for timestamping packets. 1411 * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor 1412 * size as the timestamp value added into word 4. 1413 * 1414 * This function should be called after al_eth_mac_config() and before 1415 * enabling the queues. 1416 * @param adapter pointer to the private structure. 1417 * @return 0 on success. otherwise on failure. 1418 */ 1419 int al_eth_ts_init(struct al_hal_eth_adapter *adapter); 1420 1421 /* Timestamp data path APIs */ 1422 1423 /* 1424 * This is the size of the on-chip array that keeps the time-stamp of the 1425 * latest transmitted packets 1426 */ 1427 #define AL_ETH_PTH_TX_SAMPLES_NUM 16 1428 1429 /** 1430 * read Timestamp sample value of previously transmitted packet. 1431 * 1432 * The adapter includes AL_ETH_PTH_TX_SAMPLES_NUM timestamp samples for tx 1433 * packets, those samples shared for all the UDMAs and queues. the al_eth_pkt 1434 * data structure includes the index of which sample to use for the packet 1435 * to transmit. It's the caller's responsibility to manage those samples, 1436 * for example, when using an index, the caller must make sure the packet 1437 * is completed and the tx time is sampled before using that index for 1438 * another packet. 1439 * 1440 * This function should be called after the completion indication of the 1441 * tx packet. however, there is a little chance that the timestamp sample 1442 * won't be updated yet, thus this function must be called again when it 1443 * returns -EAGAIN. 1444 * @param adapter pointer to the private structure. 1445 * @param ts_index the index (out of 16) of the timestamp register 1446 * @param timestamp the timestamp value in 2^18 femtoseconds resolution. 1447 * @return -EAGAIN if the sample was not updated yet. 0 when the sample 1448 * was updated and no errors found. 1449 */ 1450 int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index, 1451 uint32_t *timestamp); 1452 1453 /* Timestamp PTH (PTP Timestamp Handler) control and times management */ 1454 /** structure for describing PTH epoch time */ 1455 struct al_eth_pth_time { 1456 uint32_t seconds; /**< seconds */ 1457 uint64_t femto; /**< femto seconds */ 1458 }; 1459 1460 /** 1461 * Read the systime value 1462 * This API should not be used to get the timestamp of packets. 1463 * The HW maintains 50 bits for the sub-seconds portion in femto resolution, 1464 * but this function reads only the 32 MSB bits since the LSB provides 1465 * sub-nanoseconds accuracy, which is not needed. 1466 * @param adapter pointer to the private structure. 1467 * @param systime pointer to structure where the time will be stored. 1468 * @return 0 on success. otherwise on failure. 1469 */ 1470 int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter, 1471 struct al_eth_pth_time *systime); 1472 1473 /** 1474 * Set the clock period to a given value. 1475 * The systime will be incremented by this value on each posedge of the 1476 * adapters internal clock which driven by the SouthBridge clock. 1477 * @param adapter pointer to the private structure. 1478 * @param clk_period the clock period in femto seconds. 1479 * @return 0 on success. otherwise on failure. 1480 */ 1481 int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter, 1482 uint64_t clk_period); 1483 1484 /**< enum for methods when updating systime using triggers */ 1485 enum al_eth_pth_update_method { 1486 AL_ETH_PTH_UPDATE_METHOD_SET = 0, /**< Set the time in int/ext update time */ 1487 AL_ETH_PTH_UPDATE_METHOD_INC = 1, /**< increment */ 1488 AL_ETH_PTH_UPDATE_METHOD_DEC = 2, /**< decrement */ 1489 AL_ETH_PTH_UPDATE_METHOD_ADD_TO_LAST = 3, /**< Set to last time + int/ext update time.*/ 1490 }; 1491 1492 /**< systime internal update trigger types */ 1493 enum al_eth_pth_int_trig { 1494 AL_ETH_PTH_INT_TRIG_OUT_PULSE_0 = 0, /**< use output pulse as trigger */ 1495 AL_ETH_PTH_INT_TRIG_REG_WRITE = 1, /**< use the int update register 1496 * write as a trigger 1497 */ 1498 }; 1499 1500 /**< parameters for internal trigger update */ 1501 struct al_eth_pth_int_update_params { 1502 al_bool enable; /**< enable internal trigger update */ 1503 enum al_eth_pth_update_method method; /**< internal trigger update 1504 * method 1505 */ 1506 enum al_eth_pth_int_trig trigger; /**< which internal trigger to 1507 * use 1508 */ 1509 }; 1510 1511 /** 1512 * Configure the systime internal update 1513 * 1514 * @param adapter pointer to the private structure. 1515 * @param params the configuration of the internal update. 1516 * @return 0 on success. otherwise on failure. 1517 */ 1518 int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter, 1519 struct al_eth_pth_int_update_params *params); 1520 1521 /** 1522 * set internal update time 1523 * 1524 * The update time used when updating the systime with 1525 * internal update method. 1526 * 1527 * @param adapter pointer to the private structure. 1528 * @param time the internal update time value 1529 * @return 0 on success. otherwise on failure. 1530 */ 1531 int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter, 1532 struct al_eth_pth_time *time); 1533 1534 /**< parameters for external trigger update */ 1535 struct al_eth_pth_ext_update_params { 1536 uint8_t triggers; /**< bitmask of external triggers to enable */ 1537 enum al_eth_pth_update_method method; /**< external trigger update 1538 * method 1539 */ 1540 }; 1541 1542 /** 1543 * Configure the systime external update. 1544 * external update triggered by external signals such as GPIO or pulses 1545 * from other eth controllers on the SoC. 1546 * 1547 * @param adapter pointer to the private structure. 1548 * @param params the configuration of the external update. 1549 * @return 0 on success. otherwise on failure. 1550 */ 1551 int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter, 1552 struct al_eth_pth_ext_update_params *params); 1553 1554 /** 1555 * set external update time 1556 * 1557 * The update time used when updating the systime with 1558 * external update method. 1559 * @param adapter pointer to the private structure. 1560 * @param time the external update time value 1561 * @return 0 on success. otherwise on failure. 1562 */ 1563 int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter, 1564 struct al_eth_pth_time *time); 1565 /** 1566 * set the read compensation delay 1567 * 1568 * When reading the systime, the HW adds this value to compensate 1569 * read latency. 1570 * 1571 * @param adapter pointer to the private structure. 1572 * @param subseconds the read latency delay in femto seconds. 1573 * @return 0 on success. otherwise on failure. 1574 */ 1575 int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter, 1576 uint64_t subseconds); 1577 /** 1578 * set the internal write compensation delay 1579 * 1580 * When updating the systime due to an internal trigger's event, the HW adds 1581 * this value to compensate latency. 1582 * 1583 * @param adapter pointer to the private structure. 1584 * @param subseconds the write latency delay in femto seconds. 1585 * @return 0 on success. otherwise on failure. 1586 */ 1587 int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter, 1588 uint64_t subseconds); 1589 1590 /** 1591 * set the external write compensation delay 1592 * 1593 * When updating the systime due to an external trigger's event, the HW adds 1594 * this value to compensate pulse propagation latency. 1595 * 1596 * @param adapter pointer to the private structure. 1597 * @param subseconds the write latency delay in femto seconds. 1598 * @return 0 on success. otherwise on failure. 1599 */ 1600 int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter, 1601 uint64_t subseconds); 1602 1603 /** 1604 * set the sync compensation delay 1605 * 1606 * When the adapter passes systime from PTH to MAC to do the packets 1607 * timestamping, the sync compensation delay is added to systime value to 1608 * compensate the latency between the PTH and the MAC. 1609 * 1610 * @param adapter pointer to the private structure. 1611 * @param subseconds the sync latency delay in femto seconds. 1612 * @return 0 on success. otherwise on failure. 1613 */ 1614 int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter, 1615 uint64_t subseconds); 1616 1617 #define AL_ETH_PTH_PULSE_OUT_NUM 8 1618 struct al_eth_pth_pulse_out_params { 1619 uint8_t index; /**< id of the pulse (0..7) */ 1620 al_bool enable; 1621 al_bool periodic; /**< when true, generate periodic pulse (PPS) */ 1622 uint8_t period_sec; /**< for periodic pulse, this is seconds 1623 * portion of the period time 1624 */ 1625 uint32_t period_us; /**< this is microseconds portion of the 1626 * period 1627 */ 1628 struct al_eth_pth_time start_time; /**< when to start pulse triggering */ 1629 uint64_t pulse_width; /**< pulse width in femto seconds */ 1630 }; 1631 1632 /** 1633 * Configure an output pulse 1634 * This function configures an output pulse coming from the internal System 1635 * Time. This is typically a 1Hhz pulse that is used to synchronize the 1636 * rest of the components of the system. This API configure the Ethernet 1637 * Controller pulse. An additional set up is required to configure the chip 1638 * General Purpose I/O (GPIO) to enable the chip output pin. 1639 * 1640 * @param adapter pointer to the private structure. 1641 * @param params output pulse configuration. 1642 * @return 0 on success. otherwise on failure. 1643 */ 1644 int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter, 1645 struct al_eth_pth_pulse_out_params *params); 1646 1647 /* link */ 1648 struct al_eth_link_status { 1649 al_bool link_up; 1650 al_bool local_fault; 1651 al_bool remote_fault; 1652 }; 1653 1654 /** 1655 * get link status 1656 * 1657 * this function should be used when no external phy is used to get 1658 * information about the link 1659 * 1660 * @param adapter pointer to the private structure. 1661 * @param status pointer to struct where to set link information 1662 * 1663 * @return return 0 on success. otherwise on failure. 1664 */ 1665 int al_eth_link_status_get(struct al_hal_eth_adapter *adapter, 1666 struct al_eth_link_status *status); 1667 1668 /** 1669 * clear link status 1670 * 1671 * this function clear latched status of the link. 1672 * 1673 * @param adapter pointer to the private structure. 1674 * 1675 * @return return 0 if supported. 1676 */ 1677 int al_eth_link_status_clear(struct al_hal_eth_adapter *adapter); 1678 1679 /** 1680 * Set LEDs to represent link status. 1681 * 1682 * @param adapter pointer to the private structure. 1683 * @param link_is_up boolean indicating current link status. 1684 * In case link is down the leds will be turned off. 1685 * In case link is up the leds will be turned on, that means 1686 * leds will be blinking on traffic and will be constantly lighting 1687 * on inactive link 1688 * @return return 0 on success. otherwise on failure. 1689 */ 1690 int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up); 1691 1692 /* get statistics */ 1693 1694 struct al_eth_mac_stats{ 1695 /* sum the data and padding octets (i.e. without header and FCS) received with a valid frame. */ 1696 uint64_t aOctetsReceivedOK; 1697 /* sum of Payload and padding octets of frames transmitted without error*/ 1698 uint64_t aOctetsTransmittedOK; 1699 /* total number of packets received. Good and bad packets */ 1700 uint32_t etherStatsPkts; 1701 /* number of received unicast packets */ 1702 uint32_t ifInUcastPkts; 1703 /* number of received multicast packets */ 1704 uint32_t ifInMulticastPkts; 1705 /* number of received broadcast packets */ 1706 uint32_t ifInBroadcastPkts; 1707 /* Number of frames received with FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */ 1708 uint32_t ifInErrors; 1709 1710 /* number of transmitted unicast packets */ 1711 uint32_t ifOutUcastPkts; 1712 /* number of transmitted multicast packets */ 1713 uint32_t ifOutMulticastPkts; 1714 /* number of transmitted broadcast packets */ 1715 uint32_t ifOutBroadcastPkts; 1716 /* number of frames transmitted with FIFO Overflow, FIFO Underflow or Controller indicated error */ 1717 uint32_t ifOutErrors; 1718 1719 /* number of Frame received without error (Including Pause Frames). */ 1720 uint32_t aFramesReceivedOK; 1721 /* number of Frames transmitter without error (Including Pause Frames) */ 1722 uint32_t aFramesTransmittedOK; 1723 /* number of packets received with less than 64 octets */ 1724 uint32_t etherStatsUndersizePkts; 1725 /* Too short frames with CRC error, available only for RGMII and 1G Serial modes */ 1726 uint32_t etherStatsFragments; 1727 /* Too long frames with CRC error */ 1728 uint32_t etherStatsJabbers; 1729 /* packet that exceeds the valid maximum programmed frame length */ 1730 uint32_t etherStatsOversizePkts; 1731 /* number of frames received with a CRC error */ 1732 uint32_t aFrameCheckSequenceErrors; 1733 /* number of frames received with alignment error */ 1734 uint32_t aAlignmentErrors; 1735 /* number of dropped packets due to FIFO overflow */ 1736 uint32_t etherStatsDropEvents; 1737 /* number of transmitted pause frames. */ 1738 uint32_t aPAUSEMACCtrlFramesTransmitted; 1739 /* number of received pause frames. */ 1740 uint32_t aPAUSEMACCtrlFramesReceived; 1741 /* frame received exceeded the maximum length programmed with register FRM_LGTH, available only for 10G modes */ 1742 uint32_t aFrameTooLongErrors; 1743 /* received frame with bad length/type (between 46 and 0x600 or less 1744 * than 46 for packets longer than 64), available only for 10G modes */ 1745 uint32_t aInRangeLengthErrors; 1746 /* Valid VLAN tagged frames transmitted */ 1747 uint32_t VLANTransmittedOK; 1748 /* Valid VLAN tagged frames received */ 1749 uint32_t VLANReceivedOK; 1750 /* Total number of octets received. Good and bad packets */ 1751 uint32_t etherStatsOctets; 1752 1753 /* packets of 64 octets length is received (good and bad frames are counted) */ 1754 uint32_t etherStatsPkts64Octets; 1755 /* Frames (good and bad) with 65 to 127 octets */ 1756 uint32_t etherStatsPkts65to127Octets; 1757 /* Frames (good and bad) with 128 to 255 octets */ 1758 uint32_t etherStatsPkts128to255Octets; 1759 /* Frames (good and bad) with 256 to 511 octets */ 1760 uint32_t etherStatsPkts256to511Octets; 1761 /* Frames (good and bad) with 512 to 1023 octets */ 1762 uint32_t etherStatsPkts512to1023Octets; 1763 /* Frames (good and bad) with 1024 to 1518 octets */ 1764 uint32_t etherStatsPkts1024to1518Octets; 1765 /* frames with 1519 bytes to the maximum length programmed in the register FRAME_LENGTH. */ 1766 uint32_t etherStatsPkts1519toX; 1767 1768 uint32_t eee_in; 1769 uint32_t eee_out; 1770 }; 1771 1772 /** 1773 * get mac statistics 1774 * @param adapter pointer to the private structure. 1775 * @param stats pointer to structure that will be filled with statistics. 1776 * 1777 * @return return 0 on success. otherwise on failure. 1778 */ 1779 int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats); 1780 1781 struct al_eth_ec_stats{ 1782 /* Rx Frequency adjust FIFO input packets */ 1783 uint32_t faf_in_rx_pkt; 1784 /* Rx Frequency adjust FIFO input short error packets */ 1785 uint32_t faf_in_rx_short; 1786 /* Rx Frequency adjust FIFO input long error packets */ 1787 uint32_t faf_in_rx_long; 1788 /* Rx Frequency adjust FIFO output packets */ 1789 uint32_t faf_out_rx_pkt; 1790 /* Rx Frequency adjust FIFO output short error packets */ 1791 uint32_t faf_out_rx_short; 1792 /* Rx Frequency adjust FIFO output long error packets */ 1793 uint32_t faf_out_rx_long; 1794 /* Rx Frequency adjust FIFO output drop packets */ 1795 uint32_t faf_out_drop; 1796 /* Number of packets written into the Rx FIFO (without FIFO error indication) */ 1797 uint32_t rxf_in_rx_pkt; 1798 /* Number of error packets written into the Rx FIFO (with FIFO error indication, */ 1799 /* FIFO full indication during packet reception) */ 1800 uint32_t rxf_in_fifo_err; 1801 /* Number of packets read from Rx FIFO 1 */ 1802 uint32_t lbf_in_rx_pkt; 1803 /* Number of packets read from Rx FIFO 2 (loopback FIFO) */ 1804 uint32_t lbf_in_fifo_err; 1805 /* Rx FIFO output drop packets from FIFO 1 */ 1806 uint32_t rxf_out_rx_1_pkt; 1807 /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1808 uint32_t rxf_out_rx_2_pkt; 1809 /* Rx FIFO output drop packets from FIFO 1 */ 1810 uint32_t rxf_out_drop_1_pkt; 1811 /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1812 uint32_t rxf_out_drop_2_pkt; 1813 /* Rx Parser 1, input packet counter */ 1814 uint32_t rpe_1_in_rx_pkt; 1815 /* Rx Parser 1, output packet counter */ 1816 uint32_t rpe_1_out_rx_pkt; 1817 /* Rx Parser 2, input packet counter */ 1818 uint32_t rpe_2_in_rx_pkt; 1819 /* Rx Parser 2, output packet counter */ 1820 uint32_t rpe_2_out_rx_pkt; 1821 /* Rx Parser 3 (MACsec), input packet counter */ 1822 uint32_t rpe_3_in_rx_pkt; 1823 /* Rx Parser 3 (MACsec), output packet counter */ 1824 uint32_t rpe_3_out_rx_pkt; 1825 /* Tx parser, input packet counter */ 1826 uint32_t tpe_in_tx_pkt; 1827 /* Tx parser, output packet counter */ 1828 uint32_t tpe_out_tx_pkt; 1829 /* Tx packet modification, input packet counter */ 1830 uint32_t tpm_tx_pkt; 1831 /* Tx forwarding input packet counter */ 1832 uint32_t tfw_in_tx_pkt; 1833 /* Tx forwarding input packet counter */ 1834 uint32_t tfw_out_tx_pkt; 1835 /* Rx forwarding input packet counter */ 1836 uint32_t rfw_in_rx_pkt; 1837 /* Rx Forwarding, packet with VLAN command drop indication */ 1838 uint32_t rfw_in_vlan_drop; 1839 /* Rx Forwarding, packets with parse drop indication */ 1840 uint32_t rfw_in_parse_drop; 1841 /* Rx Forwarding, multicast packets */ 1842 uint32_t rfw_in_mc; 1843 /* Rx Forwarding, broadcast packets */ 1844 uint32_t rfw_in_bc; 1845 /* Rx Forwarding, tagged packets */ 1846 uint32_t rfw_in_vlan_exist; 1847 /* Rx Forwarding, untagged packets */ 1848 uint32_t rfw_in_vlan_nexist; 1849 /* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */ 1850 uint32_t rfw_in_mac_drop; 1851 /* Rx Forwarding, packets with undetected MAC address */ 1852 uint32_t rfw_in_mac_ndet_drop; 1853 /* Rx Forwarding, packets with drop indication from the control table */ 1854 uint32_t rfw_in_ctrl_drop; 1855 /* Rx Forwarding, packets with L3_protocol_index drop indication */ 1856 uint32_t rfw_in_prot_i_drop; 1857 /* EEE, number of times the system went into EEE state */ 1858 uint32_t eee_in; 1859 }; 1860 1861 /** 1862 * get ec statistics 1863 * @param adapter pointer to the private structure. 1864 * @param stats pointer to structure that will be filled with statistics. 1865 * 1866 * @return return 0 on success. otherwise on failure. 1867 */ 1868 int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats); 1869 1870 struct al_eth_ec_stat_udma{ 1871 /* Rx forwarding output packet counter */ 1872 uint32_t rfw_out_rx_pkt; 1873 /* Rx forwarding output drop packet counter */ 1874 uint32_t rfw_out_drop; 1875 /* Multi-stream write, number of Rx packets */ 1876 uint32_t msw_in_rx_pkt; 1877 /* Multi-stream write, number of dropped packets at SOP, Q full indication */ 1878 uint32_t msw_drop_q_full; 1879 /* Multi-stream write, number of dropped packets at SOP */ 1880 uint32_t msw_drop_sop; 1881 /* Multi-stream write, number of dropped packets at EOP, */ 1882 /*EOP was written with error indication (not all packet data was written) */ 1883 uint32_t msw_drop_eop; 1884 /* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet loss */ 1885 uint32_t msw_wr_eop; 1886 /* Multi-stream write, number of packets read from the FIFO into the stream */ 1887 uint32_t msw_out_rx_pkt; 1888 /* Number of transmitted packets without TSO enabled */ 1889 uint32_t tso_no_tso_pkt; 1890 /* Number of transmitted packets with TSO enabled */ 1891 uint32_t tso_tso_pkt; 1892 /* Number of TSO segments that were generated */ 1893 uint32_t tso_seg_pkt; 1894 /* Number of TSO segments that required padding */ 1895 uint32_t tso_pad_pkt; 1896 /* Tx Packet modification, MAC SA spoof error */ 1897 uint32_t tpm_tx_spoof; 1898 /* Tx MAC interface, input packet counter */ 1899 uint32_t tmi_in_tx_pkt; 1900 /* Tx MAC interface, number of packets forwarded to the MAC */ 1901 uint32_t tmi_out_to_mac; 1902 /* Tx MAC interface, number of packets forwarded to the Rx data path */ 1903 uint32_t tmi_out_to_rx; 1904 /* Tx MAC interface, number of transmitted bytes */ 1905 uint32_t tx_q0_bytes; 1906 /* Tx MAC interface, number of transmitted bytes */ 1907 uint32_t tx_q1_bytes; 1908 /* Tx MAC interface, number of transmitted bytes */ 1909 uint32_t tx_q2_bytes; 1910 /* Tx MAC interface, number of transmitted bytes */ 1911 uint32_t tx_q3_bytes; 1912 /* Tx MAC interface, number of transmitted packets */ 1913 uint32_t tx_q0_pkts; 1914 /* Tx MAC interface, number of transmitted packets */ 1915 uint32_t tx_q1_pkts; 1916 /* Tx MAC interface, number of transmitted packets */ 1917 uint32_t tx_q2_pkts; 1918 /* Tx MAC interface, number of transmitted packets */ 1919 uint32_t tx_q3_pkts; 1920 }; 1921 1922 /** 1923 * get per_udma statistics 1924 * @param adapter pointer to the private structure. 1925 * @param idx udma_id value 1926 * @param stats pointer to structure that will be filled with statistics. 1927 * 1928 * @return return 0 on success. otherwise on failure. 1929 */ 1930 int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats); 1931 1932 /* trafic control */ 1933 1934 /** 1935 * perform Function Level Reset RMN 1936 * 1937 * Addressing RMN: 714 1938 * 1939 * @param pci_read_config_u32 pointer to function that reads register from pci header 1940 * @param pci_write_config_u32 pointer to function that writes register from pci header 1941 * @param handle pointer passes to the above functions as first parameter 1942 * @param mac_base base address of the MAC registers 1943 * 1944 * @return 0. 1945 */ 1946 int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1947 int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1948 void *handle, 1949 void __iomem *mac_base); 1950 1951 /** 1952 * perform Function Level Reset RMN but restore registers that contain board specific data 1953 * 1954 * the data that save and restored is the board params and mac addresses 1955 * 1956 * @param pci_read_config_u32 pointer to function that reads register from pci header 1957 * @param pci_write_config_u32 pointer to function that writes register from pci header 1958 * @param handle pointer passes to the above functions as first parameter 1959 * @param mac_base base address of the MAC registers 1960 * @param ec_base base address of the Ethernet Controller registers 1961 * @param mac_addresses_num number of mac addresses to restore 1962 * 1963 * @return 0. 1964 */ 1965 int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1966 int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1967 void *handle, 1968 void __iomem *mac_base, 1969 void __iomem *ec_base, 1970 int mac_addresses_num); 1971 1972 /* board specific information (media type, phy address, etc.. */ 1973 1974 1975 enum al_eth_board_media_type { 1976 AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT = 0, 1977 AL_ETH_BOARD_MEDIA_TYPE_RGMII = 1, 1978 AL_ETH_BOARD_MEDIA_TYPE_10GBASE_SR = 2, 1979 AL_ETH_BOARD_MEDIA_TYPE_SGMII = 3, 1980 AL_ETH_BOARD_MEDIA_TYPE_1000BASE_X = 4, 1981 AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT_AUTO_SPEED = 5, 1982 AL_ETH_BOARD_MEDIA_TYPE_SGMII_2_5G = 6, 1983 AL_ETH_BOARD_MEDIA_TYPE_NBASE_T = 7, 1984 AL_ETH_BOARD_MEDIA_TYPE_25G = 8, 1985 }; 1986 1987 enum al_eth_board_mdio_freq { 1988 AL_ETH_BOARD_MDIO_FREQ_2_5_MHZ = 0, 1989 AL_ETH_BOARD_MDIO_FREQ_1_MHZ = 1, 1990 }; 1991 1992 enum al_eth_board_ext_phy_if { 1993 AL_ETH_BOARD_PHY_IF_MDIO = 0, 1994 AL_ETH_BOARD_PHY_IF_XMDIO = 1, 1995 AL_ETH_BOARD_PHY_IF_I2C = 2, 1996 1997 }; 1998 1999 enum al_eth_board_auto_neg_mode { 2000 AL_ETH_BOARD_AUTONEG_OUT_OF_BAND = 0, 2001 AL_ETH_BOARD_AUTONEG_IN_BAND = 1, 2002 2003 }; 2004 2005 /* declare the 1G mac active speed when auto negotiation disabled */ 2006 enum al_eth_board_1g_speed { 2007 AL_ETH_BOARD_1G_SPEED_1000M = 0, 2008 AL_ETH_BOARD_1G_SPEED_100M = 1, 2009 AL_ETH_BOARD_1G_SPEED_10M = 2, 2010 }; 2011 2012 enum al_eth_retimer_channel { 2013 AL_ETH_RETIMER_CHANNEL_A = 0, 2014 AL_ETH_RETIMER_CHANNEL_B = 1, 2015 AL_ETH_RETIMER_CHANNEL_C = 2, 2016 AL_ETH_RETIMER_CHANNEL_D = 3, 2017 AL_ETH_RETIMER_CHANNEL_E = 4, 2018 AL_ETH_RETIMER_CHANNEL_F = 5, 2019 AL_ETH_RETIMER_CHANNEL_G = 6, 2020 AL_ETH_RETIMER_CHANNEL_H = 7, 2021 AL_ETH_RETIMER_CHANNEL_MAX = 8 2022 }; 2023 2024 /* list of supported retimers */ 2025 enum al_eth_retimer_type { 2026 AL_ETH_RETIMER_BR_210 = 0, 2027 AL_ETH_RETIMER_BR_410 = 1, 2028 AL_ETH_RETIMER_DS_25 = 2, 2029 2030 AL_ETH_RETIMER_TYPE_MAX = 4, 2031 }; 2032 2033 /** structure represents the board information. this info set by boot loader 2034 * and read by OS driver. 2035 */ 2036 struct al_eth_board_params { 2037 enum al_eth_board_media_type media_type; 2038 al_bool phy_exist; /**< external phy exist */ 2039 uint8_t phy_mdio_addr; /**< mdio address of external phy */ 2040 al_bool sfp_plus_module_exist; /**< SFP+ module connected */ 2041 al_bool autoneg_enable; /**< enable Auto-Negotiation */ 2042 al_bool kr_lt_enable; /**< enable KR Link-Training */ 2043 al_bool kr_fec_enable; /**< enable KR FEC */ 2044 enum al_eth_board_mdio_freq mdio_freq; /**< MDIO frequency */ 2045 uint8_t i2c_adapter_id; /**< identifier for the i2c adapter to use to access SFP+ module */ 2046 enum al_eth_board_ext_phy_if phy_if; /**< phy interface */ 2047 enum al_eth_board_auto_neg_mode an_mode; /**< auto-negotiation mode (in-band / out-of-band) */ 2048 uint8_t serdes_grp; /**< serdes's group id */ 2049 uint8_t serdes_lane; /**< serdes's lane id */ 2050 enum al_eth_ref_clk_freq ref_clk_freq; /**< reference clock frequency */ 2051 al_bool dont_override_serdes; /**< prevent override serdes parameters */ 2052 al_bool force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */ 2053 al_bool an_disable; /**< disable auto negotiation */ 2054 enum al_eth_board_1g_speed speed; /**< port speed if AN disabled */ 2055 al_bool half_duplex; /**< force half duplex if AN disabled */ 2056 al_bool fc_disable; /**< disable flow control */ 2057 al_bool retimer_exist; /**< retimer is exist on the board */ 2058 uint8_t retimer_bus_id; /**< in what i2c bus the retimer is on */ 2059 uint8_t retimer_i2c_addr; /**< i2c address of the retimer */ 2060 enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port (Rx) */ 2061 al_bool dac; /**< assume direct attached cable is connected if auto detect is off or failed */ 2062 uint8_t dac_len; /**< assume this cable length if auto detect is off or failed */ 2063 enum al_eth_retimer_type retimer_type; /**< the type of the specific retimer */ 2064 enum al_eth_retimer_channel retimer_tx_channel; /**< what channel connected to this port (Tx) */ 2065 uint8_t gpio_sfp_present; /**< gpio number of sfp present for this port. 0 if not exist */ 2066 }; 2067 2068 /** 2069 * set board parameter of the eth port 2070 * this function used to set the board parameters into scratchpad 2071 * registers. those paramters can be read later by OS driver. 2072 * 2073 * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2074 * @param params pointer to structure the includes the paramters 2075 * 2076 * @return 0 on success. otherwise on failure. 2077 */ 2078 int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params); 2079 2080 /** 2081 * get board parameter of the eth port 2082 * this function used to get the board parameters from scratchpad 2083 * registers. 2084 * 2085 * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2086 * @param params pointer to structure where the parameters will be stored. 2087 * 2088 * @return 0 on success. otherwise on failure. 2089 */ 2090 int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params); 2091 2092 /* 2093 * Wake-On-Lan (WoL) 2094 * 2095 * The following few functions configure the Wake-On-Lan packet detection 2096 * inside the Integrated Ethernet MAC. 2097 * 2098 * There are other alternative ways to set WoL, such using the 2099 * external 1000Base-T transceiver to set WoL mode. 2100 * 2101 * These APIs do not set the system-wide power-state, nor responsible on the 2102 * transition from Sleep to Normal power state. 2103 * 2104 * For system level considerations, please refer to Annapurna Labs Alpine Wiki. 2105 */ 2106 /* Interrupt enable WoL MAC DA Unicast detected packet */ 2107 #define AL_ETH_WOL_INT_UNICAST AL_BIT(0) 2108 /* Interrupt enable WoL L2 Multicast detected packet */ 2109 #define AL_ETH_WOL_INT_MULTICAST AL_BIT(1) 2110 /* Interrupt enable WoL L2 Broadcast detected packet */ 2111 #define AL_ETH_WOL_INT_BROADCAST AL_BIT(2) 2112 /* Interrupt enable WoL IPv4 detected packet */ 2113 #define AL_ETH_WOL_INT_IPV4 AL_BIT(3) 2114 /* Interrupt enable WoL IPv6 detected packet */ 2115 #define AL_ETH_WOL_INT_IPV6 AL_BIT(4) 2116 /* Interrupt enable WoL EtherType+MAC DA detected packet */ 2117 #define AL_ETH_WOL_INT_ETHERTYPE_DA AL_BIT(5) 2118 /* Interrupt enable WoL EtherType+L2 Broadcast detected packet */ 2119 #define AL_ETH_WOL_INT_ETHERTYPE_BC AL_BIT(6) 2120 /* Interrupt enable WoL parser detected packet */ 2121 #define AL_ETH_WOL_INT_PARSER AL_BIT(7) 2122 /* Interrupt enable WoL magic detected packet */ 2123 #define AL_ETH_WOL_INT_MAGIC AL_BIT(8) 2124 /* Interrupt enable WoL magic+password detected packet */ 2125 #define AL_ETH_WOL_INT_MAGIC_PSWD AL_BIT(9) 2126 2127 /* Forward enable WoL MAC DA Unicast detected packet */ 2128 #define AL_ETH_WOL_FWRD_UNICAST AL_BIT(0) 2129 /* Forward enable WoL L2 Multicast detected packet */ 2130 #define AL_ETH_WOL_FWRD_MULTICAST AL_BIT(1) 2131 /* Forward enable WoL L2 Broadcast detected packet */ 2132 #define AL_ETH_WOL_FWRD_BROADCAST AL_BIT(2) 2133 /* Forward enable WoL IPv4 detected packet */ 2134 #define AL_ETH_WOL_FWRD_IPV4 AL_BIT(3) 2135 /* Forward enable WoL IPv6 detected packet */ 2136 #define AL_ETH_WOL_FWRD_IPV6 AL_BIT(4) 2137 /* Forward enable WoL EtherType+MAC DA detected packet */ 2138 #define AL_ETH_WOL_FWRD_ETHERTYPE_DA AL_BIT(5) 2139 /* Forward enable WoL EtherType+L2 Broadcast detected packet */ 2140 #define AL_ETH_WOL_FWRD_ETHERTYPE_BC AL_BIT(6) 2141 /* Forward enable WoL parser detected packet */ 2142 #define AL_ETH_WOL_FWRD_PARSER AL_BIT(7) 2143 2144 struct al_eth_wol_params { 2145 uint8_t *dest_addr; /**< 6 bytes array of destanation address for 2146 magic packet detection */ 2147 uint8_t *pswd; /**< 6 bytes array of the password to use */ 2148 uint8_t *ipv4; /**< 4 bytes array of the ipv4 to use. 2149 example: for ip = 192.168.1.2 2150 ipv4[0]=2, ipv4[1]=1, ipv4[2]=168, ipv4[3]=192 */ 2151 uint8_t *ipv6; /** 16 bytes array of the ipv6 to use. 2152 example: ip = 2607:f0d0:1002:0051:0000:0000:5231:1234 2153 ipv6[0]=34, ipv6[1]=12, ipv6[2]=31 .. */ 2154 uint16_t ethr_type1; /**< first ethertype to use */ 2155 uint16_t ethr_type2; /**< secound ethertype to use */ 2156 uint16_t forward_mask; /**< bitmask of AL_ETH_WOL_FWRD_* of the packet 2157 types needed to be forward. */ 2158 uint16_t int_mask; /**< bitmask of AL_ETH_WOL_INT_* of the packet types 2159 that will send interrupt to wake the system. */ 2160 }; 2161 2162 /** 2163 * enable the wol mechanism 2164 * set what type of packets will wake up the system and what type of packets 2165 * neet to forward after the system is up 2166 * 2167 * beside this function wol filter also need to be set by 2168 * calling al_eth_filter_config with AL_ETH_RFW_FILTER_WOL 2169 * 2170 * @param adapter pointer to the private structure 2171 * @param wol the parameters needed to configure the wol 2172 * 2173 * @return 0 on success. otherwise on failure. 2174 */ 2175 int al_eth_wol_enable( 2176 struct al_hal_eth_adapter *adapter, 2177 struct al_eth_wol_params *wol); 2178 2179 /** 2180 * Disable the WoL mechnism. 2181 * 2182 * @param adapter pointer to the private structure 2183 * 2184 * @return 0 on success. otherwise on failure. 2185 */ 2186 int al_eth_wol_disable( 2187 struct al_hal_eth_adapter *adapter); 2188 2189 /** 2190 * Configure tx fwd vlan table entry 2191 * 2192 * @param adapter pointer to the private structure 2193 * @param idx the entry index within the vlan table. The HW uses the vlan id 2194 * field of the packet when accessing this table. 2195 * @param udma_mask vlan table value that indicates that the packet should be forward back to 2196 * the udmas, through the Rx path (udma_mask is one-hot representation) 2197 * @param fwd_to_mac vlan table value that indicates that the packet should be forward to mac 2198 * 2199 * @return 0 on success. otherwise on failure. 2200 */ 2201 int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, al_bool fwd_to_mac); 2202 2203 /** Tx Generic protocol detect Cam compare table entry */ 2204 struct al_eth_tx_gpd_cam_entry { 2205 enum AL_ETH_PROTO_ID l3_proto_idx; 2206 enum AL_ETH_PROTO_ID l4_proto_idx; 2207 enum AL_ETH_TX_TUNNEL_MODE tunnel_control; 2208 uint8_t source_vlan_count:2; 2209 uint8_t tx_gpd_cam_ctrl:1; 2210 uint8_t l3_proto_idx_mask:5; 2211 uint8_t l4_proto_idx_mask:5; 2212 uint8_t tunnel_control_mask:3; 2213 uint8_t source_vlan_count_mask:2; 2214 }; 2215 2216 /** Rx Generic protocol detect Cam compare table entry */ 2217 struct al_eth_rx_gpd_cam_entry { 2218 enum AL_ETH_PROTO_ID outer_l3_proto_idx; 2219 enum AL_ETH_PROTO_ID outer_l4_proto_idx; 2220 enum AL_ETH_PROTO_ID inner_l3_proto_idx; 2221 enum AL_ETH_PROTO_ID inner_l4_proto_idx; 2222 uint8_t parse_ctrl; 2223 uint8_t outer_l3_len; 2224 uint8_t l3_priority; 2225 uint8_t l4_dst_port_lsb; 2226 uint8_t rx_gpd_cam_ctrl:1; 2227 uint8_t outer_l3_proto_idx_mask:5; 2228 uint8_t outer_l4_proto_idx_mask:5; 2229 uint8_t inner_l3_proto_idx_mask:5; 2230 uint8_t inner_l4_proto_idx_mask:5; 2231 uint8_t parse_ctrl_mask; 2232 uint8_t outer_l3_len_mask; 2233 uint8_t l3_priority_mask; 2234 uint8_t l4_dst_port_lsb_mask; 2235 }; 2236 2237 enum AL_ETH_TX_GCP_ALU_OPSEL { 2238 AL_ETH_TX_GCP_ALU_L3_OFFSET = 0, 2239 AL_ETH_TX_GCP_ALU_OUTER_L3_OFFSET = 1, 2240 AL_ETH_TX_GCP_ALU_L3_LEN = 2, 2241 AL_ETH_TX_GCP_ALU_OUTER_L3_LEN = 3, 2242 AL_ETH_TX_GCP_ALU_L4_OFFSET = 4, 2243 AL_ETH_TX_GCP_ALU_L4_LEN = 5, 2244 AL_ETH_TX_GCP_ALU_TABLE_VAL = 10 2245 }; 2246 2247 enum AL_ETH_RX_GCP_ALU_OPSEL { 2248 AL_ETH_RX_GCP_ALU_OUTER_L3_OFFSET = 0, 2249 AL_ETH_RX_GCP_ALU_INNER_L3_OFFSET = 1, 2250 AL_ETH_RX_GCP_ALU_OUTER_L4_OFFSET = 2, 2251 AL_ETH_RX_GCP_ALU_INNER_L4_OFFSET = 3, 2252 AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_LAT = 4, 2253 AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_LAT = 5, 2254 AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_SEL = 6, 2255 AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_SEL = 7, 2256 AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_1 = 8, 2257 AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_2 = 9, 2258 AL_ETH_RX_GCP_ALU_TABLE_VAL = 10 2259 }; 2260 2261 /** Tx Generic crc prameters table entry */ 2262 2263 struct al_eth_tx_gcp_table_entry { 2264 uint8_t poly_sel:1; 2265 uint8_t crc32_bit_comp:1; 2266 uint8_t crc32_bit_swap:1; 2267 uint8_t crc32_byte_swap:1; 2268 uint8_t data_bit_swap:1; 2269 uint8_t data_byte_swap:1; 2270 uint8_t trail_size:4; 2271 uint8_t head_size:8; 2272 uint8_t head_calc:1; 2273 uint8_t mask_polarity:1; 2274 enum AL_ETH_ALU_OPCODE tx_alu_opcode_1; 2275 enum AL_ETH_ALU_OPCODE tx_alu_opcode_2; 2276 enum AL_ETH_ALU_OPCODE tx_alu_opcode_3; 2277 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_1; 2278 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_2; 2279 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_3; 2280 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_4; 2281 uint32_t gcp_mask[6]; 2282 uint32_t crc_init; 2283 uint8_t gcp_table_res:7; 2284 uint16_t alu_val:9; 2285 }; 2286 2287 /** Rx Generic crc prameters table entry */ 2288 2289 struct al_eth_rx_gcp_table_entry { 2290 uint8_t poly_sel:1; 2291 uint8_t crc32_bit_comp:1; 2292 uint8_t crc32_bit_swap:1; 2293 uint8_t crc32_byte_swap:1; 2294 uint8_t data_bit_swap:1; 2295 uint8_t data_byte_swap:1; 2296 uint8_t trail_size:4; 2297 uint8_t head_size:8; 2298 uint8_t head_calc:1; 2299 uint8_t mask_polarity:1; 2300 enum AL_ETH_ALU_OPCODE rx_alu_opcode_1; 2301 enum AL_ETH_ALU_OPCODE rx_alu_opcode_2; 2302 enum AL_ETH_ALU_OPCODE rx_alu_opcode_3; 2303 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_1; 2304 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_2; 2305 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_3; 2306 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_4; 2307 uint32_t gcp_mask[6]; 2308 uint32_t crc_init; 2309 uint32_t gcp_table_res:27; 2310 uint16_t alu_val:9; 2311 }; 2312 2313 /** Tx per_protocol_number crc & l3_checksum & l4_checksum command table entry */ 2314 2315 struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry { 2316 al_bool crc_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2317 al_bool crc_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2318 al_bool crc_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2319 al_bool crc_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2320 al_bool l4_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2321 al_bool l4_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2322 al_bool l4_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2323 al_bool l4_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2324 al_bool l3_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2325 al_bool l3_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2326 al_bool l3_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2327 al_bool l3_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2328 }; 2329 2330 /** 2331 * Configure tx_gpd_entry 2332 * 2333 * @param adapter pointer to the private structure 2334 * @param idx the entry index 2335 * @param tx_gpd_entry entry data for the Tx protocol detect Cam compare table 2336 * 2337 * @return 0 on success. otherwise on failure. 2338 * 2339 */ 2340 int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2341 struct al_eth_tx_gpd_cam_entry *tx_gpd_entry); 2342 2343 /** 2344 * Configure tx_gcp_entry 2345 * 2346 * @param adapter pointer to the private structure 2347 * @param idx the entry index 2348 * @param tx_gcp_entry entry data for the Tx Generic crc prameters table 2349 * 2350 * @return 0 on success. otherwise on failure. 2351 * 2352 */ 2353 int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2354 struct al_eth_tx_gcp_table_entry *tx_gcp_entry); 2355 2356 /** 2357 * Configure tx_crc_chksum_replace_cmd_entry 2358 * 2359 * @param adapter pointer to the private structure 2360 * @param idx the entry index 2361 * @param tx_replace_entry entry data for the Tx crc_&_l3_checksum_&_l4_checksum replace command table 2362 * 2363 * @return 0 on success. otherwise on failure. 2364 * 2365 */ 2366 int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2367 struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry); 2368 2369 /** 2370 * Configure rx_gpd_entry 2371 * 2372 * @param adapter pointer to the private structure 2373 * @param idx the entry index 2374 * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2375 * 2376 * @return 0 on success. otherwise on failure. 2377 * 2378 */ 2379 int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2380 struct al_eth_rx_gpd_cam_entry *rx_gpd_entry); 2381 2382 /** 2383 * Configure rx_gcp_entry 2384 * 2385 * @param adapter pointer to the private structure 2386 * @param idx the entry index 2387 * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2388 * @param rx_gcp_entry entry data for the Tx Generic crc prameters table 2389 * 2390 * @return 0 on success. otherwise on failure. 2391 * 2392 */ 2393 int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2394 struct al_eth_rx_gcp_table_entry *rx_gcp_entry); 2395 2396 /** 2397 * Configure tx_gpd_table and regs 2398 * 2399 * @param adapter pointer to the private structure 2400 * 2401 */ 2402 int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2403 2404 /** 2405 * Configure crc_chksum_replace_cmd_table 2406 * 2407 * @param adapter pointer to the private structure 2408 * 2409 */ 2410 int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter); 2411 2412 /** 2413 * Configure tx_gcp_table and regs 2414 * 2415 * @param adapter pointer to the private structure 2416 * 2417 */ 2418 int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2419 2420 /** 2421 * Configure rx_gpd_table and regs 2422 * 2423 * @param adapter pointer to the private structure 2424 * 2425 */ 2426 int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2427 2428 /** 2429 * Configure rx_gcp_table and regs 2430 * 2431 * @param adapter pointer to the private structure 2432 * 2433 */ 2434 int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2435 2436 #ifdef __cplusplus 2437 } 2438 #endif 2439 /* *INDENT-ON* */ 2440 #endif /* __AL_HAL_ETH_H__ */ 2441 /** @} end of Ethernet group */ 2442